1 /* 2 * Freescale MPC85xx Memory Controller kernel module 3 * 4 * Parts Copyrighted (c) 2013 by Freescale Semiconductor, Inc. 5 * 6 * Author: Dave Jiang <djiang@mvista.com> 7 * 8 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under 9 * the terms of the GNU General Public License version 2. This program 10 * is licensed "as is" without any warranty of any kind, whether express 11 * or implied. 12 * 13 */ 14 #include <linux/module.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/ctype.h> 18 #include <linux/io.h> 19 #include <linux/edac.h> 20 #include <linux/smp.h> 21 #include <linux/gfp.h> 22 #include <linux/fsl/edac.h> 23 24 #include <linux/of.h> 25 #include <linux/of_address.h> 26 #include <linux/of_irq.h> 27 #include "edac_module.h" 28 #include "mpc85xx_edac.h" 29 #include "fsl_ddr_edac.h" 30 31 static int edac_dev_idx; 32 #ifdef CONFIG_PCI 33 static int edac_pci_idx; 34 #endif 35 36 /* 37 * PCI Err defines 38 */ 39 #ifdef CONFIG_PCI 40 static u32 orig_pci_err_cap_dr; 41 static u32 orig_pci_err_en; 42 #endif 43 44 static u32 orig_l2_err_disable; 45 46 /**************************** PCI Err device ***************************/ 47 #ifdef CONFIG_PCI 48 49 static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) 50 { 51 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 52 u32 err_detect; 53 54 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 55 56 /* master aborts can happen during PCI config cycles */ 57 if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { 58 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 59 return; 60 } 61 62 pr_err("PCI error(s) detected\n"); 63 pr_err("PCI/X ERR_DR register: %#08x\n", err_detect); 64 65 pr_err("PCI/X ERR_ATTRIB register: %#08x\n", 66 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); 67 pr_err("PCI/X ERR_ADDR register: %#08x\n", 68 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); 69 pr_err("PCI/X ERR_EXT_ADDR register: %#08x\n", 70 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); 71 pr_err("PCI/X ERR_DL register: %#08x\n", 72 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); 73 pr_err("PCI/X ERR_DH register: %#08x\n", 74 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); 75 76 /* clear error bits */ 77 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 78 79 if (err_detect & PCI_EDE_PERR_MASK) 80 edac_pci_handle_pe(pci, pci->ctl_name); 81 82 if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) 83 edac_pci_handle_npe(pci, pci->ctl_name); 84 } 85 86 static void mpc85xx_pcie_check(struct edac_pci_ctl_info *pci) 87 { 88 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 89 u32 err_detect, err_cap_stat; 90 91 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 92 err_cap_stat = in_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR); 93 94 pr_err("PCIe error(s) detected\n"); 95 pr_err("PCIe ERR_DR register: 0x%08x\n", err_detect); 96 pr_err("PCIe ERR_CAP_STAT register: 0x%08x\n", err_cap_stat); 97 pr_err("PCIe ERR_CAP_R0 register: 0x%08x\n", 98 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R0)); 99 pr_err("PCIe ERR_CAP_R1 register: 0x%08x\n", 100 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R1)); 101 pr_err("PCIe ERR_CAP_R2 register: 0x%08x\n", 102 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R2)); 103 pr_err("PCIe ERR_CAP_R3 register: 0x%08x\n", 104 in_be32(pdata->pci_vbase + MPC85XX_PCIE_ERR_CAP_R3)); 105 106 /* clear error bits */ 107 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); 108 109 /* reset error capture */ 110 out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, err_cap_stat | 0x1); 111 } 112 113 static int mpc85xx_pcie_find_capability(struct device_node *np) 114 { 115 struct pci_controller *hose; 116 117 if (!np) 118 return -EINVAL; 119 120 hose = pci_find_hose_for_OF_device(np); 121 122 return early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); 123 } 124 125 static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) 126 { 127 struct edac_pci_ctl_info *pci = dev_id; 128 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 129 u32 err_detect; 130 131 err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); 132 133 if (!err_detect) 134 return IRQ_NONE; 135 136 if (pdata->is_pcie) 137 mpc85xx_pcie_check(pci); 138 else 139 mpc85xx_pci_check(pci); 140 141 return IRQ_HANDLED; 142 } 143 144 static int mpc85xx_pci_err_probe(struct platform_device *op) 145 { 146 struct edac_pci_ctl_info *pci; 147 struct mpc85xx_pci_pdata *pdata; 148 struct mpc85xx_edac_pci_plat_data *plat_data; 149 struct device_node *of_node; 150 struct resource r; 151 int res = 0; 152 153 if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) 154 return -ENOMEM; 155 156 pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); 157 if (!pci) 158 return -ENOMEM; 159 160 /* make sure error reporting method is sane */ 161 switch (edac_op_state) { 162 case EDAC_OPSTATE_POLL: 163 case EDAC_OPSTATE_INT: 164 break; 165 default: 166 edac_op_state = EDAC_OPSTATE_INT; 167 break; 168 } 169 170 pdata = pci->pvt_info; 171 pdata->name = "mpc85xx_pci_err"; 172 173 plat_data = op->dev.platform_data; 174 if (!plat_data) { 175 dev_err(&op->dev, "no platform data"); 176 res = -ENXIO; 177 goto err; 178 } 179 of_node = plat_data->of_node; 180 181 if (mpc85xx_pcie_find_capability(of_node) > 0) 182 pdata->is_pcie = true; 183 184 dev_set_drvdata(&op->dev, pci); 185 pci->dev = &op->dev; 186 pci->mod_name = EDAC_MOD_STR; 187 pci->ctl_name = pdata->name; 188 pci->dev_name = dev_name(&op->dev); 189 190 if (edac_op_state == EDAC_OPSTATE_POLL) { 191 if (pdata->is_pcie) 192 pci->edac_check = mpc85xx_pcie_check; 193 else 194 pci->edac_check = mpc85xx_pci_check; 195 } 196 197 pdata->edac_idx = edac_pci_idx++; 198 199 res = of_address_to_resource(of_node, 0, &r); 200 if (res) { 201 pr_err("%s: Unable to get resource for PCI err regs\n", __func__); 202 goto err; 203 } 204 205 /* we only need the error registers */ 206 r.start += 0xe00; 207 208 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), 209 pdata->name)) { 210 pr_err("%s: Error while requesting mem region\n", __func__); 211 res = -EBUSY; 212 goto err; 213 } 214 215 pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); 216 if (!pdata->pci_vbase) { 217 pr_err("%s: Unable to setup PCI err regs\n", __func__); 218 res = -ENOMEM; 219 goto err; 220 } 221 222 if (pdata->is_pcie) { 223 orig_pci_err_cap_dr = 224 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR); 225 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, ~0); 226 orig_pci_err_en = 227 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); 228 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, 0); 229 } else { 230 orig_pci_err_cap_dr = 231 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); 232 233 /* PCI master abort is expected during config cycles */ 234 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); 235 236 orig_pci_err_en = 237 in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); 238 239 /* disable master abort reporting */ 240 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); 241 } 242 243 /* clear error bits */ 244 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, ~0); 245 246 /* reset error capture */ 247 out_be32(pdata->pci_vbase + MPC85XX_PCI_GAS_TIMR, 0x1); 248 249 if (edac_pci_add_device(pci, pdata->edac_idx) > 0) { 250 edac_dbg(3, "failed edac_pci_add_device()\n"); 251 goto err; 252 } 253 254 if (edac_op_state == EDAC_OPSTATE_INT) { 255 pdata->irq = irq_of_parse_and_map(of_node, 0); 256 res = devm_request_irq(&op->dev, pdata->irq, 257 mpc85xx_pci_isr, 258 IRQF_SHARED, 259 "[EDAC] PCI err", pci); 260 if (res < 0) { 261 pr_err("%s: Unable to request irq %d for MPC85xx PCI err\n", 262 __func__, pdata->irq); 263 irq_dispose_mapping(pdata->irq); 264 res = -ENODEV; 265 goto err2; 266 } 267 268 pr_info(EDAC_MOD_STR " acquired irq %d for PCI Err\n", 269 pdata->irq); 270 } 271 272 if (pdata->is_pcie) { 273 /* 274 * Enable all PCIe error interrupt & error detect except invalid 275 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation 276 * enable bit and invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access 277 * detection enable bit. Because PCIe bus code to initialize and 278 * configure these PCIe devices on booting will use some invalid 279 * PEX_CONFIG_ADDR/PEX_CONFIG_DATA, edac driver prints the much 280 * notice information. So disable this detect to fix ugly print. 281 */ 282 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0 283 & ~PEX_ERR_ICCAIE_EN_BIT); 284 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, 0 285 | PEX_ERR_ICCAD_DISR_BIT); 286 } 287 288 devres_remove_group(&op->dev, mpc85xx_pci_err_probe); 289 edac_dbg(3, "success\n"); 290 pr_info(EDAC_MOD_STR " PCI err registered\n"); 291 292 return 0; 293 294 err2: 295 edac_pci_del_device(&op->dev); 296 err: 297 edac_pci_free_ctl_info(pci); 298 devres_release_group(&op->dev, mpc85xx_pci_err_probe); 299 return res; 300 } 301 302 static void mpc85xx_pci_err_remove(struct platform_device *op) 303 { 304 struct edac_pci_ctl_info *pci = dev_get_drvdata(&op->dev); 305 struct mpc85xx_pci_pdata *pdata = pci->pvt_info; 306 307 edac_dbg(0, "\n"); 308 309 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR, orig_pci_err_cap_dr); 310 out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, orig_pci_err_en); 311 312 edac_pci_del_device(&op->dev); 313 edac_pci_free_ctl_info(pci); 314 } 315 316 static const struct platform_device_id mpc85xx_pci_err_match[] = { 317 { 318 .name = "mpc85xx-pci-edac" 319 }, 320 {} 321 }; 322 323 static struct platform_driver mpc85xx_pci_err_driver = { 324 .probe = mpc85xx_pci_err_probe, 325 .remove = mpc85xx_pci_err_remove, 326 .id_table = mpc85xx_pci_err_match, 327 .driver = { 328 .name = "mpc85xx_pci_err", 329 .suppress_bind_attrs = true, 330 }, 331 }; 332 #endif /* CONFIG_PCI */ 333 334 /**************************** L2 Err device ***************************/ 335 336 /************************ L2 SYSFS parts ***********************************/ 337 338 static ssize_t mpc85xx_l2_inject_data_hi_show(struct edac_device_ctl_info 339 *edac_dev, char *data) 340 { 341 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 342 return sprintf(data, "0x%08x", 343 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI)); 344 } 345 346 static ssize_t mpc85xx_l2_inject_data_lo_show(struct edac_device_ctl_info 347 *edac_dev, char *data) 348 { 349 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 350 return sprintf(data, "0x%08x", 351 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO)); 352 } 353 354 static ssize_t mpc85xx_l2_inject_ctrl_show(struct edac_device_ctl_info 355 *edac_dev, char *data) 356 { 357 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 358 return sprintf(data, "0x%08x", 359 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL)); 360 } 361 362 static ssize_t mpc85xx_l2_inject_data_hi_store(struct edac_device_ctl_info 363 *edac_dev, const char *data, 364 size_t count) 365 { 366 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 367 if (isdigit(*data)) { 368 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJHI, 369 simple_strtoul(data, NULL, 0)); 370 return count; 371 } 372 return 0; 373 } 374 375 static ssize_t mpc85xx_l2_inject_data_lo_store(struct edac_device_ctl_info 376 *edac_dev, const char *data, 377 size_t count) 378 { 379 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 380 if (isdigit(*data)) { 381 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJLO, 382 simple_strtoul(data, NULL, 0)); 383 return count; 384 } 385 return 0; 386 } 387 388 static ssize_t mpc85xx_l2_inject_ctrl_store(struct edac_device_ctl_info 389 *edac_dev, const char *data, 390 size_t count) 391 { 392 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 393 if (isdigit(*data)) { 394 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINJCTL, 395 simple_strtoul(data, NULL, 0)); 396 return count; 397 } 398 return 0; 399 } 400 401 static const struct edac_dev_sysfs_attribute mpc85xx_l2_sysfs_attributes[] = { 402 { 403 .attr = { 404 .name = "inject_data_hi", 405 .mode = (S_IRUGO | S_IWUSR) 406 }, 407 .show = mpc85xx_l2_inject_data_hi_show, 408 .store = mpc85xx_l2_inject_data_hi_store}, 409 { 410 .attr = { 411 .name = "inject_data_lo", 412 .mode = (S_IRUGO | S_IWUSR) 413 }, 414 .show = mpc85xx_l2_inject_data_lo_show, 415 .store = mpc85xx_l2_inject_data_lo_store}, 416 { 417 .attr = { 418 .name = "inject_ctrl", 419 .mode = (S_IRUGO | S_IWUSR) 420 }, 421 .show = mpc85xx_l2_inject_ctrl_show, 422 .store = mpc85xx_l2_inject_ctrl_store}, 423 424 /* End of list */ 425 { 426 .attr = {.name = NULL} 427 } 428 }; 429 430 static void mpc85xx_set_l2_sysfs_attributes(struct edac_device_ctl_info 431 *edac_dev) 432 { 433 edac_dev->sysfs_attributes = mpc85xx_l2_sysfs_attributes; 434 } 435 436 /***************************** L2 ops ***********************************/ 437 438 static void mpc85xx_l2_check(struct edac_device_ctl_info *edac_dev) 439 { 440 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 441 u32 err_detect; 442 443 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 444 445 if (!(err_detect & L2_EDE_MASK)) 446 return; 447 448 pr_err("ECC Error in CPU L2 cache\n"); 449 pr_err("L2 Error Detect Register: 0x%08x\n", err_detect); 450 pr_err("L2 Error Capture Data High Register: 0x%08x\n", 451 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATAHI)); 452 pr_err("L2 Error Capture Data Lo Register: 0x%08x\n", 453 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTDATALO)); 454 pr_err("L2 Error Syndrome Register: 0x%08x\n", 455 in_be32(pdata->l2_vbase + MPC85XX_L2_CAPTECC)); 456 pr_err("L2 Error Attributes Capture Register: 0x%08x\n", 457 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRATTR)); 458 pr_err("L2 Error Address Capture Register: 0x%08x\n", 459 in_be32(pdata->l2_vbase + MPC85XX_L2_ERRADDR)); 460 461 /* clear error detect register */ 462 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, err_detect); 463 464 if (err_detect & L2_EDE_CE_MASK) 465 edac_device_handle_ce(edac_dev, 0, 0, edac_dev->ctl_name); 466 467 if (err_detect & L2_EDE_UE_MASK) 468 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name); 469 } 470 471 static irqreturn_t mpc85xx_l2_isr(int irq, void *dev_id) 472 { 473 struct edac_device_ctl_info *edac_dev = dev_id; 474 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 475 u32 err_detect; 476 477 err_detect = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET); 478 479 if (!(err_detect & L2_EDE_MASK)) 480 return IRQ_NONE; 481 482 mpc85xx_l2_check(edac_dev); 483 484 return IRQ_HANDLED; 485 } 486 487 static int mpc85xx_l2_err_probe(struct platform_device *op) 488 { 489 struct edac_device_ctl_info *edac_dev; 490 struct mpc85xx_l2_pdata *pdata; 491 struct resource r; 492 int res; 493 494 if (!devres_open_group(&op->dev, mpc85xx_l2_err_probe, GFP_KERNEL)) 495 return -ENOMEM; 496 497 edac_dev = edac_device_alloc_ctl_info(sizeof(*pdata), 498 "cpu", 1, "L", 1, 2, 499 edac_dev_idx); 500 if (!edac_dev) { 501 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 502 return -ENOMEM; 503 } 504 505 pdata = edac_dev->pvt_info; 506 pdata->name = "mpc85xx_l2_err"; 507 edac_dev->dev = &op->dev; 508 dev_set_drvdata(edac_dev->dev, edac_dev); 509 edac_dev->ctl_name = pdata->name; 510 edac_dev->dev_name = pdata->name; 511 512 res = of_address_to_resource(op->dev.of_node, 0, &r); 513 if (res) { 514 pr_err("%s: Unable to get resource for L2 err regs\n", __func__); 515 goto err; 516 } 517 518 /* we only need the error registers */ 519 r.start += 0xe00; 520 521 if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), 522 pdata->name)) { 523 pr_err("%s: Error while requesting mem region\n", __func__); 524 res = -EBUSY; 525 goto err; 526 } 527 528 pdata->l2_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); 529 if (!pdata->l2_vbase) { 530 pr_err("%s: Unable to setup L2 err regs\n", __func__); 531 res = -ENOMEM; 532 goto err; 533 } 534 535 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDET, ~0); 536 537 orig_l2_err_disable = in_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS); 538 539 /* clear the err_dis */ 540 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, 0); 541 542 edac_dev->mod_name = EDAC_MOD_STR; 543 544 if (edac_op_state == EDAC_OPSTATE_POLL) 545 edac_dev->edac_check = mpc85xx_l2_check; 546 547 mpc85xx_set_l2_sysfs_attributes(edac_dev); 548 549 pdata->edac_idx = edac_dev_idx++; 550 551 if (edac_device_add_device(edac_dev) > 0) { 552 edac_dbg(3, "failed edac_device_add_device()\n"); 553 goto err; 554 } 555 556 if (edac_op_state == EDAC_OPSTATE_INT) { 557 pdata->irq = irq_of_parse_and_map(op->dev.of_node, 0); 558 res = devm_request_irq(&op->dev, pdata->irq, 559 mpc85xx_l2_isr, IRQF_SHARED, 560 "[EDAC] L2 err", edac_dev); 561 if (res < 0) { 562 pr_err("%s: Unable to request irq %d for MPC85xx L2 err\n", 563 __func__, pdata->irq); 564 irq_dispose_mapping(pdata->irq); 565 res = -ENODEV; 566 goto err2; 567 } 568 569 pr_info(EDAC_MOD_STR " acquired irq %d for L2 Err\n", pdata->irq); 570 571 edac_dev->op_state = OP_RUNNING_INTERRUPT; 572 573 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, L2_EIE_MASK); 574 } 575 576 devres_remove_group(&op->dev, mpc85xx_l2_err_probe); 577 578 edac_dbg(3, "success\n"); 579 pr_info(EDAC_MOD_STR " L2 err registered\n"); 580 581 return 0; 582 583 err2: 584 edac_device_del_device(&op->dev); 585 err: 586 devres_release_group(&op->dev, mpc85xx_l2_err_probe); 587 edac_device_free_ctl_info(edac_dev); 588 return res; 589 } 590 591 static void mpc85xx_l2_err_remove(struct platform_device *op) 592 { 593 struct edac_device_ctl_info *edac_dev = dev_get_drvdata(&op->dev); 594 struct mpc85xx_l2_pdata *pdata = edac_dev->pvt_info; 595 596 edac_dbg(0, "\n"); 597 598 if (edac_op_state == EDAC_OPSTATE_INT) { 599 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRINTEN, 0); 600 irq_dispose_mapping(pdata->irq); 601 } 602 603 out_be32(pdata->l2_vbase + MPC85XX_L2_ERRDIS, orig_l2_err_disable); 604 edac_device_del_device(&op->dev); 605 edac_device_free_ctl_info(edac_dev); 606 } 607 608 static const struct of_device_id mpc85xx_l2_err_of_match[] = { 609 { .compatible = "fsl,mpc8536-l2-cache-controller", }, 610 { .compatible = "fsl,mpc8540-l2-cache-controller", }, 611 { .compatible = "fsl,mpc8541-l2-cache-controller", }, 612 { .compatible = "fsl,mpc8544-l2-cache-controller", }, 613 { .compatible = "fsl,mpc8548-l2-cache-controller", }, 614 { .compatible = "fsl,mpc8555-l2-cache-controller", }, 615 { .compatible = "fsl,mpc8560-l2-cache-controller", }, 616 { .compatible = "fsl,mpc8568-l2-cache-controller", }, 617 { .compatible = "fsl,mpc8569-l2-cache-controller", }, 618 { .compatible = "fsl,mpc8572-l2-cache-controller", }, 619 { .compatible = "fsl,p1020-l2-cache-controller", }, 620 { .compatible = "fsl,p1021-l2-cache-controller", }, 621 { .compatible = "fsl,p2020-l2-cache-controller", }, 622 { .compatible = "fsl,t2080-l2-cache-controller", }, 623 {}, 624 }; 625 MODULE_DEVICE_TABLE(of, mpc85xx_l2_err_of_match); 626 627 static struct platform_driver mpc85xx_l2_err_driver = { 628 .probe = mpc85xx_l2_err_probe, 629 .remove = mpc85xx_l2_err_remove, 630 .driver = { 631 .name = "mpc85xx_l2_err", 632 .of_match_table = mpc85xx_l2_err_of_match, 633 }, 634 }; 635 636 static const struct of_device_id mpc85xx_mc_err_of_match[] = { 637 { .compatible = "fsl,mpc8536-memory-controller", }, 638 { .compatible = "fsl,mpc8540-memory-controller", }, 639 { .compatible = "fsl,mpc8541-memory-controller", }, 640 { .compatible = "fsl,mpc8544-memory-controller", }, 641 { .compatible = "fsl,mpc8548-memory-controller", }, 642 { .compatible = "fsl,mpc8555-memory-controller", }, 643 { .compatible = "fsl,mpc8560-memory-controller", }, 644 { .compatible = "fsl,mpc8568-memory-controller", }, 645 { .compatible = "fsl,mpc8569-memory-controller", }, 646 { .compatible = "fsl,mpc8572-memory-controller", }, 647 { .compatible = "fsl,mpc8349-memory-controller", }, 648 { .compatible = "fsl,p1020-memory-controller", }, 649 { .compatible = "fsl,p1021-memory-controller", }, 650 { .compatible = "fsl,p2020-memory-controller", }, 651 { .compatible = "fsl,qoriq-memory-controller", }, 652 {}, 653 }; 654 MODULE_DEVICE_TABLE(of, mpc85xx_mc_err_of_match); 655 656 static struct platform_driver mpc85xx_mc_err_driver = { 657 .probe = fsl_mc_err_probe, 658 .remove = fsl_mc_err_remove, 659 .driver = { 660 .name = "mpc85xx_mc_err", 661 .of_match_table = mpc85xx_mc_err_of_match, 662 }, 663 }; 664 665 static struct platform_driver * const drivers[] = { 666 &mpc85xx_mc_err_driver, 667 &mpc85xx_l2_err_driver, 668 #ifdef CONFIG_PCI 669 &mpc85xx_pci_err_driver, 670 #endif 671 }; 672 673 static int __init mpc85xx_mc_init(void) 674 { 675 int res = 0; 676 u32 __maybe_unused pvr = 0; 677 678 pr_info("Freescale(R) MPC85xx EDAC driver, (C) 2006 Montavista Software\n"); 679 680 /* make sure error reporting method is sane */ 681 switch (edac_op_state) { 682 case EDAC_OPSTATE_POLL: 683 case EDAC_OPSTATE_INT: 684 break; 685 default: 686 edac_op_state = EDAC_OPSTATE_INT; 687 break; 688 } 689 690 res = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 691 if (res) 692 pr_warn(EDAC_MOD_STR "drivers fail to register\n"); 693 694 return 0; 695 } 696 697 module_init(mpc85xx_mc_init); 698 699 static void __exit mpc85xx_mc_exit(void) 700 { 701 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 702 } 703 704 module_exit(mpc85xx_mc_exit); 705 706 MODULE_DESCRIPTION("Freescale MPC85xx Memory Controller EDAC driver"); 707 MODULE_LICENSE("GPL"); 708 MODULE_AUTHOR("Montavista Software, Inc."); 709 module_param(edac_op_state, int, 0444); 710 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); 711