1 #ifndef _EDAC_MCE_AMD_H 2 #define _EDAC_MCE_AMD_H 3 4 #include <linux/notifier.h> 5 6 #include <asm/mce.h> 7 8 #define EC(x) ((x) & 0xffff) 9 #define XEC(x, mask) (((x) >> 16) & mask) 10 11 #define LOW_SYNDROME(x) (((x) >> 15) & 0xff) 12 #define HIGH_SYNDROME(x) (((x) >> 24) & 0xff) 13 14 #define TLB_ERROR(x) (((x) & 0xFFF0) == 0x0010) 15 #define MEM_ERROR(x) (((x) & 0xFF00) == 0x0100) 16 #define BUS_ERROR(x) (((x) & 0xF800) == 0x0800) 17 18 #define TT(x) (((x) >> 2) & 0x3) 19 #define TT_MSG(x) tt_msgs[TT(x)] 20 #define II(x) (((x) >> 2) & 0x3) 21 #define II_MSG(x) ii_msgs[II(x)] 22 #define LL(x) ((x) & 0x3) 23 #define LL_MSG(x) ll_msgs[LL(x)] 24 #define TO(x) (((x) >> 8) & 0x1) 25 #define TO_MSG(x) to_msgs[TO(x)] 26 #define PP(x) (((x) >> 9) & 0x3) 27 #define PP_MSG(x) pp_msgs[PP(x)] 28 29 #define R4(x) (((x) >> 4) & 0xf) 30 #define R4_MSG(x) ((R4(x) < 9) ? rrrr_msgs[R4(x)] : "Wrong R4!") 31 32 #define MCI_STATUS_DEFERRED BIT_64(44) 33 #define MCI_STATUS_POISON BIT_64(43) 34 35 enum tt_ids { 36 TT_INSTR = 0, 37 TT_DATA, 38 TT_GEN, 39 TT_RESV, 40 }; 41 42 enum ll_ids { 43 LL_RESV = 0, 44 LL_L1, 45 LL_L2, 46 LL_LG, 47 }; 48 49 enum ii_ids { 50 II_MEM = 0, 51 II_RESV, 52 II_IO, 53 II_GEN, 54 }; 55 56 enum rrrr_ids { 57 R4_GEN = 0, 58 R4_RD, 59 R4_WR, 60 R4_DRD, 61 R4_DWR, 62 R4_IRD, 63 R4_PREF, 64 R4_EVICT, 65 R4_SNOOP, 66 }; 67 68 extern const char * const tt_msgs[]; 69 extern const char * const ll_msgs[]; 70 extern const char * const rrrr_msgs[]; 71 extern const char * const pp_msgs[]; 72 extern const char * const to_msgs[]; 73 extern const char * const ii_msgs[]; 74 75 /* 76 * per-family decoder ops 77 */ 78 struct amd_decoder_ops { 79 bool (*mc0_mce)(u16, u8); 80 bool (*mc1_mce)(u16, u8); 81 }; 82 83 void amd_report_gart_errors(bool); 84 void amd_register_ecc_decoder(void (*f)(int, struct mce *)); 85 void amd_unregister_ecc_decoder(void (*f)(int, struct mce *)); 86 int amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data); 87 88 #endif /* _EDAC_MCE_AMD_H */ 89