1 /* 2 * Freescale Memory Controller kernel module 3 * 4 * Author: York Sun <york.sun@nxp.com> 5 * 6 * Copyright 2016 NXP Semiconductor 7 * 8 * Derived from mpc85xx_edac.c 9 * Author: Dave Jiang <djiang@mvista.com> 10 * 11 * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under 12 * the terms of the GNU General Public License version 2. This program 13 * is licensed "as is" without any warranty of any kind, whether express 14 * or implied. 15 */ 16 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 18 19 #include "edac_module.h" 20 #include "fsl_ddr_edac.h" 21 22 static const struct of_device_id fsl_ddr_mc_err_of_match[] = { 23 { .compatible = "fsl,qoriq-memory-controller", }, 24 { .compatible = "nxp,imx9-memory-controller", .data = (void *)TYPE_IMX9, }, 25 {}, 26 }; 27 MODULE_DEVICE_TABLE(of, fsl_ddr_mc_err_of_match); 28 29 static struct platform_driver fsl_ddr_mc_err_driver = { 30 .probe = fsl_mc_err_probe, 31 .remove_new = fsl_mc_err_remove, 32 .driver = { 33 .name = "fsl_ddr_mc_err", 34 .of_match_table = fsl_ddr_mc_err_of_match, 35 }, 36 }; 37 38 static int __init fsl_ddr_mc_init(void) 39 { 40 int res; 41 42 if (ghes_get_devices()) 43 return -EBUSY; 44 45 /* make sure error reporting method is sane */ 46 switch (edac_op_state) { 47 case EDAC_OPSTATE_POLL: 48 case EDAC_OPSTATE_INT: 49 break; 50 default: 51 edac_op_state = EDAC_OPSTATE_INT; 52 break; 53 } 54 55 res = platform_driver_register(&fsl_ddr_mc_err_driver); 56 if (res) { 57 pr_err("MC fails to register\n"); 58 return res; 59 } 60 61 return 0; 62 } 63 64 module_init(fsl_ddr_mc_init); 65 66 static void __exit fsl_ddr_mc_exit(void) 67 { 68 platform_driver_unregister(&fsl_ddr_mc_err_driver); 69 } 70 71 module_exit(fsl_ddr_mc_exit); 72 73 MODULE_DESCRIPTION("Freescale Layerscape EDAC driver"); 74 MODULE_LICENSE("GPL"); 75 MODULE_AUTHOR("NXP Semiconductor"); 76 module_param(edac_op_state, int, 0444); 77 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll, 2=Interrupt"); 78