1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel E3-1200 4 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> 5 * 6 * Support for the E3-1200 processor family. Heavily based on previous 7 * Intel EDAC drivers. 8 * 9 * Since the DRAM controller is on the cpu chip, we can use its PCI device 10 * id to identify these processors. 11 * 12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/) 13 * 14 * 0108: Xeon E3-1200 Processor Family DRAM Controller 15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller 16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller 18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller 20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller 21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers 22 * 590f: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 23 * 5918: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 24 * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers 25 * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers 26 * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers 27 * 28 * Based on Intel specification: 29 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf 30 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html 31 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf 32 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf 33 * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html 34 * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html 35 * 36 * According to the above datasheet (p.16): 37 * " 38 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with 39 * requests that cross a DW boundary. 40 * " 41 * 42 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into 43 * 2 readl() calls. This restriction may be lifted in subsequent chip releases, 44 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. 45 */ 46 47 #include <linux/module.h> 48 #include <linux/init.h> 49 #include <linux/pci.h> 50 #include <linux/pci_ids.h> 51 #include <linux/edac.h> 52 53 #include <linux/io-64-nonatomic-lo-hi.h> 54 #include "edac_module.h" 55 56 #define EDAC_MOD_STR "ie31200_edac" 57 58 #define ie31200_printk(level, fmt, arg...) \ 59 edac_printk(level, "ie31200", fmt, ##arg) 60 61 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 62 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c 63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c 66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F 69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918 70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F 71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x590f 72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_12 0x5918 73 74 /* Coffee Lake-S */ 75 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00 76 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f 77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18 78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f 79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30 80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31 81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32 82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33 83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2 84 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6 85 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca 86 87 /* Test if HB is for Skylake or later. */ 88 #define DEVICE_ID_SKYLAKE_OR_LATER(did) \ 89 (((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) || \ 90 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) || \ 91 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) || \ 92 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) || \ 93 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_12) || \ 94 (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) == \ 95 PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK)) 96 97 #define IE31200_DIMMS 4 98 #define IE31200_RANKS 8 99 #define IE31200_RANKS_PER_CHANNEL 4 100 #define IE31200_DIMMS_PER_CHANNEL 2 101 #define IE31200_CHANNELS 2 102 103 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ 104 #define IE31200_MCHBAR_LOW 0x48 105 #define IE31200_MCHBAR_HIGH 0x4c 106 #define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15) 107 #define IE31200_MMR_WINDOW_SIZE BIT(15) 108 109 /* 110 * Error Status Register (16b) 111 * 112 * 15 reserved 113 * 14 Isochronous TBWRR Run Behind FIFO Full 114 * (ITCV) 115 * 13 Isochronous TBWRR Run Behind FIFO Put 116 * (ITSTV) 117 * 12 reserved 118 * 11 MCH Thermal Sensor Event 119 * for SMI/SCI/SERR (GTSE) 120 * 10 reserved 121 * 9 LOCK to non-DRAM Memory Flag (LCKF) 122 * 8 reserved 123 * 7 DRAM Throttle Flag (DTF) 124 * 6:2 reserved 125 * 1 Multi-bit DRAM ECC Error Flag (DMERR) 126 * 0 Single-bit DRAM ECC Error Flag (DSERR) 127 */ 128 #define IE31200_ERRSTS 0xc8 129 #define IE31200_ERRSTS_UE BIT(1) 130 #define IE31200_ERRSTS_CE BIT(0) 131 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) 132 133 /* 134 * Channel 0 ECC Error Log (64b) 135 * 136 * 63:48 Error Column Address (ERRCOL) 137 * 47:32 Error Row Address (ERRROW) 138 * 31:29 Error Bank Address (ERRBANK) 139 * 28:27 Error Rank Address (ERRRANK) 140 * 26:24 reserved 141 * 23:16 Error Syndrome (ERRSYND) 142 * 15: 2 reserved 143 * 1 Multiple Bit Error Status (MERRSTS) 144 * 0 Correctable Error Status (CERRSTS) 145 */ 146 147 #define IE31200_C0ECCERRLOG 0x40c8 148 #define IE31200_C1ECCERRLOG 0x44c8 149 #define IE31200_C0ECCERRLOG_SKL 0x4048 150 #define IE31200_C1ECCERRLOG_SKL 0x4448 151 #define IE31200_ECCERRLOG_CE BIT(0) 152 #define IE31200_ECCERRLOG_UE BIT(1) 153 #define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27) 154 #define IE31200_ECCERRLOG_RANK_SHIFT 27 155 #define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16) 156 #define IE31200_ECCERRLOG_SYNDROME_SHIFT 16 157 158 #define IE31200_ECCERRLOG_SYNDROME(log) \ 159 ((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \ 160 IE31200_ECCERRLOG_SYNDROME_SHIFT) 161 162 #define IE31200_CAPID0 0xe4 163 #define IE31200_CAPID0_PDCD BIT(4) 164 #define IE31200_CAPID0_DDPCD BIT(6) 165 #define IE31200_CAPID0_ECC BIT(1) 166 167 #define IE31200_MAD_DIMM_0_OFFSET 0x5004 168 #define IE31200_MAD_DIMM_0_OFFSET_SKL 0x500C 169 #define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0) 170 #define IE31200_MAD_DIMM_A_RANK BIT(17) 171 #define IE31200_MAD_DIMM_A_RANK_SHIFT 17 172 #define IE31200_MAD_DIMM_A_RANK_SKL BIT(10) 173 #define IE31200_MAD_DIMM_A_RANK_SKL_SHIFT 10 174 #define IE31200_MAD_DIMM_A_WIDTH BIT(19) 175 #define IE31200_MAD_DIMM_A_WIDTH_SHIFT 19 176 #define IE31200_MAD_DIMM_A_WIDTH_SKL GENMASK_ULL(9, 8) 177 #define IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT 8 178 179 /* Skylake reports 1GB increments, everything else is 256MB */ 180 #define IE31200_PAGES(n, skl) \ 181 (n << (28 + (2 * skl) - PAGE_SHIFT)) 182 183 static int nr_channels; 184 static struct pci_dev *mci_pdev; 185 static int ie31200_registered = 1; 186 187 struct ie31200_priv { 188 void __iomem *window; 189 void __iomem *c0errlog; 190 void __iomem *c1errlog; 191 }; 192 193 enum ie31200_chips { 194 IE31200 = 0, 195 }; 196 197 struct ie31200_dev_info { 198 const char *ctl_name; 199 }; 200 201 struct ie31200_error_info { 202 u16 errsts; 203 u16 errsts2; 204 u64 eccerrlog[IE31200_CHANNELS]; 205 }; 206 207 static const struct ie31200_dev_info ie31200_devs[] = { 208 [IE31200] = { 209 .ctl_name = "IE31200" 210 }, 211 }; 212 213 struct dimm_data { 214 u8 size; /* in multiples of 256MB, except Skylake is 1GB */ 215 u8 dual_rank : 1, 216 x16_width : 2; /* 0 means x8 width */ 217 }; 218 219 static int how_many_channels(struct pci_dev *pdev) 220 { 221 int n_channels; 222 unsigned char capid0_2b; /* 2nd byte of CAPID0 */ 223 224 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b); 225 226 /* check PDCD: Dual Channel Disable */ 227 if (capid0_2b & IE31200_CAPID0_PDCD) { 228 edac_dbg(0, "In single channel mode\n"); 229 n_channels = 1; 230 } else { 231 edac_dbg(0, "In dual channel mode\n"); 232 n_channels = 2; 233 } 234 235 /* check DDPCD - check if both channels are filled */ 236 if (capid0_2b & IE31200_CAPID0_DDPCD) 237 edac_dbg(0, "2 DIMMS per channel disabled\n"); 238 else 239 edac_dbg(0, "2 DIMMS per channel enabled\n"); 240 241 return n_channels; 242 } 243 244 static bool ecc_capable(struct pci_dev *pdev) 245 { 246 unsigned char capid0_4b; /* 4th byte of CAPID0 */ 247 248 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b); 249 if (capid0_4b & IE31200_CAPID0_ECC) 250 return false; 251 return true; 252 } 253 254 static int eccerrlog_row(u64 log) 255 { 256 return ((log & IE31200_ECCERRLOG_RANK_BITS) >> 257 IE31200_ECCERRLOG_RANK_SHIFT); 258 } 259 260 static void ie31200_clear_error_info(struct mem_ctl_info *mci) 261 { 262 /* 263 * Clear any error bits. 264 * (Yes, we really clear bits by writing 1 to them.) 265 */ 266 pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS, 267 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); 268 } 269 270 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, 271 struct ie31200_error_info *info) 272 { 273 struct pci_dev *pdev; 274 struct ie31200_priv *priv = mci->pvt_info; 275 276 pdev = to_pci_dev(mci->pdev); 277 278 /* 279 * This is a mess because there is no atomic way to read all the 280 * registers at once and the registers can transition from CE being 281 * overwritten by UE. 282 */ 283 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts); 284 if (!(info->errsts & IE31200_ERRSTS_BITS)) 285 return; 286 287 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 288 if (nr_channels == 2) 289 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 290 291 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2); 292 293 /* 294 * If the error is the same for both reads then the first set 295 * of reads is valid. If there is a change then there is a CE 296 * with no info and the second set of reads is valid and 297 * should be UE info. 298 */ 299 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 300 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 301 if (nr_channels == 2) 302 info->eccerrlog[1] = 303 lo_hi_readq(priv->c1errlog); 304 } 305 306 ie31200_clear_error_info(mci); 307 } 308 309 static void ie31200_process_error_info(struct mem_ctl_info *mci, 310 struct ie31200_error_info *info) 311 { 312 int channel; 313 u64 log; 314 315 if (!(info->errsts & IE31200_ERRSTS_BITS)) 316 return; 317 318 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 319 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 320 -1, -1, -1, "UE overwrote CE", ""); 321 info->errsts = info->errsts2; 322 } 323 324 for (channel = 0; channel < nr_channels; channel++) { 325 log = info->eccerrlog[channel]; 326 if (log & IE31200_ECCERRLOG_UE) { 327 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 328 0, 0, 0, 329 eccerrlog_row(log), 330 channel, -1, 331 "ie31200 UE", ""); 332 } else if (log & IE31200_ECCERRLOG_CE) { 333 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 334 0, 0, 335 IE31200_ECCERRLOG_SYNDROME(log), 336 eccerrlog_row(log), 337 channel, -1, 338 "ie31200 CE", ""); 339 } 340 } 341 } 342 343 static void ie31200_check(struct mem_ctl_info *mci) 344 { 345 struct ie31200_error_info info; 346 347 ie31200_get_and_clear_error_info(mci, &info); 348 ie31200_process_error_info(mci, &info); 349 } 350 351 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev) 352 { 353 union { 354 u64 mchbar; 355 struct { 356 u32 mchbar_low; 357 u32 mchbar_high; 358 }; 359 } u; 360 void __iomem *window; 361 362 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low); 363 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high); 364 u.mchbar &= IE31200_MCHBAR_MASK; 365 366 if (u.mchbar != (resource_size_t)u.mchbar) { 367 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n", 368 (unsigned long long)u.mchbar); 369 return NULL; 370 } 371 372 window = ioremap(u.mchbar, IE31200_MMR_WINDOW_SIZE); 373 if (!window) 374 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n", 375 (unsigned long long)u.mchbar); 376 377 return window; 378 } 379 380 static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode, 381 int chan) 382 { 383 dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE; 384 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0; 385 dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >> 386 (IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4))); 387 } 388 389 static void __populate_dimm_info(struct dimm_data *dd, u32 addr_decode, 390 int chan) 391 { 392 dd->size = (addr_decode >> (chan << 3)) & IE31200_MAD_DIMM_SIZE; 393 dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK << chan)) ? 1 : 0; 394 dd->x16_width = (addr_decode & (IE31200_MAD_DIMM_A_WIDTH << chan)) ? 1 : 0; 395 } 396 397 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int chan, 398 bool skl) 399 { 400 if (skl) 401 __skl_populate_dimm_info(dd, addr_decode, chan); 402 else 403 __populate_dimm_info(dd, addr_decode, chan); 404 } 405 406 407 static int ie31200_probe1(struct pci_dev *pdev, int dev_idx) 408 { 409 int i, j, ret; 410 struct mem_ctl_info *mci = NULL; 411 struct edac_mc_layer layers[2]; 412 struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL]; 413 void __iomem *window; 414 struct ie31200_priv *priv; 415 u32 addr_decode, mad_offset; 416 417 /* 418 * Kaby Lake, Coffee Lake seem to work like Skylake. Please re-visit 419 * this logic when adding new CPU support. 420 */ 421 bool skl = DEVICE_ID_SKYLAKE_OR_LATER(pdev->device); 422 423 edac_dbg(0, "MC:\n"); 424 425 if (!ecc_capable(pdev)) { 426 ie31200_printk(KERN_INFO, "No ECC support\n"); 427 return -ENODEV; 428 } 429 430 nr_channels = how_many_channels(pdev); 431 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 432 layers[0].size = IE31200_DIMMS; 433 layers[0].is_virt_csrow = true; 434 layers[1].type = EDAC_MC_LAYER_CHANNEL; 435 layers[1].size = nr_channels; 436 layers[1].is_virt_csrow = false; 437 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 438 sizeof(struct ie31200_priv)); 439 if (!mci) 440 return -ENOMEM; 441 442 window = ie31200_map_mchbar(pdev); 443 if (!window) { 444 ret = -ENODEV; 445 goto fail_free; 446 } 447 448 edac_dbg(3, "MC: init mci\n"); 449 mci->pdev = &pdev->dev; 450 if (skl) 451 mci->mtype_cap = MEM_FLAG_DDR4; 452 else 453 mci->mtype_cap = MEM_FLAG_DDR3; 454 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 455 mci->edac_cap = EDAC_FLAG_SECDED; 456 mci->mod_name = EDAC_MOD_STR; 457 mci->ctl_name = ie31200_devs[dev_idx].ctl_name; 458 mci->dev_name = pci_name(pdev); 459 mci->edac_check = ie31200_check; 460 mci->ctl_page_to_phys = NULL; 461 priv = mci->pvt_info; 462 priv->window = window; 463 if (skl) { 464 priv->c0errlog = window + IE31200_C0ECCERRLOG_SKL; 465 priv->c1errlog = window + IE31200_C1ECCERRLOG_SKL; 466 mad_offset = IE31200_MAD_DIMM_0_OFFSET_SKL; 467 } else { 468 priv->c0errlog = window + IE31200_C0ECCERRLOG; 469 priv->c1errlog = window + IE31200_C1ECCERRLOG; 470 mad_offset = IE31200_MAD_DIMM_0_OFFSET; 471 } 472 473 /* populate DIMM info */ 474 for (i = 0; i < IE31200_CHANNELS; i++) { 475 addr_decode = readl(window + mad_offset + 476 (i * 4)); 477 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode); 478 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { 479 populate_dimm_info(&dimm_info[i][j], addr_decode, j, 480 skl); 481 edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n", 482 dimm_info[i][j].size, 483 dimm_info[i][j].dual_rank, 484 dimm_info[i][j].x16_width); 485 } 486 } 487 488 /* 489 * The dram rank boundary (DRB) reg values are boundary addresses 490 * for each DRAM rank with a granularity of 64MB. DRB regs are 491 * cumulative; the last one will contain the total memory 492 * contained in all ranks. 493 */ 494 for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) { 495 for (j = 0; j < IE31200_CHANNELS; j++) { 496 struct dimm_info *dimm; 497 unsigned long nr_pages; 498 499 nr_pages = IE31200_PAGES(dimm_info[j][i].size, skl); 500 if (nr_pages == 0) 501 continue; 502 503 if (dimm_info[j][i].dual_rank) { 504 nr_pages = nr_pages / 2; 505 dimm = edac_get_dimm(mci, (i * 2) + 1, j, 0); 506 dimm->nr_pages = nr_pages; 507 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 508 dimm->grain = 8; /* just a guess */ 509 if (skl) 510 dimm->mtype = MEM_DDR4; 511 else 512 dimm->mtype = MEM_DDR3; 513 dimm->dtype = DEV_UNKNOWN; 514 dimm->edac_mode = EDAC_UNKNOWN; 515 } 516 dimm = edac_get_dimm(mci, i * 2, j, 0); 517 dimm->nr_pages = nr_pages; 518 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 519 dimm->grain = 8; /* same guess */ 520 if (skl) 521 dimm->mtype = MEM_DDR4; 522 else 523 dimm->mtype = MEM_DDR3; 524 dimm->dtype = DEV_UNKNOWN; 525 dimm->edac_mode = EDAC_UNKNOWN; 526 } 527 } 528 529 ie31200_clear_error_info(mci); 530 531 if (edac_mc_add_mc(mci)) { 532 edac_dbg(3, "MC: failed edac_mc_add_mc()\n"); 533 ret = -ENODEV; 534 goto fail_unmap; 535 } 536 537 /* get this far and it's successful */ 538 edac_dbg(3, "MC: success\n"); 539 return 0; 540 541 fail_unmap: 542 iounmap(window); 543 544 fail_free: 545 edac_mc_free(mci); 546 547 return ret; 548 } 549 550 static int ie31200_init_one(struct pci_dev *pdev, 551 const struct pci_device_id *ent) 552 { 553 int rc; 554 555 edac_dbg(0, "MC:\n"); 556 if (pci_enable_device(pdev) < 0) 557 return -EIO; 558 rc = ie31200_probe1(pdev, ent->driver_data); 559 if (rc == 0 && !mci_pdev) 560 mci_pdev = pci_dev_get(pdev); 561 562 return rc; 563 } 564 565 static void ie31200_remove_one(struct pci_dev *pdev) 566 { 567 struct mem_ctl_info *mci; 568 struct ie31200_priv *priv; 569 570 edac_dbg(0, "\n"); 571 pci_dev_put(mci_pdev); 572 mci_pdev = NULL; 573 mci = edac_mc_del_mc(&pdev->dev); 574 if (!mci) 575 return; 576 priv = mci->pvt_info; 577 iounmap(priv->window); 578 edac_mc_free(mci); 579 } 580 581 static const struct pci_device_id ie31200_pci_tbl[] = { 582 { PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 583 { PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 584 { PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 585 { PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 586 { PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 587 { PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 588 { PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 589 { PCI_VEND_DEV(INTEL, IE31200_HB_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 590 { PCI_VEND_DEV(INTEL, IE31200_HB_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 591 { PCI_VEND_DEV(INTEL, IE31200_HB_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 592 { PCI_VEND_DEV(INTEL, IE31200_HB_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 593 { PCI_VEND_DEV(INTEL, IE31200_HB_12), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 594 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 595 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 596 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 597 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 598 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 599 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 600 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 601 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 602 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 603 { PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 }, 604 { 0, } /* 0 terminated list. */ 605 }; 606 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); 607 608 static struct pci_driver ie31200_driver = { 609 .name = EDAC_MOD_STR, 610 .probe = ie31200_init_one, 611 .remove = ie31200_remove_one, 612 .id_table = ie31200_pci_tbl, 613 }; 614 615 static int __init ie31200_init(void) 616 { 617 int pci_rc, i; 618 619 edac_dbg(3, "MC:\n"); 620 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 621 opstate_init(); 622 623 pci_rc = pci_register_driver(&ie31200_driver); 624 if (pci_rc < 0) 625 goto fail0; 626 627 if (!mci_pdev) { 628 ie31200_registered = 0; 629 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) { 630 mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor, 631 ie31200_pci_tbl[i].device, 632 NULL); 633 if (mci_pdev) 634 break; 635 } 636 if (!mci_pdev) { 637 edac_dbg(0, "ie31200 pci_get_device fail\n"); 638 pci_rc = -ENODEV; 639 goto fail1; 640 } 641 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]); 642 if (pci_rc < 0) { 643 edac_dbg(0, "ie31200 init fail\n"); 644 pci_rc = -ENODEV; 645 goto fail1; 646 } 647 } 648 return 0; 649 650 fail1: 651 pci_unregister_driver(&ie31200_driver); 652 fail0: 653 pci_dev_put(mci_pdev); 654 655 return pci_rc; 656 } 657 658 static void __exit ie31200_exit(void) 659 { 660 edac_dbg(3, "MC:\n"); 661 pci_unregister_driver(&ie31200_driver); 662 if (!ie31200_registered) 663 ie31200_remove_one(mci_pdev); 664 } 665 666 module_init(ie31200_init); 667 module_exit(ie31200_exit); 668 669 MODULE_LICENSE("GPL"); 670 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>"); 671 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers"); 672