1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel E3-1200 4 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> 5 * 6 * Support for the E3-1200 processor family. Heavily based on previous 7 * Intel EDAC drivers. 8 * 9 * Since the DRAM controller is on the cpu chip, we can use its PCI device 10 * id to identify these processors. 11 * 12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/) 13 * 14 * 0108: Xeon E3-1200 Processor Family DRAM Controller 15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller 16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller 18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller 20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller 21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers 22 * 590f: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 23 * 5918: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 24 * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers 25 * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers 26 * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers 27 * 28 * Based on Intel specification: 29 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf 30 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html 31 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf 32 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf 33 * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html 34 * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html 35 * 36 * According to the above datasheet (p.16): 37 * " 38 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with 39 * requests that cross a DW boundary. 40 * " 41 * 42 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into 43 * 2 readl() calls. This restriction may be lifted in subsequent chip releases, 44 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. 45 */ 46 47 #include <linux/module.h> 48 #include <linux/init.h> 49 #include <linux/pci.h> 50 #include <linux/pci_ids.h> 51 #include <linux/edac.h> 52 53 #include <linux/io-64-nonatomic-lo-hi.h> 54 #include <asm/mce.h> 55 #include "edac_module.h" 56 57 #define EDAC_MOD_STR "ie31200_edac" 58 59 #define ie31200_printk(level, fmt, arg...) \ 60 edac_printk(level, "ie31200", fmt, ##arg) 61 62 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c 64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c 67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F 70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918 71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F 72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x590f 73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_12 0x5918 74 75 /* Coffee Lake-S */ 76 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00 77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f 78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18 79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f 80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30 81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31 82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32 83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33 84 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2 85 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6 86 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca 87 88 /* Raptor Lake-S */ 89 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1 0xa703 90 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2 0x4640 91 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3 0x4630 92 93 #define IE31200_RANKS_PER_CHANNEL 8 94 #define IE31200_DIMMS_PER_CHANNEL 2 95 #define IE31200_CHANNELS 2 96 #define IE31200_IMC_NUM 2 97 98 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ 99 #define IE31200_MCHBAR_LOW 0x48 100 #define IE31200_MCHBAR_HIGH 0x4c 101 102 /* 103 * Error Status Register (16b) 104 * 105 * 1 Multi-bit DRAM ECC Error Flag (DMERR) 106 * 0 Single-bit DRAM ECC Error Flag (DSERR) 107 */ 108 #define IE31200_ERRSTS 0xc8 109 #define IE31200_ERRSTS_UE BIT(1) 110 #define IE31200_ERRSTS_CE BIT(0) 111 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) 112 113 #define IE31200_CAPID0 0xe4 114 #define IE31200_CAPID0_PDCD BIT(4) 115 #define IE31200_CAPID0_DDPCD BIT(6) 116 #define IE31200_CAPID0_ECC BIT(1) 117 118 /* Non-constant mask variant of FIELD_GET() */ 119 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 120 121 static int nr_channels; 122 static struct pci_dev *mci_pdev; 123 static int ie31200_registered = 1; 124 125 struct res_config { 126 enum mem_type mtype; 127 bool cmci; 128 int imc_num; 129 /* Host MMIO configuration register */ 130 u64 reg_mchbar_mask; 131 u64 reg_mchbar_window_size; 132 /* ECC error log register */ 133 u64 reg_eccerrlog_offset[IE31200_CHANNELS]; 134 u64 reg_eccerrlog_ce_mask; 135 u64 reg_eccerrlog_ce_ovfl_mask; 136 u64 reg_eccerrlog_ue_mask; 137 u64 reg_eccerrlog_ue_ovfl_mask; 138 u64 reg_eccerrlog_rank_mask; 139 u64 reg_eccerrlog_syndrome_mask; 140 /* MSR to clear ECC error log register */ 141 u32 msr_clear_eccerrlog_offset; 142 /* DIMM characteristics register */ 143 u64 reg_mad_dimm_size_granularity; 144 u64 reg_mad_dimm_offset[IE31200_CHANNELS]; 145 u32 reg_mad_dimm_size_mask[IE31200_DIMMS_PER_CHANNEL]; 146 u32 reg_mad_dimm_rank_mask[IE31200_DIMMS_PER_CHANNEL]; 147 u32 reg_mad_dimm_width_mask[IE31200_DIMMS_PER_CHANNEL]; 148 }; 149 150 struct ie31200_priv { 151 void __iomem *window; 152 void __iomem *c0errlog; 153 void __iomem *c1errlog; 154 struct res_config *cfg; 155 struct mem_ctl_info *mci; 156 struct pci_dev *pdev; 157 struct device dev; 158 }; 159 160 static struct ie31200_pvt { 161 struct ie31200_priv *priv[IE31200_IMC_NUM]; 162 } ie31200_pvt; 163 164 enum ie31200_chips { 165 IE31200 = 0, 166 IE31200_1 = 1, 167 }; 168 169 struct ie31200_dev_info { 170 const char *ctl_name; 171 }; 172 173 struct ie31200_error_info { 174 u16 errsts; 175 u16 errsts2; 176 u64 eccerrlog[IE31200_CHANNELS]; 177 u64 erraddr; 178 }; 179 180 static const struct ie31200_dev_info ie31200_devs[] = { 181 [IE31200] = { 182 .ctl_name = "IE31200" 183 }, 184 [IE31200_1] = { 185 .ctl_name = "IE31200_1" 186 }, 187 }; 188 189 struct dimm_data { 190 u64 size; /* in bytes */ 191 u8 ranks; 192 enum dev_type dtype; 193 }; 194 195 static int how_many_channels(struct pci_dev *pdev) 196 { 197 int n_channels; 198 unsigned char capid0_2b; /* 2nd byte of CAPID0 */ 199 200 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b); 201 202 /* check PDCD: Dual Channel Disable */ 203 if (capid0_2b & IE31200_CAPID0_PDCD) { 204 edac_dbg(0, "In single channel mode\n"); 205 n_channels = 1; 206 } else { 207 edac_dbg(0, "In dual channel mode\n"); 208 n_channels = 2; 209 } 210 211 /* check DDPCD - check if both channels are filled */ 212 if (capid0_2b & IE31200_CAPID0_DDPCD) 213 edac_dbg(0, "2 DIMMS per channel disabled\n"); 214 else 215 edac_dbg(0, "2 DIMMS per channel enabled\n"); 216 217 return n_channels; 218 } 219 220 static bool ecc_capable(struct pci_dev *pdev) 221 { 222 unsigned char capid0_4b; /* 4th byte of CAPID0 */ 223 224 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b); 225 if (capid0_4b & IE31200_CAPID0_ECC) 226 return false; 227 return true; 228 } 229 230 #define mci_to_pci_dev(mci) (((struct ie31200_priv *)(mci)->pvt_info)->pdev) 231 232 static void ie31200_clear_error_info(struct mem_ctl_info *mci) 233 { 234 struct ie31200_priv *priv = mci->pvt_info; 235 struct res_config *cfg = priv->cfg; 236 237 /* 238 * The PCI ERRSTS register is deprecated. Write the MSR to clear 239 * the ECC error log registers in all memory controllers. 240 */ 241 if (cfg->msr_clear_eccerrlog_offset) { 242 if (wrmsr_safe(cfg->msr_clear_eccerrlog_offset, 243 cfg->reg_eccerrlog_ce_mask | 244 cfg->reg_eccerrlog_ce_ovfl_mask | 245 cfg->reg_eccerrlog_ue_mask | 246 cfg->reg_eccerrlog_ue_ovfl_mask, 0) < 0) 247 ie31200_printk(KERN_ERR, "Failed to wrmsr.\n"); 248 249 return; 250 } 251 252 /* 253 * Clear any error bits. 254 * (Yes, we really clear bits by writing 1 to them.) 255 */ 256 pci_write_bits16(mci_to_pci_dev(mci), IE31200_ERRSTS, 257 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); 258 } 259 260 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, 261 struct ie31200_error_info *info) 262 { 263 struct pci_dev *pdev = mci_to_pci_dev(mci); 264 struct ie31200_priv *priv = mci->pvt_info; 265 266 /* 267 * The PCI ERRSTS register is deprecated, directly read the 268 * MMIO-mapped ECC error log registers. 269 */ 270 if (priv->cfg->msr_clear_eccerrlog_offset) { 271 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 272 if (nr_channels == 2) 273 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 274 275 ie31200_clear_error_info(mci); 276 return; 277 } 278 279 /* 280 * This is a mess because there is no atomic way to read all the 281 * registers at once and the registers can transition from CE being 282 * overwritten by UE. 283 */ 284 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts); 285 if (!(info->errsts & IE31200_ERRSTS_BITS)) 286 return; 287 288 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 289 if (nr_channels == 2) 290 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 291 292 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2); 293 294 /* 295 * If the error is the same for both reads then the first set 296 * of reads is valid. If there is a change then there is a CE 297 * with no info and the second set of reads is valid and 298 * should be UE info. 299 */ 300 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 301 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 302 if (nr_channels == 2) 303 info->eccerrlog[1] = 304 lo_hi_readq(priv->c1errlog); 305 } 306 307 ie31200_clear_error_info(mci); 308 } 309 310 static void ie31200_process_error_info(struct mem_ctl_info *mci, 311 struct ie31200_error_info *info) 312 { 313 struct ie31200_priv *priv = mci->pvt_info; 314 struct res_config *cfg = priv->cfg; 315 int channel; 316 u64 log; 317 318 if (!cfg->msr_clear_eccerrlog_offset) { 319 if (!(info->errsts & IE31200_ERRSTS_BITS)) 320 return; 321 322 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 323 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 324 -1, -1, -1, "UE overwrote CE", ""); 325 info->errsts = info->errsts2; 326 } 327 } 328 329 for (channel = 0; channel < nr_channels; channel++) { 330 log = info->eccerrlog[channel]; 331 if (log & cfg->reg_eccerrlog_ue_mask) { 332 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 333 info->erraddr >> PAGE_SHIFT, 0, 0, 334 field_get(cfg->reg_eccerrlog_rank_mask, log), 335 channel, -1, 336 "ie31200 UE", ""); 337 } else if (log & cfg->reg_eccerrlog_ce_mask) { 338 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 339 info->erraddr >> PAGE_SHIFT, 0, 340 field_get(cfg->reg_eccerrlog_syndrome_mask, log), 341 field_get(cfg->reg_eccerrlog_rank_mask, log), 342 channel, -1, 343 "ie31200 CE", ""); 344 } 345 } 346 } 347 348 static void __ie31200_check(struct mem_ctl_info *mci, struct mce *mce) 349 { 350 struct ie31200_error_info info; 351 352 info.erraddr = mce ? mce->addr : 0; 353 ie31200_get_and_clear_error_info(mci, &info); 354 ie31200_process_error_info(mci, &info); 355 } 356 357 static void ie31200_check(struct mem_ctl_info *mci) 358 { 359 __ie31200_check(mci, NULL); 360 } 361 362 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev, struct res_config *cfg, int mc) 363 { 364 union { 365 u64 mchbar; 366 struct { 367 u32 mchbar_low; 368 u32 mchbar_high; 369 }; 370 } u; 371 void __iomem *window; 372 373 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low); 374 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high); 375 u.mchbar &= cfg->reg_mchbar_mask; 376 u.mchbar += cfg->reg_mchbar_window_size * mc; 377 378 if (u.mchbar != (resource_size_t)u.mchbar) { 379 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n", 380 (unsigned long long)u.mchbar); 381 return NULL; 382 } 383 384 window = ioremap(u.mchbar, cfg->reg_mchbar_window_size); 385 if (!window) 386 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n", 387 (unsigned long long)u.mchbar); 388 389 return window; 390 } 391 392 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int dimm, 393 struct res_config *cfg) 394 { 395 dd->size = field_get(cfg->reg_mad_dimm_size_mask[dimm], addr_decode) * cfg->reg_mad_dimm_size_granularity; 396 dd->ranks = field_get(cfg->reg_mad_dimm_rank_mask[dimm], addr_decode) + 1; 397 dd->dtype = field_get(cfg->reg_mad_dimm_width_mask[dimm], addr_decode) + DEV_X8; 398 } 399 400 static void ie31200_get_dimm_config(struct mem_ctl_info *mci, void __iomem *window, 401 struct res_config *cfg, int mc) 402 { 403 struct dimm_data dimm_info; 404 struct dimm_info *dimm; 405 unsigned long nr_pages; 406 u32 addr_decode; 407 int i, j, k; 408 409 for (i = 0; i < IE31200_CHANNELS; i++) { 410 addr_decode = readl(window + cfg->reg_mad_dimm_offset[i]); 411 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode); 412 413 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { 414 populate_dimm_info(&dimm_info, addr_decode, j, cfg); 415 edac_dbg(0, "mc: %d, channel: %d, dimm: %d, size: %lld MiB, ranks: %d, DRAM chip type: %d\n", 416 mc, i, j, dimm_info.size >> 20, 417 dimm_info.ranks, 418 dimm_info.dtype); 419 420 nr_pages = MiB_TO_PAGES(dimm_info.size >> 20); 421 if (nr_pages == 0) 422 continue; 423 424 nr_pages = nr_pages / dimm_info.ranks; 425 for (k = 0; k < dimm_info.ranks; k++) { 426 dimm = edac_get_dimm(mci, (j * dimm_info.ranks) + k, i, 0); 427 dimm->nr_pages = nr_pages; 428 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 429 dimm->grain = 8; /* just a guess */ 430 dimm->mtype = cfg->mtype; 431 dimm->dtype = dimm_info.dtype; 432 dimm->edac_mode = EDAC_UNKNOWN; 433 } 434 } 435 } 436 } 437 438 static int ie31200_register_mci(struct pci_dev *pdev, struct res_config *cfg, int mc) 439 { 440 struct edac_mc_layer layers[2]; 441 struct ie31200_priv *priv; 442 struct mem_ctl_info *mci; 443 void __iomem *window; 444 int ret; 445 446 nr_channels = how_many_channels(pdev); 447 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 448 layers[0].size = IE31200_RANKS_PER_CHANNEL; 449 layers[0].is_virt_csrow = true; 450 layers[1].type = EDAC_MC_LAYER_CHANNEL; 451 layers[1].size = nr_channels; 452 layers[1].is_virt_csrow = false; 453 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 454 sizeof(struct ie31200_priv)); 455 if (!mci) 456 return -ENOMEM; 457 458 window = ie31200_map_mchbar(pdev, cfg, mc); 459 if (!window) { 460 ret = -ENODEV; 461 goto fail_free; 462 } 463 464 edac_dbg(3, "MC: init mci\n"); 465 mci->mtype_cap = BIT(cfg->mtype); 466 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 467 mci->edac_cap = EDAC_FLAG_SECDED; 468 mci->mod_name = EDAC_MOD_STR; 469 mci->ctl_name = ie31200_devs[mc].ctl_name; 470 mci->dev_name = pci_name(pdev); 471 mci->edac_check = cfg->cmci ? NULL : ie31200_check; 472 mci->ctl_page_to_phys = NULL; 473 priv = mci->pvt_info; 474 priv->window = window; 475 priv->c0errlog = window + cfg->reg_eccerrlog_offset[0]; 476 priv->c1errlog = window + cfg->reg_eccerrlog_offset[1]; 477 priv->cfg = cfg; 478 priv->mci = mci; 479 priv->pdev = pdev; 480 device_initialize(&priv->dev); 481 /* 482 * The EDAC core uses mci->pdev (pointer to the structure device) 483 * as the memory controller ID. The SoCs attach one or more memory 484 * controllers to a single pci_dev (a single pci_dev->dev can 485 * correspond to multiple memory controllers). 486 * 487 * To make mci->pdev unique, assign pci_dev->dev to mci->pdev 488 * for the first memory controller and assign a unique priv->dev 489 * to mci->pdev for each additional memory controller. 490 */ 491 mci->pdev = mc ? &priv->dev : &pdev->dev; 492 493 ie31200_get_dimm_config(mci, window, cfg, mc); 494 ie31200_clear_error_info(mci); 495 496 if (edac_mc_add_mc(mci)) { 497 edac_dbg(3, "MC: failed edac_mc_add_mc()\n"); 498 ret = -ENODEV; 499 goto fail_unmap; 500 } 501 502 ie31200_pvt.priv[mc] = priv; 503 return 0; 504 fail_unmap: 505 iounmap(window); 506 fail_free: 507 edac_mc_free(mci); 508 return ret; 509 } 510 511 static void mce_check(struct mce *mce) 512 { 513 struct ie31200_priv *priv; 514 int i; 515 516 for (i = 0; i < IE31200_IMC_NUM; i++) { 517 priv = ie31200_pvt.priv[i]; 518 if (!priv) 519 continue; 520 521 __ie31200_check(priv->mci, mce); 522 } 523 } 524 525 static int mce_handler(struct notifier_block *nb, unsigned long val, void *data) 526 { 527 struct mce *mce = (struct mce *)data; 528 char *type; 529 530 if (mce->kflags & MCE_HANDLED_CEC) 531 return NOTIFY_DONE; 532 533 /* 534 * Ignore unless this is a memory related error. 535 * Don't check MCI_STATUS_ADDRV since it's not set on some CPUs. 536 */ 537 if ((mce->status & 0xefff) >> 7 != 1) 538 return NOTIFY_DONE; 539 540 type = mce->mcgstatus & MCG_STATUS_MCIP ? "Exception" : "Event"; 541 542 edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n", 543 mce->extcpu, type, mce->mcgstatus, 544 mce->bank, mce->status); 545 edac_dbg(0, "TSC 0x%llx\n", mce->tsc); 546 edac_dbg(0, "ADDR 0x%llx\n", mce->addr); 547 edac_dbg(0, "MISC 0x%llx\n", mce->misc); 548 edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n", 549 mce->cpuvendor, mce->cpuid, mce->time, 550 mce->socketid, mce->apicid); 551 552 mce_check(mce); 553 mce->kflags |= MCE_HANDLED_EDAC; 554 555 return NOTIFY_DONE; 556 } 557 558 static struct notifier_block ie31200_mce_dec = { 559 .notifier_call = mce_handler, 560 .priority = MCE_PRIO_EDAC, 561 }; 562 563 static void ie31200_unregister_mcis(void) 564 { 565 struct ie31200_priv *priv; 566 struct mem_ctl_info *mci; 567 int i; 568 569 for (i = 0; i < IE31200_IMC_NUM; i++) { 570 priv = ie31200_pvt.priv[i]; 571 if (!priv) 572 continue; 573 574 mci = priv->mci; 575 edac_mc_del_mc(mci->pdev); 576 iounmap(priv->window); 577 edac_mc_free(mci); 578 } 579 } 580 581 static int ie31200_probe1(struct pci_dev *pdev, struct res_config *cfg) 582 { 583 int i, ret; 584 585 edac_dbg(0, "MC:\n"); 586 587 if (!ecc_capable(pdev)) { 588 ie31200_printk(KERN_INFO, "No ECC support\n"); 589 return -ENODEV; 590 } 591 592 for (i = 0; i < cfg->imc_num; i++) { 593 ret = ie31200_register_mci(pdev, cfg, i); 594 if (ret) 595 goto fail_register; 596 } 597 598 if (cfg->cmci) { 599 mce_register_decode_chain(&ie31200_mce_dec); 600 edac_op_state = EDAC_OPSTATE_INT; 601 } else { 602 edac_op_state = EDAC_OPSTATE_POLL; 603 } 604 605 /* get this far and it's successful. */ 606 edac_dbg(3, "MC: success\n"); 607 return 0; 608 609 fail_register: 610 ie31200_unregister_mcis(); 611 return ret; 612 } 613 614 static int ie31200_init_one(struct pci_dev *pdev, 615 const struct pci_device_id *ent) 616 { 617 int rc; 618 619 edac_dbg(0, "MC:\n"); 620 if (pci_enable_device(pdev) < 0) 621 return -EIO; 622 rc = ie31200_probe1(pdev, (struct res_config *)ent->driver_data); 623 if (rc == 0 && !mci_pdev) 624 mci_pdev = pci_dev_get(pdev); 625 626 return rc; 627 } 628 629 static void ie31200_remove_one(struct pci_dev *pdev) 630 { 631 struct ie31200_priv *priv = ie31200_pvt.priv[0]; 632 633 edac_dbg(0, "\n"); 634 pci_dev_put(mci_pdev); 635 mci_pdev = NULL; 636 if (priv->cfg->cmci) 637 mce_unregister_decode_chain(&ie31200_mce_dec); 638 ie31200_unregister_mcis(); 639 } 640 641 static struct res_config snb_cfg = { 642 .mtype = MEM_DDR3, 643 .imc_num = 1, 644 .reg_mchbar_mask = GENMASK_ULL(38, 15), 645 .reg_mchbar_window_size = BIT_ULL(15), 646 .reg_eccerrlog_offset[0] = 0x40c8, 647 .reg_eccerrlog_offset[1] = 0x44c8, 648 .reg_eccerrlog_ce_mask = BIT_ULL(0), 649 .reg_eccerrlog_ue_mask = BIT_ULL(1), 650 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 651 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 652 .reg_mad_dimm_size_granularity = BIT_ULL(28), 653 .reg_mad_dimm_offset[0] = 0x5004, 654 .reg_mad_dimm_offset[1] = 0x5008, 655 .reg_mad_dimm_size_mask[0] = GENMASK(7, 0), 656 .reg_mad_dimm_size_mask[1] = GENMASK(15, 8), 657 .reg_mad_dimm_rank_mask[0] = BIT(17), 658 .reg_mad_dimm_rank_mask[1] = BIT(18), 659 .reg_mad_dimm_width_mask[0] = BIT(19), 660 .reg_mad_dimm_width_mask[1] = BIT(20), 661 }; 662 663 static struct res_config skl_cfg = { 664 .mtype = MEM_DDR4, 665 .imc_num = 1, 666 .reg_mchbar_mask = GENMASK_ULL(38, 15), 667 .reg_mchbar_window_size = BIT_ULL(15), 668 .reg_eccerrlog_offset[0] = 0x4048, 669 .reg_eccerrlog_offset[1] = 0x4448, 670 .reg_eccerrlog_ce_mask = BIT_ULL(0), 671 .reg_eccerrlog_ue_mask = BIT_ULL(1), 672 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 673 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 674 .reg_mad_dimm_size_granularity = BIT_ULL(30), 675 .reg_mad_dimm_offset[0] = 0x500c, 676 .reg_mad_dimm_offset[1] = 0x5010, 677 .reg_mad_dimm_size_mask[0] = GENMASK(5, 0), 678 .reg_mad_dimm_size_mask[1] = GENMASK(21, 16), 679 .reg_mad_dimm_rank_mask[0] = BIT(10), 680 .reg_mad_dimm_rank_mask[1] = BIT(26), 681 .reg_mad_dimm_width_mask[0] = GENMASK(9, 8), 682 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24), 683 }; 684 685 struct res_config rpl_s_cfg = { 686 .mtype = MEM_DDR5, 687 .cmci = true, 688 .imc_num = 2, 689 .reg_mchbar_mask = GENMASK_ULL(41, 17), 690 .reg_mchbar_window_size = BIT_ULL(16), 691 .reg_eccerrlog_offset[0] = 0xe048, 692 .reg_eccerrlog_offset[1] = 0xe848, 693 .reg_eccerrlog_ce_mask = BIT_ULL(0), 694 .reg_eccerrlog_ce_ovfl_mask = BIT_ULL(1), 695 .reg_eccerrlog_ue_mask = BIT_ULL(2), 696 .reg_eccerrlog_ue_ovfl_mask = BIT_ULL(3), 697 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 698 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 699 .msr_clear_eccerrlog_offset = 0x791, 700 .reg_mad_dimm_offset[0] = 0xd80c, 701 .reg_mad_dimm_offset[1] = 0xd810, 702 .reg_mad_dimm_size_granularity = BIT_ULL(29), 703 .reg_mad_dimm_size_mask[0] = GENMASK(6, 0), 704 .reg_mad_dimm_size_mask[1] = GENMASK(22, 16), 705 .reg_mad_dimm_rank_mask[0] = GENMASK(10, 9), 706 .reg_mad_dimm_rank_mask[1] = GENMASK(27, 26), 707 .reg_mad_dimm_width_mask[0] = GENMASK(8, 7), 708 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24), 709 }; 710 711 static const struct pci_device_id ie31200_pci_tbl[] = { 712 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_1), (kernel_ulong_t)&snb_cfg }, 713 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_2), (kernel_ulong_t)&snb_cfg }, 714 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_3), (kernel_ulong_t)&snb_cfg }, 715 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_4), (kernel_ulong_t)&snb_cfg }, 716 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_5), (kernel_ulong_t)&snb_cfg }, 717 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_6), (kernel_ulong_t)&snb_cfg }, 718 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_7), (kernel_ulong_t)&snb_cfg }, 719 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_8), (kernel_ulong_t)&skl_cfg }, 720 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_9), (kernel_ulong_t)&skl_cfg }, 721 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_10), (kernel_ulong_t)&skl_cfg }, 722 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_11), (kernel_ulong_t)&skl_cfg }, 723 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_12), (kernel_ulong_t)&skl_cfg }, 724 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1), (kernel_ulong_t)&skl_cfg }, 725 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2), (kernel_ulong_t)&skl_cfg }, 726 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3), (kernel_ulong_t)&skl_cfg }, 727 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4), (kernel_ulong_t)&skl_cfg }, 728 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5), (kernel_ulong_t)&skl_cfg }, 729 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6), (kernel_ulong_t)&skl_cfg }, 730 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7), (kernel_ulong_t)&skl_cfg }, 731 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8), (kernel_ulong_t)&skl_cfg }, 732 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9), (kernel_ulong_t)&skl_cfg }, 733 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10), (kernel_ulong_t)&skl_cfg }, 734 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1), (kernel_ulong_t)&rpl_s_cfg}, 735 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2), (kernel_ulong_t)&rpl_s_cfg}, 736 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3), (kernel_ulong_t)&rpl_s_cfg}, 737 { 0, } /* 0 terminated list. */ 738 }; 739 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); 740 741 static struct pci_driver ie31200_driver = { 742 .name = EDAC_MOD_STR, 743 .probe = ie31200_init_one, 744 .remove = ie31200_remove_one, 745 .id_table = ie31200_pci_tbl, 746 }; 747 748 static int __init ie31200_init(void) 749 { 750 int pci_rc, i; 751 752 edac_dbg(3, "MC:\n"); 753 754 pci_rc = pci_register_driver(&ie31200_driver); 755 if (pci_rc < 0) 756 return pci_rc; 757 758 if (!mci_pdev) { 759 ie31200_registered = 0; 760 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) { 761 mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor, 762 ie31200_pci_tbl[i].device, 763 NULL); 764 if (mci_pdev) 765 break; 766 } 767 768 if (!mci_pdev) { 769 edac_dbg(0, "ie31200 pci_get_device fail\n"); 770 pci_rc = -ENODEV; 771 goto fail0; 772 } 773 774 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]); 775 if (pci_rc < 0) { 776 edac_dbg(0, "ie31200 init fail\n"); 777 pci_rc = -ENODEV; 778 goto fail1; 779 } 780 } 781 782 return 0; 783 fail1: 784 pci_dev_put(mci_pdev); 785 fail0: 786 pci_unregister_driver(&ie31200_driver); 787 788 return pci_rc; 789 } 790 791 static void __exit ie31200_exit(void) 792 { 793 edac_dbg(3, "MC:\n"); 794 pci_unregister_driver(&ie31200_driver); 795 if (!ie31200_registered) 796 ie31200_remove_one(mci_pdev); 797 } 798 799 module_init(ie31200_init); 800 module_exit(ie31200_exit); 801 802 MODULE_LICENSE("GPL"); 803 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>"); 804 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers"); 805