1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel E3-1200 4 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> 5 * 6 * Support for the E3-1200 processor family. Heavily based on previous 7 * Intel EDAC drivers. 8 * 9 * Since the DRAM controller is on the cpu chip, we can use its PCI device 10 * id to identify these processors. 11 * 12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/) 13 * 14 * 0108: Xeon E3-1200 Processor Family DRAM Controller 15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller 16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller 18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller 20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller 21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers 22 * 590f: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 23 * 5918: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 24 * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers 25 * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers 26 * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers 27 * 28 * Based on Intel specification: 29 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf 30 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html 31 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf 32 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf 33 * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html 34 * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html 35 * 36 * According to the above datasheet (p.16): 37 * " 38 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with 39 * requests that cross a DW boundary. 40 * " 41 * 42 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into 43 * 2 readl() calls. This restriction may be lifted in subsequent chip releases, 44 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. 45 */ 46 47 #include <linux/module.h> 48 #include <linux/init.h> 49 #include <linux/pci.h> 50 #include <linux/pci_ids.h> 51 #include <linux/edac.h> 52 53 #include <linux/io-64-nonatomic-lo-hi.h> 54 #include <asm/mce.h> 55 #include <asm/msr.h> 56 #include "edac_module.h" 57 58 #define EDAC_MOD_STR "ie31200_edac" 59 60 #define ie31200_printk(level, fmt, arg...) \ 61 edac_printk(level, "ie31200", fmt, ##arg) 62 63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c 65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c 68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F 71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918 72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F 73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x590f 74 #define PCI_DEVICE_ID_INTEL_IE31200_HB_12 0x5918 75 76 /* Coffee Lake-S */ 77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00 78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f 79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18 80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f 81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30 82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31 83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32 84 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33 85 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2 86 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6 87 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca 88 89 /* Raptor Lake-S */ 90 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1 0xa703 91 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2 0x4640 92 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3 0x4630 93 94 #define IE31200_RANKS_PER_CHANNEL 8 95 #define IE31200_DIMMS_PER_CHANNEL 2 96 #define IE31200_CHANNELS 2 97 #define IE31200_IMC_NUM 2 98 99 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ 100 #define IE31200_MCHBAR_LOW 0x48 101 #define IE31200_MCHBAR_HIGH 0x4c 102 103 /* 104 * Error Status Register (16b) 105 * 106 * 1 Multi-bit DRAM ECC Error Flag (DMERR) 107 * 0 Single-bit DRAM ECC Error Flag (DSERR) 108 */ 109 #define IE31200_ERRSTS 0xc8 110 #define IE31200_ERRSTS_UE BIT(1) 111 #define IE31200_ERRSTS_CE BIT(0) 112 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) 113 114 #define IE31200_CAPID0 0xe4 115 #define IE31200_CAPID0_PDCD BIT(4) 116 #define IE31200_CAPID0_DDPCD BIT(6) 117 #define IE31200_CAPID0_ECC BIT(1) 118 119 /* Non-constant mask variant of FIELD_GET() */ 120 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 121 122 static int nr_channels; 123 static struct pci_dev *mci_pdev; 124 static int ie31200_registered = 1; 125 126 struct res_config { 127 enum mem_type mtype; 128 bool cmci; 129 int imc_num; 130 /* Host MMIO configuration register */ 131 u64 reg_mchbar_mask; 132 u64 reg_mchbar_window_size; 133 /* ECC error log register */ 134 u64 reg_eccerrlog_offset[IE31200_CHANNELS]; 135 u64 reg_eccerrlog_ce_mask; 136 u64 reg_eccerrlog_ce_ovfl_mask; 137 u64 reg_eccerrlog_ue_mask; 138 u64 reg_eccerrlog_ue_ovfl_mask; 139 u64 reg_eccerrlog_rank_mask; 140 u64 reg_eccerrlog_syndrome_mask; 141 /* MSR to clear ECC error log register */ 142 u32 msr_clear_eccerrlog_offset; 143 /* DIMM characteristics register */ 144 u64 reg_mad_dimm_size_granularity; 145 u64 reg_mad_dimm_offset[IE31200_CHANNELS]; 146 u32 reg_mad_dimm_size_mask[IE31200_DIMMS_PER_CHANNEL]; 147 u32 reg_mad_dimm_rank_mask[IE31200_DIMMS_PER_CHANNEL]; 148 u32 reg_mad_dimm_width_mask[IE31200_DIMMS_PER_CHANNEL]; 149 }; 150 151 struct ie31200_priv { 152 void __iomem *window; 153 void __iomem *c0errlog; 154 void __iomem *c1errlog; 155 struct res_config *cfg; 156 struct mem_ctl_info *mci; 157 struct pci_dev *pdev; 158 struct device dev; 159 }; 160 161 static struct ie31200_pvt { 162 struct ie31200_priv *priv[IE31200_IMC_NUM]; 163 } ie31200_pvt; 164 165 enum ie31200_chips { 166 IE31200 = 0, 167 IE31200_1 = 1, 168 }; 169 170 struct ie31200_dev_info { 171 const char *ctl_name; 172 }; 173 174 struct ie31200_error_info { 175 u16 errsts; 176 u16 errsts2; 177 u64 eccerrlog[IE31200_CHANNELS]; 178 u64 erraddr; 179 }; 180 181 static const struct ie31200_dev_info ie31200_devs[] = { 182 [IE31200] = { 183 .ctl_name = "IE31200" 184 }, 185 [IE31200_1] = { 186 .ctl_name = "IE31200_1" 187 }, 188 }; 189 190 struct dimm_data { 191 u64 size; /* in bytes */ 192 u8 ranks; 193 enum dev_type dtype; 194 }; 195 196 static int how_many_channels(struct pci_dev *pdev) 197 { 198 int n_channels; 199 unsigned char capid0_2b; /* 2nd byte of CAPID0 */ 200 201 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b); 202 203 /* check PDCD: Dual Channel Disable */ 204 if (capid0_2b & IE31200_CAPID0_PDCD) { 205 edac_dbg(0, "In single channel mode\n"); 206 n_channels = 1; 207 } else { 208 edac_dbg(0, "In dual channel mode\n"); 209 n_channels = 2; 210 } 211 212 /* check DDPCD - check if both channels are filled */ 213 if (capid0_2b & IE31200_CAPID0_DDPCD) 214 edac_dbg(0, "2 DIMMS per channel disabled\n"); 215 else 216 edac_dbg(0, "2 DIMMS per channel enabled\n"); 217 218 return n_channels; 219 } 220 221 static bool ecc_capable(struct pci_dev *pdev) 222 { 223 unsigned char capid0_4b; /* 4th byte of CAPID0 */ 224 225 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b); 226 if (capid0_4b & IE31200_CAPID0_ECC) 227 return false; 228 return true; 229 } 230 231 #define mci_to_pci_dev(mci) (((struct ie31200_priv *)(mci)->pvt_info)->pdev) 232 233 static void ie31200_clear_error_info(struct mem_ctl_info *mci) 234 { 235 struct ie31200_priv *priv = mci->pvt_info; 236 struct res_config *cfg = priv->cfg; 237 238 /* 239 * The PCI ERRSTS register is deprecated. Write the MSR to clear 240 * the ECC error log registers in all memory controllers. 241 */ 242 if (cfg->msr_clear_eccerrlog_offset) { 243 if (wrmsr_safe(cfg->msr_clear_eccerrlog_offset, 244 cfg->reg_eccerrlog_ce_mask | 245 cfg->reg_eccerrlog_ce_ovfl_mask | 246 cfg->reg_eccerrlog_ue_mask | 247 cfg->reg_eccerrlog_ue_ovfl_mask, 0) < 0) 248 ie31200_printk(KERN_ERR, "Failed to wrmsr.\n"); 249 250 return; 251 } 252 253 /* 254 * Clear any error bits. 255 * (Yes, we really clear bits by writing 1 to them.) 256 */ 257 pci_write_bits16(mci_to_pci_dev(mci), IE31200_ERRSTS, 258 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); 259 } 260 261 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, 262 struct ie31200_error_info *info) 263 { 264 struct pci_dev *pdev = mci_to_pci_dev(mci); 265 struct ie31200_priv *priv = mci->pvt_info; 266 267 /* 268 * The PCI ERRSTS register is deprecated, directly read the 269 * MMIO-mapped ECC error log registers. 270 */ 271 if (priv->cfg->msr_clear_eccerrlog_offset) { 272 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 273 if (nr_channels == 2) 274 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 275 276 ie31200_clear_error_info(mci); 277 return; 278 } 279 280 /* 281 * This is a mess because there is no atomic way to read all the 282 * registers at once and the registers can transition from CE being 283 * overwritten by UE. 284 */ 285 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts); 286 if (!(info->errsts & IE31200_ERRSTS_BITS)) 287 return; 288 289 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 290 if (nr_channels == 2) 291 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 292 293 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2); 294 295 /* 296 * If the error is the same for both reads then the first set 297 * of reads is valid. If there is a change then there is a CE 298 * with no info and the second set of reads is valid and 299 * should be UE info. 300 */ 301 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 302 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 303 if (nr_channels == 2) 304 info->eccerrlog[1] = 305 lo_hi_readq(priv->c1errlog); 306 } 307 308 ie31200_clear_error_info(mci); 309 } 310 311 static void ie31200_process_error_info(struct mem_ctl_info *mci, 312 struct ie31200_error_info *info) 313 { 314 struct ie31200_priv *priv = mci->pvt_info; 315 struct res_config *cfg = priv->cfg; 316 int channel; 317 u64 log; 318 319 if (!cfg->msr_clear_eccerrlog_offset) { 320 if (!(info->errsts & IE31200_ERRSTS_BITS)) 321 return; 322 323 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 324 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 325 -1, -1, -1, "UE overwrote CE", ""); 326 info->errsts = info->errsts2; 327 } 328 } 329 330 for (channel = 0; channel < nr_channels; channel++) { 331 log = info->eccerrlog[channel]; 332 if (log & cfg->reg_eccerrlog_ue_mask) { 333 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 334 info->erraddr >> PAGE_SHIFT, 0, 0, 335 field_get(cfg->reg_eccerrlog_rank_mask, log), 336 channel, -1, 337 "ie31200 UE", ""); 338 } else if (log & cfg->reg_eccerrlog_ce_mask) { 339 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 340 info->erraddr >> PAGE_SHIFT, 0, 341 field_get(cfg->reg_eccerrlog_syndrome_mask, log), 342 field_get(cfg->reg_eccerrlog_rank_mask, log), 343 channel, -1, 344 "ie31200 CE", ""); 345 } 346 } 347 } 348 349 static void __ie31200_check(struct mem_ctl_info *mci, struct mce *mce) 350 { 351 struct ie31200_error_info info; 352 353 info.erraddr = mce ? mce->addr : 0; 354 ie31200_get_and_clear_error_info(mci, &info); 355 ie31200_process_error_info(mci, &info); 356 } 357 358 static void ie31200_check(struct mem_ctl_info *mci) 359 { 360 __ie31200_check(mci, NULL); 361 } 362 363 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev, struct res_config *cfg, int mc) 364 { 365 union { 366 u64 mchbar; 367 struct { 368 u32 mchbar_low; 369 u32 mchbar_high; 370 }; 371 } u; 372 void __iomem *window; 373 374 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low); 375 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high); 376 u.mchbar &= cfg->reg_mchbar_mask; 377 u.mchbar += cfg->reg_mchbar_window_size * mc; 378 379 if (u.mchbar != (resource_size_t)u.mchbar) { 380 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n", 381 (unsigned long long)u.mchbar); 382 return NULL; 383 } 384 385 window = ioremap(u.mchbar, cfg->reg_mchbar_window_size); 386 if (!window) 387 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n", 388 (unsigned long long)u.mchbar); 389 390 return window; 391 } 392 393 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int dimm, 394 struct res_config *cfg) 395 { 396 dd->size = field_get(cfg->reg_mad_dimm_size_mask[dimm], addr_decode) * cfg->reg_mad_dimm_size_granularity; 397 dd->ranks = field_get(cfg->reg_mad_dimm_rank_mask[dimm], addr_decode) + 1; 398 dd->dtype = field_get(cfg->reg_mad_dimm_width_mask[dimm], addr_decode) + DEV_X8; 399 } 400 401 static void ie31200_get_dimm_config(struct mem_ctl_info *mci, void __iomem *window, 402 struct res_config *cfg, int mc) 403 { 404 struct dimm_data dimm_info; 405 struct dimm_info *dimm; 406 unsigned long nr_pages; 407 u32 addr_decode; 408 int i, j, k; 409 410 for (i = 0; i < IE31200_CHANNELS; i++) { 411 addr_decode = readl(window + cfg->reg_mad_dimm_offset[i]); 412 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode); 413 414 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { 415 populate_dimm_info(&dimm_info, addr_decode, j, cfg); 416 edac_dbg(0, "mc: %d, channel: %d, dimm: %d, size: %lld MiB, ranks: %d, DRAM chip type: %d\n", 417 mc, i, j, dimm_info.size >> 20, 418 dimm_info.ranks, 419 dimm_info.dtype); 420 421 nr_pages = MiB_TO_PAGES(dimm_info.size >> 20); 422 if (nr_pages == 0) 423 continue; 424 425 nr_pages = nr_pages / dimm_info.ranks; 426 for (k = 0; k < dimm_info.ranks; k++) { 427 dimm = edac_get_dimm(mci, (j * dimm_info.ranks) + k, i, 0); 428 dimm->nr_pages = nr_pages; 429 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 430 dimm->grain = 8; /* just a guess */ 431 dimm->mtype = cfg->mtype; 432 dimm->dtype = dimm_info.dtype; 433 dimm->edac_mode = EDAC_UNKNOWN; 434 } 435 } 436 } 437 } 438 439 static int ie31200_register_mci(struct pci_dev *pdev, struct res_config *cfg, int mc) 440 { 441 struct edac_mc_layer layers[2]; 442 struct ie31200_priv *priv; 443 struct mem_ctl_info *mci; 444 void __iomem *window; 445 int ret; 446 447 nr_channels = how_many_channels(pdev); 448 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 449 layers[0].size = IE31200_RANKS_PER_CHANNEL; 450 layers[0].is_virt_csrow = true; 451 layers[1].type = EDAC_MC_LAYER_CHANNEL; 452 layers[1].size = nr_channels; 453 layers[1].is_virt_csrow = false; 454 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 455 sizeof(struct ie31200_priv)); 456 if (!mci) 457 return -ENOMEM; 458 459 window = ie31200_map_mchbar(pdev, cfg, mc); 460 if (!window) { 461 ret = -ENODEV; 462 goto fail_free; 463 } 464 465 edac_dbg(3, "MC: init mci\n"); 466 mci->mtype_cap = BIT(cfg->mtype); 467 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 468 mci->edac_cap = EDAC_FLAG_SECDED; 469 mci->mod_name = EDAC_MOD_STR; 470 mci->ctl_name = ie31200_devs[mc].ctl_name; 471 mci->dev_name = pci_name(pdev); 472 mci->edac_check = cfg->cmci ? NULL : ie31200_check; 473 mci->ctl_page_to_phys = NULL; 474 priv = mci->pvt_info; 475 priv->window = window; 476 priv->c0errlog = window + cfg->reg_eccerrlog_offset[0]; 477 priv->c1errlog = window + cfg->reg_eccerrlog_offset[1]; 478 priv->cfg = cfg; 479 priv->mci = mci; 480 priv->pdev = pdev; 481 device_initialize(&priv->dev); 482 /* 483 * The EDAC core uses mci->pdev (pointer to the structure device) 484 * as the memory controller ID. The SoCs attach one or more memory 485 * controllers to a single pci_dev (a single pci_dev->dev can 486 * correspond to multiple memory controllers). 487 * 488 * To make mci->pdev unique, assign pci_dev->dev to mci->pdev 489 * for the first memory controller and assign a unique priv->dev 490 * to mci->pdev for each additional memory controller. 491 */ 492 mci->pdev = mc ? &priv->dev : &pdev->dev; 493 494 ie31200_get_dimm_config(mci, window, cfg, mc); 495 ie31200_clear_error_info(mci); 496 497 if (edac_mc_add_mc(mci)) { 498 edac_dbg(3, "MC: failed edac_mc_add_mc()\n"); 499 ret = -ENODEV; 500 goto fail_unmap; 501 } 502 503 ie31200_pvt.priv[mc] = priv; 504 return 0; 505 fail_unmap: 506 iounmap(window); 507 fail_free: 508 edac_mc_free(mci); 509 return ret; 510 } 511 512 static void mce_check(struct mce *mce) 513 { 514 struct ie31200_priv *priv; 515 int i; 516 517 for (i = 0; i < IE31200_IMC_NUM; i++) { 518 priv = ie31200_pvt.priv[i]; 519 if (!priv) 520 continue; 521 522 __ie31200_check(priv->mci, mce); 523 } 524 } 525 526 static int mce_handler(struct notifier_block *nb, unsigned long val, void *data) 527 { 528 struct mce *mce = (struct mce *)data; 529 char *type; 530 531 if (mce->kflags & MCE_HANDLED_CEC) 532 return NOTIFY_DONE; 533 534 /* 535 * Ignore unless this is a memory related error. 536 * Don't check MCI_STATUS_ADDRV since it's not set on some CPUs. 537 */ 538 if ((mce->status & 0xefff) >> 7 != 1) 539 return NOTIFY_DONE; 540 541 type = mce->mcgstatus & MCG_STATUS_MCIP ? "Exception" : "Event"; 542 543 edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n", 544 mce->extcpu, type, mce->mcgstatus, 545 mce->bank, mce->status); 546 edac_dbg(0, "TSC 0x%llx\n", mce->tsc); 547 edac_dbg(0, "ADDR 0x%llx\n", mce->addr); 548 edac_dbg(0, "MISC 0x%llx\n", mce->misc); 549 edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n", 550 mce->cpuvendor, mce->cpuid, mce->time, 551 mce->socketid, mce->apicid); 552 553 mce_check(mce); 554 mce->kflags |= MCE_HANDLED_EDAC; 555 556 return NOTIFY_DONE; 557 } 558 559 static struct notifier_block ie31200_mce_dec = { 560 .notifier_call = mce_handler, 561 .priority = MCE_PRIO_EDAC, 562 }; 563 564 static void ie31200_unregister_mcis(void) 565 { 566 struct ie31200_priv *priv; 567 struct mem_ctl_info *mci; 568 int i; 569 570 for (i = 0; i < IE31200_IMC_NUM; i++) { 571 priv = ie31200_pvt.priv[i]; 572 if (!priv) 573 continue; 574 575 mci = priv->mci; 576 edac_mc_del_mc(mci->pdev); 577 iounmap(priv->window); 578 edac_mc_free(mci); 579 } 580 } 581 582 static int ie31200_probe1(struct pci_dev *pdev, struct res_config *cfg) 583 { 584 int i, ret; 585 586 edac_dbg(0, "MC:\n"); 587 588 if (!ecc_capable(pdev)) { 589 ie31200_printk(KERN_INFO, "No ECC support\n"); 590 return -ENODEV; 591 } 592 593 for (i = 0; i < cfg->imc_num; i++) { 594 ret = ie31200_register_mci(pdev, cfg, i); 595 if (ret) 596 goto fail_register; 597 } 598 599 if (cfg->cmci) { 600 mce_register_decode_chain(&ie31200_mce_dec); 601 edac_op_state = EDAC_OPSTATE_INT; 602 } else { 603 edac_op_state = EDAC_OPSTATE_POLL; 604 } 605 606 /* get this far and it's successful. */ 607 edac_dbg(3, "MC: success\n"); 608 return 0; 609 610 fail_register: 611 ie31200_unregister_mcis(); 612 return ret; 613 } 614 615 static int ie31200_init_one(struct pci_dev *pdev, 616 const struct pci_device_id *ent) 617 { 618 int rc; 619 620 edac_dbg(0, "MC:\n"); 621 if (pci_enable_device(pdev) < 0) 622 return -EIO; 623 rc = ie31200_probe1(pdev, (struct res_config *)ent->driver_data); 624 if (rc == 0 && !mci_pdev) 625 mci_pdev = pci_dev_get(pdev); 626 627 return rc; 628 } 629 630 static void ie31200_remove_one(struct pci_dev *pdev) 631 { 632 struct ie31200_priv *priv = ie31200_pvt.priv[0]; 633 634 edac_dbg(0, "\n"); 635 pci_dev_put(mci_pdev); 636 mci_pdev = NULL; 637 if (priv->cfg->cmci) 638 mce_unregister_decode_chain(&ie31200_mce_dec); 639 ie31200_unregister_mcis(); 640 } 641 642 static struct res_config snb_cfg = { 643 .mtype = MEM_DDR3, 644 .imc_num = 1, 645 .reg_mchbar_mask = GENMASK_ULL(38, 15), 646 .reg_mchbar_window_size = BIT_ULL(15), 647 .reg_eccerrlog_offset[0] = 0x40c8, 648 .reg_eccerrlog_offset[1] = 0x44c8, 649 .reg_eccerrlog_ce_mask = BIT_ULL(0), 650 .reg_eccerrlog_ue_mask = BIT_ULL(1), 651 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 652 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 653 .reg_mad_dimm_size_granularity = BIT_ULL(28), 654 .reg_mad_dimm_offset[0] = 0x5004, 655 .reg_mad_dimm_offset[1] = 0x5008, 656 .reg_mad_dimm_size_mask[0] = GENMASK(7, 0), 657 .reg_mad_dimm_size_mask[1] = GENMASK(15, 8), 658 .reg_mad_dimm_rank_mask[0] = BIT(17), 659 .reg_mad_dimm_rank_mask[1] = BIT(18), 660 .reg_mad_dimm_width_mask[0] = BIT(19), 661 .reg_mad_dimm_width_mask[1] = BIT(20), 662 }; 663 664 static struct res_config skl_cfg = { 665 .mtype = MEM_DDR4, 666 .imc_num = 1, 667 .reg_mchbar_mask = GENMASK_ULL(38, 15), 668 .reg_mchbar_window_size = BIT_ULL(15), 669 .reg_eccerrlog_offset[0] = 0x4048, 670 .reg_eccerrlog_offset[1] = 0x4448, 671 .reg_eccerrlog_ce_mask = BIT_ULL(0), 672 .reg_eccerrlog_ue_mask = BIT_ULL(1), 673 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 674 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 675 .reg_mad_dimm_size_granularity = BIT_ULL(30), 676 .reg_mad_dimm_offset[0] = 0x500c, 677 .reg_mad_dimm_offset[1] = 0x5010, 678 .reg_mad_dimm_size_mask[0] = GENMASK(5, 0), 679 .reg_mad_dimm_size_mask[1] = GENMASK(21, 16), 680 .reg_mad_dimm_rank_mask[0] = BIT(10), 681 .reg_mad_dimm_rank_mask[1] = BIT(26), 682 .reg_mad_dimm_width_mask[0] = GENMASK(9, 8), 683 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24), 684 }; 685 686 struct res_config rpl_s_cfg = { 687 .mtype = MEM_DDR5, 688 .cmci = true, 689 .imc_num = 2, 690 .reg_mchbar_mask = GENMASK_ULL(41, 17), 691 .reg_mchbar_window_size = BIT_ULL(16), 692 .reg_eccerrlog_offset[0] = 0xe048, 693 .reg_eccerrlog_offset[1] = 0xe848, 694 .reg_eccerrlog_ce_mask = BIT_ULL(0), 695 .reg_eccerrlog_ce_ovfl_mask = BIT_ULL(1), 696 .reg_eccerrlog_ue_mask = BIT_ULL(2), 697 .reg_eccerrlog_ue_ovfl_mask = BIT_ULL(3), 698 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 699 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 700 .msr_clear_eccerrlog_offset = 0x791, 701 .reg_mad_dimm_offset[0] = 0xd80c, 702 .reg_mad_dimm_offset[1] = 0xd810, 703 .reg_mad_dimm_size_granularity = BIT_ULL(29), 704 .reg_mad_dimm_size_mask[0] = GENMASK(6, 0), 705 .reg_mad_dimm_size_mask[1] = GENMASK(22, 16), 706 .reg_mad_dimm_rank_mask[0] = GENMASK(10, 9), 707 .reg_mad_dimm_rank_mask[1] = GENMASK(27, 26), 708 .reg_mad_dimm_width_mask[0] = GENMASK(8, 7), 709 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24), 710 }; 711 712 static const struct pci_device_id ie31200_pci_tbl[] = { 713 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_1), (kernel_ulong_t)&snb_cfg }, 714 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_2), (kernel_ulong_t)&snb_cfg }, 715 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_3), (kernel_ulong_t)&snb_cfg }, 716 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_4), (kernel_ulong_t)&snb_cfg }, 717 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_5), (kernel_ulong_t)&snb_cfg }, 718 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_6), (kernel_ulong_t)&snb_cfg }, 719 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_7), (kernel_ulong_t)&snb_cfg }, 720 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_8), (kernel_ulong_t)&skl_cfg }, 721 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_9), (kernel_ulong_t)&skl_cfg }, 722 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_10), (kernel_ulong_t)&skl_cfg }, 723 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_11), (kernel_ulong_t)&skl_cfg }, 724 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_12), (kernel_ulong_t)&skl_cfg }, 725 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1), (kernel_ulong_t)&skl_cfg }, 726 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2), (kernel_ulong_t)&skl_cfg }, 727 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3), (kernel_ulong_t)&skl_cfg }, 728 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4), (kernel_ulong_t)&skl_cfg }, 729 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5), (kernel_ulong_t)&skl_cfg }, 730 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6), (kernel_ulong_t)&skl_cfg }, 731 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7), (kernel_ulong_t)&skl_cfg }, 732 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8), (kernel_ulong_t)&skl_cfg }, 733 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9), (kernel_ulong_t)&skl_cfg }, 734 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10), (kernel_ulong_t)&skl_cfg }, 735 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1), (kernel_ulong_t)&rpl_s_cfg}, 736 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2), (kernel_ulong_t)&rpl_s_cfg}, 737 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3), (kernel_ulong_t)&rpl_s_cfg}, 738 { 0, } /* 0 terminated list. */ 739 }; 740 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); 741 742 static struct pci_driver ie31200_driver = { 743 .name = EDAC_MOD_STR, 744 .probe = ie31200_init_one, 745 .remove = ie31200_remove_one, 746 .id_table = ie31200_pci_tbl, 747 }; 748 749 static int __init ie31200_init(void) 750 { 751 int pci_rc, i; 752 753 edac_dbg(3, "MC:\n"); 754 755 pci_rc = pci_register_driver(&ie31200_driver); 756 if (pci_rc < 0) 757 return pci_rc; 758 759 if (!mci_pdev) { 760 ie31200_registered = 0; 761 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) { 762 mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor, 763 ie31200_pci_tbl[i].device, 764 NULL); 765 if (mci_pdev) 766 break; 767 } 768 769 if (!mci_pdev) { 770 edac_dbg(0, "ie31200 pci_get_device fail\n"); 771 pci_rc = -ENODEV; 772 goto fail0; 773 } 774 775 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]); 776 if (pci_rc < 0) { 777 edac_dbg(0, "ie31200 init fail\n"); 778 pci_rc = -ENODEV; 779 goto fail1; 780 } 781 } 782 783 return 0; 784 fail1: 785 pci_dev_put(mci_pdev); 786 fail0: 787 pci_unregister_driver(&ie31200_driver); 788 789 return pci_rc; 790 } 791 792 static void __exit ie31200_exit(void) 793 { 794 edac_dbg(3, "MC:\n"); 795 pci_unregister_driver(&ie31200_driver); 796 if (!ie31200_registered) 797 ie31200_remove_one(mci_pdev); 798 } 799 800 module_init(ie31200_init); 801 module_exit(ie31200_exit); 802 803 MODULE_LICENSE("GPL"); 804 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>"); 805 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers"); 806