1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel E3-1200 4 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> 5 * 6 * Support for the E3-1200 processor family. Heavily based on previous 7 * Intel EDAC drivers. 8 * 9 * Since the DRAM controller is on the cpu chip, we can use its PCI device 10 * id to identify these processors. 11 * 12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/) 13 * 14 * 0108: Xeon E3-1200 Processor Family DRAM Controller 15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller 16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller 18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller 20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller 21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers 22 * 590f: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 23 * 5918: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 24 * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers 25 * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers 26 * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers 27 * 28 * Based on Intel specification: 29 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf 30 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html 31 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf 32 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf 33 * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html 34 * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html 35 * 36 * According to the above datasheet (p.16): 37 * " 38 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with 39 * requests that cross a DW boundary. 40 * " 41 * 42 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into 43 * 2 readl() calls. This restriction may be lifted in subsequent chip releases, 44 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. 45 */ 46 47 #include <linux/module.h> 48 #include <linux/init.h> 49 #include <linux/pci.h> 50 #include <linux/pci_ids.h> 51 #include <linux/edac.h> 52 53 #include <linux/io-64-nonatomic-lo-hi.h> 54 #include <asm/mce.h> 55 #include <asm/msr.h> 56 #include "edac_module.h" 57 58 #define EDAC_MOD_STR "ie31200_edac" 59 60 #define ie31200_printk(level, fmt, arg...) \ 61 edac_printk(level, "ie31200", fmt, ##arg) 62 63 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c 65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c 68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F 71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918 72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F 73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x590f 74 #define PCI_DEVICE_ID_INTEL_IE31200_HB_12 0x5918 75 76 /* Coffee Lake-S */ 77 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00 78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f 79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18 80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f 81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30 82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31 83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32 84 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33 85 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2 86 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6 87 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca 88 89 /* Raptor Lake-S */ 90 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1 0xa703 /* 8P+8E, e.g. i7-13700 */ 91 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2 0x4640 /* 6P+8E, e.g. i5-13500, i5-13600, i5-14500 */ 92 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3 0x4630 /* 4P+0E, e.g. i3-13100E */ 93 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4 0xa700 /* 8P+16E, e.g. i9-13900, i9-14900 */ 94 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_5 0xa740 /* 8P+12E, e.g. i7-14700 */ 95 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_6 0xa704 /* 6P+8E, e.g. i5-14600 */ 96 97 /* Raptor Lake-HX */ 98 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_HX_1 0xa702 /* 8P+16E, e.g. i9-13950HX */ 99 100 /* Alder Lake-S */ 101 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1 0x4660 102 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_2 0x4668 /* 8P+4E, e.g. i7-12700K */ 103 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_3 0x4648 /* 6P+4E, e.g. i5-12600K */ 104 105 /* Bartlett Lake-S */ 106 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_1 0x4639 107 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_2 0x463c 108 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_3 0x4642 109 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_4 0x4643 110 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_5 0xa731 111 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_6 0xa732 112 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_7 0xa733 113 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_8 0xa741 114 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_9 0xa744 115 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_10 0xa745 116 117 #define IE31200_RANKS_PER_CHANNEL 8 118 #define IE31200_DIMMS_PER_CHANNEL 2 119 #define IE31200_CHANNELS 2 120 #define IE31200_IMC_NUM 2 121 122 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ 123 #define IE31200_MCHBAR_LOW 0x48 124 #define IE31200_MCHBAR_HIGH 0x4c 125 126 /* 127 * Error Status Register (16b) 128 * 129 * 1 Multi-bit DRAM ECC Error Flag (DMERR) 130 * 0 Single-bit DRAM ECC Error Flag (DSERR) 131 */ 132 #define IE31200_ERRSTS 0xc8 133 #define IE31200_ERRSTS_UE BIT(1) 134 #define IE31200_ERRSTS_CE BIT(0) 135 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) 136 137 #define IE31200_CAPID0 0xe4 138 #define IE31200_CAPID0_PDCD BIT(4) 139 #define IE31200_CAPID0_DDPCD BIT(6) 140 #define IE31200_CAPID0_ECC BIT(1) 141 142 /* Non-constant mask variant of FIELD_GET() */ 143 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) 144 145 static int nr_channels; 146 static struct pci_dev *mci_pdev; 147 static int ie31200_registered = 1; 148 149 struct res_config { 150 enum mem_type mtype; 151 bool cmci; 152 int imc_num; 153 /* Host MMIO configuration register */ 154 u64 reg_mchbar_mask; 155 u64 reg_mchbar_window_size; 156 /* ECC error log register */ 157 u64 reg_eccerrlog_offset[IE31200_CHANNELS]; 158 u64 reg_eccerrlog_ce_mask; 159 u64 reg_eccerrlog_ce_ovfl_mask; 160 u64 reg_eccerrlog_ue_mask; 161 u64 reg_eccerrlog_ue_ovfl_mask; 162 u64 reg_eccerrlog_rank_mask; 163 u64 reg_eccerrlog_syndrome_mask; 164 /* MSR to clear ECC error log register */ 165 u32 msr_clear_eccerrlog_offset; 166 /* DIMM characteristics register */ 167 u64 reg_mad_dimm_size_granularity; 168 u64 reg_mad_dimm_offset[IE31200_CHANNELS]; 169 u32 reg_mad_dimm_size_mask[IE31200_DIMMS_PER_CHANNEL]; 170 u32 reg_mad_dimm_rank_mask[IE31200_DIMMS_PER_CHANNEL]; 171 u32 reg_mad_dimm_width_mask[IE31200_DIMMS_PER_CHANNEL]; 172 }; 173 174 struct ie31200_priv { 175 void __iomem *window; 176 void __iomem *c0errlog; 177 void __iomem *c1errlog; 178 struct res_config *cfg; 179 struct mem_ctl_info *mci; 180 struct pci_dev *pdev; 181 struct device dev; 182 }; 183 184 static struct ie31200_pvt { 185 struct ie31200_priv *priv[IE31200_IMC_NUM]; 186 } ie31200_pvt; 187 188 enum ie31200_chips { 189 IE31200 = 0, 190 IE31200_1 = 1, 191 }; 192 193 struct ie31200_dev_info { 194 const char *ctl_name; 195 }; 196 197 struct ie31200_error_info { 198 u16 errsts; 199 u16 errsts2; 200 u64 eccerrlog[IE31200_CHANNELS]; 201 u64 erraddr; 202 }; 203 204 static const struct ie31200_dev_info ie31200_devs[] = { 205 [IE31200] = { 206 .ctl_name = "IE31200" 207 }, 208 [IE31200_1] = { 209 .ctl_name = "IE31200_1" 210 }, 211 }; 212 213 struct dimm_data { 214 u64 size; /* in bytes */ 215 u8 ranks; 216 enum dev_type dtype; 217 }; 218 219 static int how_many_channels(struct pci_dev *pdev) 220 { 221 int n_channels; 222 unsigned char capid0_2b; /* 2nd byte of CAPID0 */ 223 224 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b); 225 226 /* check PDCD: Dual Channel Disable */ 227 if (capid0_2b & IE31200_CAPID0_PDCD) { 228 edac_dbg(0, "In single channel mode\n"); 229 n_channels = 1; 230 } else { 231 edac_dbg(0, "In dual channel mode\n"); 232 n_channels = 2; 233 } 234 235 /* check DDPCD - check if both channels are filled */ 236 if (capid0_2b & IE31200_CAPID0_DDPCD) 237 edac_dbg(0, "2 DIMMS per channel disabled\n"); 238 else 239 edac_dbg(0, "2 DIMMS per channel enabled\n"); 240 241 return n_channels; 242 } 243 244 static bool ecc_capable(struct pci_dev *pdev) 245 { 246 unsigned char capid0_4b; /* 4th byte of CAPID0 */ 247 248 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b); 249 if (capid0_4b & IE31200_CAPID0_ECC) 250 return false; 251 return true; 252 } 253 254 #define mci_to_pci_dev(mci) (((struct ie31200_priv *)(mci)->pvt_info)->pdev) 255 256 static void ie31200_clear_error_info(struct mem_ctl_info *mci) 257 { 258 struct ie31200_priv *priv = mci->pvt_info; 259 struct res_config *cfg = priv->cfg; 260 261 /* 262 * The PCI ERRSTS register is deprecated. Write the MSR to clear 263 * the ECC error log registers in all memory controllers. 264 */ 265 if (cfg->msr_clear_eccerrlog_offset) { 266 if (wrmsr_safe(cfg->msr_clear_eccerrlog_offset, 267 cfg->reg_eccerrlog_ce_mask | 268 cfg->reg_eccerrlog_ce_ovfl_mask | 269 cfg->reg_eccerrlog_ue_mask | 270 cfg->reg_eccerrlog_ue_ovfl_mask, 0) < 0) 271 ie31200_printk(KERN_ERR, "Failed to wrmsr.\n"); 272 273 return; 274 } 275 276 /* 277 * Clear any error bits. 278 * (Yes, we really clear bits by writing 1 to them.) 279 */ 280 pci_write_bits16(mci_to_pci_dev(mci), IE31200_ERRSTS, 281 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); 282 } 283 284 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, 285 struct ie31200_error_info *info) 286 { 287 struct pci_dev *pdev = mci_to_pci_dev(mci); 288 struct ie31200_priv *priv = mci->pvt_info; 289 290 /* 291 * The PCI ERRSTS register is deprecated, directly read the 292 * MMIO-mapped ECC error log registers. 293 */ 294 if (priv->cfg->msr_clear_eccerrlog_offset) { 295 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 296 if (nr_channels == 2) 297 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 298 299 ie31200_clear_error_info(mci); 300 return; 301 } 302 303 /* 304 * This is a mess because there is no atomic way to read all the 305 * registers at once and the registers can transition from CE being 306 * overwritten by UE. 307 */ 308 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts); 309 if (!(info->errsts & IE31200_ERRSTS_BITS)) 310 return; 311 312 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 313 if (nr_channels == 2) 314 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 315 316 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2); 317 318 /* 319 * If the error is the same for both reads then the first set 320 * of reads is valid. If there is a change then there is a CE 321 * with no info and the second set of reads is valid and 322 * should be UE info. 323 */ 324 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 325 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 326 if (nr_channels == 2) 327 info->eccerrlog[1] = 328 lo_hi_readq(priv->c1errlog); 329 } 330 331 ie31200_clear_error_info(mci); 332 } 333 334 static void ie31200_process_error_info(struct mem_ctl_info *mci, 335 struct ie31200_error_info *info) 336 { 337 struct ie31200_priv *priv = mci->pvt_info; 338 struct res_config *cfg = priv->cfg; 339 int channel; 340 u64 log; 341 342 if (!cfg->msr_clear_eccerrlog_offset) { 343 if (!(info->errsts & IE31200_ERRSTS_BITS)) 344 return; 345 346 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 347 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 348 -1, -1, -1, "UE overwrote CE", ""); 349 info->errsts = info->errsts2; 350 } 351 } 352 353 for (channel = 0; channel < nr_channels; channel++) { 354 log = info->eccerrlog[channel]; 355 if (log & cfg->reg_eccerrlog_ue_mask) { 356 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 357 info->erraddr >> PAGE_SHIFT, 0, 0, 358 field_get(cfg->reg_eccerrlog_rank_mask, log), 359 channel, -1, 360 "ie31200 UE", ""); 361 } else if (log & cfg->reg_eccerrlog_ce_mask) { 362 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 363 info->erraddr >> PAGE_SHIFT, 0, 364 field_get(cfg->reg_eccerrlog_syndrome_mask, log), 365 field_get(cfg->reg_eccerrlog_rank_mask, log), 366 channel, -1, 367 "ie31200 CE", ""); 368 } 369 } 370 } 371 372 static void __ie31200_check(struct mem_ctl_info *mci, struct mce *mce) 373 { 374 struct ie31200_error_info info; 375 376 info.erraddr = mce ? mce->addr : 0; 377 ie31200_get_and_clear_error_info(mci, &info); 378 ie31200_process_error_info(mci, &info); 379 } 380 381 static void ie31200_check(struct mem_ctl_info *mci) 382 { 383 __ie31200_check(mci, NULL); 384 } 385 386 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev, struct res_config *cfg, int mc) 387 { 388 union { 389 u64 mchbar; 390 struct { 391 u32 mchbar_low; 392 u32 mchbar_high; 393 }; 394 } u; 395 void __iomem *window; 396 397 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low); 398 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high); 399 u.mchbar &= cfg->reg_mchbar_mask; 400 u.mchbar += cfg->reg_mchbar_window_size * mc; 401 402 if (u.mchbar != (resource_size_t)u.mchbar) { 403 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n", 404 (unsigned long long)u.mchbar); 405 return NULL; 406 } 407 408 window = ioremap(u.mchbar, cfg->reg_mchbar_window_size); 409 if (!window) 410 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n", 411 (unsigned long long)u.mchbar); 412 413 return window; 414 } 415 416 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int dimm, 417 struct res_config *cfg) 418 { 419 dd->size = field_get(cfg->reg_mad_dimm_size_mask[dimm], addr_decode) * cfg->reg_mad_dimm_size_granularity; 420 dd->ranks = field_get(cfg->reg_mad_dimm_rank_mask[dimm], addr_decode) + 1; 421 dd->dtype = field_get(cfg->reg_mad_dimm_width_mask[dimm], addr_decode) + DEV_X8; 422 } 423 424 static void ie31200_get_dimm_config(struct mem_ctl_info *mci, void __iomem *window, 425 struct res_config *cfg, int mc) 426 { 427 struct dimm_data dimm_info; 428 struct dimm_info *dimm; 429 unsigned long nr_pages; 430 u32 addr_decode; 431 int i, j, k; 432 433 for (i = 0; i < IE31200_CHANNELS; i++) { 434 addr_decode = readl(window + cfg->reg_mad_dimm_offset[i]); 435 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode); 436 437 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { 438 populate_dimm_info(&dimm_info, addr_decode, j, cfg); 439 edac_dbg(0, "mc: %d, channel: %d, dimm: %d, size: %lld MiB, ranks: %d, DRAM chip type: %d\n", 440 mc, i, j, dimm_info.size >> 20, 441 dimm_info.ranks, 442 dimm_info.dtype); 443 444 nr_pages = MiB_TO_PAGES(dimm_info.size >> 20); 445 if (nr_pages == 0) 446 continue; 447 448 nr_pages = nr_pages / dimm_info.ranks; 449 for (k = 0; k < dimm_info.ranks; k++) { 450 dimm = edac_get_dimm(mci, (j * dimm_info.ranks) + k, i, 0); 451 dimm->nr_pages = nr_pages; 452 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 453 dimm->grain = 8; /* just a guess */ 454 dimm->mtype = cfg->mtype; 455 dimm->dtype = dimm_info.dtype; 456 dimm->edac_mode = EDAC_UNKNOWN; 457 } 458 } 459 } 460 } 461 462 static int ie31200_register_mci(struct pci_dev *pdev, struct res_config *cfg, int mc) 463 { 464 struct edac_mc_layer layers[2]; 465 struct ie31200_priv *priv; 466 struct mem_ctl_info *mci; 467 void __iomem *window; 468 int ret; 469 470 nr_channels = how_many_channels(pdev); 471 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 472 layers[0].size = IE31200_RANKS_PER_CHANNEL; 473 layers[0].is_virt_csrow = true; 474 layers[1].type = EDAC_MC_LAYER_CHANNEL; 475 layers[1].size = nr_channels; 476 layers[1].is_virt_csrow = false; 477 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 478 sizeof(struct ie31200_priv)); 479 if (!mci) 480 return -ENOMEM; 481 482 window = ie31200_map_mchbar(pdev, cfg, mc); 483 if (!window) { 484 ret = -ENODEV; 485 goto fail_free; 486 } 487 488 edac_dbg(3, "MC: init mci\n"); 489 mci->mtype_cap = BIT(cfg->mtype); 490 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 491 mci->edac_cap = EDAC_FLAG_SECDED; 492 mci->mod_name = EDAC_MOD_STR; 493 mci->ctl_name = ie31200_devs[mc].ctl_name; 494 mci->dev_name = pci_name(pdev); 495 mci->edac_check = cfg->cmci ? NULL : ie31200_check; 496 mci->ctl_page_to_phys = NULL; 497 priv = mci->pvt_info; 498 priv->window = window; 499 priv->c0errlog = window + cfg->reg_eccerrlog_offset[0]; 500 priv->c1errlog = window + cfg->reg_eccerrlog_offset[1]; 501 priv->cfg = cfg; 502 priv->mci = mci; 503 priv->pdev = pdev; 504 device_initialize(&priv->dev); 505 /* 506 * The EDAC core uses mci->pdev (pointer to the structure device) 507 * as the memory controller ID. The SoCs attach one or more memory 508 * controllers to a single pci_dev (a single pci_dev->dev can 509 * correspond to multiple memory controllers). 510 * 511 * To make mci->pdev unique, assign pci_dev->dev to mci->pdev 512 * for the first memory controller and assign a unique priv->dev 513 * to mci->pdev for each additional memory controller. 514 */ 515 mci->pdev = mc ? &priv->dev : &pdev->dev; 516 517 ie31200_get_dimm_config(mci, window, cfg, mc); 518 ie31200_clear_error_info(mci); 519 520 if (edac_mc_add_mc(mci)) { 521 edac_dbg(3, "MC: failed edac_mc_add_mc()\n"); 522 ret = -ENODEV; 523 goto fail_unmap; 524 } 525 526 ie31200_pvt.priv[mc] = priv; 527 return 0; 528 fail_unmap: 529 iounmap(window); 530 fail_free: 531 edac_mc_free(mci); 532 return ret; 533 } 534 535 static void mce_check(struct mce *mce) 536 { 537 struct ie31200_priv *priv; 538 int i; 539 540 for (i = 0; i < IE31200_IMC_NUM; i++) { 541 priv = ie31200_pvt.priv[i]; 542 if (!priv) 543 continue; 544 545 __ie31200_check(priv->mci, mce); 546 } 547 } 548 549 static int mce_handler(struct notifier_block *nb, unsigned long val, void *data) 550 { 551 struct mce *mce = (struct mce *)data; 552 char *type; 553 554 if (mce->kflags & MCE_HANDLED_CEC) 555 return NOTIFY_DONE; 556 557 /* 558 * Ignore unless this is a memory related error. 559 * Don't check MCI_STATUS_ADDRV since it's not set on some CPUs. 560 */ 561 if ((mce->status & 0xefff) >> 7 != 1) 562 return NOTIFY_DONE; 563 564 type = mce->mcgstatus & MCG_STATUS_MCIP ? "Exception" : "Event"; 565 566 edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n", 567 mce->extcpu, type, mce->mcgstatus, 568 mce->bank, mce->status); 569 edac_dbg(0, "TSC 0x%llx\n", mce->tsc); 570 edac_dbg(0, "ADDR 0x%llx\n", mce->addr); 571 edac_dbg(0, "MISC 0x%llx\n", mce->misc); 572 edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n", 573 mce->cpuvendor, mce->cpuid, mce->time, 574 mce->socketid, mce->apicid); 575 576 mce_check(mce); 577 mce->kflags |= MCE_HANDLED_EDAC; 578 579 return NOTIFY_DONE; 580 } 581 582 static struct notifier_block ie31200_mce_dec = { 583 .notifier_call = mce_handler, 584 .priority = MCE_PRIO_EDAC, 585 }; 586 587 static void ie31200_unregister_mcis(void) 588 { 589 struct ie31200_priv *priv; 590 struct mem_ctl_info *mci; 591 int i; 592 593 for (i = 0; i < IE31200_IMC_NUM; i++) { 594 priv = ie31200_pvt.priv[i]; 595 if (!priv) 596 continue; 597 598 mci = priv->mci; 599 edac_mc_del_mc(mci->pdev); 600 iounmap(priv->window); 601 edac_mc_free(mci); 602 } 603 } 604 605 static int ie31200_probe1(struct pci_dev *pdev, struct res_config *cfg) 606 { 607 int i, ret; 608 609 edac_dbg(0, "MC:\n"); 610 611 if (!ecc_capable(pdev)) { 612 ie31200_printk(KERN_INFO, "No ECC support\n"); 613 return -ENODEV; 614 } 615 616 for (i = 0; i < cfg->imc_num; i++) { 617 ret = ie31200_register_mci(pdev, cfg, i); 618 if (ret) 619 goto fail_register; 620 } 621 622 if (cfg->cmci) { 623 mce_register_decode_chain(&ie31200_mce_dec); 624 edac_op_state = EDAC_OPSTATE_INT; 625 } else { 626 edac_op_state = EDAC_OPSTATE_POLL; 627 } 628 629 /* get this far and it's successful. */ 630 edac_dbg(3, "MC: success\n"); 631 return 0; 632 633 fail_register: 634 ie31200_unregister_mcis(); 635 return ret; 636 } 637 638 static int ie31200_init_one(struct pci_dev *pdev, 639 const struct pci_device_id *ent) 640 { 641 int rc; 642 643 edac_dbg(0, "MC:\n"); 644 if (pci_enable_device(pdev) < 0) 645 return -EIO; 646 rc = ie31200_probe1(pdev, (struct res_config *)ent->driver_data); 647 if (rc == 0 && !mci_pdev) 648 mci_pdev = pci_dev_get(pdev); 649 650 return rc; 651 } 652 653 static void ie31200_remove_one(struct pci_dev *pdev) 654 { 655 struct ie31200_priv *priv = ie31200_pvt.priv[0]; 656 657 edac_dbg(0, "\n"); 658 pci_dev_put(mci_pdev); 659 mci_pdev = NULL; 660 if (priv->cfg->cmci) 661 mce_unregister_decode_chain(&ie31200_mce_dec); 662 ie31200_unregister_mcis(); 663 } 664 665 static struct res_config snb_cfg = { 666 .mtype = MEM_DDR3, 667 .imc_num = 1, 668 .reg_mchbar_mask = GENMASK_ULL(38, 15), 669 .reg_mchbar_window_size = BIT_ULL(15), 670 .reg_eccerrlog_offset[0] = 0x40c8, 671 .reg_eccerrlog_offset[1] = 0x44c8, 672 .reg_eccerrlog_ce_mask = BIT_ULL(0), 673 .reg_eccerrlog_ue_mask = BIT_ULL(1), 674 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 675 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 676 .reg_mad_dimm_size_granularity = BIT_ULL(28), 677 .reg_mad_dimm_offset[0] = 0x5004, 678 .reg_mad_dimm_offset[1] = 0x5008, 679 .reg_mad_dimm_size_mask[0] = GENMASK(7, 0), 680 .reg_mad_dimm_size_mask[1] = GENMASK(15, 8), 681 .reg_mad_dimm_rank_mask[0] = BIT(17), 682 .reg_mad_dimm_rank_mask[1] = BIT(18), 683 .reg_mad_dimm_width_mask[0] = BIT(19), 684 .reg_mad_dimm_width_mask[1] = BIT(20), 685 }; 686 687 static struct res_config skl_cfg = { 688 .mtype = MEM_DDR4, 689 .imc_num = 1, 690 .reg_mchbar_mask = GENMASK_ULL(38, 15), 691 .reg_mchbar_window_size = BIT_ULL(15), 692 .reg_eccerrlog_offset[0] = 0x4048, 693 .reg_eccerrlog_offset[1] = 0x4448, 694 .reg_eccerrlog_ce_mask = BIT_ULL(0), 695 .reg_eccerrlog_ue_mask = BIT_ULL(1), 696 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 697 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 698 .reg_mad_dimm_size_granularity = BIT_ULL(30), 699 .reg_mad_dimm_offset[0] = 0x500c, 700 .reg_mad_dimm_offset[1] = 0x5010, 701 .reg_mad_dimm_size_mask[0] = GENMASK(5, 0), 702 .reg_mad_dimm_size_mask[1] = GENMASK(21, 16), 703 .reg_mad_dimm_rank_mask[0] = BIT(10), 704 .reg_mad_dimm_rank_mask[1] = BIT(26), 705 .reg_mad_dimm_width_mask[0] = GENMASK(9, 8), 706 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24), 707 }; 708 709 struct res_config rpl_s_cfg = { 710 .mtype = MEM_DDR5, 711 .cmci = true, 712 .imc_num = 2, 713 .reg_mchbar_mask = GENMASK_ULL(41, 17), 714 .reg_mchbar_window_size = BIT_ULL(16), 715 .reg_eccerrlog_offset[0] = 0xe048, 716 .reg_eccerrlog_offset[1] = 0xe848, 717 .reg_eccerrlog_ce_mask = BIT_ULL(0), 718 .reg_eccerrlog_ce_ovfl_mask = BIT_ULL(1), 719 .reg_eccerrlog_ue_mask = BIT_ULL(2), 720 .reg_eccerrlog_ue_ovfl_mask = BIT_ULL(3), 721 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 722 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 723 .msr_clear_eccerrlog_offset = 0x791, 724 .reg_mad_dimm_offset[0] = 0xd80c, 725 .reg_mad_dimm_offset[1] = 0xd810, 726 .reg_mad_dimm_size_granularity = BIT_ULL(29), 727 .reg_mad_dimm_size_mask[0] = GENMASK(6, 0), 728 .reg_mad_dimm_size_mask[1] = GENMASK(22, 16), 729 .reg_mad_dimm_rank_mask[0] = GENMASK(10, 9), 730 .reg_mad_dimm_rank_mask[1] = GENMASK(27, 26), 731 .reg_mad_dimm_width_mask[0] = GENMASK(8, 7), 732 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24), 733 }; 734 735 static const struct pci_device_id ie31200_pci_tbl[] = { 736 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_1), (kernel_ulong_t)&snb_cfg }, 737 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_2), (kernel_ulong_t)&snb_cfg }, 738 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_3), (kernel_ulong_t)&snb_cfg }, 739 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_4), (kernel_ulong_t)&snb_cfg }, 740 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_5), (kernel_ulong_t)&snb_cfg }, 741 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_6), (kernel_ulong_t)&snb_cfg }, 742 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_7), (kernel_ulong_t)&snb_cfg }, 743 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_8), (kernel_ulong_t)&skl_cfg }, 744 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_9), (kernel_ulong_t)&skl_cfg }, 745 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_10), (kernel_ulong_t)&skl_cfg }, 746 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_11), (kernel_ulong_t)&skl_cfg }, 747 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_12), (kernel_ulong_t)&skl_cfg }, 748 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1), (kernel_ulong_t)&skl_cfg }, 749 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2), (kernel_ulong_t)&skl_cfg }, 750 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3), (kernel_ulong_t)&skl_cfg }, 751 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4), (kernel_ulong_t)&skl_cfg }, 752 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5), (kernel_ulong_t)&skl_cfg }, 753 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6), (kernel_ulong_t)&skl_cfg }, 754 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7), (kernel_ulong_t)&skl_cfg }, 755 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8), (kernel_ulong_t)&skl_cfg }, 756 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9), (kernel_ulong_t)&skl_cfg }, 757 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10), (kernel_ulong_t)&skl_cfg }, 758 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1), (kernel_ulong_t)&rpl_s_cfg}, 759 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2), (kernel_ulong_t)&rpl_s_cfg}, 760 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3), (kernel_ulong_t)&rpl_s_cfg}, 761 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4), (kernel_ulong_t)&rpl_s_cfg}, 762 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_5), (kernel_ulong_t)&rpl_s_cfg}, 763 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_6), (kernel_ulong_t)&rpl_s_cfg}, 764 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_HX_1), (kernel_ulong_t)&rpl_s_cfg}, 765 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1), (kernel_ulong_t)&rpl_s_cfg}, 766 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_2), (kernel_ulong_t)&rpl_s_cfg}, 767 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_3), (kernel_ulong_t)&rpl_s_cfg}, 768 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_1), (kernel_ulong_t)&rpl_s_cfg}, 769 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_2), (kernel_ulong_t)&rpl_s_cfg}, 770 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_3), (kernel_ulong_t)&rpl_s_cfg}, 771 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_4), (kernel_ulong_t)&rpl_s_cfg}, 772 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_5), (kernel_ulong_t)&rpl_s_cfg}, 773 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_6), (kernel_ulong_t)&rpl_s_cfg}, 774 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_7), (kernel_ulong_t)&rpl_s_cfg}, 775 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_8), (kernel_ulong_t)&rpl_s_cfg}, 776 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_9), (kernel_ulong_t)&rpl_s_cfg}, 777 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_10), (kernel_ulong_t)&rpl_s_cfg}, 778 { 0, } /* 0 terminated list. */ 779 }; 780 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); 781 782 static struct pci_driver ie31200_driver = { 783 .name = EDAC_MOD_STR, 784 .probe = ie31200_init_one, 785 .remove = ie31200_remove_one, 786 .id_table = ie31200_pci_tbl, 787 }; 788 789 static int __init ie31200_init(void) 790 { 791 int pci_rc, i; 792 793 edac_dbg(3, "MC:\n"); 794 795 pci_rc = pci_register_driver(&ie31200_driver); 796 if (pci_rc < 0) 797 return pci_rc; 798 799 if (!mci_pdev) { 800 ie31200_registered = 0; 801 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) { 802 mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor, 803 ie31200_pci_tbl[i].device, 804 NULL); 805 if (mci_pdev) 806 break; 807 } 808 809 if (!mci_pdev) { 810 edac_dbg(0, "ie31200 pci_get_device fail\n"); 811 pci_rc = -ENODEV; 812 goto fail0; 813 } 814 815 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]); 816 if (pci_rc < 0) { 817 edac_dbg(0, "ie31200 init fail\n"); 818 pci_rc = -ENODEV; 819 goto fail1; 820 } 821 } 822 823 return 0; 824 fail1: 825 pci_dev_put(mci_pdev); 826 fail0: 827 pci_unregister_driver(&ie31200_driver); 828 829 return pci_rc; 830 } 831 832 static void __exit ie31200_exit(void) 833 { 834 edac_dbg(3, "MC:\n"); 835 pci_unregister_driver(&ie31200_driver); 836 if (!ie31200_registered) 837 ie31200_remove_one(mci_pdev); 838 } 839 840 module_init(ie31200_init); 841 module_exit(ie31200_exit); 842 843 MODULE_LICENSE("GPL"); 844 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>"); 845 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers"); 846