1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel E3-1200 4 * Copyright (C) 2014 Jason Baron <jbaron@akamai.com> 5 * 6 * Support for the E3-1200 processor family. Heavily based on previous 7 * Intel EDAC drivers. 8 * 9 * Since the DRAM controller is on the cpu chip, we can use its PCI device 10 * id to identify these processors. 11 * 12 * PCI DRAM controller device ids (Taken from The PCI ID Repository - https://pci-ids.ucw.cz/) 13 * 14 * 0108: Xeon E3-1200 Processor Family DRAM Controller 15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller 16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller 18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller 19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller 20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller 21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers 22 * 590f: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 23 * 5918: Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers 24 * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers 25 * 191f: 6th Gen Core Quad-Core Processor Host Bridge/DRAM Registers 26 * 3e..: 8th/9th Gen Core Processor Host Bridge/DRAM Registers 27 * 28 * Based on Intel specification: 29 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf 30 * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html 31 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf 32 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf 33 * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html 34 * https://www.intel.com/content/www/us/en/products/docs/processors/core/8th-gen-core-family-datasheet-vol-2.html 35 * 36 * According to the above datasheet (p.16): 37 * " 38 * 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with 39 * requests that cross a DW boundary. 40 * " 41 * 42 * Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into 43 * 2 readl() calls. This restriction may be lifted in subsequent chip releases, 44 * but lo_hi_readq() ensures that we are safe across all e3-1200 processors. 45 */ 46 47 #include <linux/bitfield.h> 48 #include <linux/module.h> 49 #include <linux/init.h> 50 #include <linux/pci.h> 51 #include <linux/pci_ids.h> 52 #include <linux/edac.h> 53 54 #include <linux/io-64-nonatomic-lo-hi.h> 55 #include <asm/mce.h> 56 #include <asm/msr.h> 57 #include "edac_module.h" 58 59 #define EDAC_MOD_STR "ie31200_edac" 60 61 #define ie31200_printk(level, fmt, arg...) \ 62 edac_printk(level, "ie31200", fmt, ##arg) 63 64 #define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108 65 #define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c 66 #define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150 67 #define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158 68 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c 69 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04 70 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08 71 #define PCI_DEVICE_ID_INTEL_IE31200_HB_8 0x190F 72 #define PCI_DEVICE_ID_INTEL_IE31200_HB_9 0x1918 73 #define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F 74 #define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x590f 75 #define PCI_DEVICE_ID_INTEL_IE31200_HB_12 0x5918 76 77 /* Coffee Lake-S */ 78 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00 79 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1 0x3e0f 80 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2 0x3e18 81 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3 0x3e1f 82 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4 0x3e30 83 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5 0x3e31 84 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6 0x3e32 85 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7 0x3e33 86 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8 0x3ec2 87 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9 0x3ec6 88 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10 0x3eca 89 90 /* Raptor Lake-S */ 91 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1 0xa703 /* 8P+8E, e.g. i7-13700 */ 92 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2 0x4640 /* 6P+8E, e.g. i5-13500, i5-13600, i5-14500 */ 93 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3 0x4630 /* 4P+0E, e.g. i3-13100E */ 94 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4 0xa700 /* 8P+16E, e.g. i9-13900, i9-14900 */ 95 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_5 0xa740 /* 8P+12E, e.g. i7-14700 */ 96 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_S_6 0xa704 /* 6P+8E, e.g. i5-14600 */ 97 98 /* Raptor Lake-HX */ 99 #define PCI_DEVICE_ID_INTEL_IE31200_RPL_HX_1 0xa702 /* 8P+16E, e.g. i9-13950HX */ 100 101 /* Alder Lake-S */ 102 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1 0x4660 103 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_2 0x4668 /* 8P+4E, e.g. i7-12700K */ 104 #define PCI_DEVICE_ID_INTEL_IE31200_ADL_S_3 0x4648 /* 6P+4E, e.g. i5-12600K */ 105 106 /* Bartlett Lake-S */ 107 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_1 0x4639 108 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_2 0x463c 109 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_3 0x4642 110 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_4 0x4643 111 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_5 0xa731 112 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_6 0xa732 113 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_7 0xa733 114 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_8 0xa741 115 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_9 0xa744 116 #define PCI_DEVICE_ID_INTEL_IE31200_BTL_S_10 0xa745 117 118 #define IE31200_RANKS_PER_CHANNEL 8 119 #define IE31200_DIMMS_PER_CHANNEL 2 120 #define IE31200_CHANNELS 2 121 #define IE31200_IMC_NUM 2 122 123 /* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */ 124 #define IE31200_MCHBAR_LOW 0x48 125 #define IE31200_MCHBAR_HIGH 0x4c 126 127 /* 128 * Error Status Register (16b) 129 * 130 * 1 Multi-bit DRAM ECC Error Flag (DMERR) 131 * 0 Single-bit DRAM ECC Error Flag (DSERR) 132 */ 133 #define IE31200_ERRSTS 0xc8 134 #define IE31200_ERRSTS_UE BIT(1) 135 #define IE31200_ERRSTS_CE BIT(0) 136 #define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE) 137 138 #define IE31200_CAPID0 0xe4 139 #define IE31200_CAPID0_PDCD BIT(4) 140 #define IE31200_CAPID0_DDPCD BIT(6) 141 #define IE31200_CAPID0_ECC BIT(1) 142 143 static int nr_channels; 144 static struct pci_dev *mci_pdev; 145 static int ie31200_registered = 1; 146 147 struct res_config { 148 enum mem_type mtype; 149 bool cmci; 150 int imc_num; 151 /* Host MMIO configuration register */ 152 u64 reg_mchbar_mask; 153 u64 reg_mchbar_window_size; 154 /* ECC error log register */ 155 u64 reg_eccerrlog_offset[IE31200_CHANNELS]; 156 u64 reg_eccerrlog_ce_mask; 157 u64 reg_eccerrlog_ce_ovfl_mask; 158 u64 reg_eccerrlog_ue_mask; 159 u64 reg_eccerrlog_ue_ovfl_mask; 160 u64 reg_eccerrlog_rank_mask; 161 u64 reg_eccerrlog_syndrome_mask; 162 /* MSR to clear ECC error log register */ 163 u32 msr_clear_eccerrlog_offset; 164 /* DIMM characteristics register */ 165 u64 reg_mad_dimm_size_granularity; 166 u64 reg_mad_dimm_offset[IE31200_CHANNELS]; 167 u32 reg_mad_dimm_size_mask[IE31200_DIMMS_PER_CHANNEL]; 168 u32 reg_mad_dimm_rank_mask[IE31200_DIMMS_PER_CHANNEL]; 169 u32 reg_mad_dimm_width_mask[IE31200_DIMMS_PER_CHANNEL]; 170 }; 171 172 struct ie31200_priv { 173 void __iomem *window; 174 void __iomem *c0errlog; 175 void __iomem *c1errlog; 176 struct res_config *cfg; 177 struct mem_ctl_info *mci; 178 struct pci_dev *pdev; 179 struct device dev; 180 }; 181 182 static struct ie31200_pvt { 183 struct ie31200_priv *priv[IE31200_IMC_NUM]; 184 } ie31200_pvt; 185 186 enum ie31200_chips { 187 IE31200 = 0, 188 IE31200_1 = 1, 189 }; 190 191 struct ie31200_dev_info { 192 const char *ctl_name; 193 }; 194 195 struct ie31200_error_info { 196 u16 errsts; 197 u16 errsts2; 198 u64 eccerrlog[IE31200_CHANNELS]; 199 u64 erraddr; 200 }; 201 202 static const struct ie31200_dev_info ie31200_devs[] = { 203 [IE31200] = { 204 .ctl_name = "IE31200" 205 }, 206 [IE31200_1] = { 207 .ctl_name = "IE31200_1" 208 }, 209 }; 210 211 struct dimm_data { 212 u64 size; /* in bytes */ 213 u8 ranks; 214 enum dev_type dtype; 215 }; 216 217 static int how_many_channels(struct pci_dev *pdev) 218 { 219 int n_channels; 220 unsigned char capid0_2b; /* 2nd byte of CAPID0 */ 221 222 pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b); 223 224 /* check PDCD: Dual Channel Disable */ 225 if (capid0_2b & IE31200_CAPID0_PDCD) { 226 edac_dbg(0, "In single channel mode\n"); 227 n_channels = 1; 228 } else { 229 edac_dbg(0, "In dual channel mode\n"); 230 n_channels = 2; 231 } 232 233 /* check DDPCD - check if both channels are filled */ 234 if (capid0_2b & IE31200_CAPID0_DDPCD) 235 edac_dbg(0, "2 DIMMS per channel disabled\n"); 236 else 237 edac_dbg(0, "2 DIMMS per channel enabled\n"); 238 239 return n_channels; 240 } 241 242 static bool ecc_capable(struct pci_dev *pdev) 243 { 244 unsigned char capid0_4b; /* 4th byte of CAPID0 */ 245 246 pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b); 247 if (capid0_4b & IE31200_CAPID0_ECC) 248 return false; 249 return true; 250 } 251 252 #define mci_to_pci_dev(mci) (((struct ie31200_priv *)(mci)->pvt_info)->pdev) 253 254 static void ie31200_clear_error_info(struct mem_ctl_info *mci) 255 { 256 struct ie31200_priv *priv = mci->pvt_info; 257 struct res_config *cfg = priv->cfg; 258 259 /* 260 * The PCI ERRSTS register is deprecated. Write the MSR to clear 261 * the ECC error log registers in all memory controllers. 262 */ 263 if (cfg->msr_clear_eccerrlog_offset) { 264 if (wrmsrq_safe(cfg->msr_clear_eccerrlog_offset, 265 cfg->reg_eccerrlog_ce_mask | 266 cfg->reg_eccerrlog_ce_ovfl_mask | 267 cfg->reg_eccerrlog_ue_mask | 268 cfg->reg_eccerrlog_ue_ovfl_mask) < 0) 269 ie31200_printk(KERN_ERR, "Failed to wrmsr.\n"); 270 271 return; 272 } 273 274 /* 275 * Clear any error bits. 276 * (Yes, we really clear bits by writing 1 to them.) 277 */ 278 pci_write_bits16(mci_to_pci_dev(mci), IE31200_ERRSTS, 279 IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS); 280 } 281 282 static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci, 283 struct ie31200_error_info *info) 284 { 285 struct pci_dev *pdev = mci_to_pci_dev(mci); 286 struct ie31200_priv *priv = mci->pvt_info; 287 288 /* 289 * The PCI ERRSTS register is deprecated, directly read the 290 * MMIO-mapped ECC error log registers. 291 */ 292 if (priv->cfg->msr_clear_eccerrlog_offset) { 293 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 294 if (nr_channels == 2) 295 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 296 297 ie31200_clear_error_info(mci); 298 return; 299 } 300 301 /* 302 * This is a mess because there is no atomic way to read all the 303 * registers at once and the registers can transition from CE being 304 * overwritten by UE. 305 */ 306 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts); 307 if (!(info->errsts & IE31200_ERRSTS_BITS)) 308 return; 309 310 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 311 if (nr_channels == 2) 312 info->eccerrlog[1] = lo_hi_readq(priv->c1errlog); 313 314 pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2); 315 316 /* 317 * If the error is the same for both reads then the first set 318 * of reads is valid. If there is a change then there is a CE 319 * with no info and the second set of reads is valid and 320 * should be UE info. 321 */ 322 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 323 info->eccerrlog[0] = lo_hi_readq(priv->c0errlog); 324 if (nr_channels == 2) 325 info->eccerrlog[1] = 326 lo_hi_readq(priv->c1errlog); 327 } 328 329 ie31200_clear_error_info(mci); 330 } 331 332 static void ie31200_process_error_info(struct mem_ctl_info *mci, 333 struct ie31200_error_info *info) 334 { 335 struct ie31200_priv *priv = mci->pvt_info; 336 struct res_config *cfg = priv->cfg; 337 int channel; 338 u64 log; 339 340 if (!cfg->msr_clear_eccerrlog_offset) { 341 if (!(info->errsts & IE31200_ERRSTS_BITS)) 342 return; 343 344 if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) { 345 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 346 -1, -1, -1, "UE overwrote CE", ""); 347 info->errsts = info->errsts2; 348 } 349 } 350 351 for (channel = 0; channel < nr_channels; channel++) { 352 log = info->eccerrlog[channel]; 353 if (log & cfg->reg_eccerrlog_ue_mask) { 354 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 355 info->erraddr >> PAGE_SHIFT, 0, 0, 356 field_get(cfg->reg_eccerrlog_rank_mask, log), 357 channel, -1, 358 "ie31200 UE", ""); 359 } else if (log & cfg->reg_eccerrlog_ce_mask) { 360 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 361 info->erraddr >> PAGE_SHIFT, 0, 362 field_get(cfg->reg_eccerrlog_syndrome_mask, log), 363 field_get(cfg->reg_eccerrlog_rank_mask, log), 364 channel, -1, 365 "ie31200 CE", ""); 366 } 367 } 368 } 369 370 static void __ie31200_check(struct mem_ctl_info *mci, struct mce *mce) 371 { 372 struct ie31200_error_info info; 373 374 info.erraddr = mce ? mce->addr : 0; 375 ie31200_get_and_clear_error_info(mci, &info); 376 ie31200_process_error_info(mci, &info); 377 } 378 379 static void ie31200_check(struct mem_ctl_info *mci) 380 { 381 __ie31200_check(mci, NULL); 382 } 383 384 static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev, struct res_config *cfg, int mc) 385 { 386 union { 387 u64 mchbar; 388 struct { 389 u32 mchbar_low; 390 u32 mchbar_high; 391 }; 392 } u; 393 void __iomem *window; 394 395 pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low); 396 pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high); 397 u.mchbar &= cfg->reg_mchbar_mask; 398 u.mchbar += cfg->reg_mchbar_window_size * mc; 399 400 if (u.mchbar != (resource_size_t)u.mchbar) { 401 ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n", 402 (unsigned long long)u.mchbar); 403 return NULL; 404 } 405 406 window = ioremap(u.mchbar, cfg->reg_mchbar_window_size); 407 if (!window) 408 ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n", 409 (unsigned long long)u.mchbar); 410 411 return window; 412 } 413 414 static void populate_dimm_info(struct dimm_data *dd, u32 addr_decode, int dimm, 415 struct res_config *cfg) 416 { 417 dd->size = field_get(cfg->reg_mad_dimm_size_mask[dimm], addr_decode) * cfg->reg_mad_dimm_size_granularity; 418 dd->ranks = field_get(cfg->reg_mad_dimm_rank_mask[dimm], addr_decode) + 1; 419 420 switch (field_get(cfg->reg_mad_dimm_width_mask[dimm], addr_decode)) { 421 case 0: 422 dd->dtype = DEV_X8; 423 break; 424 case 1: 425 dd->dtype = DEV_X16; 426 break; 427 case 2: 428 dd->dtype = DEV_X32; 429 break; 430 case 3: 431 dd->dtype = DEV_X64; 432 break; 433 default: 434 dd->dtype = DEV_UNKNOWN; 435 } 436 } 437 438 static void ie31200_get_dimm_config(struct mem_ctl_info *mci, void __iomem *window, 439 struct res_config *cfg, int mc) 440 { 441 struct dimm_data dimm_info; 442 struct dimm_info *dimm; 443 unsigned long nr_pages; 444 u32 addr_decode; 445 int i, j, k; 446 447 for (i = 0; i < IE31200_CHANNELS; i++) { 448 addr_decode = readl(window + cfg->reg_mad_dimm_offset[i]); 449 edac_dbg(0, "addr_decode: 0x%x\n", addr_decode); 450 451 for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) { 452 populate_dimm_info(&dimm_info, addr_decode, j, cfg); 453 edac_dbg(0, "mc: %d, channel: %d, dimm: %d, size: %lld MiB, ranks: %d, DRAM chip type: %d\n", 454 mc, i, j, dimm_info.size >> 20, 455 dimm_info.ranks, 456 dimm_info.dtype); 457 458 nr_pages = MiB_TO_PAGES(dimm_info.size >> 20); 459 if (nr_pages == 0) 460 continue; 461 462 nr_pages = nr_pages / dimm_info.ranks; 463 for (k = 0; k < dimm_info.ranks; k++) { 464 dimm = edac_get_dimm(mci, (j * dimm_info.ranks) + k, i, 0); 465 dimm->nr_pages = nr_pages; 466 edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages); 467 dimm->grain = 8; /* just a guess */ 468 dimm->mtype = cfg->mtype; 469 dimm->dtype = dimm_info.dtype; 470 dimm->edac_mode = EDAC_UNKNOWN; 471 } 472 } 473 } 474 } 475 476 static int ie31200_register_mci(struct pci_dev *pdev, struct res_config *cfg, int mc) 477 { 478 struct edac_mc_layer layers[2]; 479 struct ie31200_priv *priv; 480 struct mem_ctl_info *mci; 481 void __iomem *window; 482 int ret; 483 484 nr_channels = how_many_channels(pdev); 485 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 486 layers[0].size = IE31200_RANKS_PER_CHANNEL; 487 layers[0].is_virt_csrow = true; 488 layers[1].type = EDAC_MC_LAYER_CHANNEL; 489 layers[1].size = nr_channels; 490 layers[1].is_virt_csrow = false; 491 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, 492 sizeof(struct ie31200_priv)); 493 if (!mci) 494 return -ENOMEM; 495 496 window = ie31200_map_mchbar(pdev, cfg, mc); 497 if (!window) { 498 ret = -ENODEV; 499 goto fail_free; 500 } 501 502 edac_dbg(3, "MC: init mci\n"); 503 mci->mtype_cap = BIT(cfg->mtype); 504 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 505 mci->edac_cap = EDAC_FLAG_SECDED; 506 mci->mod_name = EDAC_MOD_STR; 507 mci->ctl_name = ie31200_devs[mc].ctl_name; 508 mci->dev_name = pci_name(pdev); 509 mci->edac_check = cfg->cmci ? NULL : ie31200_check; 510 mci->ctl_page_to_phys = NULL; 511 priv = mci->pvt_info; 512 priv->window = window; 513 priv->c0errlog = window + cfg->reg_eccerrlog_offset[0]; 514 priv->c1errlog = window + cfg->reg_eccerrlog_offset[1]; 515 priv->cfg = cfg; 516 priv->mci = mci; 517 priv->pdev = pdev; 518 device_initialize(&priv->dev); 519 /* 520 * The EDAC core uses mci->pdev (pointer to the structure device) 521 * as the memory controller ID. The SoCs attach one or more memory 522 * controllers to a single pci_dev (a single pci_dev->dev can 523 * correspond to multiple memory controllers). 524 * 525 * To make mci->pdev unique, assign pci_dev->dev to mci->pdev 526 * for the first memory controller and assign a unique priv->dev 527 * to mci->pdev for each additional memory controller. 528 */ 529 mci->pdev = mc ? &priv->dev : &pdev->dev; 530 531 ie31200_get_dimm_config(mci, window, cfg, mc); 532 ie31200_clear_error_info(mci); 533 534 if (edac_mc_add_mc(mci)) { 535 edac_dbg(3, "MC: failed edac_mc_add_mc()\n"); 536 ret = -ENODEV; 537 goto fail_unmap; 538 } 539 540 ie31200_pvt.priv[mc] = priv; 541 return 0; 542 fail_unmap: 543 put_device(&priv->dev); 544 iounmap(window); 545 fail_free: 546 edac_mc_free(mci); 547 return ret; 548 } 549 550 static void mce_check(struct mce *mce) 551 { 552 struct ie31200_priv *priv; 553 int i; 554 555 for (i = 0; i < IE31200_IMC_NUM; i++) { 556 priv = ie31200_pvt.priv[i]; 557 if (!priv) 558 continue; 559 560 __ie31200_check(priv->mci, mce); 561 } 562 } 563 564 static int mce_handler(struct notifier_block *nb, unsigned long val, void *data) 565 { 566 struct mce *mce = (struct mce *)data; 567 char *type; 568 569 if (mce->kflags & MCE_HANDLED_CEC) 570 return NOTIFY_DONE; 571 572 /* 573 * Ignore unless this is a memory related error. 574 * Don't check MCI_STATUS_ADDRV since it's not set on some CPUs. 575 */ 576 if ((mce->status & 0xefff) >> 7 != 1) 577 return NOTIFY_DONE; 578 579 type = mce->mcgstatus & MCG_STATUS_MCIP ? "Exception" : "Event"; 580 581 edac_dbg(0, "CPU %d: Machine Check %s: 0x%llx Bank %d: 0x%llx\n", 582 mce->extcpu, type, mce->mcgstatus, 583 mce->bank, mce->status); 584 edac_dbg(0, "TSC 0x%llx\n", mce->tsc); 585 edac_dbg(0, "ADDR 0x%llx\n", mce->addr); 586 edac_dbg(0, "MISC 0x%llx\n", mce->misc); 587 edac_dbg(0, "PROCESSOR %u:0x%x TIME %llu SOCKET %u APIC 0x%x\n", 588 mce->cpuvendor, mce->cpuid, mce->time, 589 mce->socketid, mce->apicid); 590 591 mce_check(mce); 592 mce->kflags |= MCE_HANDLED_EDAC; 593 594 return NOTIFY_DONE; 595 } 596 597 static struct notifier_block ie31200_mce_dec = { 598 .notifier_call = mce_handler, 599 .priority = MCE_PRIO_EDAC, 600 }; 601 602 static void ie31200_unregister_mcis(void) 603 { 604 struct ie31200_priv *priv; 605 struct mem_ctl_info *mci; 606 int i; 607 608 for (i = 0; i < IE31200_IMC_NUM; i++) { 609 priv = ie31200_pvt.priv[i]; 610 if (!priv) 611 continue; 612 613 mci = priv->mci; 614 edac_mc_del_mc(mci->pdev); 615 iounmap(priv->window); 616 put_device(&priv->dev); 617 edac_mc_free(mci); 618 } 619 } 620 621 static int ie31200_probe1(struct pci_dev *pdev, struct res_config *cfg) 622 { 623 int i, ret; 624 625 edac_dbg(0, "MC:\n"); 626 627 if (!ecc_capable(pdev)) { 628 ie31200_printk(KERN_INFO, "No ECC support\n"); 629 return -ENODEV; 630 } 631 632 for (i = 0; i < cfg->imc_num; i++) { 633 ret = ie31200_register_mci(pdev, cfg, i); 634 if (ret) 635 goto fail_register; 636 } 637 638 if (cfg->cmci) { 639 mce_register_decode_chain(&ie31200_mce_dec); 640 edac_op_state = EDAC_OPSTATE_INT; 641 } else { 642 edac_op_state = EDAC_OPSTATE_POLL; 643 } 644 645 /* get this far and it's successful. */ 646 edac_dbg(3, "MC: success\n"); 647 return 0; 648 649 fail_register: 650 ie31200_unregister_mcis(); 651 return ret; 652 } 653 654 static int ie31200_init_one(struct pci_dev *pdev, 655 const struct pci_device_id *ent) 656 { 657 int rc; 658 659 edac_dbg(0, "MC:\n"); 660 if (pci_enable_device(pdev) < 0) 661 return -EIO; 662 rc = ie31200_probe1(pdev, (struct res_config *)ent->driver_data); 663 if (rc == 0 && !mci_pdev) 664 mci_pdev = pci_dev_get(pdev); 665 666 return rc; 667 } 668 669 static void ie31200_remove_one(struct pci_dev *pdev) 670 { 671 struct ie31200_priv *priv = ie31200_pvt.priv[0]; 672 673 edac_dbg(0, "\n"); 674 pci_dev_put(mci_pdev); 675 mci_pdev = NULL; 676 if (priv->cfg->cmci) 677 mce_unregister_decode_chain(&ie31200_mce_dec); 678 ie31200_unregister_mcis(); 679 } 680 681 static struct res_config snb_cfg = { 682 .mtype = MEM_DDR3, 683 .imc_num = 1, 684 .reg_mchbar_mask = GENMASK_ULL(38, 15), 685 .reg_mchbar_window_size = BIT_ULL(15), 686 .reg_eccerrlog_offset[0] = 0x40c8, 687 .reg_eccerrlog_offset[1] = 0x44c8, 688 .reg_eccerrlog_ce_mask = BIT_ULL(0), 689 .reg_eccerrlog_ue_mask = BIT_ULL(1), 690 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 691 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 692 .reg_mad_dimm_size_granularity = BIT_ULL(28), 693 .reg_mad_dimm_offset[0] = 0x5004, 694 .reg_mad_dimm_offset[1] = 0x5008, 695 .reg_mad_dimm_size_mask[0] = GENMASK(7, 0), 696 .reg_mad_dimm_size_mask[1] = GENMASK(15, 8), 697 .reg_mad_dimm_rank_mask[0] = BIT(17), 698 .reg_mad_dimm_rank_mask[1] = BIT(18), 699 .reg_mad_dimm_width_mask[0] = BIT(19), 700 .reg_mad_dimm_width_mask[1] = BIT(20), 701 }; 702 703 static struct res_config skl_cfg = { 704 .mtype = MEM_DDR4, 705 .imc_num = 1, 706 .reg_mchbar_mask = GENMASK_ULL(38, 15), 707 .reg_mchbar_window_size = BIT_ULL(15), 708 .reg_eccerrlog_offset[0] = 0x4048, 709 .reg_eccerrlog_offset[1] = 0x4448, 710 .reg_eccerrlog_ce_mask = BIT_ULL(0), 711 .reg_eccerrlog_ue_mask = BIT_ULL(1), 712 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 713 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 714 .reg_mad_dimm_size_granularity = BIT_ULL(30), 715 .reg_mad_dimm_offset[0] = 0x500c, 716 .reg_mad_dimm_offset[1] = 0x5010, 717 .reg_mad_dimm_size_mask[0] = GENMASK(5, 0), 718 .reg_mad_dimm_size_mask[1] = GENMASK(21, 16), 719 .reg_mad_dimm_rank_mask[0] = BIT(10), 720 .reg_mad_dimm_rank_mask[1] = BIT(26), 721 .reg_mad_dimm_width_mask[0] = GENMASK(9, 8), 722 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24), 723 }; 724 725 static struct res_config rpl_s_cfg = { 726 .mtype = MEM_DDR5, 727 .cmci = true, 728 .imc_num = 2, 729 .reg_mchbar_mask = GENMASK_ULL(41, 17), 730 .reg_mchbar_window_size = BIT_ULL(16), 731 .reg_eccerrlog_offset[0] = 0xe048, 732 .reg_eccerrlog_offset[1] = 0xe848, 733 .reg_eccerrlog_ce_mask = BIT_ULL(0), 734 .reg_eccerrlog_ce_ovfl_mask = BIT_ULL(1), 735 .reg_eccerrlog_ue_mask = BIT_ULL(2), 736 .reg_eccerrlog_ue_ovfl_mask = BIT_ULL(3), 737 .reg_eccerrlog_rank_mask = GENMASK_ULL(28, 27), 738 .reg_eccerrlog_syndrome_mask = GENMASK_ULL(23, 16), 739 .msr_clear_eccerrlog_offset = 0x791, 740 .reg_mad_dimm_offset[0] = 0xd80c, 741 .reg_mad_dimm_offset[1] = 0xd810, 742 .reg_mad_dimm_size_granularity = BIT_ULL(29), 743 .reg_mad_dimm_size_mask[0] = GENMASK(6, 0), 744 .reg_mad_dimm_size_mask[1] = GENMASK(22, 16), 745 .reg_mad_dimm_rank_mask[0] = GENMASK(10, 9), 746 .reg_mad_dimm_rank_mask[1] = GENMASK(27, 26), 747 .reg_mad_dimm_width_mask[0] = GENMASK(8, 7), 748 .reg_mad_dimm_width_mask[1] = GENMASK(25, 24), 749 }; 750 751 static const struct pci_device_id ie31200_pci_tbl[] = { 752 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_1), .driver_data = (kernel_ulong_t)&snb_cfg }, 753 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_2), .driver_data = (kernel_ulong_t)&snb_cfg }, 754 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_3), .driver_data = (kernel_ulong_t)&snb_cfg }, 755 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_4), .driver_data = (kernel_ulong_t)&snb_cfg }, 756 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_5), .driver_data = (kernel_ulong_t)&snb_cfg }, 757 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_6), .driver_data = (kernel_ulong_t)&snb_cfg }, 758 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_7), .driver_data = (kernel_ulong_t)&snb_cfg }, 759 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_8), .driver_data = (kernel_ulong_t)&skl_cfg }, 760 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_9), .driver_data = (kernel_ulong_t)&skl_cfg }, 761 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_10), .driver_data = (kernel_ulong_t)&skl_cfg }, 762 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_11), .driver_data = (kernel_ulong_t)&skl_cfg }, 763 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_12), .driver_data = (kernel_ulong_t)&skl_cfg }, 764 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1), .driver_data = (kernel_ulong_t)&skl_cfg }, 765 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2), .driver_data = (kernel_ulong_t)&skl_cfg }, 766 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3), .driver_data = (kernel_ulong_t)&skl_cfg }, 767 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4), .driver_data = (kernel_ulong_t)&skl_cfg }, 768 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5), .driver_data = (kernel_ulong_t)&skl_cfg }, 769 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6), .driver_data = (kernel_ulong_t)&skl_cfg }, 770 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7), .driver_data = (kernel_ulong_t)&skl_cfg }, 771 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8), .driver_data = (kernel_ulong_t)&skl_cfg }, 772 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9), .driver_data = (kernel_ulong_t)&skl_cfg }, 773 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10), .driver_data = (kernel_ulong_t)&skl_cfg }, 774 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_1), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 775 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_2), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 776 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_3), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 777 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_4), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 778 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_5), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 779 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_S_6), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 780 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_RPL_HX_1), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 781 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_1), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 782 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_2), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 783 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_ADL_S_3), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 784 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_1), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 785 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_2), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 786 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_3), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 787 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_4), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 788 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_5), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 789 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_6), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 790 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_7), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 791 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_8), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 792 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_9), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 793 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_IE31200_BTL_S_10), .driver_data = (kernel_ulong_t)&rpl_s_cfg }, 794 { } /* 0 terminated list. */ 795 }; 796 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl); 797 798 static struct pci_driver ie31200_driver = { 799 .name = EDAC_MOD_STR, 800 .probe = ie31200_init_one, 801 .remove = ie31200_remove_one, 802 .id_table = ie31200_pci_tbl, 803 }; 804 805 static int __init ie31200_init(void) 806 { 807 int pci_rc, i; 808 809 edac_dbg(3, "MC:\n"); 810 811 pci_rc = pci_register_driver(&ie31200_driver); 812 if (pci_rc < 0) 813 return pci_rc; 814 815 if (!mci_pdev) { 816 ie31200_registered = 0; 817 for (i = 0; ie31200_pci_tbl[i].vendor != 0; i++) { 818 mci_pdev = pci_get_device(ie31200_pci_tbl[i].vendor, 819 ie31200_pci_tbl[i].device, 820 NULL); 821 if (mci_pdev) 822 break; 823 } 824 825 if (!mci_pdev) { 826 edac_dbg(0, "ie31200 pci_get_device fail\n"); 827 pci_rc = -ENODEV; 828 goto fail0; 829 } 830 831 pci_rc = ie31200_init_one(mci_pdev, &ie31200_pci_tbl[i]); 832 if (pci_rc < 0) { 833 edac_dbg(0, "ie31200 init fail\n"); 834 pci_rc = -ENODEV; 835 goto fail1; 836 } 837 } 838 839 return 0; 840 fail1: 841 pci_dev_put(mci_pdev); 842 fail0: 843 pci_unregister_driver(&ie31200_driver); 844 845 return pci_rc; 846 } 847 848 static void __exit ie31200_exit(void) 849 { 850 edac_dbg(3, "MC:\n"); 851 pci_unregister_driver(&ie31200_driver); 852 if (!ie31200_registered) 853 ie31200_remove_one(mci_pdev); 854 } 855 856 module_init(ie31200_init); 857 module_exit(ie31200_exit); 858 859 MODULE_LICENSE("GPL"); 860 MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>"); 861 MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers"); 862