xref: /linux/drivers/edac/i82875p_edac.c (revision 60e13231561b3a4c5269bfa1ef6c0569ad6f28ec)
1 /*
2  * Intel D82875P Memory Controller kernel module
3  * (C) 2003 Linux Networx (http://lnxi.com)
4  * This file may be distributed under the terms of the
5  * GNU General Public License.
6  *
7  * Written by Thayne Harbaugh
8  * Contributors:
9  *	Wang Zhenyu at intel.com
10  *
11  * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
12  *
13  * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
14  */
15 
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/pci_ids.h>
20 #include <linux/edac.h>
21 #include "edac_core.h"
22 
23 #define I82875P_REVISION	" Ver: 2.0.2"
24 #define EDAC_MOD_STR		"i82875p_edac"
25 
26 #define i82875p_printk(level, fmt, arg...) \
27 	edac_printk(level, "i82875p", fmt, ##arg)
28 
29 #define i82875p_mc_printk(mci, level, fmt, arg...) \
30 	edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
31 
32 #ifndef PCI_DEVICE_ID_INTEL_82875_0
33 #define PCI_DEVICE_ID_INTEL_82875_0	0x2578
34 #endif				/* PCI_DEVICE_ID_INTEL_82875_0 */
35 
36 #ifndef PCI_DEVICE_ID_INTEL_82875_6
37 #define PCI_DEVICE_ID_INTEL_82875_6	0x257e
38 #endif				/* PCI_DEVICE_ID_INTEL_82875_6 */
39 
40 /* four csrows in dual channel, eight in single channel */
41 #define I82875P_NR_CSROWS(nr_chans) (8/(nr_chans))
42 
43 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
44 #define I82875P_EAP		0x58	/* Error Address Pointer (32b)
45 					 *
46 					 * 31:12 block address
47 					 * 11:0  reserved
48 					 */
49 
50 #define I82875P_DERRSYN		0x5c	/* DRAM Error Syndrome (8b)
51 					 *
52 					 *  7:0  DRAM ECC Syndrome
53 					 */
54 
55 #define I82875P_DES		0x5d	/* DRAM Error Status (8b)
56 					 *
57 					 *  7:1  reserved
58 					 *  0    Error channel 0/1
59 					 */
60 
61 #define I82875P_ERRSTS		0xc8	/* Error Status Register (16b)
62 					 *
63 					 * 15:10 reserved
64 					 *  9    non-DRAM lock error (ndlock)
65 					 *  8    Sftwr Generated SMI
66 					 *  7    ECC UE
67 					 *  6    reserved
68 					 *  5    MCH detects unimplemented cycle
69 					 *  4    AGP access outside GA
70 					 *  3    Invalid AGP access
71 					 *  2    Invalid GA translation table
72 					 *  1    Unsupported AGP command
73 					 *  0    ECC CE
74 					 */
75 
76 #define I82875P_ERRCMD		0xca	/* Error Command (16b)
77 					 *
78 					 * 15:10 reserved
79 					 *  9    SERR on non-DRAM lock
80 					 *  8    SERR on ECC UE
81 					 *  7    SERR on ECC CE
82 					 *  6    target abort on high exception
83 					 *  5    detect unimplemented cyc
84 					 *  4    AGP access outside of GA
85 					 *  3    SERR on invalid AGP access
86 					 *  2    invalid translation table
87 					 *  1    SERR on unsupported AGP command
88 					 *  0    reserved
89 					 */
90 
91 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
92 #define I82875P_PCICMD6		0x04	/* PCI Command Register (16b)
93 					 *
94 					 * 15:10 reserved
95 					 *  9    fast back-to-back - ro 0
96 					 *  8    SERR enable - ro 0
97 					 *  7    addr/data stepping - ro 0
98 					 *  6    parity err enable - ro 0
99 					 *  5    VGA palette snoop - ro 0
100 					 *  4    mem wr & invalidate - ro 0
101 					 *  3    special cycle - ro 0
102 					 *  2    bus master - ro 0
103 					 *  1    mem access dev6 - 0(dis),1(en)
104 					 *  0    IO access dev3 - 0(dis),1(en)
105 					 */
106 
107 #define I82875P_BAR6		0x10	/* Mem Delays Base ADDR Reg (32b)
108 					 *
109 					 * 31:12 mem base addr [31:12]
110 					 * 11:4  address mask - ro 0
111 					 *  3    prefetchable - ro 0(non),1(pre)
112 					 *  2:1  mem type - ro 0
113 					 *  0    mem space - ro 0
114 					 */
115 
116 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
117 
118 #define I82875P_DRB_SHIFT 26	/* 64MiB grain */
119 #define I82875P_DRB		0x00	/* DRAM Row Boundary (8b x 8)
120 					 *
121 					 *  7    reserved
122 					 *  6:0  64MiB row boundary addr
123 					 */
124 
125 #define I82875P_DRA		0x10	/* DRAM Row Attribute (4b x 8)
126 					 *
127 					 *  7    reserved
128 					 *  6:4  row attr row 1
129 					 *  3    reserved
130 					 *  2:0  row attr row 0
131 					 *
132 					 * 000 =  4KiB
133 					 * 001 =  8KiB
134 					 * 010 = 16KiB
135 					 * 011 = 32KiB
136 					 */
137 
138 #define I82875P_DRC		0x68	/* DRAM Controller Mode (32b)
139 					 *
140 					 * 31:30 reserved
141 					 * 29    init complete
142 					 * 28:23 reserved
143 					 * 22:21 nr chan 00=1,01=2
144 					 * 20    reserved
145 					 * 19:18 Data Integ Mode 00=none,01=ecc
146 					 * 17:11 reserved
147 					 * 10:8  refresh mode
148 					 *  7    reserved
149 					 *  6:4  mode select
150 					 *  3:2  reserved
151 					 *  1:0  DRAM type 01=DDR
152 					 */
153 
154 enum i82875p_chips {
155 	I82875P = 0,
156 };
157 
158 struct i82875p_pvt {
159 	struct pci_dev *ovrfl_pdev;
160 	void __iomem *ovrfl_window;
161 };
162 
163 struct i82875p_dev_info {
164 	const char *ctl_name;
165 };
166 
167 struct i82875p_error_info {
168 	u16 errsts;
169 	u32 eap;
170 	u8 des;
171 	u8 derrsyn;
172 	u16 errsts2;
173 };
174 
175 static const struct i82875p_dev_info i82875p_devs[] = {
176 	[I82875P] = {
177 		.ctl_name = "i82875p"},
178 };
179 
180 static struct pci_dev *mci_pdev;	/* init dev: in case that AGP code has
181 					 * already registered driver
182 					 */
183 
184 static struct edac_pci_ctl_info *i82875p_pci;
185 
186 static void i82875p_get_error_info(struct mem_ctl_info *mci,
187 				struct i82875p_error_info *info)
188 {
189 	struct pci_dev *pdev;
190 
191 	pdev = to_pci_dev(mci->dev);
192 
193 	/*
194 	 * This is a mess because there is no atomic way to read all the
195 	 * registers at once and the registers can transition from CE being
196 	 * overwritten by UE.
197 	 */
198 	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts);
199 
200 	if (!(info->errsts & 0x0081))
201 		return;
202 
203 	pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
204 	pci_read_config_byte(pdev, I82875P_DES, &info->des);
205 	pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
206 	pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2);
207 
208 	/*
209 	 * If the error is the same then we can for both reads then
210 	 * the first set of reads is valid.  If there is a change then
211 	 * there is a CE no info and the second set of reads is valid
212 	 * and should be UE info.
213 	 */
214 	if ((info->errsts ^ info->errsts2) & 0x0081) {
215 		pci_read_config_dword(pdev, I82875P_EAP, &info->eap);
216 		pci_read_config_byte(pdev, I82875P_DES, &info->des);
217 		pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn);
218 	}
219 
220 	pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081);
221 }
222 
223 static int i82875p_process_error_info(struct mem_ctl_info *mci,
224 				struct i82875p_error_info *info,
225 				int handle_errors)
226 {
227 	int row, multi_chan;
228 
229 	multi_chan = mci->csrows[0].nr_channels - 1;
230 
231 	if (!(info->errsts & 0x0081))
232 		return 0;
233 
234 	if (!handle_errors)
235 		return 1;
236 
237 	if ((info->errsts ^ info->errsts2) & 0x0081) {
238 		edac_mc_handle_ce_no_info(mci, "UE overwrote CE");
239 		info->errsts = info->errsts2;
240 	}
241 
242 	info->eap >>= PAGE_SHIFT;
243 	row = edac_mc_find_csrow_by_page(mci, info->eap);
244 
245 	if (info->errsts & 0x0080)
246 		edac_mc_handle_ue(mci, info->eap, 0, row, "i82875p UE");
247 	else
248 		edac_mc_handle_ce(mci, info->eap, 0, info->derrsyn, row,
249 				multi_chan ? (info->des & 0x1) : 0,
250 				"i82875p CE");
251 
252 	return 1;
253 }
254 
255 static void i82875p_check(struct mem_ctl_info *mci)
256 {
257 	struct i82875p_error_info info;
258 
259 	debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
260 	i82875p_get_error_info(mci, &info);
261 	i82875p_process_error_info(mci, &info, 1);
262 }
263 
264 /* Return 0 on success or 1 on failure. */
265 static int i82875p_setup_overfl_dev(struct pci_dev *pdev,
266 				struct pci_dev **ovrfl_pdev,
267 				void __iomem **ovrfl_window)
268 {
269 	struct pci_dev *dev;
270 	void __iomem *window;
271 	int err;
272 
273 	*ovrfl_pdev = NULL;
274 	*ovrfl_window = NULL;
275 	dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
276 
277 	if (dev == NULL) {
278 		/* Intel tells BIOS developers to hide device 6 which
279 		 * configures the overflow device access containing
280 		 * the DRBs - this is where we expose device 6.
281 		 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
282 		 */
283 		pci_write_bits8(pdev, 0xf4, 0x2, 0x2);
284 		dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0));
285 
286 		if (dev == NULL)
287 			return 1;
288 
289 		err = pci_bus_add_device(dev);
290 		if (err) {
291 			i82875p_printk(KERN_ERR,
292 				"%s(): pci_bus_add_device() Failed\n",
293 				__func__);
294 		}
295 		pci_bus_assign_resources(dev->bus);
296 	}
297 
298 	*ovrfl_pdev = dev;
299 
300 	if (pci_enable_device(dev)) {
301 		i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow "
302 			"device\n", __func__);
303 		return 1;
304 	}
305 
306 	if (pci_request_regions(dev, pci_name(dev))) {
307 #ifdef CORRECT_BIOS
308 		goto fail0;
309 #endif
310 	}
311 
312 	/* cache is irrelevant for PCI bus reads/writes */
313 	window = pci_ioremap_bar(dev, 0);
314 	if (window == NULL) {
315 		i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n",
316 			__func__);
317 		goto fail1;
318 	}
319 
320 	*ovrfl_window = window;
321 	return 0;
322 
323 fail1:
324 	pci_release_regions(dev);
325 
326 #ifdef CORRECT_BIOS
327 fail0:
328 	pci_disable_device(dev);
329 #endif
330 	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
331 	return 1;
332 }
333 
334 /* Return 1 if dual channel mode is active.  Else return 0. */
335 static inline int dual_channel_active(u32 drc)
336 {
337 	return (drc >> 21) & 0x1;
338 }
339 
340 static void i82875p_init_csrows(struct mem_ctl_info *mci,
341 				struct pci_dev *pdev,
342 				void __iomem * ovrfl_window, u32 drc)
343 {
344 	struct csrow_info *csrow;
345 	unsigned long last_cumul_size;
346 	u8 value;
347 	u32 drc_ddim;		/* DRAM Data Integrity Mode 0=none,2=edac */
348 	u32 cumul_size;
349 	int index;
350 
351 	drc_ddim = (drc >> 18) & 0x1;
352 	last_cumul_size = 0;
353 
354 	/* The dram row boundary (DRB) reg values are boundary address
355 	 * for each DRAM row with a granularity of 32 or 64MB (single/dual
356 	 * channel operation).  DRB regs are cumulative; therefore DRB7 will
357 	 * contain the total memory contained in all eight rows.
358 	 */
359 
360 	for (index = 0; index < mci->nr_csrows; index++) {
361 		csrow = &mci->csrows[index];
362 
363 		value = readb(ovrfl_window + I82875P_DRB + index);
364 		cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT);
365 		debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
366 			cumul_size);
367 		if (cumul_size == last_cumul_size)
368 			continue;	/* not populated */
369 
370 		csrow->first_page = last_cumul_size;
371 		csrow->last_page = cumul_size - 1;
372 		csrow->nr_pages = cumul_size - last_cumul_size;
373 		last_cumul_size = cumul_size;
374 		csrow->grain = 1 << 12;	/* I82875P_EAP has 4KiB reolution */
375 		csrow->mtype = MEM_DDR;
376 		csrow->dtype = DEV_UNKNOWN;
377 		csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
378 	}
379 }
380 
381 static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
382 {
383 	int rc = -ENODEV;
384 	struct mem_ctl_info *mci;
385 	struct i82875p_pvt *pvt;
386 	struct pci_dev *ovrfl_pdev;
387 	void __iomem *ovrfl_window;
388 	u32 drc;
389 	u32 nr_chans;
390 	struct i82875p_error_info discard;
391 
392 	debugf0("%s()\n", __func__);
393 
394 	ovrfl_pdev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL);
395 
396 	if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window))
397 		return -ENODEV;
398 	drc = readl(ovrfl_window + I82875P_DRC);
399 	nr_chans = dual_channel_active(drc) + 1;
400 	mci = edac_mc_alloc(sizeof(*pvt), I82875P_NR_CSROWS(nr_chans),
401 			nr_chans, 0);
402 
403 	if (!mci) {
404 		rc = -ENOMEM;
405 		goto fail0;
406 	}
407 
408 	/* Keeps mci available after edac_mc_del_mc() till edac_mc_free() */
409 	kobject_get(&mci->edac_mci_kobj);
410 
411 	debugf3("%s(): init mci\n", __func__);
412 	mci->dev = &pdev->dev;
413 	mci->mtype_cap = MEM_FLAG_DDR;
414 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
415 	mci->edac_cap = EDAC_FLAG_UNKNOWN;
416 	mci->mod_name = EDAC_MOD_STR;
417 	mci->mod_ver = I82875P_REVISION;
418 	mci->ctl_name = i82875p_devs[dev_idx].ctl_name;
419 	mci->dev_name = pci_name(pdev);
420 	mci->edac_check = i82875p_check;
421 	mci->ctl_page_to_phys = NULL;
422 	debugf3("%s(): init pvt\n", __func__);
423 	pvt = (struct i82875p_pvt *)mci->pvt_info;
424 	pvt->ovrfl_pdev = ovrfl_pdev;
425 	pvt->ovrfl_window = ovrfl_window;
426 	i82875p_init_csrows(mci, pdev, ovrfl_window, drc);
427 	i82875p_get_error_info(mci, &discard);	/* clear counters */
428 
429 	/* Here we assume that we will never see multiple instances of this
430 	 * type of memory controller.  The ID is therefore hardcoded to 0.
431 	 */
432 	if (edac_mc_add_mc(mci)) {
433 		debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
434 		goto fail1;
435 	}
436 
437 	/* allocating generic PCI control info */
438 	i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
439 	if (!i82875p_pci) {
440 		printk(KERN_WARNING
441 			"%s(): Unable to create PCI control\n",
442 			__func__);
443 		printk(KERN_WARNING
444 			"%s(): PCI error report via EDAC not setup\n",
445 			__func__);
446 	}
447 
448 	/* get this far and it's successful */
449 	debugf3("%s(): success\n", __func__);
450 	return 0;
451 
452 fail1:
453 	kobject_put(&mci->edac_mci_kobj);
454 	edac_mc_free(mci);
455 
456 fail0:
457 	iounmap(ovrfl_window);
458 	pci_release_regions(ovrfl_pdev);
459 
460 	pci_disable_device(ovrfl_pdev);
461 	/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
462 	return rc;
463 }
464 
465 /* returns count (>= 0), or negative on error */
466 static int __devinit i82875p_init_one(struct pci_dev *pdev,
467 				const struct pci_device_id *ent)
468 {
469 	int rc;
470 
471 	debugf0("%s()\n", __func__);
472 	i82875p_printk(KERN_INFO, "i82875p init one\n");
473 
474 	if (pci_enable_device(pdev) < 0)
475 		return -EIO;
476 
477 	rc = i82875p_probe1(pdev, ent->driver_data);
478 
479 	if (mci_pdev == NULL)
480 		mci_pdev = pci_dev_get(pdev);
481 
482 	return rc;
483 }
484 
485 static void __devexit i82875p_remove_one(struct pci_dev *pdev)
486 {
487 	struct mem_ctl_info *mci;
488 	struct i82875p_pvt *pvt = NULL;
489 
490 	debugf0("%s()\n", __func__);
491 
492 	if (i82875p_pci)
493 		edac_pci_release_generic_ctl(i82875p_pci);
494 
495 	if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
496 		return;
497 
498 	pvt = (struct i82875p_pvt *)mci->pvt_info;
499 
500 	if (pvt->ovrfl_window)
501 		iounmap(pvt->ovrfl_window);
502 
503 	if (pvt->ovrfl_pdev) {
504 #ifdef CORRECT_BIOS
505 		pci_release_regions(pvt->ovrfl_pdev);
506 #endif				/*CORRECT_BIOS */
507 		pci_disable_device(pvt->ovrfl_pdev);
508 		pci_dev_put(pvt->ovrfl_pdev);
509 	}
510 
511 	edac_mc_free(mci);
512 }
513 
514 static const struct pci_device_id i82875p_pci_tbl[] __devinitdata = {
515 	{
516 	 PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
517 	 I82875P},
518 	{
519 	 0,
520 	 }			/* 0 terminated list. */
521 };
522 
523 MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl);
524 
525 static struct pci_driver i82875p_driver = {
526 	.name = EDAC_MOD_STR,
527 	.probe = i82875p_init_one,
528 	.remove = __devexit_p(i82875p_remove_one),
529 	.id_table = i82875p_pci_tbl,
530 };
531 
532 static int __init i82875p_init(void)
533 {
534 	int pci_rc;
535 
536 	debugf3("%s()\n", __func__);
537 
538        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
539        opstate_init();
540 
541 	pci_rc = pci_register_driver(&i82875p_driver);
542 
543 	if (pci_rc < 0)
544 		goto fail0;
545 
546 	if (mci_pdev == NULL) {
547 		mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
548 					PCI_DEVICE_ID_INTEL_82875_0, NULL);
549 
550 		if (!mci_pdev) {
551 			debugf0("875p pci_get_device fail\n");
552 			pci_rc = -ENODEV;
553 			goto fail1;
554 		}
555 
556 		pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl);
557 
558 		if (pci_rc < 0) {
559 			debugf0("875p init fail\n");
560 			pci_rc = -ENODEV;
561 			goto fail1;
562 		}
563 	}
564 
565 	return 0;
566 
567 fail1:
568 	pci_unregister_driver(&i82875p_driver);
569 
570 fail0:
571 	if (mci_pdev != NULL)
572 		pci_dev_put(mci_pdev);
573 
574 	return pci_rc;
575 }
576 
577 static void __exit i82875p_exit(void)
578 {
579 	debugf3("%s()\n", __func__);
580 
581 	i82875p_remove_one(mci_pdev);
582 	pci_dev_put(mci_pdev);
583 
584 	pci_unregister_driver(&i82875p_driver);
585 
586 }
587 
588 module_init(i82875p_init);
589 module_exit(i82875p_exit);
590 
591 MODULE_LICENSE("GPL");
592 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
593 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
594 
595 module_param(edac_op_state, int, 0444);
596 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
597