1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel 7300 class Memory Controllers kernel module (Clarksboro) 4 * 5 * Copyright (c) 2010 by: 6 * Mauro Carvalho Chehab 7 * 8 * Red Hat Inc. https://www.redhat.com 9 * 10 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet 11 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf 12 * 13 * TODO: The chipset allow checking for PCI Express errors also. Currently, 14 * the driver covers only memory error errors 15 * 16 * This driver uses "csrows" EDAC attribute to represent DIMM slot# 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/pci.h> 22 #include <linux/pci_ids.h> 23 #include <linux/slab.h> 24 #include <linux/edac.h> 25 #include <linux/mmzone.h> 26 #include <linux/string_choices.h> 27 28 #include "edac_module.h" 29 30 /* 31 * Alter this version for the I7300 module when modifications are made 32 */ 33 #define I7300_REVISION " Ver: 1.0.0" 34 35 #define EDAC_MOD_STR "i7300_edac" 36 37 #define i7300_printk(level, fmt, arg...) \ 38 edac_printk(level, "i7300", fmt, ##arg) 39 40 #define i7300_mc_printk(mci, level, fmt, arg...) \ 41 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg) 42 43 /*********************************************** 44 * i7300 Limit constants Structs and static vars 45 ***********************************************/ 46 47 /* 48 * Memory topology is organized as: 49 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0) 50 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0) 51 * Each channel can have to 8 DIMM sets (called as SLOTS) 52 * Slots should generally be filled in pairs 53 * Except on Single Channel mode of operation 54 * just slot 0/channel0 filled on this mode 55 * On normal operation mode, the two channels on a branch should be 56 * filled together for the same SLOT# 57 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four 58 * channels on both branches should be filled 59 */ 60 61 /* Limits for i7300 */ 62 #define MAX_SLOTS 8 63 #define MAX_BRANCHES 2 64 #define MAX_CH_PER_BRANCH 2 65 #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES) 66 #define MAX_MIR 3 67 68 #define to_channel(ch, branch) ((((branch)) << 1) | (ch)) 69 70 #define to_csrow(slot, ch, branch) \ 71 (to_channel(ch, branch) | ((slot) << 2)) 72 73 /* Device name and register DID (Device ID) */ 74 struct i7300_dev_info { 75 const char *ctl_name; /* name for this device */ 76 u16 fsb_mapping_errors; /* DID for the branchmap,control */ 77 }; 78 79 /* Table of devices attributes supported by this driver */ 80 static const struct i7300_dev_info i7300_devs[] = { 81 { 82 .ctl_name = "I7300", 83 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, 84 }, 85 }; 86 87 struct i7300_dimm_info { 88 int megabytes; /* size, 0 means not present */ 89 }; 90 91 /* driver private data structure */ 92 struct i7300_pvt { 93 struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */ 94 struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */ 95 struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */ 96 struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */ 97 98 u16 tolm; /* top of low memory */ 99 u64 ambase; /* AMB BAR */ 100 101 u32 mc_settings; /* Report several settings */ 102 u32 mc_settings_a; 103 104 u16 mir[MAX_MIR]; /* Memory Interleave Reg*/ 105 106 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ 107 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */ 108 109 /* DIMM information matrix, allocating architecture maximums */ 110 struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS]; 111 112 /* Temporary buffer for use when preparing error messages */ 113 char *tmp_prt_buffer; 114 115 /* Hardware error reporting status */ 116 bool enabled_error_reporting; 117 }; 118 119 /* FIXME: Why do we need to have this static? */ 120 static struct edac_pci_ctl_info *i7300_pci; 121 122 /*************************************************** 123 * i7300 Register definitions for memory enumeration 124 ***************************************************/ 125 126 /* 127 * Device 16, 128 * Function 0: System Address (not documented) 129 * Function 1: Memory Branch Map, Control, Errors Register 130 */ 131 132 /* OFFSETS for Function 0 */ 133 #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ 134 #define MAXCH 0x56 /* Max Channel Number */ 135 #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ 136 137 /* OFFSETS for Function 1 */ 138 #define MC_SETTINGS 0x40 139 #define IS_MIRRORED(mc) ((mc) & (1 << 16)) 140 #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5)) 141 #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31)) 142 #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8)) 143 144 #define MC_SETTINGS_A 0x58 145 #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14)) 146 147 #define TOLM 0x6C 148 149 #define MIR0 0x80 150 #define MIR1 0x84 151 #define MIR2 0x88 152 153 /* 154 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available 155 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it 156 * seems that we cannot use this information directly for the same usage. 157 * Each memory slot may have up to 2 AMB interfaces, one for income and another 158 * for outcome interface to the next slot. 159 * For now, the driver just stores the AMB present registers, but rely only at 160 * the MTR info to detect memory. 161 * Datasheet is also not clear about how to map each AMBPRESENT registers to 162 * one of the 4 available channels. 163 */ 164 #define AMBPRESENT_0 0x64 165 #define AMBPRESENT_1 0x66 166 167 static const u16 mtr_regs[MAX_SLOTS] = { 168 0x80, 0x84, 0x88, 0x8c, 169 0x82, 0x86, 0x8a, 0x8e 170 }; 171 172 /* 173 * Defines to extract the vaious fields from the 174 * MTRx - Memory Technology Registers 175 */ 176 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) 177 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) 178 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) 179 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) 180 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) 181 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) 182 #define MTR_DRAM_BANKS_ADDR_BITS 2 183 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) 184 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) 185 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) 186 187 /************************************************ 188 * i7300 Register definitions for error detection 189 ************************************************/ 190 191 /* 192 * Device 16.1: FBD Error Registers 193 */ 194 #define FERR_FAT_FBD 0x98 195 static const char *ferr_fat_fbd_name[] = { 196 [22] = "Non-Redundant Fast Reset Timeout", 197 [2] = ">Tmid Thermal event with intelligent throttling disabled", 198 [1] = "Memory or FBD configuration CRC read error", 199 [0] = "Memory Write error on non-redundant retry or " 200 "FBD configuration Write error on retry", 201 }; 202 #define GET_FBD_FAT_IDX(fbderr) (((fbderr) >> 28) & 3) 203 #define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 22)) 204 205 #define FERR_NF_FBD 0xa0 206 static const char *ferr_nf_fbd_name[] = { 207 [24] = "DIMM-Spare Copy Completed", 208 [23] = "DIMM-Spare Copy Initiated", 209 [22] = "Redundant Fast Reset Timeout", 210 [21] = "Memory Write error on redundant retry", 211 [18] = "SPD protocol Error", 212 [17] = "FBD Northbound parity error on FBD Sync Status", 213 [16] = "Correctable Patrol Data ECC", 214 [15] = "Correctable Resilver- or Spare-Copy Data ECC", 215 [14] = "Correctable Mirrored Demand Data ECC", 216 [13] = "Correctable Non-Mirrored Demand Data ECC", 217 [11] = "Memory or FBD configuration CRC read error", 218 [10] = "FBD Configuration Write error on first attempt", 219 [9] = "Memory Write error on first attempt", 220 [8] = "Non-Aliased Uncorrectable Patrol Data ECC", 221 [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 222 [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC", 223 [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", 224 [4] = "Aliased Uncorrectable Patrol Data ECC", 225 [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 226 [2] = "Aliased Uncorrectable Mirrored Demand Data ECC", 227 [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", 228 [0] = "Uncorrectable Data ECC on Replay", 229 }; 230 #define GET_FBD_NF_IDX(fbderr) (((fbderr) >> 28) & 3) 231 #define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\ 232 (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\ 233 (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\ 234 (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ 235 (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ 236 (1 << 1) | (1 << 0)) 237 238 #define EMASK_FBD 0xa8 239 #define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\ 240 (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\ 241 (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\ 242 (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\ 243 (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ 244 (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ 245 (1 << 1) | (1 << 0)) 246 247 /* 248 * Device 16.2: Global Error Registers 249 */ 250 251 #define FERR_GLOBAL_HI 0x48 252 static const char *ferr_global_hi_name[] = { 253 [3] = "FSB 3 Fatal Error", 254 [2] = "FSB 2 Fatal Error", 255 [1] = "FSB 1 Fatal Error", 256 [0] = "FSB 0 Fatal Error", 257 }; 258 #define ferr_global_hi_is_fatal(errno) 1 259 260 #define FERR_GLOBAL_LO 0x40 261 static const char *ferr_global_lo_name[] = { 262 [31] = "Internal MCH Fatal Error", 263 [30] = "Intel QuickData Technology Device Fatal Error", 264 [29] = "FSB1 Fatal Error", 265 [28] = "FSB0 Fatal Error", 266 [27] = "FBD Channel 3 Fatal Error", 267 [26] = "FBD Channel 2 Fatal Error", 268 [25] = "FBD Channel 1 Fatal Error", 269 [24] = "FBD Channel 0 Fatal Error", 270 [23] = "PCI Express Device 7Fatal Error", 271 [22] = "PCI Express Device 6 Fatal Error", 272 [21] = "PCI Express Device 5 Fatal Error", 273 [20] = "PCI Express Device 4 Fatal Error", 274 [19] = "PCI Express Device 3 Fatal Error", 275 [18] = "PCI Express Device 2 Fatal Error", 276 [17] = "PCI Express Device 1 Fatal Error", 277 [16] = "ESI Fatal Error", 278 [15] = "Internal MCH Non-Fatal Error", 279 [14] = "Intel QuickData Technology Device Non Fatal Error", 280 [13] = "FSB1 Non-Fatal Error", 281 [12] = "FSB 0 Non-Fatal Error", 282 [11] = "FBD Channel 3 Non-Fatal Error", 283 [10] = "FBD Channel 2 Non-Fatal Error", 284 [9] = "FBD Channel 1 Non-Fatal Error", 285 [8] = "FBD Channel 0 Non-Fatal Error", 286 [7] = "PCI Express Device 7 Non-Fatal Error", 287 [6] = "PCI Express Device 6 Non-Fatal Error", 288 [5] = "PCI Express Device 5 Non-Fatal Error", 289 [4] = "PCI Express Device 4 Non-Fatal Error", 290 [3] = "PCI Express Device 3 Non-Fatal Error", 291 [2] = "PCI Express Device 2 Non-Fatal Error", 292 [1] = "PCI Express Device 1 Non-Fatal Error", 293 [0] = "ESI Non-Fatal Error", 294 }; 295 #define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1) 296 297 #define NRECMEMA 0xbe 298 #define NRECMEMA_BANK(v) (((v) >> 12) & 7) 299 #define NRECMEMA_RANK(v) (((v) >> 8) & 15) 300 301 #define NRECMEMB 0xc0 302 #define NRECMEMB_IS_WR(v) ((v) & (1 << 31)) 303 #define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff) 304 #define NRECMEMB_RAS(v) ((v) & 0xffff) 305 306 #define REDMEMA 0xdc 307 308 #define REDMEMB 0x7c 309 310 #define RECMEMA 0xe0 311 #define RECMEMA_BANK(v) (((v) >> 12) & 7) 312 #define RECMEMA_RANK(v) (((v) >> 8) & 15) 313 314 #define RECMEMB 0xe4 315 #define RECMEMB_IS_WR(v) ((v) & (1 << 31)) 316 #define RECMEMB_CAS(v) (((v) >> 16) & 0x1fff) 317 #define RECMEMB_RAS(v) ((v) & 0xffff) 318 319 /******************************************** 320 * i7300 Functions related to error detection 321 ********************************************/ 322 323 /** 324 * get_err_from_table() - Gets the error message from a table 325 * @table: table name (array of char *) 326 * @size: number of elements at the table 327 * @pos: position of the element to be returned 328 * 329 * This is a small routine that gets the pos-th element of a table. If the 330 * element doesn't exist (or it is empty), it returns "reserved". 331 * Instead of calling it directly, the better is to call via the macro 332 * GET_ERR_FROM_TABLE(), that automatically checks the table size via 333 * ARRAY_SIZE() macro 334 */ 335 static const char *get_err_from_table(const char *table[], int size, int pos) 336 { 337 if (unlikely(pos >= size)) 338 return "Reserved"; 339 340 if (unlikely(!table[pos])) 341 return "Reserved"; 342 343 return table[pos]; 344 } 345 346 #define GET_ERR_FROM_TABLE(table, pos) \ 347 get_err_from_table(table, ARRAY_SIZE(table), pos) 348 349 /** 350 * i7300_process_error_global() - Retrieve the hardware error information from 351 * the hardware global error registers and 352 * sends it to dmesg 353 * @mci: struct mem_ctl_info pointer 354 */ 355 static void i7300_process_error_global(struct mem_ctl_info *mci) 356 { 357 struct i7300_pvt *pvt; 358 u32 errnum, error_reg; 359 unsigned long errors; 360 const char *specific; 361 bool is_fatal; 362 363 pvt = mci->pvt_info; 364 365 /* read in the 1st FATAL error register */ 366 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 367 FERR_GLOBAL_HI, &error_reg); 368 if (unlikely(error_reg)) { 369 errors = error_reg; 370 errnum = find_first_bit(&errors, 371 ARRAY_SIZE(ferr_global_hi_name)); 372 specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum); 373 is_fatal = ferr_global_hi_is_fatal(errnum); 374 375 /* Clear the error bit */ 376 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 377 FERR_GLOBAL_HI, error_reg); 378 379 goto error_global; 380 } 381 382 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 383 FERR_GLOBAL_LO, &error_reg); 384 if (unlikely(error_reg)) { 385 errors = error_reg; 386 errnum = find_first_bit(&errors, 387 ARRAY_SIZE(ferr_global_lo_name)); 388 specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum); 389 is_fatal = ferr_global_lo_is_fatal(errnum); 390 391 /* Clear the error bit */ 392 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 393 FERR_GLOBAL_LO, error_reg); 394 395 goto error_global; 396 } 397 return; 398 399 error_global: 400 i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n", 401 is_fatal ? "Fatal" : "NOT fatal", specific); 402 } 403 404 /** 405 * i7300_process_fbd_error() - Retrieve the hardware error information from 406 * the FBD error registers and sends it via 407 * EDAC error API calls 408 * @mci: struct mem_ctl_info pointer 409 */ 410 static void i7300_process_fbd_error(struct mem_ctl_info *mci) 411 { 412 struct i7300_pvt *pvt; 413 u32 errnum, value, error_reg; 414 u16 val16; 415 unsigned branch, channel, bank, rank, cas, ras; 416 u32 syndrome; 417 418 unsigned long errors; 419 const char *specific; 420 bool is_wr; 421 422 pvt = mci->pvt_info; 423 424 /* read in the 1st FATAL error register */ 425 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 426 FERR_FAT_FBD, &error_reg); 427 if (unlikely(error_reg & FERR_FAT_FBD_ERR_MASK)) { 428 errors = error_reg & FERR_FAT_FBD_ERR_MASK ; 429 errnum = find_first_bit(&errors, 430 ARRAY_SIZE(ferr_fat_fbd_name)); 431 specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum); 432 branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0; 433 434 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, 435 NRECMEMA, &val16); 436 bank = NRECMEMA_BANK(val16); 437 rank = NRECMEMA_RANK(val16); 438 439 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 440 NRECMEMB, &value); 441 is_wr = NRECMEMB_IS_WR(value); 442 cas = NRECMEMB_CAS(value); 443 ras = NRECMEMB_RAS(value); 444 445 /* Clean the error register */ 446 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 447 FERR_FAT_FBD, error_reg); 448 449 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, 450 "Bank=%d RAS=%d CAS=%d Err=0x%lx (%s))", 451 bank, ras, cas, errors, specific); 452 453 edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0, 454 branch, -1, rank, 455 is_wr ? "Write error" : "Read error", 456 pvt->tmp_prt_buffer); 457 458 } 459 460 /* read in the 1st NON-FATAL error register */ 461 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 462 FERR_NF_FBD, &error_reg); 463 if (unlikely(error_reg & FERR_NF_FBD_ERR_MASK)) { 464 errors = error_reg & FERR_NF_FBD_ERR_MASK; 465 errnum = find_first_bit(&errors, 466 ARRAY_SIZE(ferr_nf_fbd_name)); 467 specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum); 468 branch = (GET_FBD_NF_IDX(error_reg) == 2) ? 1 : 0; 469 470 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 471 REDMEMA, &syndrome); 472 473 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, 474 RECMEMA, &val16); 475 bank = RECMEMA_BANK(val16); 476 rank = RECMEMA_RANK(val16); 477 478 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 479 RECMEMB, &value); 480 is_wr = RECMEMB_IS_WR(value); 481 cas = RECMEMB_CAS(value); 482 ras = RECMEMB_RAS(value); 483 484 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 485 REDMEMB, &value); 486 channel = (branch << 1); 487 488 /* Second channel ? */ 489 channel += !!(value & BIT(17)); 490 491 /* Clear the error bit */ 492 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 493 FERR_NF_FBD, error_reg); 494 495 /* Form out message */ 496 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, 497 "DRAM-Bank=%d RAS=%d CAS=%d, Err=0x%lx (%s))", 498 bank, ras, cas, errors, specific); 499 500 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 501 syndrome, 502 branch >> 1, channel % 2, rank, 503 is_wr ? "Write error" : "Read error", 504 pvt->tmp_prt_buffer); 505 } 506 return; 507 } 508 509 /** 510 * i7300_check_error() - Calls the error checking subroutines 511 * @mci: struct mem_ctl_info pointer 512 */ 513 static void i7300_check_error(struct mem_ctl_info *mci) 514 { 515 i7300_process_error_global(mci); 516 i7300_process_fbd_error(mci); 517 }; 518 519 /** 520 * i7300_clear_error() - Clears the error registers 521 * @mci: struct mem_ctl_info pointer 522 */ 523 static void i7300_clear_error(struct mem_ctl_info *mci) 524 { 525 struct i7300_pvt *pvt = mci->pvt_info; 526 u32 value; 527 /* 528 * All error values are RWC - we need to read and write 1 to the 529 * bit that we want to cleanup 530 */ 531 532 /* Clear global error registers */ 533 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 534 FERR_GLOBAL_HI, &value); 535 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 536 FERR_GLOBAL_HI, value); 537 538 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 539 FERR_GLOBAL_LO, &value); 540 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 541 FERR_GLOBAL_LO, value); 542 543 /* Clear FBD error registers */ 544 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 545 FERR_FAT_FBD, &value); 546 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 547 FERR_FAT_FBD, value); 548 549 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 550 FERR_NF_FBD, &value); 551 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 552 FERR_NF_FBD, value); 553 } 554 555 /** 556 * i7300_set_error_reporting() - Enable or disable the memory reporting logic at the 557 * hardware 558 * @mci: struct mem_ctl_info pointer 559 * @enable: enables if 'true', disables if 'false' 560 */ 561 static void i7300_set_error_reporting(struct mem_ctl_info *mci, bool enable) 562 { 563 struct i7300_pvt *pvt = mci->pvt_info; 564 u32 fbd_error_mask; 565 566 /* Read the FBD Error Mask Register */ 567 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 568 EMASK_FBD, &fbd_error_mask); 569 570 /* Enable with 0, disable with 1 */ 571 if (enable) 572 fbd_error_mask &= ~(EMASK_FBD_ERR_MASK); 573 else 574 fbd_error_mask |= EMASK_FBD_ERR_MASK; 575 576 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 577 EMASK_FBD, fbd_error_mask); 578 } 579 580 /************************************************ 581 * i7300 Functions related to memory enumberation 582 ************************************************/ 583 584 /** 585 * decode_mtr() - Decodes the MTR descriptor, filling the edac structs 586 * @pvt: pointer to the private data struct used by i7300 driver 587 * @slot: DIMM slot (0 to 7) 588 * @ch: Channel number within the branch (0 or 1) 589 * @branch: Branch number (0 or 1) 590 * @dinfo: Pointer to DIMM info where dimm size is stored 591 * @dimm: Pointer to the struct dimm_info that corresponds to that element 592 */ 593 static int decode_mtr(struct i7300_pvt *pvt, 594 int slot, int ch, int branch, 595 struct i7300_dimm_info *dinfo, 596 struct dimm_info *dimm) 597 { 598 int mtr, ans, addrBits, channel; 599 600 channel = to_channel(ch, branch); 601 602 mtr = pvt->mtr[slot][branch]; 603 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; 604 605 edac_dbg(2, "\tMTR%d CH%d: DIMMs are %sPresent (mtr)\n", 606 slot, channel, ans ? "" : "NOT "); 607 608 /* Determine if there is a DIMM present in this DIMM slot */ 609 if (!ans) 610 return 0; 611 612 /* Start with the number of bits for a Bank 613 * on the DRAM */ 614 addrBits = MTR_DRAM_BANKS_ADDR_BITS; 615 /* Add thenumber of ROW bits */ 616 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); 617 /* add the number of COLUMN bits */ 618 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); 619 /* add the number of RANK bits */ 620 addrBits += MTR_DIMM_RANKS(mtr); 621 622 addrBits += 6; /* add 64 bits per DIMM */ 623 addrBits -= 20; /* divide by 2^^20 */ 624 addrBits -= 3; /* 8 bits per bytes */ 625 626 dinfo->megabytes = 1 << addrBits; 627 628 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); 629 630 edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n", 631 str_enabled_disabled(MTR_DIMMS_ETHROTTLE(mtr))); 632 633 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); 634 edac_dbg(2, "\t\tNUMRANK: %s\n", 635 MTR_DIMM_RANKS(mtr) ? "double" : "single"); 636 edac_dbg(2, "\t\tNUMROW: %s\n", 637 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : 638 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : 639 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : 640 "65,536 - 16 rows"); 641 edac_dbg(2, "\t\tNUMCOL: %s\n", 642 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : 643 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : 644 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : 645 "reserved"); 646 edac_dbg(2, "\t\tSIZE: %d MB\n", dinfo->megabytes); 647 648 /* 649 * The type of error detection actually depends of the 650 * mode of operation. When it is just one single memory chip, at 651 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. 652 * In normal or mirrored mode, it uses Lockstep mode, 653 * with the possibility of using an extended algorithm for x8 memories 654 * See datasheet Sections 7.3.6 to 7.3.8 655 */ 656 657 dimm->nr_pages = MiB_TO_PAGES(dinfo->megabytes); 658 dimm->grain = 8; 659 dimm->mtype = MEM_FB_DDR2; 660 if (IS_SINGLE_MODE(pvt->mc_settings_a)) { 661 dimm->edac_mode = EDAC_SECDED; 662 edac_dbg(2, "\t\tECC code is 8-byte-over-32-byte SECDED+ code\n"); 663 } else { 664 edac_dbg(2, "\t\tECC code is on Lockstep mode\n"); 665 if (MTR_DRAM_WIDTH(mtr) == 8) 666 dimm->edac_mode = EDAC_S8ECD8ED; 667 else 668 dimm->edac_mode = EDAC_S4ECD4ED; 669 } 670 671 /* ask what device type on this row */ 672 if (MTR_DRAM_WIDTH(mtr) == 8) { 673 edac_dbg(2, "\t\tScrub algorithm for x8 is on %s mode\n", 674 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ? 675 "enhanced" : "normal"); 676 677 dimm->dtype = DEV_X8; 678 } else 679 dimm->dtype = DEV_X4; 680 681 return mtr; 682 } 683 684 /** 685 * print_dimm_size() - Prints dump of the memory organization 686 * @pvt: pointer to the private data struct used by i7300 driver 687 * 688 * Useful for debug. If debug is disabled, this routine do nothing 689 */ 690 static void print_dimm_size(struct i7300_pvt *pvt) 691 { 692 #ifdef CONFIG_EDAC_DEBUG 693 struct i7300_dimm_info *dinfo; 694 char *p; 695 int space, n; 696 int channel, slot; 697 698 space = PAGE_SIZE; 699 p = pvt->tmp_prt_buffer; 700 701 n = snprintf(p, space, " "); 702 p += n; 703 space -= n; 704 for (channel = 0; channel < MAX_CHANNELS; channel++) { 705 n = snprintf(p, space, "channel %d | ", channel); 706 p += n; 707 space -= n; 708 } 709 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer); 710 p = pvt->tmp_prt_buffer; 711 space = PAGE_SIZE; 712 n = snprintf(p, space, "-------------------------------" 713 "------------------------------"); 714 p += n; 715 space -= n; 716 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer); 717 p = pvt->tmp_prt_buffer; 718 space = PAGE_SIZE; 719 720 for (slot = 0; slot < MAX_SLOTS; slot++) { 721 n = snprintf(p, space, "csrow/SLOT %d ", slot); 722 p += n; 723 space -= n; 724 725 for (channel = 0; channel < MAX_CHANNELS; channel++) { 726 dinfo = &pvt->dimm_info[slot][channel]; 727 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); 728 p += n; 729 space -= n; 730 } 731 732 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer); 733 p = pvt->tmp_prt_buffer; 734 space = PAGE_SIZE; 735 } 736 737 n = snprintf(p, space, "-------------------------------" 738 "------------------------------"); 739 p += n; 740 space -= n; 741 edac_dbg(2, "%s\n", pvt->tmp_prt_buffer); 742 p = pvt->tmp_prt_buffer; 743 space = PAGE_SIZE; 744 #endif 745 } 746 747 /** 748 * i7300_init_csrows() - Initialize the 'csrows' table within 749 * the mci control structure with the 750 * addressing of memory. 751 * @mci: struct mem_ctl_info pointer 752 */ 753 static int i7300_init_csrows(struct mem_ctl_info *mci) 754 { 755 struct i7300_pvt *pvt; 756 struct i7300_dimm_info *dinfo; 757 int rc = -ENODEV; 758 int mtr; 759 int ch, branch, slot, channel, max_channel, max_branch; 760 struct dimm_info *dimm; 761 762 pvt = mci->pvt_info; 763 764 edac_dbg(2, "Memory Technology Registers:\n"); 765 766 if (IS_SINGLE_MODE(pvt->mc_settings_a)) { 767 max_branch = 1; 768 max_channel = 1; 769 } else { 770 max_branch = MAX_BRANCHES; 771 max_channel = MAX_CH_PER_BRANCH; 772 } 773 774 /* Get the AMB present registers for the four channels */ 775 for (branch = 0; branch < max_branch; branch++) { 776 /* Read and dump branch 0's MTRs */ 777 channel = to_channel(0, branch); 778 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], 779 AMBPRESENT_0, 780 &pvt->ambpresent[channel]); 781 edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n", 782 channel, pvt->ambpresent[channel]); 783 784 if (max_channel == 1) 785 continue; 786 787 channel = to_channel(1, branch); 788 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], 789 AMBPRESENT_1, 790 &pvt->ambpresent[channel]); 791 edac_dbg(2, "\t\tAMB-present CH%d = 0x%x:\n", 792 channel, pvt->ambpresent[channel]); 793 } 794 795 /* Get the set of MTR[0-7] regs by each branch */ 796 for (slot = 0; slot < MAX_SLOTS; slot++) { 797 int where = mtr_regs[slot]; 798 for (branch = 0; branch < max_branch; branch++) { 799 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], 800 where, 801 &pvt->mtr[slot][branch]); 802 for (ch = 0; ch < max_channel; ch++) { 803 int channel = to_channel(ch, branch); 804 805 dimm = edac_get_dimm(mci, branch, ch, slot); 806 807 dinfo = &pvt->dimm_info[slot][channel]; 808 809 mtr = decode_mtr(pvt, slot, ch, branch, 810 dinfo, dimm); 811 812 /* if no DIMMS on this row, continue */ 813 if (!MTR_DIMMS_PRESENT(mtr)) 814 continue; 815 816 rc = 0; 817 818 } 819 } 820 } 821 822 return rc; 823 } 824 825 /** 826 * decode_mir() - Decodes Memory Interleave Register (MIR) info 827 * @mir_no: number of the MIR register to decode 828 * @mir: array with the MIR data cached on the driver 829 */ 830 static void decode_mir(int mir_no, u16 mir[MAX_MIR]) 831 { 832 if (mir[mir_no] & 3) 833 edac_dbg(2, "MIR%d: limit= 0x%x Branch(es) that participate: %s %s\n", 834 mir_no, 835 (mir[mir_no] >> 4) & 0xfff, 836 (mir[mir_no] & 1) ? "B0" : "", 837 (mir[mir_no] & 2) ? "B1" : ""); 838 } 839 840 /** 841 * i7300_get_mc_regs() - Get the contents of the MC enumeration registers 842 * @mci: struct mem_ctl_info pointer 843 * 844 * Data read is cached internally for its usage when needed 845 */ 846 static int i7300_get_mc_regs(struct mem_ctl_info *mci) 847 { 848 struct i7300_pvt *pvt; 849 u32 actual_tolm; 850 int i, rc; 851 852 pvt = mci->pvt_info; 853 854 pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE, 855 (u32 *) &pvt->ambase); 856 857 edac_dbg(2, "AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase); 858 859 /* Get the Branch Map regs */ 860 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm); 861 pvt->tolm >>= 12; 862 edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n", 863 pvt->tolm, pvt->tolm); 864 865 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); 866 edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n", 867 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); 868 869 /* Get memory controller settings */ 870 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS, 871 &pvt->mc_settings); 872 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A, 873 &pvt->mc_settings_a); 874 875 if (IS_SINGLE_MODE(pvt->mc_settings_a)) 876 edac_dbg(0, "Memory controller operating on single mode\n"); 877 else 878 edac_dbg(0, "Memory controller operating on %smirrored mode\n", 879 IS_MIRRORED(pvt->mc_settings) ? "" : "non-"); 880 881 edac_dbg(0, "Error detection is %s\n", 882 str_enabled_disabled(IS_ECC_ENABLED(pvt->mc_settings))); 883 edac_dbg(0, "Retry is %s\n", 884 str_enabled_disabled(IS_RETRY_ENABLED(pvt->mc_settings))); 885 886 /* Get Memory Interleave Range registers */ 887 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, 888 &pvt->mir[0]); 889 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, 890 &pvt->mir[1]); 891 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, 892 &pvt->mir[2]); 893 894 /* Decode the MIR regs */ 895 for (i = 0; i < MAX_MIR; i++) 896 decode_mir(i, pvt->mir); 897 898 rc = i7300_init_csrows(mci); 899 if (rc < 0) 900 return rc; 901 902 /* Go and determine the size of each DIMM and place in an 903 * orderly matrix */ 904 print_dimm_size(pvt); 905 906 return 0; 907 } 908 909 /************************************************* 910 * i7300 Functions related to device probe/release 911 *************************************************/ 912 913 /** 914 * i7300_put_devices() - Release the PCI devices 915 * @mci: struct mem_ctl_info pointer 916 */ 917 static void i7300_put_devices(struct mem_ctl_info *mci) 918 { 919 struct i7300_pvt *pvt; 920 int branch; 921 922 pvt = mci->pvt_info; 923 924 /* Decrement usage count for devices */ 925 for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++) 926 pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]); 927 pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs); 928 pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map); 929 } 930 931 /** 932 * i7300_get_devices() - Find and perform 'get' operation on the MCH's 933 * device/functions we want to reference for this driver 934 * @mci: struct mem_ctl_info pointer 935 * 936 * Access and prepare the several devices for usage: 937 * I7300 devices used by this driver: 938 * Device 16, functions 0,1 and 2: PCI_DEVICE_ID_INTEL_I7300_MCH_ERR 939 * Device 21 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 940 * Device 22 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 941 */ 942 static int i7300_get_devices(struct mem_ctl_info *mci) 943 { 944 struct i7300_pvt *pvt; 945 struct pci_dev *pdev; 946 947 pvt = mci->pvt_info; 948 949 /* Attempt to 'get' the MCH register we want */ 950 pdev = NULL; 951 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 952 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, 953 pdev))) { 954 /* Store device 16 funcs 1 and 2 */ 955 switch (PCI_FUNC(pdev->devfn)) { 956 case 1: 957 if (!pvt->pci_dev_16_1_fsb_addr_map) 958 pvt->pci_dev_16_1_fsb_addr_map = 959 pci_dev_get(pdev); 960 break; 961 case 2: 962 if (!pvt->pci_dev_16_2_fsb_err_regs) 963 pvt->pci_dev_16_2_fsb_err_regs = 964 pci_dev_get(pdev); 965 break; 966 } 967 } 968 969 if (!pvt->pci_dev_16_1_fsb_addr_map || 970 !pvt->pci_dev_16_2_fsb_err_regs) { 971 /* At least one device was not found */ 972 i7300_printk(KERN_ERR, 973 "'system address,Process Bus' device not found:" 974 "vendor 0x%x device 0x%x ERR funcs (broken BIOS?)\n", 975 PCI_VENDOR_ID_INTEL, 976 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR); 977 goto error; 978 } 979 980 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n", 981 pci_name(pvt->pci_dev_16_0_fsb_ctlr), 982 pvt->pci_dev_16_0_fsb_ctlr->vendor, 983 pvt->pci_dev_16_0_fsb_ctlr->device); 984 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", 985 pci_name(pvt->pci_dev_16_1_fsb_addr_map), 986 pvt->pci_dev_16_1_fsb_addr_map->vendor, 987 pvt->pci_dev_16_1_fsb_addr_map->device); 988 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n", 989 pci_name(pvt->pci_dev_16_2_fsb_err_regs), 990 pvt->pci_dev_16_2_fsb_err_regs->vendor, 991 pvt->pci_dev_16_2_fsb_err_regs->device); 992 993 pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL, 994 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0, 995 NULL); 996 if (!pvt->pci_dev_2x_0_fbd_branch[0]) { 997 i7300_printk(KERN_ERR, 998 "MC: 'BRANCH 0' device not found:" 999 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", 1000 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0); 1001 goto error; 1002 } 1003 1004 pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL, 1005 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1, 1006 NULL); 1007 if (!pvt->pci_dev_2x_0_fbd_branch[1]) { 1008 i7300_printk(KERN_ERR, 1009 "MC: 'BRANCH 1' device not found:" 1010 "vendor 0x%x device 0x%x Func 0 " 1011 "(broken BIOS?)\n", 1012 PCI_VENDOR_ID_INTEL, 1013 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1); 1014 goto error; 1015 } 1016 1017 return 0; 1018 1019 error: 1020 i7300_put_devices(mci); 1021 return -ENODEV; 1022 } 1023 1024 /** 1025 * i7300_init_one() - Probe for one instance of the device 1026 * @pdev: struct pci_dev pointer 1027 * @id: struct pci_device_id pointer - currently unused 1028 */ 1029 static int i7300_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 1030 { 1031 struct mem_ctl_info *mci; 1032 struct edac_mc_layer layers[3]; 1033 struct i7300_pvt *pvt; 1034 int rc; 1035 1036 /* wake up device */ 1037 rc = pci_enable_device(pdev); 1038 if (rc == -EIO) 1039 return rc; 1040 1041 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n", 1042 pdev->bus->number, 1043 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1044 1045 /* We only are looking for func 0 of the set */ 1046 if (PCI_FUNC(pdev->devfn) != 0) 1047 return -ENODEV; 1048 1049 /* allocate a new MC control structure */ 1050 layers[0].type = EDAC_MC_LAYER_BRANCH; 1051 layers[0].size = MAX_BRANCHES; 1052 layers[0].is_virt_csrow = false; 1053 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1054 layers[1].size = MAX_CH_PER_BRANCH; 1055 layers[1].is_virt_csrow = true; 1056 layers[2].type = EDAC_MC_LAYER_SLOT; 1057 layers[2].size = MAX_SLOTS; 1058 layers[2].is_virt_csrow = true; 1059 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); 1060 if (mci == NULL) 1061 return -ENOMEM; 1062 1063 edac_dbg(0, "MC: mci = %p\n", mci); 1064 1065 mci->pdev = &pdev->dev; /* record ptr to the generic device */ 1066 1067 pvt = mci->pvt_info; 1068 pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */ 1069 1070 pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL); 1071 if (!pvt->tmp_prt_buffer) { 1072 edac_mc_free(mci); 1073 return -ENOMEM; 1074 } 1075 1076 /* 'get' the pci devices we want to reserve for our use */ 1077 if (i7300_get_devices(mci)) 1078 goto fail0; 1079 1080 mci->mc_idx = 0; 1081 mci->mtype_cap = MEM_FLAG_FB_DDR2; 1082 mci->edac_ctl_cap = EDAC_FLAG_NONE; 1083 mci->edac_cap = EDAC_FLAG_NONE; 1084 mci->mod_name = "i7300_edac.c"; 1085 mci->ctl_name = i7300_devs[0].ctl_name; 1086 mci->dev_name = pci_name(pdev); 1087 mci->ctl_page_to_phys = NULL; 1088 1089 /* Set the function pointer to an actual operation function */ 1090 mci->edac_check = i7300_check_error; 1091 1092 /* initialize the MC control structure 'csrows' table 1093 * with the mapping and control information */ 1094 if (i7300_get_mc_regs(mci)) { 1095 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i7300_init_csrows() returned nonzero value\n"); 1096 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ 1097 pvt->enabled_error_reporting = false; 1098 } else { 1099 edac_dbg(1, "MC: Enable error reporting now\n"); 1100 i7300_set_error_reporting(mci, true); 1101 pvt->enabled_error_reporting = true; 1102 } 1103 1104 /* add this new MC control structure to EDAC's list of MCs */ 1105 if (edac_mc_add_mc(mci)) { 1106 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 1107 /* Disable error reporting if we just enabled it */ 1108 if (pvt->enabled_error_reporting) 1109 i7300_set_error_reporting(mci, false); 1110 goto fail1; 1111 } 1112 1113 i7300_clear_error(mci); 1114 1115 /* allocating generic PCI control info */ 1116 i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 1117 if (!i7300_pci) { 1118 printk(KERN_WARNING 1119 "%s(): Unable to create PCI control\n", 1120 __func__); 1121 printk(KERN_WARNING 1122 "%s(): PCI error report via EDAC not setup\n", 1123 __func__); 1124 } 1125 1126 return 0; 1127 1128 /* Error exit unwinding stack */ 1129 fail1: 1130 1131 i7300_put_devices(mci); 1132 1133 fail0: 1134 kfree(pvt->tmp_prt_buffer); 1135 edac_mc_free(mci); 1136 return -ENODEV; 1137 } 1138 1139 /** 1140 * i7300_remove_one() - Remove the driver 1141 * @pdev: struct pci_dev pointer 1142 */ 1143 static void i7300_remove_one(struct pci_dev *pdev) 1144 { 1145 struct mem_ctl_info *mci; 1146 struct i7300_pvt *pvt; 1147 char *tmp; 1148 1149 edac_dbg(0, "\n"); 1150 1151 if (i7300_pci) 1152 edac_pci_release_generic_ctl(i7300_pci); 1153 1154 mci = edac_mc_del_mc(&pdev->dev); 1155 if (!mci) 1156 return; 1157 1158 pvt = (struct i7300_pvt *)mci->pvt_info; 1159 tmp = pvt->tmp_prt_buffer; 1160 1161 /* Disable error reporting before unregistering device */ 1162 if (pvt->enabled_error_reporting) 1163 i7300_set_error_reporting(mci, false); 1164 1165 /* retrieve references to resources, and free those resources */ 1166 i7300_put_devices(mci); 1167 1168 kfree(tmp); 1169 edac_mc_free(mci); 1170 } 1171 1172 /* 1173 * pci_device_id: table for which devices we are looking for 1174 * 1175 * Has only 8086:360c PCI ID 1176 */ 1177 static const struct pci_device_id i7300_pci_tbl[] = { 1178 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)}, 1179 {0,} /* 0 terminated list. */ 1180 }; 1181 1182 MODULE_DEVICE_TABLE(pci, i7300_pci_tbl); 1183 1184 /* 1185 * i7300_driver: pci_driver structure for this module 1186 */ 1187 static struct pci_driver i7300_driver = { 1188 .name = "i7300_edac", 1189 .probe = i7300_init_one, 1190 .remove = i7300_remove_one, 1191 .id_table = i7300_pci_tbl, 1192 }; 1193 1194 /** 1195 * i7300_init() - Registers the driver 1196 */ 1197 static int __init i7300_init(void) 1198 { 1199 int pci_rc; 1200 1201 edac_dbg(2, "\n"); 1202 1203 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1204 opstate_init(); 1205 1206 pci_rc = pci_register_driver(&i7300_driver); 1207 1208 return (pci_rc < 0) ? pci_rc : 0; 1209 } 1210 1211 /** 1212 * i7300_exit() - Unregisters the driver 1213 */ 1214 static void __exit i7300_exit(void) 1215 { 1216 edac_dbg(2, "\n"); 1217 pci_unregister_driver(&i7300_driver); 1218 } 1219 1220 module_init(i7300_init); 1221 module_exit(i7300_exit); 1222 1223 MODULE_LICENSE("GPL"); 1224 MODULE_AUTHOR("Mauro Carvalho Chehab"); 1225 MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)"); 1226 MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - " 1227 I7300_REVISION); 1228 1229 module_param(edac_op_state, int, 0444); 1230 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 1231