1 /* 2 * Intel 7300 class Memory Controllers kernel module (Clarksboro) 3 * 4 * This file may be distributed under the terms of the 5 * GNU General Public License version 2 only. 6 * 7 * Copyright (c) 2010 by: 8 * Mauro Carvalho Chehab <mchehab@redhat.com> 9 * 10 * Red Hat Inc. http://www.redhat.com 11 * 12 * Intel 7300 Chipset Memory Controller Hub (MCH) - Datasheet 13 * http://www.intel.com/Assets/PDF/datasheet/318082.pdf 14 * 15 * TODO: The chipset allow checking for PCI Express errors also. Currently, 16 * the driver covers only memory error errors 17 * 18 * This driver uses "csrows" EDAC attribute to represent DIMM slot# 19 */ 20 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/pci.h> 24 #include <linux/pci_ids.h> 25 #include <linux/slab.h> 26 #include <linux/edac.h> 27 #include <linux/mmzone.h> 28 29 #include "edac_core.h" 30 31 /* 32 * Alter this version for the I7300 module when modifications are made 33 */ 34 #define I7300_REVISION " Ver: 1.0.0" 35 36 #define EDAC_MOD_STR "i7300_edac" 37 38 #define i7300_printk(level, fmt, arg...) \ 39 edac_printk(level, "i7300", fmt, ##arg) 40 41 #define i7300_mc_printk(mci, level, fmt, arg...) \ 42 edac_mc_chipset_printk(mci, level, "i7300", fmt, ##arg) 43 44 /*********************************************** 45 * i7300 Limit constants Structs and static vars 46 ***********************************************/ 47 48 /* 49 * Memory topology is organized as: 50 * Branch 0 - 2 channels: channels 0 and 1 (FDB0 PCI dev 21.0) 51 * Branch 1 - 2 channels: channels 2 and 3 (FDB1 PCI dev 22.0) 52 * Each channel can have to 8 DIMM sets (called as SLOTS) 53 * Slots should generally be filled in pairs 54 * Except on Single Channel mode of operation 55 * just slot 0/channel0 filled on this mode 56 * On normal operation mode, the two channels on a branch should be 57 * filled together for the same SLOT# 58 * When in mirrored mode, Branch 1 replicate memory at Branch 0, so, the four 59 * channels on both branches should be filled 60 */ 61 62 /* Limits for i7300 */ 63 #define MAX_SLOTS 8 64 #define MAX_BRANCHES 2 65 #define MAX_CH_PER_BRANCH 2 66 #define MAX_CHANNELS (MAX_CH_PER_BRANCH * MAX_BRANCHES) 67 #define MAX_MIR 3 68 69 #define to_channel(ch, branch) ((((branch)) << 1) | (ch)) 70 71 #define to_csrow(slot, ch, branch) \ 72 (to_channel(ch, branch) | ((slot) << 2)) 73 74 /* Device name and register DID (Device ID) */ 75 struct i7300_dev_info { 76 const char *ctl_name; /* name for this device */ 77 u16 fsb_mapping_errors; /* DID for the branchmap,control */ 78 }; 79 80 /* Table of devices attributes supported by this driver */ 81 static const struct i7300_dev_info i7300_devs[] = { 82 { 83 .ctl_name = "I7300", 84 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, 85 }, 86 }; 87 88 struct i7300_dimm_info { 89 int megabytes; /* size, 0 means not present */ 90 }; 91 92 /* driver private data structure */ 93 struct i7300_pvt { 94 struct pci_dev *pci_dev_16_0_fsb_ctlr; /* 16.0 */ 95 struct pci_dev *pci_dev_16_1_fsb_addr_map; /* 16.1 */ 96 struct pci_dev *pci_dev_16_2_fsb_err_regs; /* 16.2 */ 97 struct pci_dev *pci_dev_2x_0_fbd_branch[MAX_BRANCHES]; /* 21.0 and 22.0 */ 98 99 u16 tolm; /* top of low memory */ 100 u64 ambase; /* AMB BAR */ 101 102 u32 mc_settings; /* Report several settings */ 103 u32 mc_settings_a; 104 105 u16 mir[MAX_MIR]; /* Memory Interleave Reg*/ 106 107 u16 mtr[MAX_SLOTS][MAX_BRANCHES]; /* Memory Technlogy Reg */ 108 u16 ambpresent[MAX_CHANNELS]; /* AMB present regs */ 109 110 /* DIMM information matrix, allocating architecture maximums */ 111 struct i7300_dimm_info dimm_info[MAX_SLOTS][MAX_CHANNELS]; 112 113 /* Temporary buffer for use when preparing error messages */ 114 char *tmp_prt_buffer; 115 }; 116 117 /* FIXME: Why do we need to have this static? */ 118 static struct edac_pci_ctl_info *i7300_pci; 119 120 /*************************************************** 121 * i7300 Register definitions for memory enumeration 122 ***************************************************/ 123 124 /* 125 * Device 16, 126 * Function 0: System Address (not documented) 127 * Function 1: Memory Branch Map, Control, Errors Register 128 */ 129 130 /* OFFSETS for Function 0 */ 131 #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ 132 #define MAXCH 0x56 /* Max Channel Number */ 133 #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ 134 135 /* OFFSETS for Function 1 */ 136 #define MC_SETTINGS 0x40 137 #define IS_MIRRORED(mc) ((mc) & (1 << 16)) 138 #define IS_ECC_ENABLED(mc) ((mc) & (1 << 5)) 139 #define IS_RETRY_ENABLED(mc) ((mc) & (1 << 31)) 140 #define IS_SCRBALGO_ENHANCED(mc) ((mc) & (1 << 8)) 141 142 #define MC_SETTINGS_A 0x58 143 #define IS_SINGLE_MODE(mca) ((mca) & (1 << 14)) 144 145 #define TOLM 0x6C 146 147 #define MIR0 0x80 148 #define MIR1 0x84 149 #define MIR2 0x88 150 151 /* 152 * Note: Other Intel EDAC drivers use AMBPRESENT to identify if the available 153 * memory. From datasheet item 7.3.1 (FB-DIMM technology & organization), it 154 * seems that we cannot use this information directly for the same usage. 155 * Each memory slot may have up to 2 AMB interfaces, one for income and another 156 * for outcome interface to the next slot. 157 * For now, the driver just stores the AMB present registers, but rely only at 158 * the MTR info to detect memory. 159 * Datasheet is also not clear about how to map each AMBPRESENT registers to 160 * one of the 4 available channels. 161 */ 162 #define AMBPRESENT_0 0x64 163 #define AMBPRESENT_1 0x66 164 165 static const u16 mtr_regs[MAX_SLOTS] = { 166 0x80, 0x84, 0x88, 0x8c, 167 0x82, 0x86, 0x8a, 0x8e 168 }; 169 170 /* 171 * Defines to extract the vaious fields from the 172 * MTRx - Memory Technology Registers 173 */ 174 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 8)) 175 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 7)) 176 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 6)) ? 8 : 4) 177 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 5)) ? 8 : 4) 178 #define MTR_DIMM_RANKS(mtr) (((mtr) & (1 << 4)) ? 1 : 0) 179 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) 180 #define MTR_DRAM_BANKS_ADDR_BITS 2 181 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) 182 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) 183 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) 184 185 #ifdef CONFIG_EDAC_DEBUG 186 /* MTR NUMROW */ 187 static const char *numrow_toString[] = { 188 "8,192 - 13 rows", 189 "16,384 - 14 rows", 190 "32,768 - 15 rows", 191 "65,536 - 16 rows" 192 }; 193 194 /* MTR NUMCOL */ 195 static const char *numcol_toString[] = { 196 "1,024 - 10 columns", 197 "2,048 - 11 columns", 198 "4,096 - 12 columns", 199 "reserved" 200 }; 201 #endif 202 203 /************************************************ 204 * i7300 Register definitions for error detection 205 ************************************************/ 206 207 /* 208 * Device 16.1: FBD Error Registers 209 */ 210 #define FERR_FAT_FBD 0x98 211 static const char *ferr_fat_fbd_name[] = { 212 [22] = "Non-Redundant Fast Reset Timeout", 213 [2] = ">Tmid Thermal event with intelligent throttling disabled", 214 [1] = "Memory or FBD configuration CRC read error", 215 [0] = "Memory Write error on non-redundant retry or " 216 "FBD configuration Write error on retry", 217 }; 218 #define GET_FBD_FAT_IDX(fbderr) (fbderr & (3 << 28)) 219 #define FERR_FAT_FBD_ERR_MASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) 220 221 #define FERR_NF_FBD 0xa0 222 static const char *ferr_nf_fbd_name[] = { 223 [24] = "DIMM-Spare Copy Completed", 224 [23] = "DIMM-Spare Copy Initiated", 225 [22] = "Redundant Fast Reset Timeout", 226 [21] = "Memory Write error on redundant retry", 227 [18] = "SPD protocol Error", 228 [17] = "FBD Northbound parity error on FBD Sync Status", 229 [16] = "Correctable Patrol Data ECC", 230 [15] = "Correctable Resilver- or Spare-Copy Data ECC", 231 [14] = "Correctable Mirrored Demand Data ECC", 232 [13] = "Correctable Non-Mirrored Demand Data ECC", 233 [11] = "Memory or FBD configuration CRC read error", 234 [10] = "FBD Configuration Write error on first attempt", 235 [9] = "Memory Write error on first attempt", 236 [8] = "Non-Aliased Uncorrectable Patrol Data ECC", 237 [7] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 238 [6] = "Non-Aliased Uncorrectable Mirrored Demand Data ECC", 239 [5] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", 240 [4] = "Aliased Uncorrectable Patrol Data ECC", 241 [3] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 242 [2] = "Aliased Uncorrectable Mirrored Demand Data ECC", 243 [1] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", 244 [0] = "Uncorrectable Data ECC on Replay", 245 }; 246 #define GET_FBD_NF_IDX(fbderr) (fbderr & (3 << 28)) 247 #define FERR_NF_FBD_ERR_MASK ((1 << 24) | (1 << 23) | (1 << 22) | (1 << 21) |\ 248 (1 << 18) | (1 << 17) | (1 << 16) | (1 << 15) |\ 249 (1 << 14) | (1 << 13) | (1 << 11) | (1 << 10) |\ 250 (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ 251 (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ 252 (1 << 1) | (1 << 0)) 253 254 #define EMASK_FBD 0xa8 255 #define EMASK_FBD_ERR_MASK ((1 << 27) | (1 << 26) | (1 << 25) | (1 << 24) |\ 256 (1 << 22) | (1 << 21) | (1 << 20) | (1 << 19) |\ 257 (1 << 18) | (1 << 17) | (1 << 16) | (1 << 14) |\ 258 (1 << 13) | (1 << 12) | (1 << 11) | (1 << 10) |\ 259 (1 << 9) | (1 << 8) | (1 << 7) | (1 << 6) |\ 260 (1 << 5) | (1 << 4) | (1 << 3) | (1 << 2) |\ 261 (1 << 1) | (1 << 0)) 262 263 /* 264 * Device 16.2: Global Error Registers 265 */ 266 267 #define FERR_GLOBAL_HI 0x48 268 static const char *ferr_global_hi_name[] = { 269 [3] = "FSB 3 Fatal Error", 270 [2] = "FSB 2 Fatal Error", 271 [1] = "FSB 1 Fatal Error", 272 [0] = "FSB 0 Fatal Error", 273 }; 274 #define ferr_global_hi_is_fatal(errno) 1 275 276 #define FERR_GLOBAL_LO 0x40 277 static const char *ferr_global_lo_name[] = { 278 [31] = "Internal MCH Fatal Error", 279 [30] = "Intel QuickData Technology Device Fatal Error", 280 [29] = "FSB1 Fatal Error", 281 [28] = "FSB0 Fatal Error", 282 [27] = "FBD Channel 3 Fatal Error", 283 [26] = "FBD Channel 2 Fatal Error", 284 [25] = "FBD Channel 1 Fatal Error", 285 [24] = "FBD Channel 0 Fatal Error", 286 [23] = "PCI Express Device 7Fatal Error", 287 [22] = "PCI Express Device 6 Fatal Error", 288 [21] = "PCI Express Device 5 Fatal Error", 289 [20] = "PCI Express Device 4 Fatal Error", 290 [19] = "PCI Express Device 3 Fatal Error", 291 [18] = "PCI Express Device 2 Fatal Error", 292 [17] = "PCI Express Device 1 Fatal Error", 293 [16] = "ESI Fatal Error", 294 [15] = "Internal MCH Non-Fatal Error", 295 [14] = "Intel QuickData Technology Device Non Fatal Error", 296 [13] = "FSB1 Non-Fatal Error", 297 [12] = "FSB 0 Non-Fatal Error", 298 [11] = "FBD Channel 3 Non-Fatal Error", 299 [10] = "FBD Channel 2 Non-Fatal Error", 300 [9] = "FBD Channel 1 Non-Fatal Error", 301 [8] = "FBD Channel 0 Non-Fatal Error", 302 [7] = "PCI Express Device 7 Non-Fatal Error", 303 [6] = "PCI Express Device 6 Non-Fatal Error", 304 [5] = "PCI Express Device 5 Non-Fatal Error", 305 [4] = "PCI Express Device 4 Non-Fatal Error", 306 [3] = "PCI Express Device 3 Non-Fatal Error", 307 [2] = "PCI Express Device 2 Non-Fatal Error", 308 [1] = "PCI Express Device 1 Non-Fatal Error", 309 [0] = "ESI Non-Fatal Error", 310 }; 311 #define ferr_global_lo_is_fatal(errno) ((errno < 16) ? 0 : 1) 312 313 #define NRECMEMA 0xbe 314 #define NRECMEMA_BANK(v) (((v) >> 12) & 7) 315 #define NRECMEMA_RANK(v) (((v) >> 8) & 15) 316 317 #define NRECMEMB 0xc0 318 #define NRECMEMB_IS_WR(v) ((v) & (1 << 31)) 319 #define NRECMEMB_CAS(v) (((v) >> 16) & 0x1fff) 320 #define NRECMEMB_RAS(v) ((v) & 0xffff) 321 322 #define REDMEMA 0xdc 323 324 #define REDMEMB 0x7c 325 #define IS_SECOND_CH(v) ((v) * (1 << 17)) 326 327 #define RECMEMA 0xe0 328 #define RECMEMA_BANK(v) (((v) >> 12) & 7) 329 #define RECMEMA_RANK(v) (((v) >> 8) & 15) 330 331 #define RECMEMB 0xe4 332 #define RECMEMB_IS_WR(v) ((v) & (1 << 31)) 333 #define RECMEMB_CAS(v) (((v) >> 16) & 0x1fff) 334 #define RECMEMB_RAS(v) ((v) & 0xffff) 335 336 /******************************************** 337 * i7300 Functions related to error detection 338 ********************************************/ 339 340 /** 341 * get_err_from_table() - Gets the error message from a table 342 * @table: table name (array of char *) 343 * @size: number of elements at the table 344 * @pos: position of the element to be returned 345 * 346 * This is a small routine that gets the pos-th element of a table. If the 347 * element doesn't exist (or it is empty), it returns "reserved". 348 * Instead of calling it directly, the better is to call via the macro 349 * GET_ERR_FROM_TABLE(), that automatically checks the table size via 350 * ARRAY_SIZE() macro 351 */ 352 static const char *get_err_from_table(const char *table[], int size, int pos) 353 { 354 if (unlikely(pos >= size)) 355 return "Reserved"; 356 357 if (unlikely(!table[pos])) 358 return "Reserved"; 359 360 return table[pos]; 361 } 362 363 #define GET_ERR_FROM_TABLE(table, pos) \ 364 get_err_from_table(table, ARRAY_SIZE(table), pos) 365 366 /** 367 * i7300_process_error_global() - Retrieve the hardware error information from 368 * the hardware global error registers and 369 * sends it to dmesg 370 * @mci: struct mem_ctl_info pointer 371 */ 372 static void i7300_process_error_global(struct mem_ctl_info *mci) 373 { 374 struct i7300_pvt *pvt; 375 u32 errnum, error_reg; 376 unsigned long errors; 377 const char *specific; 378 bool is_fatal; 379 380 pvt = mci->pvt_info; 381 382 /* read in the 1st FATAL error register */ 383 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 384 FERR_GLOBAL_HI, &error_reg); 385 if (unlikely(error_reg)) { 386 errors = error_reg; 387 errnum = find_first_bit(&errors, 388 ARRAY_SIZE(ferr_global_hi_name)); 389 specific = GET_ERR_FROM_TABLE(ferr_global_hi_name, errnum); 390 is_fatal = ferr_global_hi_is_fatal(errnum); 391 392 /* Clear the error bit */ 393 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 394 FERR_GLOBAL_HI, error_reg); 395 396 goto error_global; 397 } 398 399 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 400 FERR_GLOBAL_LO, &error_reg); 401 if (unlikely(error_reg)) { 402 errors = error_reg; 403 errnum = find_first_bit(&errors, 404 ARRAY_SIZE(ferr_global_lo_name)); 405 specific = GET_ERR_FROM_TABLE(ferr_global_lo_name, errnum); 406 is_fatal = ferr_global_lo_is_fatal(errnum); 407 408 /* Clear the error bit */ 409 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 410 FERR_GLOBAL_LO, error_reg); 411 412 goto error_global; 413 } 414 return; 415 416 error_global: 417 i7300_mc_printk(mci, KERN_EMERG, "%s misc error: %s\n", 418 is_fatal ? "Fatal" : "NOT fatal", specific); 419 } 420 421 /** 422 * i7300_process_fbd_error() - Retrieve the hardware error information from 423 * the FBD error registers and sends it via 424 * EDAC error API calls 425 * @mci: struct mem_ctl_info pointer 426 */ 427 static void i7300_process_fbd_error(struct mem_ctl_info *mci) 428 { 429 struct i7300_pvt *pvt; 430 u32 errnum, value, error_reg; 431 u16 val16; 432 unsigned branch, channel, bank, rank, cas, ras; 433 u32 syndrome; 434 435 unsigned long errors; 436 const char *specific; 437 bool is_wr; 438 439 pvt = mci->pvt_info; 440 441 /* read in the 1st FATAL error register */ 442 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 443 FERR_FAT_FBD, &error_reg); 444 if (unlikely(error_reg & FERR_FAT_FBD_ERR_MASK)) { 445 errors = error_reg & FERR_FAT_FBD_ERR_MASK ; 446 errnum = find_first_bit(&errors, 447 ARRAY_SIZE(ferr_fat_fbd_name)); 448 specific = GET_ERR_FROM_TABLE(ferr_fat_fbd_name, errnum); 449 branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0; 450 451 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, 452 NRECMEMA, &val16); 453 bank = NRECMEMA_BANK(val16); 454 rank = NRECMEMA_RANK(val16); 455 456 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 457 NRECMEMB, &value); 458 is_wr = NRECMEMB_IS_WR(value); 459 cas = NRECMEMB_CAS(value); 460 ras = NRECMEMB_RAS(value); 461 462 /* Clean the error register */ 463 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 464 FERR_FAT_FBD, error_reg); 465 466 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, 467 "Bank=%d RAS=%d CAS=%d Err=0x%lx (%s))", 468 bank, ras, cas, errors, specific); 469 470 edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 0, 0, 0, 471 branch, -1, rank, 472 is_wr ? "Write error" : "Read error", 473 pvt->tmp_prt_buffer, NULL); 474 475 } 476 477 /* read in the 1st NON-FATAL error register */ 478 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 479 FERR_NF_FBD, &error_reg); 480 if (unlikely(error_reg & FERR_NF_FBD_ERR_MASK)) { 481 errors = error_reg & FERR_NF_FBD_ERR_MASK; 482 errnum = find_first_bit(&errors, 483 ARRAY_SIZE(ferr_nf_fbd_name)); 484 specific = GET_ERR_FROM_TABLE(ferr_nf_fbd_name, errnum); 485 branch = (GET_FBD_FAT_IDX(error_reg) == 2) ? 1 : 0; 486 487 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 488 REDMEMA, &syndrome); 489 490 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, 491 RECMEMA, &val16); 492 bank = RECMEMA_BANK(val16); 493 rank = RECMEMA_RANK(val16); 494 495 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 496 RECMEMB, &value); 497 is_wr = RECMEMB_IS_WR(value); 498 cas = RECMEMB_CAS(value); 499 ras = RECMEMB_RAS(value); 500 501 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 502 REDMEMB, &value); 503 channel = (branch << 1); 504 if (IS_SECOND_CH(value)) 505 channel++; 506 507 /* Clear the error bit */ 508 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 509 FERR_NF_FBD, error_reg); 510 511 /* Form out message */ 512 snprintf(pvt->tmp_prt_buffer, PAGE_SIZE, 513 "DRAM-Bank=%d RAS=%d CAS=%d, Err=0x%lx (%s))", 514 bank, ras, cas, errors, specific); 515 516 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 517 syndrome, 518 branch >> 1, channel % 2, rank, 519 is_wr ? "Write error" : "Read error", 520 pvt->tmp_prt_buffer, NULL); 521 } 522 return; 523 } 524 525 /** 526 * i7300_check_error() - Calls the error checking subroutines 527 * @mci: struct mem_ctl_info pointer 528 */ 529 static void i7300_check_error(struct mem_ctl_info *mci) 530 { 531 i7300_process_error_global(mci); 532 i7300_process_fbd_error(mci); 533 }; 534 535 /** 536 * i7300_clear_error() - Clears the error registers 537 * @mci: struct mem_ctl_info pointer 538 */ 539 static void i7300_clear_error(struct mem_ctl_info *mci) 540 { 541 struct i7300_pvt *pvt = mci->pvt_info; 542 u32 value; 543 /* 544 * All error values are RWC - we need to read and write 1 to the 545 * bit that we want to cleanup 546 */ 547 548 /* Clear global error registers */ 549 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 550 FERR_GLOBAL_HI, &value); 551 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 552 FERR_GLOBAL_HI, value); 553 554 pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 555 FERR_GLOBAL_LO, &value); 556 pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs, 557 FERR_GLOBAL_LO, value); 558 559 /* Clear FBD error registers */ 560 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 561 FERR_FAT_FBD, &value); 562 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 563 FERR_FAT_FBD, value); 564 565 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 566 FERR_NF_FBD, &value); 567 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 568 FERR_NF_FBD, value); 569 } 570 571 /** 572 * i7300_enable_error_reporting() - Enable the memory reporting logic at the 573 * hardware 574 * @mci: struct mem_ctl_info pointer 575 */ 576 static void i7300_enable_error_reporting(struct mem_ctl_info *mci) 577 { 578 struct i7300_pvt *pvt = mci->pvt_info; 579 u32 fbd_error_mask; 580 581 /* Read the FBD Error Mask Register */ 582 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 583 EMASK_FBD, &fbd_error_mask); 584 585 /* Enable with a '0' */ 586 fbd_error_mask &= ~(EMASK_FBD_ERR_MASK); 587 588 pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map, 589 EMASK_FBD, fbd_error_mask); 590 } 591 592 /************************************************ 593 * i7300 Functions related to memory enumberation 594 ************************************************/ 595 596 /** 597 * decode_mtr() - Decodes the MTR descriptor, filling the edac structs 598 * @pvt: pointer to the private data struct used by i7300 driver 599 * @slot: DIMM slot (0 to 7) 600 * @ch: Channel number within the branch (0 or 1) 601 * @branch: Branch number (0 or 1) 602 * @dinfo: Pointer to DIMM info where dimm size is stored 603 * @p_csrow: Pointer to the struct csrow_info that corresponds to that element 604 */ 605 static int decode_mtr(struct i7300_pvt *pvt, 606 int slot, int ch, int branch, 607 struct i7300_dimm_info *dinfo, 608 struct dimm_info *dimm) 609 { 610 int mtr, ans, addrBits, channel; 611 612 channel = to_channel(ch, branch); 613 614 mtr = pvt->mtr[slot][branch]; 615 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0; 616 617 debugf2("\tMTR%d CH%d: DIMMs are %s (mtr)\n", 618 slot, channel, 619 ans ? "Present" : "NOT Present"); 620 621 /* Determine if there is a DIMM present in this DIMM slot */ 622 if (!ans) 623 return 0; 624 625 /* Start with the number of bits for a Bank 626 * on the DRAM */ 627 addrBits = MTR_DRAM_BANKS_ADDR_BITS; 628 /* Add thenumber of ROW bits */ 629 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); 630 /* add the number of COLUMN bits */ 631 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); 632 /* add the number of RANK bits */ 633 addrBits += MTR_DIMM_RANKS(mtr); 634 635 addrBits += 6; /* add 64 bits per DIMM */ 636 addrBits -= 20; /* divide by 2^^20 */ 637 addrBits -= 3; /* 8 bits per bytes */ 638 639 dinfo->megabytes = 1 << addrBits; 640 641 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); 642 643 debugf2("\t\tELECTRICAL THROTTLING is %s\n", 644 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled"); 645 646 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); 647 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single"); 648 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]); 649 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]); 650 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes); 651 652 /* 653 * The type of error detection actually depends of the 654 * mode of operation. When it is just one single memory chip, at 655 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code. 656 * In normal or mirrored mode, it uses Lockstep mode, 657 * with the possibility of using an extended algorithm for x8 memories 658 * See datasheet Sections 7.3.6 to 7.3.8 659 */ 660 661 dimm->nr_pages = MiB_TO_PAGES(dinfo->megabytes); 662 dimm->grain = 8; 663 dimm->mtype = MEM_FB_DDR2; 664 if (IS_SINGLE_MODE(pvt->mc_settings_a)) { 665 dimm->edac_mode = EDAC_SECDED; 666 debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n"); 667 } else { 668 debugf2("\t\tECC code is on Lockstep mode\n"); 669 if (MTR_DRAM_WIDTH(mtr) == 8) 670 dimm->edac_mode = EDAC_S8ECD8ED; 671 else 672 dimm->edac_mode = EDAC_S4ECD4ED; 673 } 674 675 /* ask what device type on this row */ 676 if (MTR_DRAM_WIDTH(mtr) == 8) { 677 debugf2("\t\tScrub algorithm for x8 is on %s mode\n", 678 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ? 679 "enhanced" : "normal"); 680 681 dimm->dtype = DEV_X8; 682 } else 683 dimm->dtype = DEV_X4; 684 685 return mtr; 686 } 687 688 /** 689 * print_dimm_size() - Prints dump of the memory organization 690 * @pvt: pointer to the private data struct used by i7300 driver 691 * 692 * Useful for debug. If debug is disabled, this routine do nothing 693 */ 694 static void print_dimm_size(struct i7300_pvt *pvt) 695 { 696 #ifdef CONFIG_EDAC_DEBUG 697 struct i7300_dimm_info *dinfo; 698 char *p; 699 int space, n; 700 int channel, slot; 701 702 space = PAGE_SIZE; 703 p = pvt->tmp_prt_buffer; 704 705 n = snprintf(p, space, " "); 706 p += n; 707 space -= n; 708 for (channel = 0; channel < MAX_CHANNELS; channel++) { 709 n = snprintf(p, space, "channel %d | ", channel); 710 p += n; 711 space -= n; 712 } 713 debugf2("%s\n", pvt->tmp_prt_buffer); 714 p = pvt->tmp_prt_buffer; 715 space = PAGE_SIZE; 716 n = snprintf(p, space, "-------------------------------" 717 "------------------------------"); 718 p += n; 719 space -= n; 720 debugf2("%s\n", pvt->tmp_prt_buffer); 721 p = pvt->tmp_prt_buffer; 722 space = PAGE_SIZE; 723 724 for (slot = 0; slot < MAX_SLOTS; slot++) { 725 n = snprintf(p, space, "csrow/SLOT %d ", slot); 726 p += n; 727 space -= n; 728 729 for (channel = 0; channel < MAX_CHANNELS; channel++) { 730 dinfo = &pvt->dimm_info[slot][channel]; 731 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); 732 p += n; 733 space -= n; 734 } 735 736 debugf2("%s\n", pvt->tmp_prt_buffer); 737 p = pvt->tmp_prt_buffer; 738 space = PAGE_SIZE; 739 } 740 741 n = snprintf(p, space, "-------------------------------" 742 "------------------------------"); 743 p += n; 744 space -= n; 745 debugf2("%s\n", pvt->tmp_prt_buffer); 746 p = pvt->tmp_prt_buffer; 747 space = PAGE_SIZE; 748 #endif 749 } 750 751 /** 752 * i7300_init_csrows() - Initialize the 'csrows' table within 753 * the mci control structure with the 754 * addressing of memory. 755 * @mci: struct mem_ctl_info pointer 756 */ 757 static int i7300_init_csrows(struct mem_ctl_info *mci) 758 { 759 struct i7300_pvt *pvt; 760 struct i7300_dimm_info *dinfo; 761 int rc = -ENODEV; 762 int mtr; 763 int ch, branch, slot, channel; 764 struct dimm_info *dimm; 765 766 pvt = mci->pvt_info; 767 768 debugf2("Memory Technology Registers:\n"); 769 770 /* Get the AMB present registers for the four channels */ 771 for (branch = 0; branch < MAX_BRANCHES; branch++) { 772 /* Read and dump branch 0's MTRs */ 773 channel = to_channel(0, branch); 774 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], 775 AMBPRESENT_0, 776 &pvt->ambpresent[channel]); 777 debugf2("\t\tAMB-present CH%d = 0x%x:\n", 778 channel, pvt->ambpresent[channel]); 779 780 channel = to_channel(1, branch); 781 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], 782 AMBPRESENT_1, 783 &pvt->ambpresent[channel]); 784 debugf2("\t\tAMB-present CH%d = 0x%x:\n", 785 channel, pvt->ambpresent[channel]); 786 } 787 788 /* Get the set of MTR[0-7] regs by each branch */ 789 for (slot = 0; slot < MAX_SLOTS; slot++) { 790 int where = mtr_regs[slot]; 791 for (branch = 0; branch < MAX_BRANCHES; branch++) { 792 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch], 793 where, 794 &pvt->mtr[slot][branch]); 795 for (ch = 0; ch < MAX_CH_PER_BRANCH; ch++) { 796 int channel = to_channel(ch, branch); 797 798 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, 799 mci->n_layers, branch, ch, slot); 800 801 dinfo = &pvt->dimm_info[slot][channel]; 802 803 mtr = decode_mtr(pvt, slot, ch, branch, 804 dinfo, dimm); 805 806 /* if no DIMMS on this row, continue */ 807 if (!MTR_DIMMS_PRESENT(mtr)) 808 continue; 809 810 rc = 0; 811 812 } 813 } 814 } 815 816 return rc; 817 } 818 819 /** 820 * decode_mir() - Decodes Memory Interleave Register (MIR) info 821 * @int mir_no: number of the MIR register to decode 822 * @mir: array with the MIR data cached on the driver 823 */ 824 static void decode_mir(int mir_no, u16 mir[MAX_MIR]) 825 { 826 if (mir[mir_no] & 3) 827 debugf2("MIR%d: limit= 0x%x Branch(es) that participate:" 828 " %s %s\n", 829 mir_no, 830 (mir[mir_no] >> 4) & 0xfff, 831 (mir[mir_no] & 1) ? "B0" : "", 832 (mir[mir_no] & 2) ? "B1" : ""); 833 } 834 835 /** 836 * i7300_get_mc_regs() - Get the contents of the MC enumeration registers 837 * @mci: struct mem_ctl_info pointer 838 * 839 * Data read is cached internally for its usage when needed 840 */ 841 static int i7300_get_mc_regs(struct mem_ctl_info *mci) 842 { 843 struct i7300_pvt *pvt; 844 u32 actual_tolm; 845 int i, rc; 846 847 pvt = mci->pvt_info; 848 849 pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE, 850 (u32 *) &pvt->ambase); 851 852 debugf2("AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase); 853 854 /* Get the Branch Map regs */ 855 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm); 856 pvt->tolm >>= 12; 857 debugf2("TOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm, 858 pvt->tolm); 859 860 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); 861 debugf2("Actual TOLM byte addr=%u.%03u GB (0x%x)\n", 862 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); 863 864 /* Get memory controller settings */ 865 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS, 866 &pvt->mc_settings); 867 pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A, 868 &pvt->mc_settings_a); 869 870 if (IS_SINGLE_MODE(pvt->mc_settings_a)) 871 debugf0("Memory controller operating on single mode\n"); 872 else 873 debugf0("Memory controller operating on %s mode\n", 874 IS_MIRRORED(pvt->mc_settings) ? "mirrored" : "non-mirrored"); 875 876 debugf0("Error detection is %s\n", 877 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); 878 debugf0("Retry is %s\n", 879 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled"); 880 881 /* Get Memory Interleave Range registers */ 882 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0, 883 &pvt->mir[0]); 884 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1, 885 &pvt->mir[1]); 886 pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2, 887 &pvt->mir[2]); 888 889 /* Decode the MIR regs */ 890 for (i = 0; i < MAX_MIR; i++) 891 decode_mir(i, pvt->mir); 892 893 rc = i7300_init_csrows(mci); 894 if (rc < 0) 895 return rc; 896 897 /* Go and determine the size of each DIMM and place in an 898 * orderly matrix */ 899 print_dimm_size(pvt); 900 901 return 0; 902 } 903 904 /************************************************* 905 * i7300 Functions related to device probe/release 906 *************************************************/ 907 908 /** 909 * i7300_put_devices() - Release the PCI devices 910 * @mci: struct mem_ctl_info pointer 911 */ 912 static void i7300_put_devices(struct mem_ctl_info *mci) 913 { 914 struct i7300_pvt *pvt; 915 int branch; 916 917 pvt = mci->pvt_info; 918 919 /* Decrement usage count for devices */ 920 for (branch = 0; branch < MAX_CH_PER_BRANCH; branch++) 921 pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]); 922 pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs); 923 pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map); 924 } 925 926 /** 927 * i7300_get_devices() - Find and perform 'get' operation on the MCH's 928 * device/functions we want to reference for this driver 929 * @mci: struct mem_ctl_info pointer 930 * 931 * Access and prepare the several devices for usage: 932 * I7300 devices used by this driver: 933 * Device 16, functions 0,1 and 2: PCI_DEVICE_ID_INTEL_I7300_MCH_ERR 934 * Device 21 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 935 * Device 22 function 0: PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 936 */ 937 static int __devinit i7300_get_devices(struct mem_ctl_info *mci) 938 { 939 struct i7300_pvt *pvt; 940 struct pci_dev *pdev; 941 942 pvt = mci->pvt_info; 943 944 /* Attempt to 'get' the MCH register we want */ 945 pdev = NULL; 946 while (!pvt->pci_dev_16_1_fsb_addr_map || 947 !pvt->pci_dev_16_2_fsb_err_regs) { 948 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 949 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR, pdev); 950 if (!pdev) { 951 /* End of list, leave */ 952 i7300_printk(KERN_ERR, 953 "'system address,Process Bus' " 954 "device not found:" 955 "vendor 0x%x device 0x%x ERR funcs " 956 "(broken BIOS?)\n", 957 PCI_VENDOR_ID_INTEL, 958 PCI_DEVICE_ID_INTEL_I7300_MCH_ERR); 959 goto error; 960 } 961 962 /* Store device 16 funcs 1 and 2 */ 963 switch (PCI_FUNC(pdev->devfn)) { 964 case 1: 965 pvt->pci_dev_16_1_fsb_addr_map = pdev; 966 break; 967 case 2: 968 pvt->pci_dev_16_2_fsb_err_regs = pdev; 969 break; 970 } 971 } 972 973 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n", 974 pci_name(pvt->pci_dev_16_0_fsb_ctlr), 975 pvt->pci_dev_16_0_fsb_ctlr->vendor, 976 pvt->pci_dev_16_0_fsb_ctlr->device); 977 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", 978 pci_name(pvt->pci_dev_16_1_fsb_addr_map), 979 pvt->pci_dev_16_1_fsb_addr_map->vendor, 980 pvt->pci_dev_16_1_fsb_addr_map->device); 981 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n", 982 pci_name(pvt->pci_dev_16_2_fsb_err_regs), 983 pvt->pci_dev_16_2_fsb_err_regs->vendor, 984 pvt->pci_dev_16_2_fsb_err_regs->device); 985 986 pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL, 987 PCI_DEVICE_ID_INTEL_I7300_MCH_FB0, 988 NULL); 989 if (!pvt->pci_dev_2x_0_fbd_branch[0]) { 990 i7300_printk(KERN_ERR, 991 "MC: 'BRANCH 0' device not found:" 992 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", 993 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_FB0); 994 goto error; 995 } 996 997 pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL, 998 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1, 999 NULL); 1000 if (!pvt->pci_dev_2x_0_fbd_branch[1]) { 1001 i7300_printk(KERN_ERR, 1002 "MC: 'BRANCH 1' device not found:" 1003 "vendor 0x%x device 0x%x Func 0 " 1004 "(broken BIOS?)\n", 1005 PCI_VENDOR_ID_INTEL, 1006 PCI_DEVICE_ID_INTEL_I7300_MCH_FB1); 1007 goto error; 1008 } 1009 1010 return 0; 1011 1012 error: 1013 i7300_put_devices(mci); 1014 return -ENODEV; 1015 } 1016 1017 /** 1018 * i7300_init_one() - Probe for one instance of the device 1019 * @pdev: struct pci_dev pointer 1020 * @id: struct pci_device_id pointer - currently unused 1021 */ 1022 static int __devinit i7300_init_one(struct pci_dev *pdev, 1023 const struct pci_device_id *id) 1024 { 1025 struct mem_ctl_info *mci; 1026 struct edac_mc_layer layers[3]; 1027 struct i7300_pvt *pvt; 1028 int rc; 1029 1030 /* wake up device */ 1031 rc = pci_enable_device(pdev); 1032 if (rc == -EIO) 1033 return rc; 1034 1035 debugf0("MC: " __FILE__ ": %s(), pdev bus %u dev=0x%x fn=0x%x\n", 1036 __func__, 1037 pdev->bus->number, 1038 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1039 1040 /* We only are looking for func 0 of the set */ 1041 if (PCI_FUNC(pdev->devfn) != 0) 1042 return -ENODEV; 1043 1044 /* allocate a new MC control structure */ 1045 layers[0].type = EDAC_MC_LAYER_BRANCH; 1046 layers[0].size = MAX_BRANCHES; 1047 layers[0].is_virt_csrow = false; 1048 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1049 layers[1].size = MAX_CH_PER_BRANCH; 1050 layers[1].is_virt_csrow = true; 1051 layers[2].type = EDAC_MC_LAYER_SLOT; 1052 layers[2].size = MAX_SLOTS; 1053 layers[2].is_virt_csrow = true; 1054 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); 1055 if (mci == NULL) 1056 return -ENOMEM; 1057 1058 debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci); 1059 1060 mci->dev = &pdev->dev; /* record ptr to the generic device */ 1061 1062 pvt = mci->pvt_info; 1063 pvt->pci_dev_16_0_fsb_ctlr = pdev; /* Record this device in our private */ 1064 1065 pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL); 1066 if (!pvt->tmp_prt_buffer) { 1067 edac_mc_free(mci); 1068 return -ENOMEM; 1069 } 1070 1071 /* 'get' the pci devices we want to reserve for our use */ 1072 if (i7300_get_devices(mci)) 1073 goto fail0; 1074 1075 mci->mc_idx = 0; 1076 mci->mtype_cap = MEM_FLAG_FB_DDR2; 1077 mci->edac_ctl_cap = EDAC_FLAG_NONE; 1078 mci->edac_cap = EDAC_FLAG_NONE; 1079 mci->mod_name = "i7300_edac.c"; 1080 mci->mod_ver = I7300_REVISION; 1081 mci->ctl_name = i7300_devs[0].ctl_name; 1082 mci->dev_name = pci_name(pdev); 1083 mci->ctl_page_to_phys = NULL; 1084 1085 /* Set the function pointer to an actual operation function */ 1086 mci->edac_check = i7300_check_error; 1087 1088 /* initialize the MC control structure 'csrows' table 1089 * with the mapping and control information */ 1090 if (i7300_get_mc_regs(mci)) { 1091 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n" 1092 " because i7300_init_csrows() returned nonzero " 1093 "value\n"); 1094 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ 1095 } else { 1096 debugf1("MC: Enable error reporting now\n"); 1097 i7300_enable_error_reporting(mci); 1098 } 1099 1100 /* add this new MC control structure to EDAC's list of MCs */ 1101 if (edac_mc_add_mc(mci)) { 1102 debugf0("MC: " __FILE__ 1103 ": %s(): failed edac_mc_add_mc()\n", __func__); 1104 /* FIXME: perhaps some code should go here that disables error 1105 * reporting if we just enabled it 1106 */ 1107 goto fail1; 1108 } 1109 1110 i7300_clear_error(mci); 1111 1112 /* allocating generic PCI control info */ 1113 i7300_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 1114 if (!i7300_pci) { 1115 printk(KERN_WARNING 1116 "%s(): Unable to create PCI control\n", 1117 __func__); 1118 printk(KERN_WARNING 1119 "%s(): PCI error report via EDAC not setup\n", 1120 __func__); 1121 } 1122 1123 return 0; 1124 1125 /* Error exit unwinding stack */ 1126 fail1: 1127 1128 i7300_put_devices(mci); 1129 1130 fail0: 1131 kfree(pvt->tmp_prt_buffer); 1132 edac_mc_free(mci); 1133 return -ENODEV; 1134 } 1135 1136 /** 1137 * i7300_remove_one() - Remove the driver 1138 * @pdev: struct pci_dev pointer 1139 */ 1140 static void __devexit i7300_remove_one(struct pci_dev *pdev) 1141 { 1142 struct mem_ctl_info *mci; 1143 char *tmp; 1144 1145 debugf0(__FILE__ ": %s()\n", __func__); 1146 1147 if (i7300_pci) 1148 edac_pci_release_generic_ctl(i7300_pci); 1149 1150 mci = edac_mc_del_mc(&pdev->dev); 1151 if (!mci) 1152 return; 1153 1154 tmp = ((struct i7300_pvt *)mci->pvt_info)->tmp_prt_buffer; 1155 1156 /* retrieve references to resources, and free those resources */ 1157 i7300_put_devices(mci); 1158 1159 kfree(tmp); 1160 edac_mc_free(mci); 1161 } 1162 1163 /* 1164 * pci_device_id: table for which devices we are looking for 1165 * 1166 * Has only 8086:360c PCI ID 1167 */ 1168 static DEFINE_PCI_DEVICE_TABLE(i7300_pci_tbl) = { 1169 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I7300_MCH_ERR)}, 1170 {0,} /* 0 terminated list. */ 1171 }; 1172 1173 MODULE_DEVICE_TABLE(pci, i7300_pci_tbl); 1174 1175 /* 1176 * i7300_driver: pci_driver structure for this module 1177 */ 1178 static struct pci_driver i7300_driver = { 1179 .name = "i7300_edac", 1180 .probe = i7300_init_one, 1181 .remove = __devexit_p(i7300_remove_one), 1182 .id_table = i7300_pci_tbl, 1183 }; 1184 1185 /** 1186 * i7300_init() - Registers the driver 1187 */ 1188 static int __init i7300_init(void) 1189 { 1190 int pci_rc; 1191 1192 debugf2("MC: " __FILE__ ": %s()\n", __func__); 1193 1194 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1195 opstate_init(); 1196 1197 pci_rc = pci_register_driver(&i7300_driver); 1198 1199 return (pci_rc < 0) ? pci_rc : 0; 1200 } 1201 1202 /** 1203 * i7300_init() - Unregisters the driver 1204 */ 1205 static void __exit i7300_exit(void) 1206 { 1207 debugf2("MC: " __FILE__ ": %s()\n", __func__); 1208 pci_unregister_driver(&i7300_driver); 1209 } 1210 1211 module_init(i7300_init); 1212 module_exit(i7300_exit); 1213 1214 MODULE_LICENSE("GPL"); 1215 MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>"); 1216 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)"); 1217 MODULE_DESCRIPTION("MC Driver for Intel I7300 memory controllers - " 1218 I7300_REVISION); 1219 1220 module_param(edac_op_state, int, 0444); 1221 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 1222