1 /* 2 * Intel 5400 class Memory Controllers kernel module (Seaburg) 3 * 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * Copyright (c) 2008 by: 8 * Ben Woodard <woodard@redhat.com> 9 * Mauro Carvalho Chehab 10 * 11 * Red Hat Inc. https://www.redhat.com 12 * 13 * Forked and adapted from the i5000_edac driver which was 14 * written by Douglas Thompson Linux Networx <norsk5@xmission.com> 15 * 16 * This module is based on the following document: 17 * 18 * Intel 5400 Chipset Memory Controller Hub (MCH) - Datasheet 19 * http://developer.intel.com/design/chipsets/datashts/313070.htm 20 * 21 * This Memory Controller manages DDR2 FB-DIMMs. It has 2 branches, each with 22 * 2 channels operating in lockstep no-mirror mode. Each channel can have up to 23 * 4 dimm's, each with up to 8GB. 24 * 25 */ 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/pci.h> 30 #include <linux/pci_ids.h> 31 #include <linux/slab.h> 32 #include <linux/edac.h> 33 #include <linux/mmzone.h> 34 #include <linux/string_choices.h> 35 36 #include "edac_module.h" 37 38 /* 39 * Alter this version for the I5400 module when modifications are made 40 */ 41 #define I5400_REVISION " Ver: 1.0.0" 42 43 #define EDAC_MOD_STR "i5400_edac" 44 45 #define i5400_printk(level, fmt, arg...) \ 46 edac_printk(level, "i5400", fmt, ##arg) 47 48 #define i5400_mc_printk(mci, level, fmt, arg...) \ 49 edac_mc_chipset_printk(mci, level, "i5400", fmt, ##arg) 50 51 /* Limits for i5400 */ 52 #define MAX_BRANCHES 2 53 #define CHANNELS_PER_BRANCH 2 54 #define DIMMS_PER_CHANNEL 4 55 #define MAX_CHANNELS (MAX_BRANCHES * CHANNELS_PER_BRANCH) 56 57 /* Device 16, 58 * Function 0: System Address 59 * Function 1: Memory Branch Map, Control, Errors Register 60 * Function 2: FSB Error Registers 61 * 62 * All 3 functions of Device 16 (0,1,2) share the SAME DID and 63 * uses PCI_DEVICE_ID_INTEL_5400_ERR for device 16 (0,1,2), 64 * PCI_DEVICE_ID_INTEL_5400_FBD0 and PCI_DEVICE_ID_INTEL_5400_FBD1 65 * for device 21 (0,1). 66 */ 67 68 /* OFFSETS for Function 0 */ 69 #define AMBASE 0x48 /* AMB Mem Mapped Reg Region Base */ 70 #define MAXCH 0x56 /* Max Channel Number */ 71 #define MAXDIMMPERCH 0x57 /* Max DIMM PER Channel Number */ 72 73 /* OFFSETS for Function 1 */ 74 #define TOLM 0x6C 75 #define REDMEMB 0x7C 76 #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3fe00) /* bits [17:9] indicate ODD, [8:0] indicate EVEN */ 77 #define MIR0 0x80 78 #define MIR1 0x84 79 #define AMIR0 0x8c 80 #define AMIR1 0x90 81 82 /* Fatal error registers */ 83 #define FERR_FAT_FBD 0x98 /* also called as FERR_FAT_FB_DIMM at datasheet */ 84 #define FERR_FAT_FBDCHAN (3<<28) /* channel index where the highest-order error occurred */ 85 86 #define NERR_FAT_FBD 0x9c 87 #define FERR_NF_FBD 0xa0 /* also called as FERR_NFAT_FB_DIMM at datasheet */ 88 89 /* Non-fatal error register */ 90 #define NERR_NF_FBD 0xa4 91 92 /* Enable error mask */ 93 #define EMASK_FBD 0xa8 94 95 #define ERR0_FBD 0xac 96 #define ERR1_FBD 0xb0 97 #define ERR2_FBD 0xb4 98 #define MCERR_FBD 0xb8 99 100 /* No OFFSETS for Device 16 Function 2 */ 101 102 /* 103 * Device 21, 104 * Function 0: Memory Map Branch 0 105 * 106 * Device 22, 107 * Function 0: Memory Map Branch 1 108 */ 109 110 /* OFFSETS for Function 0 */ 111 #define AMBPRESENT_0 0x64 112 #define AMBPRESENT_1 0x66 113 #define MTR0 0x80 114 #define MTR1 0x82 115 #define MTR2 0x84 116 #define MTR3 0x86 117 118 /* OFFSETS for Function 1 */ 119 #define NRECFGLOG 0x74 120 #define RECFGLOG 0x78 121 #define NRECMEMA 0xbe 122 #define NRECMEMB 0xc0 123 #define NRECFB_DIMMA 0xc4 124 #define NRECFB_DIMMB 0xc8 125 #define NRECFB_DIMMC 0xcc 126 #define NRECFB_DIMMD 0xd0 127 #define NRECFB_DIMME 0xd4 128 #define NRECFB_DIMMF 0xd8 129 #define REDMEMA 0xdC 130 #define RECMEMA 0xf0 131 #define RECMEMB 0xf4 132 #define RECFB_DIMMA 0xf8 133 #define RECFB_DIMMB 0xec 134 #define RECFB_DIMMC 0xf0 135 #define RECFB_DIMMD 0xf4 136 #define RECFB_DIMME 0xf8 137 #define RECFB_DIMMF 0xfC 138 139 /* 140 * Error indicator bits and masks 141 * Error masks are according with Table 5-17 of i5400 datasheet 142 */ 143 144 enum error_mask { 145 EMASK_M1 = 1<<0, /* Memory Write error on non-redundant retry */ 146 EMASK_M2 = 1<<1, /* Memory or FB-DIMM configuration CRC read error */ 147 EMASK_M3 = 1<<2, /* Reserved */ 148 EMASK_M4 = 1<<3, /* Uncorrectable Data ECC on Replay */ 149 EMASK_M5 = 1<<4, /* Aliased Uncorrectable Non-Mirrored Demand Data ECC */ 150 EMASK_M6 = 1<<5, /* Unsupported on i5400 */ 151 EMASK_M7 = 1<<6, /* Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ 152 EMASK_M8 = 1<<7, /* Aliased Uncorrectable Patrol Data ECC */ 153 EMASK_M9 = 1<<8, /* Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC */ 154 EMASK_M10 = 1<<9, /* Unsupported on i5400 */ 155 EMASK_M11 = 1<<10, /* Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC */ 156 EMASK_M12 = 1<<11, /* Non-Aliased Uncorrectable Patrol Data ECC */ 157 EMASK_M13 = 1<<12, /* Memory Write error on first attempt */ 158 EMASK_M14 = 1<<13, /* FB-DIMM Configuration Write error on first attempt */ 159 EMASK_M15 = 1<<14, /* Memory or FB-DIMM configuration CRC read error */ 160 EMASK_M16 = 1<<15, /* Channel Failed-Over Occurred */ 161 EMASK_M17 = 1<<16, /* Correctable Non-Mirrored Demand Data ECC */ 162 EMASK_M18 = 1<<17, /* Unsupported on i5400 */ 163 EMASK_M19 = 1<<18, /* Correctable Resilver- or Spare-Copy Data ECC */ 164 EMASK_M20 = 1<<19, /* Correctable Patrol Data ECC */ 165 EMASK_M21 = 1<<20, /* FB-DIMM Northbound parity error on FB-DIMM Sync Status */ 166 EMASK_M22 = 1<<21, /* SPD protocol Error */ 167 EMASK_M23 = 1<<22, /* Non-Redundant Fast Reset Timeout */ 168 EMASK_M24 = 1<<23, /* Refresh error */ 169 EMASK_M25 = 1<<24, /* Memory Write error on redundant retry */ 170 EMASK_M26 = 1<<25, /* Redundant Fast Reset Timeout */ 171 EMASK_M27 = 1<<26, /* Correctable Counter Threshold Exceeded */ 172 EMASK_M28 = 1<<27, /* DIMM-Spare Copy Completed */ 173 EMASK_M29 = 1<<28, /* DIMM-Isolation Completed */ 174 }; 175 176 /* 177 * Names to translate bit error into something useful 178 */ 179 static const char *error_name[] = { 180 [0] = "Memory Write error on non-redundant retry", 181 [1] = "Memory or FB-DIMM configuration CRC read error", 182 /* Reserved */ 183 [3] = "Uncorrectable Data ECC on Replay", 184 [4] = "Aliased Uncorrectable Non-Mirrored Demand Data ECC", 185 /* M6 Unsupported on i5400 */ 186 [6] = "Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 187 [7] = "Aliased Uncorrectable Patrol Data ECC", 188 [8] = "Non-Aliased Uncorrectable Non-Mirrored Demand Data ECC", 189 /* M10 Unsupported on i5400 */ 190 [10] = "Non-Aliased Uncorrectable Resilver- or Spare-Copy Data ECC", 191 [11] = "Non-Aliased Uncorrectable Patrol Data ECC", 192 [12] = "Memory Write error on first attempt", 193 [13] = "FB-DIMM Configuration Write error on first attempt", 194 [14] = "Memory or FB-DIMM configuration CRC read error", 195 [15] = "Channel Failed-Over Occurred", 196 [16] = "Correctable Non-Mirrored Demand Data ECC", 197 /* M18 Unsupported on i5400 */ 198 [18] = "Correctable Resilver- or Spare-Copy Data ECC", 199 [19] = "Correctable Patrol Data ECC", 200 [20] = "FB-DIMM Northbound parity error on FB-DIMM Sync Status", 201 [21] = "SPD protocol Error", 202 [22] = "Non-Redundant Fast Reset Timeout", 203 [23] = "Refresh error", 204 [24] = "Memory Write error on redundant retry", 205 [25] = "Redundant Fast Reset Timeout", 206 [26] = "Correctable Counter Threshold Exceeded", 207 [27] = "DIMM-Spare Copy Completed", 208 [28] = "DIMM-Isolation Completed", 209 }; 210 211 /* Fatal errors */ 212 #define ERROR_FAT_MASK (EMASK_M1 | \ 213 EMASK_M2 | \ 214 EMASK_M23) 215 216 /* Correctable errors */ 217 #define ERROR_NF_CORRECTABLE (EMASK_M27 | \ 218 EMASK_M20 | \ 219 EMASK_M19 | \ 220 EMASK_M18 | \ 221 EMASK_M17 | \ 222 EMASK_M16) 223 #define ERROR_NF_DIMM_SPARE (EMASK_M29 | \ 224 EMASK_M28) 225 #define ERROR_NF_SPD_PROTOCOL (EMASK_M22) 226 #define ERROR_NF_NORTH_CRC (EMASK_M21) 227 228 /* Recoverable errors */ 229 #define ERROR_NF_RECOVERABLE (EMASK_M26 | \ 230 EMASK_M25 | \ 231 EMASK_M24 | \ 232 EMASK_M15 | \ 233 EMASK_M14 | \ 234 EMASK_M13 | \ 235 EMASK_M12 | \ 236 EMASK_M11 | \ 237 EMASK_M9 | \ 238 EMASK_M8 | \ 239 EMASK_M7 | \ 240 EMASK_M5) 241 242 /* uncorrectable errors */ 243 #define ERROR_NF_UNCORRECTABLE (EMASK_M4) 244 245 /* mask to all non-fatal errors */ 246 #define ERROR_NF_MASK (ERROR_NF_CORRECTABLE | \ 247 ERROR_NF_UNCORRECTABLE | \ 248 ERROR_NF_RECOVERABLE | \ 249 ERROR_NF_DIMM_SPARE | \ 250 ERROR_NF_SPD_PROTOCOL | \ 251 ERROR_NF_NORTH_CRC) 252 253 /* 254 * Define error masks for the several registers 255 */ 256 257 /* Enable all fatal and non fatal errors */ 258 #define ENABLE_EMASK_ALL (ERROR_FAT_MASK | ERROR_NF_MASK) 259 260 /* mask for fatal error registers */ 261 #define FERR_FAT_MASK ERROR_FAT_MASK 262 263 /* masks for non-fatal error register */ 264 static inline int to_nf_mask(unsigned int mask) 265 { 266 return (mask & EMASK_M29) | (mask >> 3); 267 }; 268 269 static inline int from_nf_ferr(unsigned int mask) 270 { 271 return (mask & EMASK_M29) | /* Bit 28 */ 272 (mask & ((1 << 28) - 1) << 3); /* Bits 0 to 27 */ 273 }; 274 275 #define FERR_NF_MASK to_nf_mask(ERROR_NF_MASK) 276 #define FERR_NF_CORRECTABLE to_nf_mask(ERROR_NF_CORRECTABLE) 277 #define FERR_NF_DIMM_SPARE to_nf_mask(ERROR_NF_DIMM_SPARE) 278 #define FERR_NF_SPD_PROTOCOL to_nf_mask(ERROR_NF_SPD_PROTOCOL) 279 #define FERR_NF_NORTH_CRC to_nf_mask(ERROR_NF_NORTH_CRC) 280 #define FERR_NF_RECOVERABLE to_nf_mask(ERROR_NF_RECOVERABLE) 281 #define FERR_NF_UNCORRECTABLE to_nf_mask(ERROR_NF_UNCORRECTABLE) 282 283 /* 284 * Defines to extract the various fields from the 285 * MTRx - Memory Technology Registers 286 */ 287 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (1 << 10)) 288 #define MTR_DIMMS_ETHROTTLE(mtr) ((mtr) & (1 << 9)) 289 #define MTR_DRAM_WIDTH(mtr) (((mtr) & (1 << 8)) ? 8 : 4) 290 #define MTR_DRAM_BANKS(mtr) (((mtr) & (1 << 6)) ? 8 : 4) 291 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) 292 #define MTR_DIMM_RANK(mtr) (((mtr) >> 5) & 0x1) 293 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) 294 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) 295 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) 296 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) 297 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) 298 299 /* This applies to FERR_NF_FB-DIMM as well as FERR_FAT_FB-DIMM */ 300 static inline int extract_fbdchan_indx(u32 x) 301 { 302 return (x>>28) & 0x3; 303 } 304 305 /* Device name and register DID (Device ID) */ 306 struct i5400_dev_info { 307 const char *ctl_name; /* name for this device */ 308 u16 fsb_mapping_errors; /* DID for the branchmap,control */ 309 }; 310 311 /* Table of devices attributes supported by this driver */ 312 static const struct i5400_dev_info i5400_devs[] = { 313 { 314 .ctl_name = "I5400", 315 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_5400_ERR, 316 }, 317 }; 318 319 struct i5400_dimm_info { 320 int megabytes; /* size, 0 means not present */ 321 }; 322 323 /* driver private data structure */ 324 struct i5400_pvt { 325 struct pci_dev *system_address; /* 16.0 */ 326 struct pci_dev *branchmap_werrors; /* 16.1 */ 327 struct pci_dev *fsb_error_regs; /* 16.2 */ 328 struct pci_dev *branch_0; /* 21.0 */ 329 struct pci_dev *branch_1; /* 22.0 */ 330 331 u16 tolm; /* top of low memory */ 332 union { 333 u64 ambase; /* AMB BAR */ 334 struct { 335 u32 ambase_bottom; 336 u32 ambase_top; 337 } u __packed; 338 }; 339 340 u16 mir0, mir1; 341 342 u16 b0_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ 343 u16 b0_ambpresent0; /* Branch 0, Channel 0 */ 344 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */ 345 346 u16 b1_mtr[DIMMS_PER_CHANNEL]; /* Memory Technlogy Reg */ 347 u16 b1_ambpresent0; /* Branch 1, Channel 8 */ 348 u16 b1_ambpresent1; /* Branch 1, Channel 1 */ 349 350 /* DIMM information matrix, allocating architecture maximums */ 351 struct i5400_dimm_info dimm_info[DIMMS_PER_CHANNEL][MAX_CHANNELS]; 352 353 /* Actual values for this controller */ 354 int maxch; /* Max channels */ 355 int maxdimmperch; /* Max DIMMs per channel */ 356 357 /* Hardware error reporting status */ 358 bool enabled_error_reporting; 359 }; 360 361 /* I5400 MCH error information retrieved from Hardware */ 362 struct i5400_error_info { 363 /* These registers are always read from the MC */ 364 u32 ferr_fat_fbd; /* First Errors Fatal */ 365 u32 nerr_fat_fbd; /* Next Errors Fatal */ 366 u32 ferr_nf_fbd; /* First Errors Non-Fatal */ 367 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */ 368 369 /* These registers are input ONLY if there was a Recoverable Error */ 370 u32 redmemb; /* Recoverable Mem Data Error log B */ 371 u16 recmema; /* Recoverable Mem Error log A */ 372 u32 recmemb; /* Recoverable Mem Error log B */ 373 374 /* These registers are input ONLY if there was a Non-Rec Error */ 375 u16 nrecmema; /* Non-Recoverable Mem log A */ 376 u32 nrecmemb; /* Non-Recoverable Mem log B */ 377 378 }; 379 380 /* note that nrec_rdwr changed from NRECMEMA to NRECMEMB between the 5000 and 381 5400 better to use an inline function than a macro in this case */ 382 static inline int nrec_bank(struct i5400_error_info *info) 383 { 384 return ((info->nrecmema) >> 12) & 0x7; 385 } 386 static inline int nrec_rank(struct i5400_error_info *info) 387 { 388 return ((info->nrecmema) >> 8) & 0xf; 389 } 390 static inline int nrec_buf_id(struct i5400_error_info *info) 391 { 392 return ((info->nrecmema)) & 0xff; 393 } 394 static inline int nrec_rdwr(struct i5400_error_info *info) 395 { 396 return (info->nrecmemb) >> 31; 397 } 398 /* This applies to both NREC and REC string so it can be used with nrec_rdwr 399 and rec_rdwr */ 400 static inline const char *rdwr_str(int rdwr) 401 { 402 return rdwr ? "Write" : "Read"; 403 } 404 static inline int nrec_cas(struct i5400_error_info *info) 405 { 406 return ((info->nrecmemb) >> 16) & 0x1fff; 407 } 408 static inline int nrec_ras(struct i5400_error_info *info) 409 { 410 return (info->nrecmemb) & 0xffff; 411 } 412 static inline int rec_bank(struct i5400_error_info *info) 413 { 414 return ((info->recmema) >> 12) & 0x7; 415 } 416 static inline int rec_rank(struct i5400_error_info *info) 417 { 418 return ((info->recmema) >> 8) & 0xf; 419 } 420 static inline int rec_rdwr(struct i5400_error_info *info) 421 { 422 return (info->recmemb) >> 31; 423 } 424 static inline int rec_cas(struct i5400_error_info *info) 425 { 426 return ((info->recmemb) >> 16) & 0x1fff; 427 } 428 static inline int rec_ras(struct i5400_error_info *info) 429 { 430 return (info->recmemb) & 0xffff; 431 } 432 433 static struct edac_pci_ctl_info *i5400_pci; 434 435 /* 436 * i5400_get_error_info Retrieve the hardware error information from 437 * the hardware and cache it in the 'info' 438 * structure 439 */ 440 static void i5400_get_error_info(struct mem_ctl_info *mci, 441 struct i5400_error_info *info) 442 { 443 struct i5400_pvt *pvt; 444 u32 value; 445 446 pvt = mci->pvt_info; 447 448 /* read in the 1st FATAL error register */ 449 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); 450 451 /* Mask only the bits that the doc says are valid 452 */ 453 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK); 454 455 /* If there is an error, then read in the 456 NEXT FATAL error register and the Memory Error Log Register A 457 */ 458 if (value & FERR_FAT_MASK) { 459 info->ferr_fat_fbd = value; 460 461 /* harvest the various error data we need */ 462 pci_read_config_dword(pvt->branchmap_werrors, 463 NERR_FAT_FBD, &info->nerr_fat_fbd); 464 pci_read_config_word(pvt->branchmap_werrors, 465 NRECMEMA, &info->nrecmema); 466 pci_read_config_dword(pvt->branchmap_werrors, 467 NRECMEMB, &info->nrecmemb); 468 469 /* Clear the error bits, by writing them back */ 470 pci_write_config_dword(pvt->branchmap_werrors, 471 FERR_FAT_FBD, value); 472 } else { 473 info->ferr_fat_fbd = 0; 474 info->nerr_fat_fbd = 0; 475 info->nrecmema = 0; 476 info->nrecmemb = 0; 477 } 478 479 /* read in the 1st NON-FATAL error register */ 480 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); 481 482 /* If there is an error, then read in the 1st NON-FATAL error 483 * register as well */ 484 if (value & FERR_NF_MASK) { 485 info->ferr_nf_fbd = value; 486 487 /* harvest the various error data we need */ 488 pci_read_config_dword(pvt->branchmap_werrors, 489 NERR_NF_FBD, &info->nerr_nf_fbd); 490 pci_read_config_word(pvt->branchmap_werrors, 491 RECMEMA, &info->recmema); 492 pci_read_config_dword(pvt->branchmap_werrors, 493 RECMEMB, &info->recmemb); 494 pci_read_config_dword(pvt->branchmap_werrors, 495 REDMEMB, &info->redmemb); 496 497 /* Clear the error bits, by writing them back */ 498 pci_write_config_dword(pvt->branchmap_werrors, 499 FERR_NF_FBD, value); 500 } else { 501 info->ferr_nf_fbd = 0; 502 info->nerr_nf_fbd = 0; 503 info->recmema = 0; 504 info->recmemb = 0; 505 info->redmemb = 0; 506 } 507 } 508 509 /* 510 * i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, 511 * struct i5400_error_info *info, 512 * int handle_errors); 513 * 514 * handle the Intel FATAL and unrecoverable errors, if any 515 */ 516 static void i5400_proccess_non_recoverable_info(struct mem_ctl_info *mci, 517 struct i5400_error_info *info, 518 unsigned long allErrors) 519 { 520 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; 521 int branch; 522 int channel; 523 int bank; 524 int buf_id; 525 int rank; 526 int rdwr; 527 int ras, cas; 528 int errnum; 529 char *type = NULL; 530 enum hw_event_mc_err_type tp_event = HW_EVENT_ERR_UNCORRECTED; 531 532 if (!allErrors) 533 return; /* if no error, return now */ 534 535 if (allErrors & ERROR_FAT_MASK) { 536 type = "FATAL"; 537 tp_event = HW_EVENT_ERR_FATAL; 538 } else if (allErrors & FERR_NF_UNCORRECTABLE) 539 type = "NON-FATAL uncorrected"; 540 else 541 type = "NON-FATAL recoverable"; 542 543 /* ONLY ONE of the possible error bits will be set, as per the docs */ 544 545 branch = extract_fbdchan_indx(info->ferr_fat_fbd); 546 channel = branch; 547 548 /* Use the NON-Recoverable macros to extract data */ 549 bank = nrec_bank(info); 550 rank = nrec_rank(info); 551 buf_id = nrec_buf_id(info); 552 rdwr = nrec_rdwr(info); 553 ras = nrec_ras(info); 554 cas = nrec_cas(info); 555 556 edac_dbg(0, "\t\t%s DIMM= %d Channels= %d,%d (Branch= %d DRAM Bank= %d Buffer ID = %d rdwr= %s ras= %d cas= %d)\n", 557 type, rank, channel, channel + 1, branch >> 1, bank, 558 buf_id, rdwr_str(rdwr), ras, cas); 559 560 /* Only 1 bit will be on */ 561 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 562 563 /* Form out message */ 564 snprintf(msg, sizeof(msg), 565 "Bank=%d Buffer ID = %d RAS=%d CAS=%d Err=0x%lx (%s)", 566 bank, buf_id, ras, cas, allErrors, error_name[errnum]); 567 568 edac_mc_handle_error(tp_event, mci, 1, 0, 0, 0, 569 branch >> 1, -1, rank, 570 rdwr ? "Write error" : "Read error", 571 msg); 572 } 573 574 /* 575 * i5400_process_fatal_error_info(struct mem_ctl_info *mci, 576 * struct i5400_error_info *info, 577 * int handle_errors); 578 * 579 * handle the Intel NON-FATAL errors, if any 580 */ 581 static void i5400_process_nonfatal_error_info(struct mem_ctl_info *mci, 582 struct i5400_error_info *info) 583 { 584 char msg[EDAC_MC_LABEL_LEN + 1 + 90 + 80]; 585 unsigned long allErrors; 586 int branch; 587 int channel; 588 int bank; 589 int rank; 590 int rdwr; 591 int ras, cas; 592 int errnum; 593 594 /* mask off the Error bits that are possible */ 595 allErrors = from_nf_ferr(info->ferr_nf_fbd & FERR_NF_MASK); 596 if (!allErrors) 597 return; /* if no error, return now */ 598 599 /* ONLY ONE of the possible error bits will be set, as per the docs */ 600 601 if (allErrors & (ERROR_NF_UNCORRECTABLE | ERROR_NF_RECOVERABLE)) { 602 i5400_proccess_non_recoverable_info(mci, info, allErrors); 603 return; 604 } 605 606 /* Correctable errors */ 607 if (allErrors & ERROR_NF_CORRECTABLE) { 608 edac_dbg(0, "\tCorrected bits= 0x%lx\n", allErrors); 609 610 branch = extract_fbdchan_indx(info->ferr_nf_fbd); 611 612 channel = 0; 613 if (REC_ECC_LOCATOR_ODD(info->redmemb)) 614 channel = 1; 615 616 /* Convert channel to be based from zero, instead of 617 * from branch base of 0 */ 618 channel += branch; 619 620 bank = rec_bank(info); 621 rank = rec_rank(info); 622 rdwr = rec_rdwr(info); 623 ras = rec_ras(info); 624 cas = rec_cas(info); 625 626 /* Only 1 bit will be on */ 627 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 628 629 edac_dbg(0, "\t\tDIMM= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 630 rank, channel, branch >> 1, bank, 631 rdwr_str(rdwr), ras, cas); 632 633 /* Form out message */ 634 snprintf(msg, sizeof(msg), 635 "Corrected error (Branch=%d DRAM-Bank=%d RDWR=%s " 636 "RAS=%d CAS=%d, CE Err=0x%lx (%s))", 637 branch >> 1, bank, rdwr_str(rdwr), ras, cas, 638 allErrors, error_name[errnum]); 639 640 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, 641 branch >> 1, channel % 2, rank, 642 rdwr ? "Write error" : "Read error", 643 msg); 644 645 return; 646 } 647 648 /* Miscellaneous errors */ 649 errnum = find_first_bit(&allErrors, ARRAY_SIZE(error_name)); 650 651 branch = extract_fbdchan_indx(info->ferr_nf_fbd); 652 653 i5400_mc_printk(mci, KERN_EMERG, 654 "Non-Fatal misc error (Branch=%d Err=%#lx (%s))", 655 branch >> 1, allErrors, error_name[errnum]); 656 } 657 658 /* 659 * i5400_process_error_info Process the error info that is 660 * in the 'info' structure, previously retrieved from hardware 661 */ 662 static void i5400_process_error_info(struct mem_ctl_info *mci, 663 struct i5400_error_info *info) 664 { u32 allErrors; 665 666 /* First handle any fatal errors that occurred */ 667 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK); 668 i5400_proccess_non_recoverable_info(mci, info, allErrors); 669 670 /* now handle any non-fatal errors that occurred */ 671 i5400_process_nonfatal_error_info(mci, info); 672 } 673 674 /* 675 * i5400_clear_error Retrieve any error from the hardware 676 * but do NOT process that error. 677 * Used for 'clearing' out of previous errors 678 * Called by the Core module. 679 */ 680 static void i5400_clear_error(struct mem_ctl_info *mci) 681 { 682 struct i5400_error_info info; 683 684 i5400_get_error_info(mci, &info); 685 } 686 687 /* 688 * i5400_check_error Retrieve and process errors reported by the 689 * hardware. Called by the Core module. 690 */ 691 static void i5400_check_error(struct mem_ctl_info *mci) 692 { 693 struct i5400_error_info info; 694 695 i5400_get_error_info(mci, &info); 696 i5400_process_error_info(mci, &info); 697 } 698 699 /* 700 * i5400_put_devices 'put' all the devices that we have 701 * reserved via 'get' 702 */ 703 static void i5400_put_devices(struct mem_ctl_info *mci) 704 { 705 struct i5400_pvt *pvt; 706 707 pvt = mci->pvt_info; 708 709 /* Decrement usage count for devices */ 710 pci_dev_put(pvt->branch_1); 711 pci_dev_put(pvt->branch_0); 712 pci_dev_put(pvt->fsb_error_regs); 713 pci_dev_put(pvt->branchmap_werrors); 714 } 715 716 /* 717 * i5400_get_devices Find and perform 'get' operation on the MCH's 718 * device/functions we want to reference for this driver 719 * 720 * Need to 'get' device 16 func 1 and func 2 721 */ 722 static int i5400_get_devices(struct mem_ctl_info *mci, int dev_idx) 723 { 724 struct i5400_pvt *pvt; 725 struct pci_dev *pdev; 726 727 pvt = mci->pvt_info; 728 pvt->branchmap_werrors = NULL; 729 pvt->fsb_error_regs = NULL; 730 pvt->branch_0 = NULL; 731 pvt->branch_1 = NULL; 732 733 /* Attempt to 'get' the MCH register we want */ 734 pdev = NULL; 735 while (1) { 736 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 737 PCI_DEVICE_ID_INTEL_5400_ERR, pdev); 738 if (!pdev) { 739 /* End of list, leave */ 740 i5400_printk(KERN_ERR, 741 "'system address,Process Bus' " 742 "device not found:" 743 "vendor 0x%x device 0x%x ERR func 1 " 744 "(broken BIOS?)\n", 745 PCI_VENDOR_ID_INTEL, 746 PCI_DEVICE_ID_INTEL_5400_ERR); 747 return -ENODEV; 748 } 749 750 /* Store device 16 func 1 */ 751 if (PCI_FUNC(pdev->devfn) == 1) 752 break; 753 } 754 pvt->branchmap_werrors = pdev; 755 756 pdev = NULL; 757 while (1) { 758 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 759 PCI_DEVICE_ID_INTEL_5400_ERR, pdev); 760 if (!pdev) { 761 /* End of list, leave */ 762 i5400_printk(KERN_ERR, 763 "'system address,Process Bus' " 764 "device not found:" 765 "vendor 0x%x device 0x%x ERR func 2 " 766 "(broken BIOS?)\n", 767 PCI_VENDOR_ID_INTEL, 768 PCI_DEVICE_ID_INTEL_5400_ERR); 769 770 pci_dev_put(pvt->branchmap_werrors); 771 return -ENODEV; 772 } 773 774 /* Store device 16 func 2 */ 775 if (PCI_FUNC(pdev->devfn) == 2) 776 break; 777 } 778 pvt->fsb_error_regs = pdev; 779 780 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n", 781 pci_name(pvt->system_address), 782 pvt->system_address->vendor, pvt->system_address->device); 783 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", 784 pci_name(pvt->branchmap_werrors), 785 pvt->branchmap_werrors->vendor, 786 pvt->branchmap_werrors->device); 787 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n", 788 pci_name(pvt->fsb_error_regs), 789 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); 790 791 pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL, 792 PCI_DEVICE_ID_INTEL_5400_FBD0, NULL); 793 if (!pvt->branch_0) { 794 i5400_printk(KERN_ERR, 795 "MC: 'BRANCH 0' device not found:" 796 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", 797 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_FBD0); 798 799 pci_dev_put(pvt->fsb_error_regs); 800 pci_dev_put(pvt->branchmap_werrors); 801 return -ENODEV; 802 } 803 804 /* If this device claims to have more than 2 channels then 805 * fetch Branch 1's information 806 */ 807 if (pvt->maxch < CHANNELS_PER_BRANCH) 808 return 0; 809 810 pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL, 811 PCI_DEVICE_ID_INTEL_5400_FBD1, NULL); 812 if (!pvt->branch_1) { 813 i5400_printk(KERN_ERR, 814 "MC: 'BRANCH 1' device not found:" 815 "vendor 0x%x device 0x%x Func 0 " 816 "(broken BIOS?)\n", 817 PCI_VENDOR_ID_INTEL, 818 PCI_DEVICE_ID_INTEL_5400_FBD1); 819 820 pci_dev_put(pvt->branch_0); 821 pci_dev_put(pvt->fsb_error_regs); 822 pci_dev_put(pvt->branchmap_werrors); 823 return -ENODEV; 824 } 825 826 return 0; 827 } 828 829 /* 830 * determine_amb_present 831 * 832 * the information is contained in DIMMS_PER_CHANNEL different 833 * registers determining which of the DIMMS_PER_CHANNEL requires 834 * knowing which channel is in question 835 * 836 * 2 branches, each with 2 channels 837 * b0_ambpresent0 for channel '0' 838 * b0_ambpresent1 for channel '1' 839 * b1_ambpresent0 for channel '2' 840 * b1_ambpresent1 for channel '3' 841 */ 842 static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel) 843 { 844 int amb_present; 845 846 if (channel < CHANNELS_PER_BRANCH) { 847 if (channel & 0x1) 848 amb_present = pvt->b0_ambpresent1; 849 else 850 amb_present = pvt->b0_ambpresent0; 851 } else { 852 if (channel & 0x1) 853 amb_present = pvt->b1_ambpresent1; 854 else 855 amb_present = pvt->b1_ambpresent0; 856 } 857 858 return amb_present; 859 } 860 861 /* 862 * determine_mtr(pvt, dimm, channel) 863 * 864 * return the proper MTR register as determine by the dimm and desired channel 865 */ 866 static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel) 867 { 868 int mtr; 869 int n; 870 871 /* There is one MTR for each slot pair of FB-DIMMs, 872 Each slot pair may be at branch 0 or branch 1. 873 */ 874 n = dimm; 875 876 if (n >= DIMMS_PER_CHANNEL) { 877 edac_dbg(0, "ERROR: trying to access an invalid dimm: %d\n", 878 dimm); 879 return 0; 880 } 881 882 if (channel < CHANNELS_PER_BRANCH) 883 mtr = pvt->b0_mtr[n]; 884 else 885 mtr = pvt->b1_mtr[n]; 886 887 return mtr; 888 } 889 890 /* 891 */ 892 static void decode_mtr(int slot_row, u16 mtr) 893 { 894 int ans; 895 896 ans = MTR_DIMMS_PRESENT(mtr); 897 898 edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n", 899 slot_row, mtr, ans ? "" : "NOT "); 900 if (!ans) 901 return; 902 903 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); 904 905 edac_dbg(2, "\t\tELECTRICAL THROTTLING is %s\n", 906 str_enabled_disabled(MTR_DIMMS_ETHROTTLE(mtr))); 907 908 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); 909 edac_dbg(2, "\t\tNUMRANK: %s\n", 910 MTR_DIMM_RANK(mtr) ? "double" : "single"); 911 edac_dbg(2, "\t\tNUMROW: %s\n", 912 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : 913 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : 914 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : 915 "65,536 - 16 rows"); 916 edac_dbg(2, "\t\tNUMCOL: %s\n", 917 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : 918 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : 919 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : 920 "reserved"); 921 } 922 923 static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel, 924 struct i5400_dimm_info *dinfo) 925 { 926 int mtr; 927 int amb_present_reg; 928 int addrBits; 929 930 mtr = determine_mtr(pvt, dimm, channel); 931 if (MTR_DIMMS_PRESENT(mtr)) { 932 amb_present_reg = determine_amb_present_reg(pvt, channel); 933 934 /* Determine if there is a DIMM present in this DIMM slot */ 935 if (amb_present_reg & (1 << dimm)) { 936 /* Start with the number of bits for a Bank 937 * on the DRAM */ 938 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); 939 /* Add thenumber of ROW bits */ 940 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); 941 /* add the number of COLUMN bits */ 942 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); 943 /* add the number of RANK bits */ 944 addrBits += MTR_DIMM_RANK(mtr); 945 946 addrBits += 6; /* add 64 bits per DIMM */ 947 addrBits -= 20; /* divide by 2^^20 */ 948 addrBits -= 3; /* 8 bits per bytes */ 949 950 dinfo->megabytes = 1 << addrBits; 951 } 952 } 953 } 954 955 /* 956 * calculate_dimm_size 957 * 958 * also will output a DIMM matrix map, if debug is enabled, for viewing 959 * how the DIMMs are populated 960 */ 961 static void calculate_dimm_size(struct i5400_pvt *pvt) 962 { 963 struct i5400_dimm_info *dinfo; 964 int dimm, max_dimms; 965 char *p, *mem_buffer; 966 int space, n; 967 int channel, branch; 968 969 /* ================= Generate some debug output ================= */ 970 space = PAGE_SIZE; 971 mem_buffer = p = kmalloc(space, GFP_KERNEL); 972 if (p == NULL) { 973 i5400_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n", 974 __FILE__, __func__); 975 return; 976 } 977 978 /* Scan all the actual DIMMS 979 * and calculate the information for each DIMM 980 * Start with the highest dimm first, to display it first 981 * and work toward the 0th dimm 982 */ 983 max_dimms = pvt->maxdimmperch; 984 for (dimm = max_dimms - 1; dimm >= 0; dimm--) { 985 986 /* on an odd dimm, first output a 'boundary' marker, 987 * then reset the message buffer */ 988 if (dimm & 0x1) { 989 n = snprintf(p, space, "---------------------------" 990 "-------------------------------"); 991 p += n; 992 space -= n; 993 edac_dbg(2, "%s\n", mem_buffer); 994 p = mem_buffer; 995 space = PAGE_SIZE; 996 } 997 n = snprintf(p, space, "dimm %2d ", dimm); 998 p += n; 999 space -= n; 1000 1001 for (channel = 0; channel < pvt->maxch; channel++) { 1002 dinfo = &pvt->dimm_info[dimm][channel]; 1003 handle_channel(pvt, dimm, channel, dinfo); 1004 n = snprintf(p, space, "%4d MB | ", dinfo->megabytes); 1005 p += n; 1006 space -= n; 1007 } 1008 edac_dbg(2, "%s\n", mem_buffer); 1009 p = mem_buffer; 1010 space = PAGE_SIZE; 1011 } 1012 1013 /* Output the last bottom 'boundary' marker */ 1014 n = snprintf(p, space, "---------------------------" 1015 "-------------------------------"); 1016 p += n; 1017 space -= n; 1018 edac_dbg(2, "%s\n", mem_buffer); 1019 p = mem_buffer; 1020 space = PAGE_SIZE; 1021 1022 /* now output the 'channel' labels */ 1023 n = snprintf(p, space, " "); 1024 p += n; 1025 space -= n; 1026 for (channel = 0; channel < pvt->maxch; channel++) { 1027 n = snprintf(p, space, "channel %d | ", channel); 1028 p += n; 1029 space -= n; 1030 } 1031 1032 edac_dbg(2, "%s\n", mem_buffer); 1033 p = mem_buffer; 1034 space = PAGE_SIZE; 1035 1036 n = snprintf(p, space, " "); 1037 p += n; 1038 space -= n; 1039 for (branch = 0; branch < MAX_BRANCHES; branch++) { 1040 n = snprintf(p, space, " branch %d | ", branch); 1041 p += n; 1042 space -= n; 1043 } 1044 1045 /* output the last message and free buffer */ 1046 edac_dbg(2, "%s\n", mem_buffer); 1047 kfree(mem_buffer); 1048 } 1049 1050 /* 1051 * i5400_get_mc_regs read in the necessary registers and 1052 * cache locally 1053 * 1054 * Fills in the private data members 1055 */ 1056 static void i5400_get_mc_regs(struct mem_ctl_info *mci) 1057 { 1058 struct i5400_pvt *pvt; 1059 u32 actual_tolm; 1060 u16 limit; 1061 int slot_row; 1062 int way0, way1; 1063 1064 pvt = mci->pvt_info; 1065 1066 pci_read_config_dword(pvt->system_address, AMBASE, 1067 &pvt->u.ambase_bottom); 1068 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), 1069 &pvt->u.ambase_top); 1070 1071 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", 1072 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); 1073 1074 /* Get the Branch Map regs */ 1075 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); 1076 pvt->tolm >>= 12; 1077 edac_dbg(2, "\nTOLM (number of 256M regions) =%u (0x%x)\n", 1078 pvt->tolm, pvt->tolm); 1079 1080 actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28)); 1081 edac_dbg(2, "Actual TOLM byte addr=%u.%03u GB (0x%x)\n", 1082 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28); 1083 1084 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); 1085 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); 1086 1087 /* Get the MIR[0-1] regs */ 1088 limit = (pvt->mir0 >> 4) & 0x0fff; 1089 way0 = pvt->mir0 & 0x1; 1090 way1 = pvt->mir0 & 0x2; 1091 edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", 1092 limit, way1, way0); 1093 limit = (pvt->mir1 >> 4) & 0xfff; 1094 way0 = pvt->mir1 & 0x1; 1095 way1 = pvt->mir1 & 0x2; 1096 edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", 1097 limit, way1, way0); 1098 1099 /* Get the set of MTR[0-3] regs by each branch */ 1100 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) { 1101 int where = MTR0 + (slot_row * sizeof(u16)); 1102 1103 /* Branch 0 set of MTR registers */ 1104 pci_read_config_word(pvt->branch_0, where, 1105 &pvt->b0_mtr[slot_row]); 1106 1107 edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n", 1108 slot_row, where, pvt->b0_mtr[slot_row]); 1109 1110 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1111 pvt->b1_mtr[slot_row] = 0; 1112 continue; 1113 } 1114 1115 /* Branch 1 set of MTR registers */ 1116 pci_read_config_word(pvt->branch_1, where, 1117 &pvt->b1_mtr[slot_row]); 1118 edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n", 1119 slot_row, where, pvt->b1_mtr[slot_row]); 1120 } 1121 1122 /* Read and dump branch 0's MTRs */ 1123 edac_dbg(2, "Memory Technology Registers:\n"); 1124 edac_dbg(2, " Branch 0:\n"); 1125 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) 1126 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); 1127 1128 pci_read_config_word(pvt->branch_0, AMBPRESENT_0, 1129 &pvt->b0_ambpresent0); 1130 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); 1131 pci_read_config_word(pvt->branch_0, AMBPRESENT_1, 1132 &pvt->b0_ambpresent1); 1133 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); 1134 1135 /* Only if we have 2 branchs (4 channels) */ 1136 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1137 pvt->b1_ambpresent0 = 0; 1138 pvt->b1_ambpresent1 = 0; 1139 } else { 1140 /* Read and dump branch 1's MTRs */ 1141 edac_dbg(2, " Branch 1:\n"); 1142 for (slot_row = 0; slot_row < DIMMS_PER_CHANNEL; slot_row++) 1143 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); 1144 1145 pci_read_config_word(pvt->branch_1, AMBPRESENT_0, 1146 &pvt->b1_ambpresent0); 1147 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n", 1148 pvt->b1_ambpresent0); 1149 pci_read_config_word(pvt->branch_1, AMBPRESENT_1, 1150 &pvt->b1_ambpresent1); 1151 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n", 1152 pvt->b1_ambpresent1); 1153 } 1154 1155 /* Go and determine the size of each DIMM and place in an 1156 * orderly matrix */ 1157 calculate_dimm_size(pvt); 1158 } 1159 1160 /* 1161 * i5400_init_dimms Initialize the 'dimms' table within 1162 * the mci control structure with the 1163 * addressing of memory. 1164 * 1165 * return: 1166 * 0 success 1167 * 1 no actual memory found on this MC 1168 */ 1169 static int i5400_init_dimms(struct mem_ctl_info *mci) 1170 { 1171 struct i5400_pvt *pvt; 1172 struct dimm_info *dimm; 1173 int ndimms; 1174 int mtr; 1175 int size_mb; 1176 int channel, slot; 1177 1178 pvt = mci->pvt_info; 1179 1180 ndimms = 0; 1181 1182 /* 1183 * FIXME: remove pvt->dimm_info[slot][channel] and use the 3 1184 * layers here. 1185 */ 1186 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; 1187 channel++) { 1188 for (slot = 0; slot < mci->layers[2].size; slot++) { 1189 mtr = determine_mtr(pvt, slot, channel); 1190 1191 /* if no DIMMS on this slot, continue */ 1192 if (!MTR_DIMMS_PRESENT(mtr)) 1193 continue; 1194 1195 dimm = edac_get_dimm(mci, channel / 2, channel % 2, slot); 1196 1197 size_mb = pvt->dimm_info[slot][channel].megabytes; 1198 1199 edac_dbg(2, "dimm (branch %d channel %d slot %d): %d.%03d GB\n", 1200 channel / 2, channel % 2, slot, 1201 size_mb / 1000, size_mb % 1000); 1202 1203 dimm->nr_pages = size_mb << 8; 1204 dimm->grain = 8; 1205 dimm->dtype = MTR_DRAM_WIDTH(mtr) == 8 ? 1206 DEV_X8 : DEV_X4; 1207 dimm->mtype = MEM_FB_DDR2; 1208 /* 1209 * The eccc mechanism is SDDC (aka SECC), with 1210 * is similar to Chipkill. 1211 */ 1212 dimm->edac_mode = MTR_DRAM_WIDTH(mtr) == 8 ? 1213 EDAC_S8ECD8ED : EDAC_S4ECD4ED; 1214 ndimms++; 1215 } 1216 } 1217 1218 /* 1219 * When just one memory is provided, it should be at location (0,0,0). 1220 * With such single-DIMM mode, the SDCC algorithm degrades to SECDEC+. 1221 */ 1222 if (ndimms == 1) 1223 mci->dimms[0]->edac_mode = EDAC_SECDED; 1224 1225 return (ndimms == 0); 1226 } 1227 1228 /* 1229 * i5400_set_error_reporting 1230 * Turn on/off the memory reporting features of the hardware 1231 */ 1232 static void i5400_set_error_reporting(struct mem_ctl_info *mci, bool enable) 1233 { 1234 struct i5400_pvt *pvt; 1235 u32 fbd_error_mask; 1236 1237 pvt = mci->pvt_info; 1238 1239 /* Read the FBD Error Mask Register */ 1240 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, 1241 &fbd_error_mask); 1242 1243 /* Enable with 0, disable with 1 */ 1244 if (enable) 1245 fbd_error_mask &= ~(ENABLE_EMASK_ALL); 1246 else 1247 fbd_error_mask |= ENABLE_EMASK_ALL; 1248 1249 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, 1250 fbd_error_mask); 1251 } 1252 1253 /* 1254 * i5400_probe1 Probe for ONE instance of device to see if it is 1255 * present. 1256 * return: 1257 * 0 for FOUND a device 1258 * < 0 for error code 1259 */ 1260 static int i5400_probe1(struct pci_dev *pdev, int dev_idx) 1261 { 1262 struct mem_ctl_info *mci; 1263 struct i5400_pvt *pvt; 1264 struct edac_mc_layer layers[3]; 1265 1266 if (dev_idx >= ARRAY_SIZE(i5400_devs)) 1267 return -EINVAL; 1268 1269 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n", 1270 pdev->bus->number, 1271 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1272 1273 /* We only are looking for func 0 of the set */ 1274 if (PCI_FUNC(pdev->devfn) != 0) 1275 return -ENODEV; 1276 1277 /* 1278 * allocate a new MC control structure 1279 * 1280 * This drivers uses the DIMM slot as "csrow" and the rest as "channel". 1281 */ 1282 layers[0].type = EDAC_MC_LAYER_BRANCH; 1283 layers[0].size = MAX_BRANCHES; 1284 layers[0].is_virt_csrow = false; 1285 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1286 layers[1].size = CHANNELS_PER_BRANCH; 1287 layers[1].is_virt_csrow = false; 1288 layers[2].type = EDAC_MC_LAYER_SLOT; 1289 layers[2].size = DIMMS_PER_CHANNEL; 1290 layers[2].is_virt_csrow = true; 1291 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); 1292 if (mci == NULL) 1293 return -ENOMEM; 1294 1295 edac_dbg(0, "MC: mci = %p\n", mci); 1296 1297 mci->pdev = &pdev->dev; /* record ptr to the generic device */ 1298 1299 pvt = mci->pvt_info; 1300 pvt->system_address = pdev; /* Record this device in our private */ 1301 pvt->maxch = MAX_CHANNELS; 1302 pvt->maxdimmperch = DIMMS_PER_CHANNEL; 1303 1304 /* 'get' the pci devices we want to reserve for our use */ 1305 if (i5400_get_devices(mci, dev_idx)) 1306 goto fail0; 1307 1308 /* Time to get serious */ 1309 i5400_get_mc_regs(mci); /* retrieve the hardware registers */ 1310 1311 mci->mc_idx = 0; 1312 mci->mtype_cap = MEM_FLAG_FB_DDR2; 1313 mci->edac_ctl_cap = EDAC_FLAG_NONE; 1314 mci->edac_cap = EDAC_FLAG_NONE; 1315 mci->mod_name = "i5400_edac.c"; 1316 mci->ctl_name = i5400_devs[dev_idx].ctl_name; 1317 mci->dev_name = pci_name(pdev); 1318 mci->ctl_page_to_phys = NULL; 1319 1320 /* Set the function pointer to an actual operation function */ 1321 mci->edac_check = i5400_check_error; 1322 1323 /* initialize the MC control structure 'dimms' table 1324 * with the mapping and control information */ 1325 if (i5400_init_dimms(mci)) { 1326 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5400_init_dimms() returned nonzero value\n"); 1327 mci->edac_cap = EDAC_FLAG_NONE; /* no dimms found */ 1328 pvt->enabled_error_reporting = false; 1329 } else { 1330 edac_dbg(1, "MC: Enable error reporting now\n"); 1331 i5400_set_error_reporting(mci, true); 1332 pvt->enabled_error_reporting = true; 1333 } 1334 1335 /* add this new MC control structure to EDAC's list of MCs */ 1336 if (edac_mc_add_mc(mci)) { 1337 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 1338 /* Disable error reporting if we just enabled it */ 1339 if (pvt->enabled_error_reporting) 1340 i5400_set_error_reporting(mci, false); 1341 goto fail1; 1342 } 1343 1344 i5400_clear_error(mci); 1345 1346 /* allocating generic PCI control info */ 1347 i5400_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 1348 if (!i5400_pci) { 1349 printk(KERN_WARNING 1350 "%s(): Unable to create PCI control\n", 1351 __func__); 1352 printk(KERN_WARNING 1353 "%s(): PCI error report via EDAC not setup\n", 1354 __func__); 1355 } 1356 1357 return 0; 1358 1359 /* Error exit unwinding stack */ 1360 fail1: 1361 1362 i5400_put_devices(mci); 1363 1364 fail0: 1365 edac_mc_free(mci); 1366 return -ENODEV; 1367 } 1368 1369 /* 1370 * i5400_init_one constructor for one instance of device 1371 * 1372 * returns: 1373 * negative on error 1374 * count (>= 0) 1375 */ 1376 static int i5400_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 1377 { 1378 int rc; 1379 1380 edac_dbg(0, "MC:\n"); 1381 1382 /* wake up device */ 1383 rc = pci_enable_device(pdev); 1384 if (rc) 1385 return rc; 1386 1387 /* now probe and enable the device */ 1388 return i5400_probe1(pdev, id->driver_data); 1389 } 1390 1391 /* 1392 * i5400_remove_one destructor for one instance of device 1393 * 1394 */ 1395 static void i5400_remove_one(struct pci_dev *pdev) 1396 { 1397 struct mem_ctl_info *mci; 1398 struct i5400_pvt *pvt; 1399 1400 edac_dbg(0, "\n"); 1401 1402 if (i5400_pci) 1403 edac_pci_release_generic_ctl(i5400_pci); 1404 1405 mci = edac_mc_del_mc(&pdev->dev); 1406 if (!mci) 1407 return; 1408 1409 pvt = mci->pvt_info; 1410 1411 /* Disable error reporting on teardown */ 1412 if (pvt->enabled_error_reporting) 1413 i5400_set_error_reporting(mci, false); 1414 1415 /* retrieve references to resources, and free those resources */ 1416 i5400_put_devices(mci); 1417 1418 pci_disable_device(pdev); 1419 1420 edac_mc_free(mci); 1421 } 1422 1423 /* 1424 * pci_device_id table for which devices we are looking for 1425 * 1426 * The "E500P" device is the first device supported. 1427 */ 1428 static const struct pci_device_id i5400_pci_tbl[] = { 1429 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5400_ERR)}, 1430 {0,} /* 0 terminated list. */ 1431 }; 1432 1433 MODULE_DEVICE_TABLE(pci, i5400_pci_tbl); 1434 1435 /* 1436 * i5400_driver pci_driver structure for this module 1437 * 1438 */ 1439 static struct pci_driver i5400_driver = { 1440 .name = "i5400_edac", 1441 .probe = i5400_init_one, 1442 .remove = i5400_remove_one, 1443 .id_table = i5400_pci_tbl, 1444 }; 1445 1446 /* 1447 * i5400_init Module entry function 1448 * Try to initialize this module for its devices 1449 */ 1450 static int __init i5400_init(void) 1451 { 1452 int pci_rc; 1453 1454 edac_dbg(2, "MC:\n"); 1455 1456 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1457 opstate_init(); 1458 1459 pci_rc = pci_register_driver(&i5400_driver); 1460 1461 return (pci_rc < 0) ? pci_rc : 0; 1462 } 1463 1464 /* 1465 * i5400_exit() Module exit function 1466 * Unregister the driver 1467 */ 1468 static void __exit i5400_exit(void) 1469 { 1470 edac_dbg(2, "MC:\n"); 1471 pci_unregister_driver(&i5400_driver); 1472 } 1473 1474 module_init(i5400_init); 1475 module_exit(i5400_exit); 1476 1477 MODULE_LICENSE("GPL"); 1478 MODULE_AUTHOR("Ben Woodard <woodard@redhat.com>"); 1479 MODULE_AUTHOR("Mauro Carvalho Chehab"); 1480 MODULE_AUTHOR("Red Hat Inc. (https://www.redhat.com)"); 1481 MODULE_DESCRIPTION("MC Driver for Intel I5400 memory controllers - " 1482 I5400_REVISION); 1483 1484 module_param(edac_op_state, int, 0444); 1485 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 1486