1 /* 2 * Intel 5100 Memory Controllers kernel module 3 * 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * This module is based on the following document: 8 * 9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet 10 * http://download.intel.com/design/chipsets/datashts/318378.pdf 11 * 12 * The intel 5100 has two independent channels. EDAC core currently 13 * can not reflect this configuration so instead the chip-select 14 * rows for each respective channel are laid out one after another, 15 * the first half belonging to channel 0, the second half belonging 16 * to channel 1. 17 * 18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the 19 * several ranks. However, instead of showing memories as ranks, it outputs 20 * them as DIMM's. An internal table creates the association between ranks 21 * and DIMM's. 22 */ 23 #include <linux/module.h> 24 #include <linux/init.h> 25 #include <linux/pci.h> 26 #include <linux/pci_ids.h> 27 #include <linux/edac.h> 28 #include <linux/delay.h> 29 #include <linux/mmzone.h> 30 #include <linux/debugfs.h> 31 32 #include "edac_module.h" 33 34 /* register addresses */ 35 36 /* device 16, func 1 */ 37 #define I5100_MC 0x40 /* Memory Control Register */ 38 #define I5100_MC_SCRBEN_MASK (1 << 7) 39 #define I5100_MC_SCRBDONE_MASK (1 << 4) 40 #define I5100_MS 0x44 /* Memory Status Register */ 41 #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */ 42 #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */ 43 #define I5100_TOLM 0x6c /* Top of Low Memory */ 44 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */ 45 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */ 46 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */ 47 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */ 48 #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */ 49 #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16) 50 #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15) 51 #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14) 52 #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12) 53 #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11) 54 #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10) 55 #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6) 56 #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5) 57 #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4) 58 #define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1) 59 #define I5100_FERR_NF_MEM_ANY_MASK \ 60 (I5100_FERR_NF_MEM_M16ERR_MASK | \ 61 I5100_FERR_NF_MEM_M15ERR_MASK | \ 62 I5100_FERR_NF_MEM_M14ERR_MASK | \ 63 I5100_FERR_NF_MEM_M12ERR_MASK | \ 64 I5100_FERR_NF_MEM_M11ERR_MASK | \ 65 I5100_FERR_NF_MEM_M10ERR_MASK | \ 66 I5100_FERR_NF_MEM_M6ERR_MASK | \ 67 I5100_FERR_NF_MEM_M5ERR_MASK | \ 68 I5100_FERR_NF_MEM_M4ERR_MASK | \ 69 I5100_FERR_NF_MEM_M1ERR_MASK) 70 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */ 71 #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */ 72 #define I5100_MEM0EINJMSK0 0x200 /* Injection Mask0 Register Channel 0 */ 73 #define I5100_MEM1EINJMSK0 0x208 /* Injection Mask0 Register Channel 1 */ 74 #define I5100_MEMXEINJMSK0_EINJEN (1 << 27) 75 #define I5100_MEM0EINJMSK1 0x204 /* Injection Mask1 Register Channel 0 */ 76 #define I5100_MEM1EINJMSK1 0x206 /* Injection Mask1 Register Channel 1 */ 77 78 /* Device 19, Function 0 */ 79 #define I5100_DINJ0 0x9a 80 81 /* device 21 and 22, func 0 */ 82 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */ 83 #define I5100_DMIR 0x15c /* DIMM Interleave Range */ 84 #define I5100_VALIDLOG 0x18c /* Valid Log Markers */ 85 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */ 86 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */ 87 #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */ 88 #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */ 89 #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */ 90 #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */ 91 #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */ 92 93 /* bit field accessors */ 94 95 static inline u32 i5100_mc_scrben(u32 mc) 96 { 97 return mc >> 7 & 1; 98 } 99 100 static inline u32 i5100_mc_errdeten(u32 mc) 101 { 102 return mc >> 5 & 1; 103 } 104 105 static inline u32 i5100_mc_scrbdone(u32 mc) 106 { 107 return mc >> 4 & 1; 108 } 109 110 static inline u16 i5100_spddata_rdo(u16 a) 111 { 112 return a >> 15 & 1; 113 } 114 115 static inline u16 i5100_spddata_sbe(u16 a) 116 { 117 return a >> 13 & 1; 118 } 119 120 static inline u16 i5100_spddata_busy(u16 a) 121 { 122 return a >> 12 & 1; 123 } 124 125 static inline u16 i5100_spddata_data(u16 a) 126 { 127 return a & ((1 << 8) - 1); 128 } 129 130 static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba, 131 u32 data, u32 cmd) 132 { 133 return ((dti & ((1 << 4) - 1)) << 28) | 134 ((ckovrd & 1) << 27) | 135 ((sa & ((1 << 3) - 1)) << 24) | 136 ((ba & ((1 << 8) - 1)) << 16) | 137 ((data & ((1 << 8) - 1)) << 8) | 138 (cmd & 1); 139 } 140 141 static inline u16 i5100_tolm_tolm(u16 a) 142 { 143 return a >> 12 & ((1 << 4) - 1); 144 } 145 146 static inline u16 i5100_mir_limit(u16 a) 147 { 148 return a >> 4 & ((1 << 12) - 1); 149 } 150 151 static inline u16 i5100_mir_way1(u16 a) 152 { 153 return a >> 1 & 1; 154 } 155 156 static inline u16 i5100_mir_way0(u16 a) 157 { 158 return a & 1; 159 } 160 161 static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a) 162 { 163 return a >> 28 & 1; 164 } 165 166 static inline u32 i5100_ferr_nf_mem_any(u32 a) 167 { 168 return a & I5100_FERR_NF_MEM_ANY_MASK; 169 } 170 171 static inline u32 i5100_nerr_nf_mem_any(u32 a) 172 { 173 return i5100_ferr_nf_mem_any(a); 174 } 175 176 static inline u32 i5100_dmir_limit(u32 a) 177 { 178 return a >> 16 & ((1 << 11) - 1); 179 } 180 181 static inline u32 i5100_dmir_rank(u32 a, u32 i) 182 { 183 return a >> (4 * i) & ((1 << 2) - 1); 184 } 185 186 static inline u16 i5100_mtr_present(u16 a) 187 { 188 return a >> 10 & 1; 189 } 190 191 static inline u16 i5100_mtr_ethrottle(u16 a) 192 { 193 return a >> 9 & 1; 194 } 195 196 static inline u16 i5100_mtr_width(u16 a) 197 { 198 return a >> 8 & 1; 199 } 200 201 static inline u16 i5100_mtr_numbank(u16 a) 202 { 203 return a >> 6 & 1; 204 } 205 206 static inline u16 i5100_mtr_numrow(u16 a) 207 { 208 return a >> 2 & ((1 << 2) - 1); 209 } 210 211 static inline u16 i5100_mtr_numcol(u16 a) 212 { 213 return a & ((1 << 2) - 1); 214 } 215 216 217 static inline u32 i5100_validlog_redmemvalid(u32 a) 218 { 219 return a >> 2 & 1; 220 } 221 222 static inline u32 i5100_validlog_recmemvalid(u32 a) 223 { 224 return a >> 1 & 1; 225 } 226 227 static inline u32 i5100_validlog_nrecmemvalid(u32 a) 228 { 229 return a & 1; 230 } 231 232 static inline u32 i5100_nrecmema_merr(u32 a) 233 { 234 return a >> 15 & ((1 << 5) - 1); 235 } 236 237 static inline u32 i5100_nrecmema_bank(u32 a) 238 { 239 return a >> 12 & ((1 << 3) - 1); 240 } 241 242 static inline u32 i5100_nrecmema_rank(u32 a) 243 { 244 return a >> 8 & ((1 << 3) - 1); 245 } 246 247 static inline u32 i5100_nrecmema_dm_buf_id(u32 a) 248 { 249 return a & ((1 << 8) - 1); 250 } 251 252 static inline u32 i5100_nrecmemb_cas(u32 a) 253 { 254 return a >> 16 & ((1 << 13) - 1); 255 } 256 257 static inline u32 i5100_nrecmemb_ras(u32 a) 258 { 259 return a & ((1 << 16) - 1); 260 } 261 262 static inline u32 i5100_recmema_merr(u32 a) 263 { 264 return i5100_nrecmema_merr(a); 265 } 266 267 static inline u32 i5100_recmema_bank(u32 a) 268 { 269 return i5100_nrecmema_bank(a); 270 } 271 272 static inline u32 i5100_recmema_rank(u32 a) 273 { 274 return i5100_nrecmema_rank(a); 275 } 276 277 static inline u32 i5100_recmemb_cas(u32 a) 278 { 279 return i5100_nrecmemb_cas(a); 280 } 281 282 static inline u32 i5100_recmemb_ras(u32 a) 283 { 284 return i5100_nrecmemb_ras(a); 285 } 286 287 /* some generic limits */ 288 #define I5100_MAX_RANKS_PER_CHAN 6 289 #define I5100_CHANNELS 2 290 #define I5100_MAX_RANKS_PER_DIMM 4 291 #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */ 292 #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4 293 #define I5100_MAX_RANK_INTERLEAVE 4 294 #define I5100_MAX_DMIRS 5 295 #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ) 296 297 struct i5100_priv { 298 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */ 299 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN]; 300 301 /* 302 * mainboard chip select map -- maps i5100 chip selects to 303 * DIMM slot chip selects. In the case of only 4 ranks per 304 * channel, the mapping is fairly obvious but not unique. 305 * we map -1 -> NC and assume both channels use the same 306 * map... 307 * 308 */ 309 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM]; 310 311 /* memory interleave range */ 312 struct { 313 u64 limit; 314 unsigned way[2]; 315 } mir[I5100_CHANNELS]; 316 317 /* adjusted memory interleave range register */ 318 unsigned amir[I5100_CHANNELS]; 319 320 /* dimm interleave range */ 321 struct { 322 unsigned rank[I5100_MAX_RANK_INTERLEAVE]; 323 u64 limit; 324 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS]; 325 326 /* memory technology registers... */ 327 struct { 328 unsigned present; /* 0 or 1 */ 329 unsigned ethrottle; /* 0 or 1 */ 330 unsigned width; /* 4 or 8 bits */ 331 unsigned numbank; /* 2 or 3 lines */ 332 unsigned numrow; /* 13 .. 16 lines */ 333 unsigned numcol; /* 11 .. 12 lines */ 334 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN]; 335 336 u64 tolm; /* top of low memory in bytes */ 337 unsigned ranksperchan; /* number of ranks per channel */ 338 339 struct pci_dev *mc; /* device 16 func 1 */ 340 struct pci_dev *einj; /* device 19 func 0 */ 341 struct pci_dev *ch0mm; /* device 21 func 0 */ 342 struct pci_dev *ch1mm; /* device 22 func 0 */ 343 344 struct delayed_work i5100_scrubbing; 345 int scrub_enable; 346 347 /* Error injection */ 348 u8 inject_channel; 349 u8 inject_hlinesel; 350 u8 inject_deviceptr1; 351 u8 inject_deviceptr2; 352 u16 inject_eccmask1; 353 u16 inject_eccmask2; 354 355 struct dentry *debugfs; 356 }; 357 358 static struct dentry *i5100_debugfs; 359 360 /* map a rank/chan to a slot number on the mainboard */ 361 static int i5100_rank_to_slot(const struct mem_ctl_info *mci, 362 int chan, int rank) 363 { 364 const struct i5100_priv *priv = mci->pvt_info; 365 int i; 366 367 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { 368 int j; 369 const int numrank = priv->dimm_numrank[chan][i]; 370 371 for (j = 0; j < numrank; j++) 372 if (priv->dimm_csmap[i][j] == rank) 373 return i * 2 + chan; 374 } 375 376 return -1; 377 } 378 379 static const char *i5100_err_msg(unsigned err) 380 { 381 static const char *merrs[] = { 382 "unknown", /* 0 */ 383 "uncorrectable data ECC on replay", /* 1 */ 384 "unknown", /* 2 */ 385 "unknown", /* 3 */ 386 "aliased uncorrectable demand data ECC", /* 4 */ 387 "aliased uncorrectable spare-copy data ECC", /* 5 */ 388 "aliased uncorrectable patrol data ECC", /* 6 */ 389 "unknown", /* 7 */ 390 "unknown", /* 8 */ 391 "unknown", /* 9 */ 392 "non-aliased uncorrectable demand data ECC", /* 10 */ 393 "non-aliased uncorrectable spare-copy data ECC", /* 11 */ 394 "non-aliased uncorrectable patrol data ECC", /* 12 */ 395 "unknown", /* 13 */ 396 "correctable demand data ECC", /* 14 */ 397 "correctable spare-copy data ECC", /* 15 */ 398 "correctable patrol data ECC", /* 16 */ 399 "unknown", /* 17 */ 400 "SPD protocol error", /* 18 */ 401 "unknown", /* 19 */ 402 "spare copy initiated", /* 20 */ 403 "spare copy completed", /* 21 */ 404 }; 405 unsigned i; 406 407 for (i = 0; i < ARRAY_SIZE(merrs); i++) 408 if (1 << i & err) 409 return merrs[i]; 410 411 return "none"; 412 } 413 414 /* convert csrow index into a rank (per channel -- 0..5) */ 415 static unsigned int i5100_csrow_to_rank(const struct mem_ctl_info *mci, 416 unsigned int csrow) 417 { 418 const struct i5100_priv *priv = mci->pvt_info; 419 420 return csrow % priv->ranksperchan; 421 } 422 423 /* convert csrow index into a channel (0..1) */ 424 static unsigned int i5100_csrow_to_chan(const struct mem_ctl_info *mci, 425 unsigned int csrow) 426 { 427 const struct i5100_priv *priv = mci->pvt_info; 428 429 return csrow / priv->ranksperchan; 430 } 431 432 static void i5100_handle_ce(struct mem_ctl_info *mci, 433 int chan, 434 unsigned bank, 435 unsigned rank, 436 unsigned long syndrome, 437 unsigned cas, 438 unsigned ras, 439 const char *msg) 440 { 441 char detail[80]; 442 443 /* Form out message */ 444 snprintf(detail, sizeof(detail), 445 "bank %u, cas %u, ras %u\n", 446 bank, cas, ras); 447 448 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 449 0, 0, syndrome, 450 chan, rank, -1, 451 msg, detail); 452 } 453 454 static void i5100_handle_ue(struct mem_ctl_info *mci, 455 int chan, 456 unsigned bank, 457 unsigned rank, 458 unsigned long syndrome, 459 unsigned cas, 460 unsigned ras, 461 const char *msg) 462 { 463 char detail[80]; 464 465 /* Form out message */ 466 snprintf(detail, sizeof(detail), 467 "bank %u, cas %u, ras %u\n", 468 bank, cas, ras); 469 470 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 471 0, 0, syndrome, 472 chan, rank, -1, 473 msg, detail); 474 } 475 476 static void i5100_read_log(struct mem_ctl_info *mci, int chan, 477 u32 ferr, u32 nerr) 478 { 479 struct i5100_priv *priv = mci->pvt_info; 480 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm; 481 u32 dw; 482 u32 dw2; 483 unsigned syndrome = 0; 484 unsigned merr; 485 unsigned bank; 486 unsigned rank; 487 unsigned cas; 488 unsigned ras; 489 490 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw); 491 492 if (i5100_validlog_redmemvalid(dw)) { 493 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2); 494 syndrome = dw2; 495 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2); 496 } 497 498 if (i5100_validlog_recmemvalid(dw)) { 499 const char *msg; 500 501 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2); 502 merr = i5100_recmema_merr(dw2); 503 bank = i5100_recmema_bank(dw2); 504 rank = i5100_recmema_rank(dw2); 505 506 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2); 507 cas = i5100_recmemb_cas(dw2); 508 ras = i5100_recmemb_ras(dw2); 509 510 /* FIXME: not really sure if this is what merr is... 511 */ 512 if (!merr) 513 msg = i5100_err_msg(ferr); 514 else 515 msg = i5100_err_msg(nerr); 516 517 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg); 518 } 519 520 if (i5100_validlog_nrecmemvalid(dw)) { 521 const char *msg; 522 523 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2); 524 merr = i5100_nrecmema_merr(dw2); 525 bank = i5100_nrecmema_bank(dw2); 526 rank = i5100_nrecmema_rank(dw2); 527 528 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2); 529 cas = i5100_nrecmemb_cas(dw2); 530 ras = i5100_nrecmemb_ras(dw2); 531 532 /* FIXME: not really sure if this is what merr is... 533 */ 534 if (!merr) 535 msg = i5100_err_msg(ferr); 536 else 537 msg = i5100_err_msg(nerr); 538 539 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg); 540 } 541 542 pci_write_config_dword(pdev, I5100_VALIDLOG, dw); 543 } 544 545 static void i5100_check_error(struct mem_ctl_info *mci) 546 { 547 struct i5100_priv *priv = mci->pvt_info; 548 u32 dw, dw2; 549 550 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw); 551 if (i5100_ferr_nf_mem_any(dw)) { 552 553 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2); 554 555 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw), 556 i5100_ferr_nf_mem_any(dw), 557 i5100_nerr_nf_mem_any(dw2)); 558 559 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2); 560 } 561 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw); 562 } 563 564 /* The i5100 chipset will scrub the entire memory once, then 565 * set a done bit. Continuous scrubbing is achieved by enqueing 566 * delayed work to a workqueue, checking every few minutes if 567 * the scrubbing has completed and if so reinitiating it. 568 */ 569 570 static void i5100_refresh_scrubbing(struct work_struct *work) 571 { 572 struct delayed_work *i5100_scrubbing = to_delayed_work(work); 573 struct i5100_priv *priv = container_of(i5100_scrubbing, 574 struct i5100_priv, 575 i5100_scrubbing); 576 u32 dw; 577 578 pci_read_config_dword(priv->mc, I5100_MC, &dw); 579 580 if (priv->scrub_enable) { 581 582 pci_read_config_dword(priv->mc, I5100_MC, &dw); 583 584 if (i5100_mc_scrbdone(dw)) { 585 dw |= I5100_MC_SCRBEN_MASK; 586 pci_write_config_dword(priv->mc, I5100_MC, dw); 587 pci_read_config_dword(priv->mc, I5100_MC, &dw); 588 } 589 590 schedule_delayed_work(&(priv->i5100_scrubbing), 591 I5100_SCRUB_REFRESH_RATE); 592 } 593 } 594 /* 595 * The bandwidth is based on experimentation, feel free to refine it. 596 */ 597 static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth) 598 { 599 struct i5100_priv *priv = mci->pvt_info; 600 u32 dw; 601 602 pci_read_config_dword(priv->mc, I5100_MC, &dw); 603 if (bandwidth) { 604 priv->scrub_enable = 1; 605 dw |= I5100_MC_SCRBEN_MASK; 606 schedule_delayed_work(&(priv->i5100_scrubbing), 607 I5100_SCRUB_REFRESH_RATE); 608 } else { 609 priv->scrub_enable = 0; 610 dw &= ~I5100_MC_SCRBEN_MASK; 611 cancel_delayed_work(&(priv->i5100_scrubbing)); 612 } 613 pci_write_config_dword(priv->mc, I5100_MC, dw); 614 615 pci_read_config_dword(priv->mc, I5100_MC, &dw); 616 617 bandwidth = 5900000 * i5100_mc_scrben(dw); 618 619 return bandwidth; 620 } 621 622 static int i5100_get_scrub_rate(struct mem_ctl_info *mci) 623 { 624 struct i5100_priv *priv = mci->pvt_info; 625 u32 dw; 626 627 pci_read_config_dword(priv->mc, I5100_MC, &dw); 628 629 return 5900000 * i5100_mc_scrben(dw); 630 } 631 632 static struct pci_dev *pci_get_device_func(unsigned vendor, 633 unsigned device, 634 unsigned func) 635 { 636 struct pci_dev *ret = NULL; 637 638 while (1) { 639 ret = pci_get_device(vendor, device, ret); 640 641 if (!ret) 642 break; 643 644 if (PCI_FUNC(ret->devfn) == func) 645 break; 646 } 647 648 return ret; 649 } 650 651 static unsigned long i5100_npages(struct mem_ctl_info *mci, unsigned int csrow) 652 { 653 struct i5100_priv *priv = mci->pvt_info; 654 const unsigned int chan_rank = i5100_csrow_to_rank(mci, csrow); 655 const unsigned int chan = i5100_csrow_to_chan(mci, csrow); 656 unsigned addr_lines; 657 658 /* dimm present? */ 659 if (!priv->mtr[chan][chan_rank].present) 660 return 0ULL; 661 662 addr_lines = 663 I5100_DIMM_ADDR_LINES + 664 priv->mtr[chan][chan_rank].numcol + 665 priv->mtr[chan][chan_rank].numrow + 666 priv->mtr[chan][chan_rank].numbank; 667 668 return (unsigned long) 669 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE); 670 } 671 672 static void i5100_init_mtr(struct mem_ctl_info *mci) 673 { 674 struct i5100_priv *priv = mci->pvt_info; 675 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; 676 int i; 677 678 for (i = 0; i < I5100_CHANNELS; i++) { 679 int j; 680 struct pci_dev *pdev = mms[i]; 681 682 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) { 683 const unsigned addr = 684 (j < 4) ? I5100_MTR_0 + j * 2 : 685 I5100_MTR_4 + (j - 4) * 2; 686 u16 w; 687 688 pci_read_config_word(pdev, addr, &w); 689 690 priv->mtr[i][j].present = i5100_mtr_present(w); 691 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w); 692 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w); 693 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w); 694 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w); 695 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w); 696 } 697 } 698 } 699 700 /* 701 * FIXME: make this into a real i2c adapter (so that dimm-decode 702 * will work)? 703 */ 704 static int i5100_read_spd_byte(const struct mem_ctl_info *mci, 705 u8 ch, u8 slot, u8 addr, u8 *byte) 706 { 707 struct i5100_priv *priv = mci->pvt_info; 708 u16 w; 709 710 pci_read_config_word(priv->mc, I5100_SPDDATA, &w); 711 if (i5100_spddata_busy(w)) 712 return -1; 713 714 pci_write_config_dword(priv->mc, I5100_SPDCMD, 715 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr, 716 0, 0)); 717 718 /* wait up to 100ms */ 719 udelay(100); 720 while (1) { 721 pci_read_config_word(priv->mc, I5100_SPDDATA, &w); 722 if (!i5100_spddata_busy(w)) 723 break; 724 udelay(100); 725 } 726 727 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w)) 728 return -1; 729 730 *byte = i5100_spddata_data(w); 731 732 return 0; 733 } 734 735 /* 736 * fill dimm chip select map 737 * 738 * FIXME: 739 * o not the only way to may chip selects to dimm slots 740 * o investigate if there is some way to obtain this map from the bios 741 */ 742 static void i5100_init_dimm_csmap(struct mem_ctl_info *mci) 743 { 744 struct i5100_priv *priv = mci->pvt_info; 745 int i; 746 747 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) { 748 int j; 749 750 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++) 751 priv->dimm_csmap[i][j] = -1; /* default NC */ 752 } 753 754 /* only 2 chip selects per slot... */ 755 if (priv->ranksperchan == 4) { 756 priv->dimm_csmap[0][0] = 0; 757 priv->dimm_csmap[0][1] = 3; 758 priv->dimm_csmap[1][0] = 1; 759 priv->dimm_csmap[1][1] = 2; 760 priv->dimm_csmap[2][0] = 2; 761 priv->dimm_csmap[3][0] = 3; 762 } else { 763 priv->dimm_csmap[0][0] = 0; 764 priv->dimm_csmap[0][1] = 1; 765 priv->dimm_csmap[1][0] = 2; 766 priv->dimm_csmap[1][1] = 3; 767 priv->dimm_csmap[2][0] = 4; 768 priv->dimm_csmap[2][1] = 5; 769 } 770 } 771 772 static void i5100_init_dimm_layout(struct pci_dev *pdev, 773 struct mem_ctl_info *mci) 774 { 775 struct i5100_priv *priv = mci->pvt_info; 776 int i; 777 778 for (i = 0; i < I5100_CHANNELS; i++) { 779 int j; 780 781 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) { 782 u8 rank; 783 784 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0) 785 priv->dimm_numrank[i][j] = 0; 786 else 787 priv->dimm_numrank[i][j] = (rank & 3) + 1; 788 } 789 } 790 791 i5100_init_dimm_csmap(mci); 792 } 793 794 static void i5100_init_interleaving(struct pci_dev *pdev, 795 struct mem_ctl_info *mci) 796 { 797 u16 w; 798 u32 dw; 799 struct i5100_priv *priv = mci->pvt_info; 800 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm }; 801 int i; 802 803 pci_read_config_word(pdev, I5100_TOLM, &w); 804 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024; 805 806 pci_read_config_word(pdev, I5100_MIR0, &w); 807 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28; 808 priv->mir[0].way[1] = i5100_mir_way1(w); 809 priv->mir[0].way[0] = i5100_mir_way0(w); 810 811 pci_read_config_word(pdev, I5100_MIR1, &w); 812 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28; 813 priv->mir[1].way[1] = i5100_mir_way1(w); 814 priv->mir[1].way[0] = i5100_mir_way0(w); 815 816 pci_read_config_word(pdev, I5100_AMIR_0, &w); 817 priv->amir[0] = w; 818 pci_read_config_word(pdev, I5100_AMIR_1, &w); 819 priv->amir[1] = w; 820 821 for (i = 0; i < I5100_CHANNELS; i++) { 822 int j; 823 824 for (j = 0; j < 5; j++) { 825 int k; 826 827 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw); 828 829 priv->dmir[i][j].limit = 830 (u64) i5100_dmir_limit(dw) << 28; 831 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++) 832 priv->dmir[i][j].rank[k] = 833 i5100_dmir_rank(dw, k); 834 } 835 } 836 837 i5100_init_mtr(mci); 838 } 839 840 static void i5100_init_csrows(struct mem_ctl_info *mci) 841 { 842 struct i5100_priv *priv = mci->pvt_info; 843 struct dimm_info *dimm; 844 845 mci_for_each_dimm(mci, dimm) { 846 const unsigned long npages = i5100_npages(mci, dimm->idx); 847 const unsigned int chan = i5100_csrow_to_chan(mci, dimm->idx); 848 const unsigned int rank = i5100_csrow_to_rank(mci, dimm->idx); 849 850 if (!npages) 851 continue; 852 853 dimm->nr_pages = npages; 854 dimm->grain = 32; 855 dimm->dtype = (priv->mtr[chan][rank].width == 4) ? 856 DEV_X4 : DEV_X8; 857 dimm->mtype = MEM_RDDR2; 858 dimm->edac_mode = EDAC_SECDED; 859 snprintf(dimm->label, sizeof(dimm->label), "DIMM%u", 860 i5100_rank_to_slot(mci, chan, rank)); 861 862 edac_dbg(2, "dimm channel %d, rank %d, size %ld\n", 863 chan, rank, (long)PAGES_TO_MiB(npages)); 864 } 865 } 866 867 /**************************************************************************** 868 * Error injection routines 869 ****************************************************************************/ 870 871 static void i5100_do_inject(struct mem_ctl_info *mci) 872 { 873 struct i5100_priv *priv = mci->pvt_info; 874 u32 mask0; 875 u16 mask1; 876 877 /* MEM[1:0]EINJMSK0 878 * 31 - ADDRMATCHEN 879 * 29:28 - HLINESEL 880 * 00 Reserved 881 * 01 Lower half of cache line 882 * 10 Upper half of cache line 883 * 11 Both upper and lower parts of cache line 884 * 27 - EINJEN 885 * 25:19 - XORMASK1 for deviceptr1 886 * 9:5 - SEC2RAM for deviceptr2 887 * 4:0 - FIR2RAM for deviceptr1 888 */ 889 mask0 = ((priv->inject_hlinesel & 0x3) << 28) | 890 I5100_MEMXEINJMSK0_EINJEN | 891 ((priv->inject_eccmask1 & 0xffff) << 10) | 892 ((priv->inject_deviceptr2 & 0x1f) << 5) | 893 (priv->inject_deviceptr1 & 0x1f); 894 895 /* MEM[1:0]EINJMSK1 896 * 15:0 - XORMASK2 for deviceptr2 897 */ 898 mask1 = priv->inject_eccmask2; 899 900 if (priv->inject_channel == 0) { 901 pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0); 902 pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1); 903 } else { 904 pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0); 905 pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1); 906 } 907 908 /* Error Injection Response Function 909 * Intel 5100 Memory Controller Hub Chipset (318378) datasheet 910 * hints about this register but carry no data about them. All 911 * data regarding device 19 is based on experimentation and the 912 * Intel 7300 Chipset Memory Controller Hub (318082) datasheet 913 * which appears to be accurate for the i5100 in this area. 914 * 915 * The injection code don't work without setting this register. 916 * The register needs to be flipped off then on else the hardware 917 * will only preform the first injection. 918 * 919 * Stop condition bits 7:4 920 * 1010 - Stop after one injection 921 * 1011 - Never stop injecting faults 922 * 923 * Start condition bits 3:0 924 * 1010 - Never start 925 * 1011 - Start immediately 926 */ 927 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa); 928 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab); 929 } 930 931 #define to_mci(k) container_of(k, struct mem_ctl_info, dev) 932 static ssize_t inject_enable_write(struct file *file, const char __user *data, 933 size_t count, loff_t *ppos) 934 { 935 struct device *dev = file->private_data; 936 struct mem_ctl_info *mci = to_mci(dev); 937 938 i5100_do_inject(mci); 939 940 return count; 941 } 942 943 static const struct file_operations i5100_inject_enable_fops = { 944 .open = simple_open, 945 .write = inject_enable_write, 946 .llseek = generic_file_llseek, 947 }; 948 949 static int i5100_setup_debugfs(struct mem_ctl_info *mci) 950 { 951 struct i5100_priv *priv = mci->pvt_info; 952 953 if (!i5100_debugfs) 954 return -ENODEV; 955 956 priv->debugfs = edac_debugfs_create_dir_at(mci->bus->name, i5100_debugfs); 957 958 if (!priv->debugfs) 959 return -ENOMEM; 960 961 edac_debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs, 962 &priv->inject_channel); 963 edac_debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs, 964 &priv->inject_hlinesel); 965 edac_debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs, 966 &priv->inject_deviceptr1); 967 edac_debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs, 968 &priv->inject_deviceptr2); 969 edac_debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs, 970 &priv->inject_eccmask1); 971 edac_debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs, 972 &priv->inject_eccmask2); 973 edac_debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs, 974 &mci->dev, &i5100_inject_enable_fops); 975 976 return 0; 977 978 } 979 980 static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 981 { 982 int rc; 983 struct mem_ctl_info *mci; 984 struct edac_mc_layer layers[2]; 985 struct i5100_priv *priv; 986 struct pci_dev *ch0mm, *ch1mm, *einj; 987 int ret = 0; 988 u32 dw; 989 int ranksperch; 990 991 if (PCI_FUNC(pdev->devfn) != 1) 992 return -ENODEV; 993 994 rc = pci_enable_device(pdev); 995 if (rc < 0) { 996 ret = rc; 997 goto bail; 998 } 999 1000 /* ECC enabled? */ 1001 pci_read_config_dword(pdev, I5100_MC, &dw); 1002 if (!i5100_mc_errdeten(dw)) { 1003 printk(KERN_INFO "i5100_edac: ECC not enabled.\n"); 1004 ret = -ENODEV; 1005 goto bail_pdev; 1006 } 1007 1008 /* figure out how many ranks, from strapped state of 48GB_Mode input */ 1009 pci_read_config_dword(pdev, I5100_MS, &dw); 1010 ranksperch = !!(dw & (1 << 8)) * 2 + 4; 1011 1012 /* enable error reporting... */ 1013 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw); 1014 dw &= ~I5100_FERR_NF_MEM_ANY_MASK; 1015 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw); 1016 1017 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */ 1018 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, 1019 PCI_DEVICE_ID_INTEL_5100_21, 0); 1020 if (!ch0mm) { 1021 ret = -ENODEV; 1022 goto bail_pdev; 1023 } 1024 1025 rc = pci_enable_device(ch0mm); 1026 if (rc < 0) { 1027 ret = rc; 1028 goto bail_ch0; 1029 } 1030 1031 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */ 1032 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL, 1033 PCI_DEVICE_ID_INTEL_5100_22, 0); 1034 if (!ch1mm) { 1035 ret = -ENODEV; 1036 goto bail_disable_ch0; 1037 } 1038 1039 rc = pci_enable_device(ch1mm); 1040 if (rc < 0) { 1041 ret = rc; 1042 goto bail_ch1; 1043 } 1044 1045 layers[0].type = EDAC_MC_LAYER_CHANNEL; 1046 layers[0].size = 2; 1047 layers[0].is_virt_csrow = false; 1048 layers[1].type = EDAC_MC_LAYER_SLOT; 1049 layers[1].size = ranksperch; 1050 layers[1].is_virt_csrow = true; 1051 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 1052 sizeof(*priv)); 1053 if (!mci) { 1054 ret = -ENOMEM; 1055 goto bail_disable_ch1; 1056 } 1057 1058 1059 /* device 19, func 0, Error injection */ 1060 einj = pci_get_device_func(PCI_VENDOR_ID_INTEL, 1061 PCI_DEVICE_ID_INTEL_5100_19, 0); 1062 if (!einj) { 1063 ret = -ENODEV; 1064 goto bail_mc_free; 1065 } 1066 1067 rc = pci_enable_device(einj); 1068 if (rc < 0) { 1069 ret = rc; 1070 goto bail_einj; 1071 } 1072 1073 mci->pdev = &pdev->dev; 1074 1075 priv = mci->pvt_info; 1076 priv->ranksperchan = ranksperch; 1077 priv->mc = pdev; 1078 priv->ch0mm = ch0mm; 1079 priv->ch1mm = ch1mm; 1080 priv->einj = einj; 1081 1082 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing); 1083 1084 /* If scrubbing was already enabled by the bios, start maintaining it */ 1085 pci_read_config_dword(pdev, I5100_MC, &dw); 1086 if (i5100_mc_scrben(dw)) { 1087 priv->scrub_enable = 1; 1088 schedule_delayed_work(&(priv->i5100_scrubbing), 1089 I5100_SCRUB_REFRESH_RATE); 1090 } 1091 1092 i5100_init_dimm_layout(pdev, mci); 1093 i5100_init_interleaving(pdev, mci); 1094 1095 mci->mtype_cap = MEM_FLAG_FB_DDR2; 1096 mci->edac_ctl_cap = EDAC_FLAG_SECDED; 1097 mci->edac_cap = EDAC_FLAG_SECDED; 1098 mci->mod_name = "i5100_edac.c"; 1099 mci->ctl_name = "i5100"; 1100 mci->dev_name = pci_name(pdev); 1101 mci->ctl_page_to_phys = NULL; 1102 1103 mci->edac_check = i5100_check_error; 1104 mci->set_sdram_scrub_rate = i5100_set_scrub_rate; 1105 mci->get_sdram_scrub_rate = i5100_get_scrub_rate; 1106 1107 priv->inject_channel = 0; 1108 priv->inject_hlinesel = 0; 1109 priv->inject_deviceptr1 = 0; 1110 priv->inject_deviceptr2 = 0; 1111 priv->inject_eccmask1 = 0; 1112 priv->inject_eccmask2 = 0; 1113 1114 i5100_init_csrows(mci); 1115 1116 /* this strange construction seems to be in every driver, dunno why */ 1117 switch (edac_op_state) { 1118 case EDAC_OPSTATE_POLL: 1119 case EDAC_OPSTATE_NMI: 1120 break; 1121 default: 1122 edac_op_state = EDAC_OPSTATE_POLL; 1123 break; 1124 } 1125 1126 if (edac_mc_add_mc(mci)) { 1127 ret = -ENODEV; 1128 goto bail_scrub; 1129 } 1130 1131 i5100_setup_debugfs(mci); 1132 1133 return ret; 1134 1135 bail_scrub: 1136 priv->scrub_enable = 0; 1137 cancel_delayed_work_sync(&(priv->i5100_scrubbing)); 1138 pci_disable_device(einj); 1139 1140 bail_einj: 1141 pci_dev_put(einj); 1142 1143 bail_mc_free: 1144 edac_mc_free(mci); 1145 1146 bail_disable_ch1: 1147 pci_disable_device(ch1mm); 1148 1149 bail_ch1: 1150 pci_dev_put(ch1mm); 1151 1152 bail_disable_ch0: 1153 pci_disable_device(ch0mm); 1154 1155 bail_ch0: 1156 pci_dev_put(ch0mm); 1157 1158 bail_pdev: 1159 pci_disable_device(pdev); 1160 1161 bail: 1162 return ret; 1163 } 1164 1165 static void i5100_remove_one(struct pci_dev *pdev) 1166 { 1167 struct mem_ctl_info *mci; 1168 struct i5100_priv *priv; 1169 1170 mci = edac_mc_del_mc(&pdev->dev); 1171 1172 if (!mci) 1173 return; 1174 1175 priv = mci->pvt_info; 1176 1177 edac_debugfs_remove_recursive(priv->debugfs); 1178 1179 priv->scrub_enable = 0; 1180 cancel_delayed_work_sync(&(priv->i5100_scrubbing)); 1181 1182 pci_disable_device(pdev); 1183 pci_disable_device(priv->ch0mm); 1184 pci_disable_device(priv->ch1mm); 1185 pci_disable_device(priv->einj); 1186 pci_dev_put(priv->ch0mm); 1187 pci_dev_put(priv->ch1mm); 1188 pci_dev_put(priv->einj); 1189 1190 edac_mc_free(mci); 1191 } 1192 1193 static const struct pci_device_id i5100_pci_tbl[] = { 1194 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */ 1195 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) }, 1196 { 0, } 1197 }; 1198 MODULE_DEVICE_TABLE(pci, i5100_pci_tbl); 1199 1200 static struct pci_driver i5100_driver = { 1201 .name = KBUILD_BASENAME, 1202 .probe = i5100_init_one, 1203 .remove = i5100_remove_one, 1204 .id_table = i5100_pci_tbl, 1205 }; 1206 1207 static int __init i5100_init(void) 1208 { 1209 int pci_rc; 1210 1211 i5100_debugfs = edac_debugfs_create_dir_at("i5100_edac", NULL); 1212 1213 pci_rc = pci_register_driver(&i5100_driver); 1214 return (pci_rc < 0) ? pci_rc : 0; 1215 } 1216 1217 static void __exit i5100_exit(void) 1218 { 1219 edac_debugfs_remove(i5100_debugfs); 1220 1221 pci_unregister_driver(&i5100_driver); 1222 } 1223 1224 module_init(i5100_init); 1225 module_exit(i5100_exit); 1226 1227 MODULE_LICENSE("GPL"); 1228 MODULE_AUTHOR 1229 ("Arthur Jones <ajones@riverbed.com>"); 1230 MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers"); 1231