1 /* 2 * Intel 5000(P/V/X) class Memory Controllers kernel module 3 * 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * Written by Douglas Thompson Linux Networx (http://lnxi.com) 8 * norsk5@xmission.com 9 * 10 * This module is based on the following document: 11 * 12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet 13 * http://developer.intel.com/design/chipsets/datashts/313070.htm 14 * 15 */ 16 17 #include <linux/module.h> 18 #include <linux/init.h> 19 #include <linux/pci.h> 20 #include <linux/pci_ids.h> 21 #include <linux/slab.h> 22 #include <linux/edac.h> 23 #include <asm/mmzone.h> 24 25 #include "edac_module.h" 26 27 /* 28 * Alter this version for the I5000 module when modifications are made 29 */ 30 #define I5000_REVISION " Ver: 2.0.12" 31 #define EDAC_MOD_STR "i5000_edac" 32 33 #define i5000_printk(level, fmt, arg...) \ 34 edac_printk(level, "i5000", fmt, ##arg) 35 36 #define i5000_mc_printk(mci, level, fmt, arg...) \ 37 edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg) 38 39 #ifndef PCI_DEVICE_ID_INTEL_FBD_0 40 #define PCI_DEVICE_ID_INTEL_FBD_0 0x25F5 41 #endif 42 #ifndef PCI_DEVICE_ID_INTEL_FBD_1 43 #define PCI_DEVICE_ID_INTEL_FBD_1 0x25F6 44 #endif 45 46 /* Device 16, 47 * Function 0: System Address 48 * Function 1: Memory Branch Map, Control, Errors Register 49 * Function 2: FSB Error Registers 50 * 51 * All 3 functions of Device 16 (0,1,2) share the SAME DID 52 */ 53 #define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0 54 55 /* OFFSETS for Function 0 */ 56 57 /* OFFSETS for Function 1 */ 58 #define AMBASE 0x48 59 #define MAXCH 0x56 60 #define MAXDIMMPERCH 0x57 61 #define TOLM 0x6C 62 #define REDMEMB 0x7C 63 #define RED_ECC_LOCATOR(x) ((x) & 0x3FFFF) 64 #define REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF) 65 #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3FE00) 66 #define MIR0 0x80 67 #define MIR1 0x84 68 #define MIR2 0x88 69 #define AMIR0 0x8C 70 #define AMIR1 0x90 71 #define AMIR2 0x94 72 73 #define FERR_FAT_FBD 0x98 74 #define NERR_FAT_FBD 0x9C 75 #define EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3) 76 #define FERR_FAT_FBDCHAN 0x30000000 77 #define FERR_FAT_M3ERR 0x00000004 78 #define FERR_FAT_M2ERR 0x00000002 79 #define FERR_FAT_M1ERR 0x00000001 80 #define FERR_FAT_MASK (FERR_FAT_M1ERR | \ 81 FERR_FAT_M2ERR | \ 82 FERR_FAT_M3ERR) 83 84 #define FERR_NF_FBD 0xA0 85 86 /* Thermal and SPD or BFD errors */ 87 #define FERR_NF_M28ERR 0x01000000 88 #define FERR_NF_M27ERR 0x00800000 89 #define FERR_NF_M26ERR 0x00400000 90 #define FERR_NF_M25ERR 0x00200000 91 #define FERR_NF_M24ERR 0x00100000 92 #define FERR_NF_M23ERR 0x00080000 93 #define FERR_NF_M22ERR 0x00040000 94 #define FERR_NF_M21ERR 0x00020000 95 96 /* Correctable errors */ 97 #define FERR_NF_M20ERR 0x00010000 98 #define FERR_NF_M19ERR 0x00008000 99 #define FERR_NF_M18ERR 0x00004000 100 #define FERR_NF_M17ERR 0x00002000 101 102 /* Non-Retry or redundant Retry errors */ 103 #define FERR_NF_M16ERR 0x00001000 104 #define FERR_NF_M15ERR 0x00000800 105 #define FERR_NF_M14ERR 0x00000400 106 #define FERR_NF_M13ERR 0x00000200 107 108 /* Uncorrectable errors */ 109 #define FERR_NF_M12ERR 0x00000100 110 #define FERR_NF_M11ERR 0x00000080 111 #define FERR_NF_M10ERR 0x00000040 112 #define FERR_NF_M9ERR 0x00000020 113 #define FERR_NF_M8ERR 0x00000010 114 #define FERR_NF_M7ERR 0x00000008 115 #define FERR_NF_M6ERR 0x00000004 116 #define FERR_NF_M5ERR 0x00000002 117 #define FERR_NF_M4ERR 0x00000001 118 119 #define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \ 120 FERR_NF_M11ERR | \ 121 FERR_NF_M10ERR | \ 122 FERR_NF_M9ERR | \ 123 FERR_NF_M8ERR | \ 124 FERR_NF_M7ERR | \ 125 FERR_NF_M6ERR | \ 126 FERR_NF_M5ERR | \ 127 FERR_NF_M4ERR) 128 #define FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \ 129 FERR_NF_M19ERR | \ 130 FERR_NF_M18ERR | \ 131 FERR_NF_M17ERR) 132 #define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \ 133 FERR_NF_M28ERR) 134 #define FERR_NF_THERMAL (FERR_NF_M26ERR | \ 135 FERR_NF_M25ERR | \ 136 FERR_NF_M24ERR | \ 137 FERR_NF_M23ERR) 138 #define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR) 139 #define FERR_NF_NORTH_CRC (FERR_NF_M21ERR) 140 #define FERR_NF_NON_RETRY (FERR_NF_M13ERR | \ 141 FERR_NF_M14ERR | \ 142 FERR_NF_M15ERR) 143 144 #define NERR_NF_FBD 0xA4 145 #define FERR_NF_MASK (FERR_NF_UNCORRECTABLE | \ 146 FERR_NF_CORRECTABLE | \ 147 FERR_NF_DIMM_SPARE | \ 148 FERR_NF_THERMAL | \ 149 FERR_NF_SPD_PROTOCOL | \ 150 FERR_NF_NORTH_CRC | \ 151 FERR_NF_NON_RETRY) 152 153 #define EMASK_FBD 0xA8 154 #define EMASK_FBD_M28ERR 0x08000000 155 #define EMASK_FBD_M27ERR 0x04000000 156 #define EMASK_FBD_M26ERR 0x02000000 157 #define EMASK_FBD_M25ERR 0x01000000 158 #define EMASK_FBD_M24ERR 0x00800000 159 #define EMASK_FBD_M23ERR 0x00400000 160 #define EMASK_FBD_M22ERR 0x00200000 161 #define EMASK_FBD_M21ERR 0x00100000 162 #define EMASK_FBD_M20ERR 0x00080000 163 #define EMASK_FBD_M19ERR 0x00040000 164 #define EMASK_FBD_M18ERR 0x00020000 165 #define EMASK_FBD_M17ERR 0x00010000 166 167 #define EMASK_FBD_M15ERR 0x00004000 168 #define EMASK_FBD_M14ERR 0x00002000 169 #define EMASK_FBD_M13ERR 0x00001000 170 #define EMASK_FBD_M12ERR 0x00000800 171 #define EMASK_FBD_M11ERR 0x00000400 172 #define EMASK_FBD_M10ERR 0x00000200 173 #define EMASK_FBD_M9ERR 0x00000100 174 #define EMASK_FBD_M8ERR 0x00000080 175 #define EMASK_FBD_M7ERR 0x00000040 176 #define EMASK_FBD_M6ERR 0x00000020 177 #define EMASK_FBD_M5ERR 0x00000010 178 #define EMASK_FBD_M4ERR 0x00000008 179 #define EMASK_FBD_M3ERR 0x00000004 180 #define EMASK_FBD_M2ERR 0x00000002 181 #define EMASK_FBD_M1ERR 0x00000001 182 183 #define ENABLE_EMASK_FBD_FATAL_ERRORS (EMASK_FBD_M1ERR | \ 184 EMASK_FBD_M2ERR | \ 185 EMASK_FBD_M3ERR) 186 187 #define ENABLE_EMASK_FBD_UNCORRECTABLE (EMASK_FBD_M4ERR | \ 188 EMASK_FBD_M5ERR | \ 189 EMASK_FBD_M6ERR | \ 190 EMASK_FBD_M7ERR | \ 191 EMASK_FBD_M8ERR | \ 192 EMASK_FBD_M9ERR | \ 193 EMASK_FBD_M10ERR | \ 194 EMASK_FBD_M11ERR | \ 195 EMASK_FBD_M12ERR) 196 #define ENABLE_EMASK_FBD_CORRECTABLE (EMASK_FBD_M17ERR | \ 197 EMASK_FBD_M18ERR | \ 198 EMASK_FBD_M19ERR | \ 199 EMASK_FBD_M20ERR) 200 #define ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \ 201 EMASK_FBD_M28ERR) 202 #define ENABLE_EMASK_FBD_THERMALS (EMASK_FBD_M26ERR | \ 203 EMASK_FBD_M25ERR | \ 204 EMASK_FBD_M24ERR | \ 205 EMASK_FBD_M23ERR) 206 #define ENABLE_EMASK_FBD_SPD_PROTOCOL (EMASK_FBD_M22ERR) 207 #define ENABLE_EMASK_FBD_NORTH_CRC (EMASK_FBD_M21ERR) 208 #define ENABLE_EMASK_FBD_NON_RETRY (EMASK_FBD_M15ERR | \ 209 EMASK_FBD_M14ERR | \ 210 EMASK_FBD_M13ERR) 211 212 #define ENABLE_EMASK_ALL (ENABLE_EMASK_FBD_NON_RETRY | \ 213 ENABLE_EMASK_FBD_NORTH_CRC | \ 214 ENABLE_EMASK_FBD_SPD_PROTOCOL | \ 215 ENABLE_EMASK_FBD_THERMALS | \ 216 ENABLE_EMASK_FBD_DIMM_SPARE | \ 217 ENABLE_EMASK_FBD_FATAL_ERRORS | \ 218 ENABLE_EMASK_FBD_CORRECTABLE | \ 219 ENABLE_EMASK_FBD_UNCORRECTABLE) 220 221 #define ERR0_FBD 0xAC 222 #define ERR1_FBD 0xB0 223 #define ERR2_FBD 0xB4 224 #define MCERR_FBD 0xB8 225 #define NRECMEMA 0xBE 226 #define NREC_BANK(x) (((x)>>12) & 0x7) 227 #define NREC_RDWR(x) (((x)>>11) & 1) 228 #define NREC_RANK(x) (((x)>>8) & 0x7) 229 #define NRECMEMB 0xC0 230 #define NREC_CAS(x) (((x)>>16) & 0xFFF) 231 #define NREC_RAS(x) ((x) & 0x7FFF) 232 #define NRECFGLOG 0xC4 233 #define NREEECFBDA 0xC8 234 #define NREEECFBDB 0xCC 235 #define NREEECFBDC 0xD0 236 #define NREEECFBDD 0xD4 237 #define NREEECFBDE 0xD8 238 #define REDMEMA 0xDC 239 #define RECMEMA 0xE2 240 #define REC_BANK(x) (((x)>>12) & 0x7) 241 #define REC_RDWR(x) (((x)>>11) & 1) 242 #define REC_RANK(x) (((x)>>8) & 0x7) 243 #define RECMEMB 0xE4 244 #define REC_CAS(x) (((x)>>16) & 0xFFFFFF) 245 #define REC_RAS(x) ((x) & 0x7FFF) 246 #define RECFGLOG 0xE8 247 #define RECFBDA 0xEC 248 #define RECFBDB 0xF0 249 #define RECFBDC 0xF4 250 #define RECFBDD 0xF8 251 #define RECFBDE 0xFC 252 253 /* OFFSETS for Function 2 */ 254 255 /* 256 * Device 21, 257 * Function 0: Memory Map Branch 0 258 * 259 * Device 22, 260 * Function 0: Memory Map Branch 1 261 */ 262 #define PCI_DEVICE_ID_I5000_BRANCH_0 0x25F5 263 #define PCI_DEVICE_ID_I5000_BRANCH_1 0x25F6 264 265 #define AMB_PRESENT_0 0x64 266 #define AMB_PRESENT_1 0x66 267 #define MTR0 0x80 268 #define MTR1 0x84 269 #define MTR2 0x88 270 #define MTR3 0x8C 271 272 #define NUM_MTRS 4 273 #define CHANNELS_PER_BRANCH 2 274 #define MAX_BRANCHES 2 275 276 /* Defines to extract the various fields from the 277 * MTRx - Memory Technology Registers 278 */ 279 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8)) 280 #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4) 281 #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4) 282 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2) 283 #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1) 284 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1) 285 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3) 286 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13) 287 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3) 288 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10) 289 290 /* enables the report of miscellaneous messages as CE errors - default off */ 291 static int misc_messages; 292 293 /* Enumeration of supported devices */ 294 enum i5000_chips { 295 I5000P = 0, 296 I5000V = 1, /* future */ 297 I5000X = 2 /* future */ 298 }; 299 300 /* Device name and register DID (Device ID) */ 301 struct i5000_dev_info { 302 const char *ctl_name; /* name for this device */ 303 u16 fsb_mapping_errors; /* DID for the branchmap,control */ 304 }; 305 306 /* Table of devices attributes supported by this driver */ 307 static const struct i5000_dev_info i5000_devs[] = { 308 [I5000P] = { 309 .ctl_name = "I5000", 310 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16, 311 }, 312 }; 313 314 struct i5000_dimm_info { 315 int megabytes; /* size, 0 means not present */ 316 int dual_rank; 317 }; 318 319 #define MAX_CHANNELS 6 /* max possible channels */ 320 #define MAX_CSROWS (8*2) /* max possible csrows per channel */ 321 322 /* driver private data structure */ 323 struct i5000_pvt { 324 struct pci_dev *system_address; /* 16.0 */ 325 struct pci_dev *branchmap_werrors; /* 16.1 */ 326 struct pci_dev *fsb_error_regs; /* 16.2 */ 327 struct pci_dev *branch_0; /* 21.0 */ 328 struct pci_dev *branch_1; /* 22.0 */ 329 330 u16 tolm; /* top of low memory */ 331 union { 332 u64 ambase; /* AMB BAR */ 333 struct { 334 u32 ambase_bottom; 335 u32 ambase_top; 336 } u __packed; 337 }; 338 339 u16 mir0, mir1, mir2; 340 341 u16 b0_mtr[NUM_MTRS]; /* Memory Technology Reg */ 342 u16 b0_ambpresent0; /* Branch 0, Channel 0 */ 343 u16 b0_ambpresent1; /* Branch 0, Channel 1 */ 344 345 u16 b1_mtr[NUM_MTRS]; /* Memory Technology Reg */ 346 u16 b1_ambpresent0; /* Branch 1, Channel 8 */ 347 u16 b1_ambpresent1; /* Branch 1, Channel 1 */ 348 349 /* DIMM information matrix, allocating architecture maximums */ 350 struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS]; 351 352 /* Actual values for this controller */ 353 int maxch; /* Max channels */ 354 int maxdimmperch; /* Max DIMMs per channel */ 355 356 /* Hardware error reporting status */ 357 bool enabled_error_reporting; 358 }; 359 360 /* I5000 MCH error information retrieved from Hardware */ 361 struct i5000_error_info { 362 363 /* These registers are always read from the MC */ 364 u32 ferr_fat_fbd; /* First Errors Fatal */ 365 u32 nerr_fat_fbd; /* Next Errors Fatal */ 366 u32 ferr_nf_fbd; /* First Errors Non-Fatal */ 367 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */ 368 369 /* These registers are input ONLY if there was a Recoverable Error */ 370 u32 redmemb; /* Recoverable Mem Data Error log B */ 371 u16 recmema; /* Recoverable Mem Error log A */ 372 u32 recmemb; /* Recoverable Mem Error log B */ 373 374 /* These registers are input ONLY if there was a 375 * Non-Recoverable Error */ 376 u16 nrecmema; /* Non-Recoverable Mem log A */ 377 u32 nrecmemb; /* Non-Recoverable Mem log B */ 378 379 }; 380 381 static struct edac_pci_ctl_info *i5000_pci; 382 383 /* 384 * i5000_get_error_info Retrieve the hardware error information from 385 * the hardware and cache it in the 'info' 386 * structure 387 */ 388 static void i5000_get_error_info(struct mem_ctl_info *mci, 389 struct i5000_error_info *info) 390 { 391 struct i5000_pvt *pvt; 392 u32 value; 393 394 pvt = mci->pvt_info; 395 396 /* read in the 1st FATAL error register */ 397 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value); 398 399 /* Mask only the bits that the doc says are valid 400 */ 401 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK); 402 403 /* If there is an error, then read in the */ 404 /* NEXT FATAL error register and the Memory Error Log Register A */ 405 if (value & FERR_FAT_MASK) { 406 info->ferr_fat_fbd = value; 407 408 /* harvest the various error data we need */ 409 pci_read_config_dword(pvt->branchmap_werrors, 410 NERR_FAT_FBD, &info->nerr_fat_fbd); 411 pci_read_config_word(pvt->branchmap_werrors, 412 NRECMEMA, &info->nrecmema); 413 pci_read_config_dword(pvt->branchmap_werrors, 414 NRECMEMB, &info->nrecmemb); 415 416 /* Clear the error bits, by writing them back */ 417 pci_write_config_dword(pvt->branchmap_werrors, 418 FERR_FAT_FBD, value); 419 } else { 420 info->ferr_fat_fbd = 0; 421 info->nerr_fat_fbd = 0; 422 info->nrecmema = 0; 423 info->nrecmemb = 0; 424 } 425 426 /* read in the 1st NON-FATAL error register */ 427 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value); 428 429 /* If there is an error, then read in the 1st NON-FATAL error 430 * register as well */ 431 if (value & FERR_NF_MASK) { 432 info->ferr_nf_fbd = value; 433 434 /* harvest the various error data we need */ 435 pci_read_config_dword(pvt->branchmap_werrors, 436 NERR_NF_FBD, &info->nerr_nf_fbd); 437 pci_read_config_word(pvt->branchmap_werrors, 438 RECMEMA, &info->recmema); 439 pci_read_config_dword(pvt->branchmap_werrors, 440 RECMEMB, &info->recmemb); 441 pci_read_config_dword(pvt->branchmap_werrors, 442 REDMEMB, &info->redmemb); 443 444 /* Clear the error bits, by writing them back */ 445 pci_write_config_dword(pvt->branchmap_werrors, 446 FERR_NF_FBD, value); 447 } else { 448 info->ferr_nf_fbd = 0; 449 info->nerr_nf_fbd = 0; 450 info->recmema = 0; 451 info->recmemb = 0; 452 info->redmemb = 0; 453 } 454 } 455 456 /* 457 * i5000_process_fatal_error_info(struct mem_ctl_info *mci, 458 * struct i5000_error_info *info, 459 * int handle_errors); 460 * 461 * handle the Intel FATAL errors, if any 462 */ 463 static void i5000_process_fatal_error_info(struct mem_ctl_info *mci, 464 struct i5000_error_info *info, 465 int handle_errors) 466 { 467 char msg[EDAC_MC_LABEL_LEN + 1 + 160]; 468 char *specific = NULL; 469 u32 allErrors; 470 int channel; 471 int bank; 472 int rank; 473 int rdwr; 474 int ras, cas; 475 476 /* mask off the Error bits that are possible */ 477 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK); 478 if (!allErrors) 479 return; /* if no error, return now */ 480 481 channel = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd); 482 483 /* Use the NON-Recoverable macros to extract data */ 484 bank = NREC_BANK(info->nrecmema); 485 rank = NREC_RANK(info->nrecmema); 486 rdwr = NREC_RDWR(info->nrecmema); 487 ras = NREC_RAS(info->nrecmemb); 488 cas = NREC_CAS(info->nrecmemb); 489 490 edac_dbg(0, "\t\tCSROW= %d Channel= %d (DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 491 rank, channel, bank, 492 rdwr ? "Write" : "Read", ras, cas); 493 494 /* Only 1 bit will be on */ 495 switch (allErrors) { 496 case FERR_FAT_M1ERR: 497 specific = "Alert on non-redundant retry or fast " 498 "reset timeout"; 499 break; 500 case FERR_FAT_M2ERR: 501 specific = "Northbound CRC error on non-redundant " 502 "retry"; 503 break; 504 case FERR_FAT_M3ERR: 505 { 506 static int done; 507 508 /* 509 * This error is generated to inform that the intelligent 510 * throttling is disabled and the temperature passed the 511 * specified middle point. Since this is something the BIOS 512 * should take care of, we'll warn only once to avoid 513 * worthlessly flooding the log. 514 */ 515 if (done) 516 return; 517 done++; 518 519 specific = ">Tmid Thermal event with intelligent " 520 "throttling disabled"; 521 } 522 break; 523 } 524 525 /* Form out message */ 526 snprintf(msg, sizeof(msg), 527 "Bank=%d RAS=%d CAS=%d FATAL Err=0x%x (%s)", 528 bank, ras, cas, allErrors, specific); 529 530 /* Call the helper to output message */ 531 edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0, 532 channel >> 1, channel & 1, rank, 533 rdwr ? "Write error" : "Read error", 534 msg); 535 } 536 537 /* 538 * i5000_process_fatal_error_info(struct mem_ctl_info *mci, 539 * struct i5000_error_info *info, 540 * int handle_errors); 541 * 542 * handle the Intel NON-FATAL errors, if any 543 */ 544 static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci, 545 struct i5000_error_info *info, 546 int handle_errors) 547 { 548 char msg[EDAC_MC_LABEL_LEN + 1 + 170]; 549 char *specific = NULL; 550 u32 allErrors; 551 u32 ue_errors; 552 u32 ce_errors; 553 u32 misc_errors; 554 int branch; 555 int channel; 556 int bank; 557 int rank; 558 int rdwr; 559 int ras, cas; 560 561 /* mask off the Error bits that are possible */ 562 allErrors = (info->ferr_nf_fbd & FERR_NF_MASK); 563 if (!allErrors) 564 return; /* if no error, return now */ 565 566 /* ONLY ONE of the possible error bits will be set, as per the docs */ 567 ue_errors = allErrors & FERR_NF_UNCORRECTABLE; 568 if (ue_errors) { 569 edac_dbg(0, "\tUncorrected bits= 0x%x\n", ue_errors); 570 571 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd); 572 573 /* 574 * According with i5000 datasheet, bit 28 has no significance 575 * for errors M4Err-M12Err and M17Err-M21Err, on FERR_NF_FBD 576 */ 577 channel = branch & 2; 578 579 bank = NREC_BANK(info->nrecmema); 580 rank = NREC_RANK(info->nrecmema); 581 rdwr = NREC_RDWR(info->nrecmema); 582 ras = NREC_RAS(info->nrecmemb); 583 cas = NREC_CAS(info->nrecmemb); 584 585 edac_dbg(0, "\t\tCSROW= %d Channels= %d,%d (Branch= %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 586 rank, channel, channel + 1, branch >> 1, bank, 587 rdwr ? "Write" : "Read", ras, cas); 588 589 switch (ue_errors) { 590 case FERR_NF_M12ERR: 591 specific = "Non-Aliased Uncorrectable Patrol Data ECC"; 592 break; 593 case FERR_NF_M11ERR: 594 specific = "Non-Aliased Uncorrectable Spare-Copy " 595 "Data ECC"; 596 break; 597 case FERR_NF_M10ERR: 598 specific = "Non-Aliased Uncorrectable Mirrored Demand " 599 "Data ECC"; 600 break; 601 case FERR_NF_M9ERR: 602 specific = "Non-Aliased Uncorrectable Non-Mirrored " 603 "Demand Data ECC"; 604 break; 605 case FERR_NF_M8ERR: 606 specific = "Aliased Uncorrectable Patrol Data ECC"; 607 break; 608 case FERR_NF_M7ERR: 609 specific = "Aliased Uncorrectable Spare-Copy Data ECC"; 610 break; 611 case FERR_NF_M6ERR: 612 specific = "Aliased Uncorrectable Mirrored Demand " 613 "Data ECC"; 614 break; 615 case FERR_NF_M5ERR: 616 specific = "Aliased Uncorrectable Non-Mirrored Demand " 617 "Data ECC"; 618 break; 619 case FERR_NF_M4ERR: 620 specific = "Uncorrectable Data ECC on Replay"; 621 break; 622 } 623 624 /* Form out message */ 625 snprintf(msg, sizeof(msg), 626 "Rank=%d Bank=%d RAS=%d CAS=%d, UE Err=0x%x (%s)", 627 rank, bank, ras, cas, ue_errors, specific); 628 629 /* Call the helper to output message */ 630 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, 631 channel >> 1, -1, rank, 632 rdwr ? "Write error" : "Read error", 633 msg); 634 } 635 636 /* Check correctable errors */ 637 ce_errors = allErrors & FERR_NF_CORRECTABLE; 638 if (ce_errors) { 639 edac_dbg(0, "\tCorrected bits= 0x%x\n", ce_errors); 640 641 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd); 642 643 channel = 0; 644 if (REC_ECC_LOCATOR_ODD(info->redmemb)) 645 channel = 1; 646 647 /* Convert channel to be based from zero, instead of 648 * from branch base of 0 */ 649 channel += branch; 650 651 bank = REC_BANK(info->recmema); 652 rank = REC_RANK(info->recmema); 653 rdwr = REC_RDWR(info->recmema); 654 ras = REC_RAS(info->recmemb); 655 cas = REC_CAS(info->recmemb); 656 657 edac_dbg(0, "\t\tCSROW= %d Channel= %d (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n", 658 rank, channel, branch >> 1, bank, 659 rdwr ? "Write" : "Read", ras, cas); 660 661 switch (ce_errors) { 662 case FERR_NF_M17ERR: 663 specific = "Correctable Non-Mirrored Demand Data ECC"; 664 break; 665 case FERR_NF_M18ERR: 666 specific = "Correctable Mirrored Demand Data ECC"; 667 break; 668 case FERR_NF_M19ERR: 669 specific = "Correctable Spare-Copy Data ECC"; 670 break; 671 case FERR_NF_M20ERR: 672 specific = "Correctable Patrol Data ECC"; 673 break; 674 } 675 676 /* Form out message */ 677 snprintf(msg, sizeof(msg), 678 "Rank=%d Bank=%d RDWR=%s RAS=%d " 679 "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank, 680 rdwr ? "Write" : "Read", ras, cas, ce_errors, 681 specific); 682 683 /* Call the helper to output message */ 684 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, 685 channel >> 1, channel % 2, rank, 686 rdwr ? "Write error" : "Read error", 687 msg); 688 } 689 690 if (!misc_messages) 691 return; 692 693 misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC | 694 FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE); 695 if (misc_errors) { 696 switch (misc_errors) { 697 case FERR_NF_M13ERR: 698 specific = "Non-Retry or Redundant Retry FBD Memory " 699 "Alert or Redundant Fast Reset Timeout"; 700 break; 701 case FERR_NF_M14ERR: 702 specific = "Non-Retry or Redundant Retry FBD " 703 "Configuration Alert"; 704 break; 705 case FERR_NF_M15ERR: 706 specific = "Non-Retry or Redundant Retry FBD " 707 "Northbound CRC error on read data"; 708 break; 709 case FERR_NF_M21ERR: 710 specific = "FBD Northbound CRC error on " 711 "FBD Sync Status"; 712 break; 713 case FERR_NF_M22ERR: 714 specific = "SPD protocol error"; 715 break; 716 case FERR_NF_M27ERR: 717 specific = "DIMM-spare copy started"; 718 break; 719 case FERR_NF_M28ERR: 720 specific = "DIMM-spare copy completed"; 721 break; 722 } 723 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd); 724 725 /* Form out message */ 726 snprintf(msg, sizeof(msg), 727 "Err=%#x (%s)", misc_errors, specific); 728 729 /* Call the helper to output message */ 730 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0, 731 branch >> 1, -1, -1, 732 "Misc error", msg); 733 } 734 } 735 736 /* 737 * i5000_process_error_info Process the error info that is 738 * in the 'info' structure, previously retrieved from hardware 739 */ 740 static void i5000_process_error_info(struct mem_ctl_info *mci, 741 struct i5000_error_info *info, 742 int handle_errors) 743 { 744 /* First handle any fatal errors that occurred */ 745 i5000_process_fatal_error_info(mci, info, handle_errors); 746 747 /* now handle any non-fatal errors that occurred */ 748 i5000_process_nonfatal_error_info(mci, info, handle_errors); 749 } 750 751 /* 752 * i5000_clear_error Retrieve any error from the hardware 753 * but do NOT process that error. 754 * Used for 'clearing' out of previous errors 755 * Called by the Core module. 756 */ 757 static void i5000_clear_error(struct mem_ctl_info *mci) 758 { 759 struct i5000_error_info info; 760 761 i5000_get_error_info(mci, &info); 762 } 763 764 /* 765 * i5000_check_error Retrieve and process errors reported by the 766 * hardware. Called by the Core module. 767 */ 768 static void i5000_check_error(struct mem_ctl_info *mci) 769 { 770 struct i5000_error_info info; 771 772 i5000_get_error_info(mci, &info); 773 i5000_process_error_info(mci, &info, 1); 774 } 775 776 /* 777 * i5000_get_devices Find and perform 'get' operation on the MCH's 778 * device/functions we want to reference for this driver 779 * 780 * Need to 'get' device 16 func 1 and func 2 781 */ 782 static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx) 783 { 784 //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx]; 785 struct i5000_pvt *pvt; 786 struct pci_dev *pdev; 787 788 pvt = mci->pvt_info; 789 790 /* Attempt to 'get' the MCH register we want */ 791 pdev = NULL; 792 while (1) { 793 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 794 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev); 795 796 /* End of list, leave */ 797 if (pdev == NULL) { 798 i5000_printk(KERN_ERR, 799 "'system address,Process Bus' " 800 "device not found:" 801 "vendor 0x%x device 0x%x FUNC 1 " 802 "(broken BIOS?)\n", 803 PCI_VENDOR_ID_INTEL, 804 PCI_DEVICE_ID_INTEL_I5000_DEV16); 805 806 return 1; 807 } 808 809 /* Scan for device 16 func 1 */ 810 if (PCI_FUNC(pdev->devfn) == 1) 811 break; 812 } 813 814 pvt->branchmap_werrors = pdev; 815 816 /* Attempt to 'get' the MCH register we want */ 817 pdev = NULL; 818 while (1) { 819 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 820 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev); 821 822 if (pdev == NULL) { 823 i5000_printk(KERN_ERR, 824 "MC: 'branchmap,control,errors' " 825 "device not found:" 826 "vendor 0x%x device 0x%x Func 2 " 827 "(broken BIOS?)\n", 828 PCI_VENDOR_ID_INTEL, 829 PCI_DEVICE_ID_INTEL_I5000_DEV16); 830 831 pci_dev_put(pvt->branchmap_werrors); 832 return 1; 833 } 834 835 /* Scan for device 16 func 1 */ 836 if (PCI_FUNC(pdev->devfn) == 2) 837 break; 838 } 839 840 pvt->fsb_error_regs = pdev; 841 842 edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s %x:%x\n", 843 pci_name(pvt->system_address), 844 pvt->system_address->vendor, pvt->system_address->device); 845 edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s %x:%x\n", 846 pci_name(pvt->branchmap_werrors), 847 pvt->branchmap_werrors->vendor, 848 pvt->branchmap_werrors->device); 849 edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s %x:%x\n", 850 pci_name(pvt->fsb_error_regs), 851 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device); 852 853 pdev = NULL; 854 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 855 PCI_DEVICE_ID_I5000_BRANCH_0, pdev); 856 857 if (pdev == NULL) { 858 i5000_printk(KERN_ERR, 859 "MC: 'BRANCH 0' device not found:" 860 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n", 861 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0); 862 863 pci_dev_put(pvt->branchmap_werrors); 864 pci_dev_put(pvt->fsb_error_regs); 865 return 1; 866 } 867 868 pvt->branch_0 = pdev; 869 870 /* If this device claims to have more than 2 channels then 871 * fetch Branch 1's information 872 */ 873 if (pvt->maxch >= CHANNELS_PER_BRANCH) { 874 pdev = NULL; 875 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 876 PCI_DEVICE_ID_I5000_BRANCH_1, pdev); 877 878 if (pdev == NULL) { 879 i5000_printk(KERN_ERR, 880 "MC: 'BRANCH 1' device not found:" 881 "vendor 0x%x device 0x%x Func 0 " 882 "(broken BIOS?)\n", 883 PCI_VENDOR_ID_INTEL, 884 PCI_DEVICE_ID_I5000_BRANCH_1); 885 886 pci_dev_put(pvt->branchmap_werrors); 887 pci_dev_put(pvt->fsb_error_regs); 888 pci_dev_put(pvt->branch_0); 889 return 1; 890 } 891 892 pvt->branch_1 = pdev; 893 } 894 895 return 0; 896 } 897 898 /* 899 * i5000_put_devices 'put' all the devices that we have 900 * reserved via 'get' 901 */ 902 static void i5000_put_devices(struct mem_ctl_info *mci) 903 { 904 struct i5000_pvt *pvt; 905 906 pvt = mci->pvt_info; 907 908 pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */ 909 pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */ 910 pci_dev_put(pvt->branch_0); /* DEV 21 */ 911 912 /* Only if more than 2 channels do we release the second branch */ 913 if (pvt->maxch >= CHANNELS_PER_BRANCH) 914 pci_dev_put(pvt->branch_1); /* DEV 22 */ 915 } 916 917 /* 918 * determine_amb_resent 919 * 920 * the information is contained in NUM_MTRS different registers 921 * determineing which of the NUM_MTRS requires knowing 922 * which channel is in question 923 * 924 * 2 branches, each with 2 channels 925 * b0_ambpresent0 for channel '0' 926 * b0_ambpresent1 for channel '1' 927 * b1_ambpresent0 for channel '2' 928 * b1_ambpresent1 for channel '3' 929 */ 930 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel) 931 { 932 int amb_present; 933 934 if (channel < CHANNELS_PER_BRANCH) { 935 if (channel & 0x1) 936 amb_present = pvt->b0_ambpresent1; 937 else 938 amb_present = pvt->b0_ambpresent0; 939 } else { 940 if (channel & 0x1) 941 amb_present = pvt->b1_ambpresent1; 942 else 943 amb_present = pvt->b1_ambpresent0; 944 } 945 946 return amb_present; 947 } 948 949 /* 950 * determine_mtr(pvt, csrow, channel) 951 * 952 * return the proper MTR register as determine by the csrow and channel desired 953 */ 954 static int determine_mtr(struct i5000_pvt *pvt, int slot, int channel) 955 { 956 int mtr; 957 958 if (channel < CHANNELS_PER_BRANCH) 959 mtr = pvt->b0_mtr[slot]; 960 else 961 mtr = pvt->b1_mtr[slot]; 962 963 return mtr; 964 } 965 966 /* 967 */ 968 static void decode_mtr(int slot_row, u16 mtr) 969 { 970 int ans; 971 972 ans = MTR_DIMMS_PRESENT(mtr); 973 974 edac_dbg(2, "\tMTR%d=0x%x: DIMMs are %sPresent\n", 975 slot_row, mtr, ans ? "" : "NOT "); 976 if (!ans) 977 return; 978 979 edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr)); 980 edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr)); 981 edac_dbg(2, "\t\tNUMRANK: %s\n", 982 MTR_DIMM_RANK(mtr) ? "double" : "single"); 983 edac_dbg(2, "\t\tNUMROW: %s\n", 984 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" : 985 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" : 986 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" : 987 "reserved"); 988 edac_dbg(2, "\t\tNUMCOL: %s\n", 989 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" : 990 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" : 991 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" : 992 "reserved"); 993 } 994 995 static void handle_channel(struct i5000_pvt *pvt, int slot, int channel, 996 struct i5000_dimm_info *dinfo) 997 { 998 int mtr; 999 int amb_present_reg; 1000 int addrBits; 1001 1002 mtr = determine_mtr(pvt, slot, channel); 1003 if (MTR_DIMMS_PRESENT(mtr)) { 1004 amb_present_reg = determine_amb_present_reg(pvt, channel); 1005 1006 /* Determine if there is a DIMM present in this DIMM slot */ 1007 if (amb_present_reg) { 1008 dinfo->dual_rank = MTR_DIMM_RANK(mtr); 1009 1010 /* Start with the number of bits for a Bank 1011 * on the DRAM */ 1012 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr); 1013 /* Add the number of ROW bits */ 1014 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr); 1015 /* add the number of COLUMN bits */ 1016 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr); 1017 1018 /* Dual-rank memories have twice the size */ 1019 if (dinfo->dual_rank) 1020 addrBits++; 1021 1022 addrBits += 6; /* add 64 bits per DIMM */ 1023 addrBits -= 20; /* divide by 2^^20 */ 1024 addrBits -= 3; /* 8 bits per bytes */ 1025 1026 dinfo->megabytes = 1 << addrBits; 1027 } 1028 } 1029 } 1030 1031 /* 1032 * calculate_dimm_size 1033 * 1034 * also will output a DIMM matrix map, if debug is enabled, for viewing 1035 * how the DIMMs are populated 1036 */ 1037 static void calculate_dimm_size(struct i5000_pvt *pvt) 1038 { 1039 struct i5000_dimm_info *dinfo; 1040 int slot, channel, branch; 1041 char *p, *mem_buffer; 1042 int space, n; 1043 1044 /* ================= Generate some debug output ================= */ 1045 space = PAGE_SIZE; 1046 mem_buffer = p = kmalloc(space, GFP_KERNEL); 1047 if (p == NULL) { 1048 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n", 1049 __FILE__, __func__); 1050 return; 1051 } 1052 1053 /* Scan all the actual slots 1054 * and calculate the information for each DIMM 1055 * Start with the highest slot first, to display it first 1056 * and work toward the 0th slot 1057 */ 1058 for (slot = pvt->maxdimmperch - 1; slot >= 0; slot--) { 1059 1060 /* on an odd slot, first output a 'boundary' marker, 1061 * then reset the message buffer */ 1062 if (slot & 0x1) { 1063 n = snprintf(p, space, "--------------------------" 1064 "--------------------------------"); 1065 p += n; 1066 space -= n; 1067 edac_dbg(2, "%s\n", mem_buffer); 1068 p = mem_buffer; 1069 space = PAGE_SIZE; 1070 } 1071 n = snprintf(p, space, "slot %2d ", slot); 1072 p += n; 1073 space -= n; 1074 1075 for (channel = 0; channel < pvt->maxch; channel++) { 1076 dinfo = &pvt->dimm_info[slot][channel]; 1077 handle_channel(pvt, slot, channel, dinfo); 1078 if (dinfo->megabytes) 1079 n = snprintf(p, space, "%4d MB %dR| ", 1080 dinfo->megabytes, dinfo->dual_rank + 1); 1081 else 1082 n = snprintf(p, space, "%4d MB | ", 0); 1083 p += n; 1084 space -= n; 1085 } 1086 p += n; 1087 space -= n; 1088 edac_dbg(2, "%s\n", mem_buffer); 1089 p = mem_buffer; 1090 space = PAGE_SIZE; 1091 } 1092 1093 /* Output the last bottom 'boundary' marker */ 1094 n = snprintf(p, space, "--------------------------" 1095 "--------------------------------"); 1096 p += n; 1097 space -= n; 1098 edac_dbg(2, "%s\n", mem_buffer); 1099 p = mem_buffer; 1100 space = PAGE_SIZE; 1101 1102 /* now output the 'channel' labels */ 1103 n = snprintf(p, space, " "); 1104 p += n; 1105 space -= n; 1106 for (channel = 0; channel < pvt->maxch; channel++) { 1107 n = snprintf(p, space, "channel %d | ", channel); 1108 p += n; 1109 space -= n; 1110 } 1111 edac_dbg(2, "%s\n", mem_buffer); 1112 p = mem_buffer; 1113 space = PAGE_SIZE; 1114 1115 n = snprintf(p, space, " "); 1116 p += n; 1117 space -= n; 1118 for (branch = 0; branch < MAX_BRANCHES; branch++) { 1119 n = snprintf(p, space, " branch %d | ", branch); 1120 p += n; 1121 space -= n; 1122 } 1123 1124 /* output the last message and free buffer */ 1125 edac_dbg(2, "%s\n", mem_buffer); 1126 kfree(mem_buffer); 1127 } 1128 1129 /* 1130 * i5000_get_mc_regs read in the necessary registers and 1131 * cache locally 1132 * 1133 * Fills in the private data members 1134 */ 1135 static void i5000_get_mc_regs(struct mem_ctl_info *mci) 1136 { 1137 struct i5000_pvt *pvt; 1138 u32 actual_tolm; 1139 u16 limit; 1140 int slot_row; 1141 int way0, way1; 1142 1143 pvt = mci->pvt_info; 1144 1145 pci_read_config_dword(pvt->system_address, AMBASE, 1146 &pvt->u.ambase_bottom); 1147 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32), 1148 &pvt->u.ambase_top); 1149 1150 edac_dbg(2, "AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n", 1151 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch); 1152 1153 /* Get the Branch Map regs */ 1154 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm); 1155 pvt->tolm >>= 12; 1156 edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n", 1157 pvt->tolm, pvt->tolm); 1158 1159 actual_tolm = pvt->tolm << 28; 1160 edac_dbg(2, "Actual TOLM byte addr=%u (0x%x)\n", 1161 actual_tolm, actual_tolm); 1162 1163 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0); 1164 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1); 1165 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2); 1166 1167 /* Get the MIR[0-2] regs */ 1168 limit = (pvt->mir0 >> 4) & 0x0FFF; 1169 way0 = pvt->mir0 & 0x1; 1170 way1 = pvt->mir0 & 0x2; 1171 edac_dbg(2, "MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", 1172 limit, way1, way0); 1173 limit = (pvt->mir1 >> 4) & 0x0FFF; 1174 way0 = pvt->mir1 & 0x1; 1175 way1 = pvt->mir1 & 0x2; 1176 edac_dbg(2, "MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", 1177 limit, way1, way0); 1178 limit = (pvt->mir2 >> 4) & 0x0FFF; 1179 way0 = pvt->mir2 & 0x1; 1180 way1 = pvt->mir2 & 0x2; 1181 edac_dbg(2, "MIR2: limit= 0x%x WAY1= %u WAY0= %x\n", 1182 limit, way1, way0); 1183 1184 /* Get the MTR[0-3] regs */ 1185 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) { 1186 int where = MTR0 + (slot_row * sizeof(u32)); 1187 1188 pci_read_config_word(pvt->branch_0, where, 1189 &pvt->b0_mtr[slot_row]); 1190 1191 edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n", 1192 slot_row, where, pvt->b0_mtr[slot_row]); 1193 1194 if (pvt->maxch >= CHANNELS_PER_BRANCH) { 1195 pci_read_config_word(pvt->branch_1, where, 1196 &pvt->b1_mtr[slot_row]); 1197 edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n", 1198 slot_row, where, pvt->b1_mtr[slot_row]); 1199 } else { 1200 pvt->b1_mtr[slot_row] = 0; 1201 } 1202 } 1203 1204 /* Read and dump branch 0's MTRs */ 1205 edac_dbg(2, "Memory Technology Registers:\n"); 1206 edac_dbg(2, " Branch 0:\n"); 1207 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) { 1208 decode_mtr(slot_row, pvt->b0_mtr[slot_row]); 1209 } 1210 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0, 1211 &pvt->b0_ambpresent0); 1212 edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0); 1213 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1, 1214 &pvt->b0_ambpresent1); 1215 edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1); 1216 1217 /* Only if we have 2 branches (4 channels) */ 1218 if (pvt->maxch < CHANNELS_PER_BRANCH) { 1219 pvt->b1_ambpresent0 = 0; 1220 pvt->b1_ambpresent1 = 0; 1221 } else { 1222 /* Read and dump branch 1's MTRs */ 1223 edac_dbg(2, " Branch 1:\n"); 1224 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) { 1225 decode_mtr(slot_row, pvt->b1_mtr[slot_row]); 1226 } 1227 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0, 1228 &pvt->b1_ambpresent0); 1229 edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n", 1230 pvt->b1_ambpresent0); 1231 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1, 1232 &pvt->b1_ambpresent1); 1233 edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n", 1234 pvt->b1_ambpresent1); 1235 } 1236 1237 /* Go and determine the size of each DIMM and place in an 1238 * orderly matrix */ 1239 calculate_dimm_size(pvt); 1240 } 1241 1242 /* 1243 * i5000_init_csrows Initialize the 'csrows' table within 1244 * the mci control structure with the 1245 * addressing of memory. 1246 * 1247 * return: 1248 * 0 success 1249 * 1 no actual memory found on this MC 1250 */ 1251 static int i5000_init_csrows(struct mem_ctl_info *mci) 1252 { 1253 struct i5000_pvt *pvt; 1254 struct dimm_info *dimm; 1255 int empty; 1256 int max_csrows; 1257 int mtr; 1258 int csrow_megs; 1259 int channel; 1260 int slot; 1261 1262 pvt = mci->pvt_info; 1263 max_csrows = pvt->maxdimmperch * 2; 1264 1265 empty = 1; /* Assume NO memory */ 1266 1267 /* 1268 * FIXME: The memory layout used to map slot/channel into the 1269 * real memory architecture is weird: branch+slot are "csrows" 1270 * and channel is channel. That required an extra array (dimm_info) 1271 * to map the dimms. A good cleanup would be to remove this array, 1272 * and do a loop here with branch, channel, slot 1273 */ 1274 for (slot = 0; slot < max_csrows; slot++) { 1275 for (channel = 0; channel < pvt->maxch; channel++) { 1276 1277 mtr = determine_mtr(pvt, slot, channel); 1278 1279 if (!MTR_DIMMS_PRESENT(mtr)) 1280 continue; 1281 1282 dimm = edac_get_dimm(mci, channel / MAX_BRANCHES, 1283 channel % MAX_BRANCHES, slot); 1284 1285 csrow_megs = pvt->dimm_info[slot][channel].megabytes; 1286 dimm->grain = 8; 1287 1288 /* Assume DDR2 for now */ 1289 dimm->mtype = MEM_FB_DDR2; 1290 1291 /* ask what device type on this row */ 1292 if (MTR_DRAM_WIDTH(mtr) == 8) 1293 dimm->dtype = DEV_X8; 1294 else 1295 dimm->dtype = DEV_X4; 1296 1297 dimm->edac_mode = EDAC_S8ECD8ED; 1298 dimm->nr_pages = csrow_megs << 8; 1299 } 1300 1301 empty = 0; 1302 } 1303 1304 return empty; 1305 } 1306 1307 /* 1308 * i5000_set_error_reporting 1309 * Turn on/off the memory reporting features of the hardware 1310 */ 1311 static void i5000_set_error_reporting(struct mem_ctl_info *mci, bool enable) 1312 { 1313 struct i5000_pvt *pvt; 1314 u32 fbd_error_mask; 1315 1316 pvt = mci->pvt_info; 1317 1318 /* Read the FBD Error Mask Register */ 1319 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD, 1320 &fbd_error_mask); 1321 1322 /* Enable with 0, disable with 1 */ 1323 if (enable) 1324 fbd_error_mask &= ~(ENABLE_EMASK_ALL); 1325 else 1326 fbd_error_mask |= ENABLE_EMASK_ALL; 1327 1328 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD, 1329 fbd_error_mask); 1330 } 1331 1332 /* 1333 * i5000_get_dimm_and_channel_counts(pdev, &nr_csrows, &num_channels) 1334 * 1335 * ask the device how many channels are present and how many CSROWS 1336 * as well 1337 */ 1338 static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev, 1339 int *num_dimms_per_channel, 1340 int *num_channels) 1341 { 1342 u8 value; 1343 1344 /* Need to retrieve just how many channels and dimms per channel are 1345 * supported on this memory controller 1346 */ 1347 pci_read_config_byte(pdev, MAXDIMMPERCH, &value); 1348 *num_dimms_per_channel = (int)value; 1349 1350 pci_read_config_byte(pdev, MAXCH, &value); 1351 *num_channels = (int)value; 1352 } 1353 1354 /* 1355 * i5000_probe1 Probe for ONE instance of device to see if it is 1356 * present. 1357 * return: 1358 * 0 for FOUND a device 1359 * < 0 for error code 1360 */ 1361 static int i5000_probe1(struct pci_dev *pdev, int dev_idx) 1362 { 1363 struct mem_ctl_info *mci; 1364 struct edac_mc_layer layers[3]; 1365 struct i5000_pvt *pvt; 1366 int num_channels; 1367 int num_dimms_per_channel; 1368 1369 edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n", 1370 pdev->bus->number, 1371 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 1372 1373 /* We only are looking for func 0 of the set */ 1374 if (PCI_FUNC(pdev->devfn) != 0) 1375 return -ENODEV; 1376 1377 /* Ask the devices for the number of CSROWS and CHANNELS so 1378 * that we can calculate the memory resources, etc 1379 * 1380 * The Chipset will report what it can handle which will be greater 1381 * or equal to what the motherboard manufacturer will implement. 1382 * 1383 * As we don't have a motherboard identification routine to determine 1384 * actual number of slots/dimms per channel, we thus utilize the 1385 * resource as specified by the chipset. Thus, we might have 1386 * have more DIMMs per channel than actually on the mobo, but this 1387 * allows the driver to support up to the chipset max, without 1388 * some fancy mobo determination. 1389 */ 1390 i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel, 1391 &num_channels); 1392 1393 edac_dbg(0, "MC: Number of Branches=2 Channels= %d DIMMS= %d\n", 1394 num_channels, num_dimms_per_channel); 1395 1396 /* allocate a new MC control structure */ 1397 1398 layers[0].type = EDAC_MC_LAYER_BRANCH; 1399 layers[0].size = MAX_BRANCHES; 1400 layers[0].is_virt_csrow = false; 1401 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1402 layers[1].size = num_channels / MAX_BRANCHES; 1403 layers[1].is_virt_csrow = false; 1404 layers[2].type = EDAC_MC_LAYER_SLOT; 1405 layers[2].size = num_dimms_per_channel; 1406 layers[2].is_virt_csrow = true; 1407 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); 1408 if (mci == NULL) 1409 return -ENOMEM; 1410 1411 edac_dbg(0, "MC: mci = %p\n", mci); 1412 1413 mci->pdev = &pdev->dev; /* record ptr to the generic device */ 1414 1415 pvt = mci->pvt_info; 1416 pvt->system_address = pdev; /* Record this device in our private */ 1417 pvt->maxch = num_channels; 1418 pvt->maxdimmperch = num_dimms_per_channel; 1419 1420 /* 'get' the pci devices we want to reserve for our use */ 1421 if (i5000_get_devices(mci, dev_idx)) 1422 goto fail0; 1423 1424 /* Time to get serious */ 1425 i5000_get_mc_regs(mci); /* retrieve the hardware registers */ 1426 1427 mci->mc_idx = 0; 1428 mci->mtype_cap = MEM_FLAG_FB_DDR2; 1429 mci->edac_ctl_cap = EDAC_FLAG_NONE; 1430 mci->edac_cap = EDAC_FLAG_NONE; 1431 mci->mod_name = "i5000_edac.c"; 1432 mci->ctl_name = i5000_devs[dev_idx].ctl_name; 1433 mci->dev_name = pci_name(pdev); 1434 mci->ctl_page_to_phys = NULL; 1435 1436 /* Set the function pointer to an actual operation function */ 1437 mci->edac_check = i5000_check_error; 1438 1439 /* initialize the MC control structure 'csrows' table 1440 * with the mapping and control information */ 1441 if (i5000_init_csrows(mci)) { 1442 edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5000_init_csrows() returned nonzero value\n"); 1443 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */ 1444 pvt->enabled_error_reporting = false; 1445 } else { 1446 edac_dbg(1, "MC: Enable error reporting now\n"); 1447 i5000_set_error_reporting(mci, true); 1448 pvt->enabled_error_reporting = true; 1449 } 1450 1451 /* add this new MC control structure to EDAC's list of MCs */ 1452 if (edac_mc_add_mc(mci)) { 1453 edac_dbg(0, "MC: failed edac_mc_add_mc()\n"); 1454 /* Disable error reporting if we previously enabled it */ 1455 if (pvt->enabled_error_reporting) 1456 i5000_set_error_reporting(mci, false); 1457 goto fail1; 1458 } 1459 1460 i5000_clear_error(mci); 1461 1462 /* allocating generic PCI control info */ 1463 i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); 1464 if (!i5000_pci) { 1465 printk(KERN_WARNING 1466 "%s(): Unable to create PCI control\n", 1467 __func__); 1468 printk(KERN_WARNING 1469 "%s(): PCI error report via EDAC not setup\n", 1470 __func__); 1471 } 1472 1473 return 0; 1474 1475 /* Error exit unwinding stack */ 1476 fail1: 1477 1478 i5000_put_devices(mci); 1479 1480 fail0: 1481 edac_mc_free(mci); 1482 return -ENODEV; 1483 } 1484 1485 /* 1486 * i5000_init_one constructor for one instance of device 1487 * 1488 * returns: 1489 * negative on error 1490 * count (>= 0) 1491 */ 1492 static int i5000_init_one(struct pci_dev *pdev, const struct pci_device_id *id) 1493 { 1494 int rc; 1495 1496 edac_dbg(0, "MC:\n"); 1497 1498 /* wake up device */ 1499 rc = pci_enable_device(pdev); 1500 if (rc) 1501 return rc; 1502 1503 /* now probe and enable the device */ 1504 return i5000_probe1(pdev, id->driver_data); 1505 } 1506 1507 /* 1508 * i5000_remove_one destructor for one instance of device 1509 * 1510 */ 1511 static void i5000_remove_one(struct pci_dev *pdev) 1512 { 1513 struct mem_ctl_info *mci; 1514 struct i5000_pvt *pvt; 1515 1516 edac_dbg(0, "\n"); 1517 1518 if (i5000_pci) 1519 edac_pci_release_generic_ctl(i5000_pci); 1520 1521 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) 1522 return; 1523 1524 pvt = mci->pvt_info; 1525 1526 /* Disable error reporting on teardown */ 1527 if (pvt->enabled_error_reporting) 1528 i5000_set_error_reporting(mci, false); 1529 1530 /* retrieve references to resources, and free those resources */ 1531 i5000_put_devices(mci); 1532 edac_mc_free(mci); 1533 } 1534 1535 /* 1536 * pci_device_id table for which devices we are looking for 1537 * 1538 * The "E500P" device is the first device supported. 1539 */ 1540 static const struct pci_device_id i5000_pci_tbl[] = { 1541 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16), 1542 .driver_data = I5000P}, 1543 1544 {0,} /* 0 terminated list. */ 1545 }; 1546 1547 MODULE_DEVICE_TABLE(pci, i5000_pci_tbl); 1548 1549 /* 1550 * i5000_driver pci_driver structure for this module 1551 * 1552 */ 1553 static struct pci_driver i5000_driver = { 1554 .name = KBUILD_BASENAME, 1555 .probe = i5000_init_one, 1556 .remove = i5000_remove_one, 1557 .id_table = i5000_pci_tbl, 1558 }; 1559 1560 /* 1561 * i5000_init Module entry function 1562 * Try to initialize this module for its devices 1563 */ 1564 static int __init i5000_init(void) 1565 { 1566 int pci_rc; 1567 1568 edac_dbg(2, "MC:\n"); 1569 1570 /* Ensure that the OPSTATE is set correctly for POLL or NMI */ 1571 opstate_init(); 1572 1573 pci_rc = pci_register_driver(&i5000_driver); 1574 1575 return (pci_rc < 0) ? pci_rc : 0; 1576 } 1577 1578 /* 1579 * i5000_exit() Module exit function 1580 * Unregister the driver 1581 */ 1582 static void __exit i5000_exit(void) 1583 { 1584 edac_dbg(2, "MC:\n"); 1585 pci_unregister_driver(&i5000_driver); 1586 } 1587 1588 module_init(i5000_init); 1589 module_exit(i5000_exit); 1590 1591 MODULE_LICENSE("GPL"); 1592 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>"); 1593 MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - " I5000_REVISION); 1594 1595 module_param(edac_op_state, int, 0444); 1596 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); 1597 module_param(misc_messages, int, 0444); 1598 MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages"); 1599