1 /* 2 * MC kernel module 3 * (C) 2003 Linux Networx (http://lnxi.com) 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * Written by Thayne Harbaugh 8 * Based on work by Dan Hollis <goemon at anime dot net> and others. 9 * http://www.anime.net/~goemon/linux-ecc/ 10 * 11 * NMI handling support added by 12 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com> 13 * 14 * $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $ 15 * 16 */ 17 18 #ifndef _EDAC_MC_H_ 19 #define _EDAC_MC_H_ 20 21 #include <linux/config.h> 22 #include <linux/kernel.h> 23 #include <linux/types.h> 24 #include <linux/module.h> 25 #include <linux/spinlock.h> 26 #include <linux/smp.h> 27 #include <linux/pci.h> 28 #include <linux/time.h> 29 #include <linux/nmi.h> 30 #include <linux/rcupdate.h> 31 #include <linux/completion.h> 32 #include <linux/kobject.h> 33 34 #define EDAC_MC_LABEL_LEN 31 35 #define MC_PROC_NAME_MAX_LEN 7 36 37 #if PAGE_SHIFT < 20 38 #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) ) 39 #else /* PAGE_SHIFT > 20 */ 40 #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) ) 41 #endif 42 43 #define edac_printk(level, prefix, fmt, arg...) \ 44 printk(level "EDAC " prefix ": " fmt, ##arg) 45 46 #define edac_mc_printk(mci, level, fmt, arg...) \ 47 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg) 48 49 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \ 50 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg) 51 52 /* prefixes for edac_printk() and edac_mc_printk() */ 53 #define EDAC_MC "MC" 54 #define EDAC_PCI "PCI" 55 #define EDAC_DEBUG "DEBUG" 56 57 #ifdef CONFIG_EDAC_DEBUG 58 extern int edac_debug_level; 59 60 #define edac_debug_printk(level, fmt, arg...) \ 61 do { \ 62 if (level <= edac_debug_level) \ 63 edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \ 64 } while(0) 65 66 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ ) 67 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ ) 68 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ ) 69 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ ) 70 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ ) 71 72 #else /* !CONFIG_EDAC_DEBUG */ 73 74 #define debugf0( ... ) 75 #define debugf1( ... ) 76 #define debugf2( ... ) 77 #define debugf3( ... ) 78 #define debugf4( ... ) 79 80 #endif /* !CONFIG_EDAC_DEBUG */ 81 82 #define edac_xstr(s) edac_str(s) 83 #define edac_str(s) #s 84 #define EDAC_MOD_STR edac_xstr(KBUILD_BASENAME) 85 86 #define BIT(x) (1 << (x)) 87 88 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \ 89 PCI_DEVICE_ID_ ## vend ## _ ## dev 90 91 /* memory devices */ 92 enum dev_type { 93 DEV_UNKNOWN = 0, 94 DEV_X1, 95 DEV_X2, 96 DEV_X4, 97 DEV_X8, 98 DEV_X16, 99 DEV_X32, /* Do these parts exist? */ 100 DEV_X64 /* Do these parts exist? */ 101 }; 102 103 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) 104 #define DEV_FLAG_X1 BIT(DEV_X1) 105 #define DEV_FLAG_X2 BIT(DEV_X2) 106 #define DEV_FLAG_X4 BIT(DEV_X4) 107 #define DEV_FLAG_X8 BIT(DEV_X8) 108 #define DEV_FLAG_X16 BIT(DEV_X16) 109 #define DEV_FLAG_X32 BIT(DEV_X32) 110 #define DEV_FLAG_X64 BIT(DEV_X64) 111 112 /* memory types */ 113 enum mem_type { 114 MEM_EMPTY = 0, /* Empty csrow */ 115 MEM_RESERVED, /* Reserved csrow type */ 116 MEM_UNKNOWN, /* Unknown csrow type */ 117 MEM_FPM, /* Fast page mode */ 118 MEM_EDO, /* Extended data out */ 119 MEM_BEDO, /* Burst Extended data out */ 120 MEM_SDR, /* Single data rate SDRAM */ 121 MEM_RDR, /* Registered single data rate SDRAM */ 122 MEM_DDR, /* Double data rate SDRAM */ 123 MEM_RDDR, /* Registered Double data rate SDRAM */ 124 MEM_RMBS /* Rambus DRAM */ 125 }; 126 127 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) 128 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) 129 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) 130 #define MEM_FLAG_FPM BIT(MEM_FPM) 131 #define MEM_FLAG_EDO BIT(MEM_EDO) 132 #define MEM_FLAG_BEDO BIT(MEM_BEDO) 133 #define MEM_FLAG_SDR BIT(MEM_SDR) 134 #define MEM_FLAG_RDR BIT(MEM_RDR) 135 #define MEM_FLAG_DDR BIT(MEM_DDR) 136 #define MEM_FLAG_RDDR BIT(MEM_RDDR) 137 #define MEM_FLAG_RMBS BIT(MEM_RMBS) 138 139 /* chipset Error Detection and Correction capabilities and mode */ 140 enum edac_type { 141 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */ 142 EDAC_NONE, /* Doesnt support ECC */ 143 EDAC_RESERVED, /* Reserved ECC type */ 144 EDAC_PARITY, /* Detects parity errors */ 145 EDAC_EC, /* Error Checking - no correction */ 146 EDAC_SECDED, /* Single bit error correction, Double detection */ 147 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */ 148 EDAC_S4ECD4ED, /* Chipkill x4 devices */ 149 EDAC_S8ECD8ED, /* Chipkill x8 devices */ 150 EDAC_S16ECD16ED, /* Chipkill x16 devices */ 151 }; 152 153 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) 154 #define EDAC_FLAG_NONE BIT(EDAC_NONE) 155 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) 156 #define EDAC_FLAG_EC BIT(EDAC_EC) 157 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) 158 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) 159 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) 160 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) 161 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) 162 163 /* scrubbing capabilities */ 164 enum scrub_type { 165 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */ 166 SCRUB_NONE, /* No scrubber */ 167 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */ 168 SCRUB_SW_SRC, /* Software scrub only errors */ 169 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */ 170 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */ 171 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */ 172 SCRUB_HW_SRC, /* Hardware scrub only errors */ 173 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */ 174 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */ 175 }; 176 177 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) 178 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC_CORR) 179 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC_CORR) 180 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) 181 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) 182 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC_CORR) 183 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC_CORR) 184 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) 185 186 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ 187 188 /* 189 * There are several things to be aware of that aren't at all obvious: 190 * 191 * 192 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. 193 * 194 * These are some of the many terms that are thrown about that don't always 195 * mean what people think they mean (Inconceivable!). In the interest of 196 * creating a common ground for discussion, terms and their definitions 197 * will be established. 198 * 199 * Memory devices: The individual chip on a memory stick. These devices 200 * commonly output 4 and 8 bits each. Grouping several 201 * of these in parallel provides 64 bits which is common 202 * for a memory stick. 203 * 204 * Memory Stick: A printed circuit board that agregates multiple 205 * memory devices in parallel. This is the atomic 206 * memory component that is purchaseable by Joe consumer 207 * and loaded into a memory socket. 208 * 209 * Socket: A physical connector on the motherboard that accepts 210 * a single memory stick. 211 * 212 * Channel: Set of memory devices on a memory stick that must be 213 * grouped in parallel with one or more additional 214 * channels from other memory sticks. This parallel 215 * grouping of the output from multiple channels are 216 * necessary for the smallest granularity of memory access. 217 * Some memory controllers are capable of single channel - 218 * which means that memory sticks can be loaded 219 * individually. Other memory controllers are only 220 * capable of dual channel - which means that memory 221 * sticks must be loaded as pairs (see "socket set"). 222 * 223 * Chip-select row: All of the memory devices that are selected together. 224 * for a single, minimum grain of memory access. 225 * This selects all of the parallel memory devices across 226 * all of the parallel channels. Common chip-select rows 227 * for single channel are 64 bits, for dual channel 128 228 * bits. 229 * 230 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory. 231 * Motherboards commonly drive two chip-select pins to 232 * a memory stick. A single-ranked stick, will occupy 233 * only one of those rows. The other will be unused. 234 * 235 * Double-Ranked stick: A double-ranked stick has two chip-select rows which 236 * access different sets of memory devices. The two 237 * rows cannot be accessed concurrently. 238 * 239 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. 240 * A double-sided stick has two chip-select rows which 241 * access different sets of memory devices. The two 242 * rows cannot be accessed concurrently. "Double-sided" 243 * is irrespective of the memory devices being mounted 244 * on both sides of the memory stick. 245 * 246 * Socket set: All of the memory sticks that are required for for 247 * a single memory access or all of the memory sticks 248 * spanned by a chip-select row. A single socket set 249 * has two chip-select rows and if double-sided sticks 250 * are used these will occupy those chip-select rows. 251 * 252 * Bank: This term is avoided because it is unclear when 253 * needing to distinguish between chip-select rows and 254 * socket sets. 255 * 256 * Controller pages: 257 * 258 * Physical pages: 259 * 260 * Virtual pages: 261 * 262 * 263 * STRUCTURE ORGANIZATION AND CHOICES 264 * 265 * 266 * 267 * PS - I enjoyed writing all that about as much as you enjoyed reading it. 268 */ 269 270 struct channel_info { 271 int chan_idx; /* channel index */ 272 u32 ce_count; /* Correctable Errors for this CHANNEL */ 273 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ 274 struct csrow_info *csrow; /* the parent */ 275 }; 276 277 struct csrow_info { 278 unsigned long first_page; /* first page number in dimm */ 279 unsigned long last_page; /* last page number in dimm */ 280 unsigned long page_mask; /* used for interleaving - 281 * 0UL for non intlv 282 */ 283 u32 nr_pages; /* number of pages in csrow */ 284 u32 grain; /* granularity of reported error in bytes */ 285 int csrow_idx; /* the chip-select row */ 286 enum dev_type dtype; /* memory device type */ 287 u32 ue_count; /* Uncorrectable Errors for this csrow */ 288 u32 ce_count; /* Correctable Errors for this csrow */ 289 enum mem_type mtype; /* memory csrow type */ 290 enum edac_type edac_mode; /* EDAC mode for this csrow */ 291 struct mem_ctl_info *mci; /* the parent */ 292 293 struct kobject kobj; /* sysfs kobject for this csrow */ 294 struct completion kobj_complete; 295 296 /* FIXME the number of CHANNELs might need to become dynamic */ 297 u32 nr_channels; 298 struct channel_info *channels; 299 }; 300 301 struct mem_ctl_info { 302 struct list_head link; /* for global list of mem_ctl_info structs */ 303 unsigned long mtype_cap; /* memory types supported by mc */ 304 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ 305 unsigned long edac_cap; /* configuration capabilities - this is 306 * closely related to edac_ctl_cap. The 307 * difference is that the controller may be 308 * capable of s4ecd4ed which would be listed 309 * in edac_ctl_cap, but if channels aren't 310 * capable of s4ecd4ed then the edac_cap would 311 * not have that capability. 312 */ 313 unsigned long scrub_cap; /* chipset scrub capabilities */ 314 enum scrub_type scrub_mode; /* current scrub mode */ 315 316 /* pointer to edac checking routine */ 317 void (*edac_check) (struct mem_ctl_info * mci); 318 /* 319 * Remaps memory pages: controller pages to physical pages. 320 * For most MC's, this will be NULL. 321 */ 322 /* FIXME - why not send the phys page to begin with? */ 323 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, 324 unsigned long page); 325 int mc_idx; 326 int nr_csrows; 327 struct csrow_info *csrows; 328 /* 329 * FIXME - what about controllers on other busses? - IDs must be 330 * unique. pdev pointer should be sufficiently unique, but 331 * BUS:SLOT.FUNC numbers may not be unique. 332 */ 333 struct pci_dev *pdev; 334 const char *mod_name; 335 const char *mod_ver; 336 const char *ctl_name; 337 char proc_name[MC_PROC_NAME_MAX_LEN + 1]; 338 void *pvt_info; 339 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */ 340 u32 ce_noinfo_count; /* Correctable Errors w/o info */ 341 u32 ue_count; /* Total Uncorrectable Errors for this MC */ 342 u32 ce_count; /* Total Correctable Errors for this MC */ 343 unsigned long start_time; /* mci load start time (in jiffies) */ 344 345 /* this stuff is for safe removal of mc devices from global list while 346 * NMI handlers may be traversing list 347 */ 348 struct rcu_head rcu; 349 struct completion complete; 350 351 /* edac sysfs device control */ 352 struct kobject edac_mci_kobj; 353 struct completion kobj_complete; 354 }; 355 356 /* write all or some bits in a byte-register*/ 357 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value, 358 u8 mask) 359 { 360 if (mask != 0xff) { 361 u8 buf; 362 363 pci_read_config_byte(pdev, offset, &buf); 364 value &= mask; 365 buf &= ~mask; 366 value |= buf; 367 } 368 369 pci_write_config_byte(pdev, offset, value); 370 } 371 372 /* write all or some bits in a word-register*/ 373 static inline void pci_write_bits16(struct pci_dev *pdev, int offset, 374 u16 value, u16 mask) 375 { 376 if (mask != 0xffff) { 377 u16 buf; 378 379 pci_read_config_word(pdev, offset, &buf); 380 value &= mask; 381 buf &= ~mask; 382 value |= buf; 383 } 384 385 pci_write_config_word(pdev, offset, value); 386 } 387 388 /* write all or some bits in a dword-register*/ 389 static inline void pci_write_bits32(struct pci_dev *pdev, int offset, 390 u32 value, u32 mask) 391 { 392 if (mask != 0xffff) { 393 u32 buf; 394 395 pci_read_config_dword(pdev, offset, &buf); 396 value &= mask; 397 buf &= ~mask; 398 value |= buf; 399 } 400 401 pci_write_config_dword(pdev, offset, value); 402 } 403 404 #ifdef CONFIG_EDAC_DEBUG 405 void edac_mc_dump_channel(struct channel_info *chan); 406 void edac_mc_dump_mci(struct mem_ctl_info *mci); 407 void edac_mc_dump_csrow(struct csrow_info *csrow); 408 #endif /* CONFIG_EDAC_DEBUG */ 409 410 extern int edac_mc_add_mc(struct mem_ctl_info *mci); 411 extern struct mem_ctl_info * edac_mc_del_mc(struct pci_dev *pdev); 412 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, 413 unsigned long page); 414 extern void edac_mc_scrub_block(unsigned long page, unsigned long offset, 415 u32 size); 416 417 /* 418 * The no info errors are used when error overflows are reported. 419 * There are a limited number of error logging registers that can 420 * be exausted. When all registers are exhausted and an additional 421 * error occurs then an error overflow register records that an 422 * error occured and the type of error, but doesn't have any 423 * further information. The ce/ue versions make for cleaner 424 * reporting logic and function interface - reduces conditional 425 * statement clutter and extra function arguments. 426 */ 427 extern void edac_mc_handle_ce(struct mem_ctl_info *mci, 428 unsigned long page_frame_number, unsigned long offset_in_page, 429 unsigned long syndrome, int row, int channel, 430 const char *msg); 431 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci, 432 const char *msg); 433 extern void edac_mc_handle_ue(struct mem_ctl_info *mci, 434 unsigned long page_frame_number, unsigned long offset_in_page, 435 int row, const char *msg); 436 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci, 437 const char *msg); 438 439 /* 440 * This kmalloc's and initializes all the structures. 441 * Can't be used if all structures don't have the same lifetime. 442 */ 443 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows, 444 unsigned nr_chans); 445 446 /* Free an mc previously allocated by edac_mc_alloc() */ 447 extern void edac_mc_free(struct mem_ctl_info *mci); 448 449 #endif /* _EDAC_MC_H_ */ 450