1 /* 2 * MC kernel module 3 * (C) 2003 Linux Networx (http://lnxi.com) 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * Written by Thayne Harbaugh 8 * Based on work by Dan Hollis <goemon at anime dot net> and others. 9 * http://www.anime.net/~goemon/linux-ecc/ 10 * 11 * NMI handling support added by 12 * Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com> 13 * 14 * $Id: edac_mc.h,v 1.4.2.10 2005/10/05 00:43:44 dsp_llnl Exp $ 15 * 16 */ 17 18 #ifndef _EDAC_MC_H_ 19 #define _EDAC_MC_H_ 20 21 #include <linux/kernel.h> 22 #include <linux/types.h> 23 #include <linux/module.h> 24 #include <linux/spinlock.h> 25 #include <linux/smp.h> 26 #include <linux/pci.h> 27 #include <linux/time.h> 28 #include <linux/nmi.h> 29 #include <linux/rcupdate.h> 30 #include <linux/completion.h> 31 #include <linux/kobject.h> 32 #include <linux/platform_device.h> 33 34 #define EDAC_MC_LABEL_LEN 31 35 #define MC_PROC_NAME_MAX_LEN 7 36 37 #if PAGE_SHIFT < 20 38 #define PAGES_TO_MiB( pages ) ( ( pages ) >> ( 20 - PAGE_SHIFT ) ) 39 #else /* PAGE_SHIFT > 20 */ 40 #define PAGES_TO_MiB( pages ) ( ( pages ) << ( PAGE_SHIFT - 20 ) ) 41 #endif 42 43 #define edac_printk(level, prefix, fmt, arg...) \ 44 printk(level "EDAC " prefix ": " fmt, ##arg) 45 46 #define edac_mc_printk(mci, level, fmt, arg...) \ 47 printk(level "EDAC MC%d: " fmt, mci->mc_idx, ##arg) 48 49 #define edac_mc_chipset_printk(mci, level, prefix, fmt, arg...) \ 50 printk(level "EDAC " prefix " MC%d: " fmt, mci->mc_idx, ##arg) 51 52 /* prefixes for edac_printk() and edac_mc_printk() */ 53 #define EDAC_MC "MC" 54 #define EDAC_PCI "PCI" 55 #define EDAC_DEBUG "DEBUG" 56 57 #ifdef CONFIG_EDAC_DEBUG 58 extern int edac_debug_level; 59 60 #define edac_debug_printk(level, fmt, arg...) \ 61 do { \ 62 if (level <= edac_debug_level) \ 63 edac_printk(KERN_DEBUG, EDAC_DEBUG, fmt, ##arg); \ 64 } while(0) 65 66 #define debugf0( ... ) edac_debug_printk(0, __VA_ARGS__ ) 67 #define debugf1( ... ) edac_debug_printk(1, __VA_ARGS__ ) 68 #define debugf2( ... ) edac_debug_printk(2, __VA_ARGS__ ) 69 #define debugf3( ... ) edac_debug_printk(3, __VA_ARGS__ ) 70 #define debugf4( ... ) edac_debug_printk(4, __VA_ARGS__ ) 71 72 #else /* !CONFIG_EDAC_DEBUG */ 73 74 #define debugf0( ... ) 75 #define debugf1( ... ) 76 #define debugf2( ... ) 77 #define debugf3( ... ) 78 #define debugf4( ... ) 79 80 #endif /* !CONFIG_EDAC_DEBUG */ 81 82 #define BIT(x) (1 << (x)) 83 84 #define PCI_VEND_DEV(vend, dev) PCI_VENDOR_ID_ ## vend, \ 85 PCI_DEVICE_ID_ ## vend ## _ ## dev 86 87 #if defined(CONFIG_X86) && defined(CONFIG_PCI) 88 #define dev_name(dev) pci_name(to_pci_dev(dev)) 89 #else 90 #define dev_name(dev) to_platform_device(dev)->name 91 #endif 92 93 /* memory devices */ 94 enum dev_type { 95 DEV_UNKNOWN = 0, 96 DEV_X1, 97 DEV_X2, 98 DEV_X4, 99 DEV_X8, 100 DEV_X16, 101 DEV_X32, /* Do these parts exist? */ 102 DEV_X64 /* Do these parts exist? */ 103 }; 104 105 #define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN) 106 #define DEV_FLAG_X1 BIT(DEV_X1) 107 #define DEV_FLAG_X2 BIT(DEV_X2) 108 #define DEV_FLAG_X4 BIT(DEV_X4) 109 #define DEV_FLAG_X8 BIT(DEV_X8) 110 #define DEV_FLAG_X16 BIT(DEV_X16) 111 #define DEV_FLAG_X32 BIT(DEV_X32) 112 #define DEV_FLAG_X64 BIT(DEV_X64) 113 114 /* memory types */ 115 enum mem_type { 116 MEM_EMPTY = 0, /* Empty csrow */ 117 MEM_RESERVED, /* Reserved csrow type */ 118 MEM_UNKNOWN, /* Unknown csrow type */ 119 MEM_FPM, /* Fast page mode */ 120 MEM_EDO, /* Extended data out */ 121 MEM_BEDO, /* Burst Extended data out */ 122 MEM_SDR, /* Single data rate SDRAM */ 123 MEM_RDR, /* Registered single data rate SDRAM */ 124 MEM_DDR, /* Double data rate SDRAM */ 125 MEM_RDDR, /* Registered Double data rate SDRAM */ 126 MEM_RMBS /* Rambus DRAM */ 127 }; 128 129 #define MEM_FLAG_EMPTY BIT(MEM_EMPTY) 130 #define MEM_FLAG_RESERVED BIT(MEM_RESERVED) 131 #define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN) 132 #define MEM_FLAG_FPM BIT(MEM_FPM) 133 #define MEM_FLAG_EDO BIT(MEM_EDO) 134 #define MEM_FLAG_BEDO BIT(MEM_BEDO) 135 #define MEM_FLAG_SDR BIT(MEM_SDR) 136 #define MEM_FLAG_RDR BIT(MEM_RDR) 137 #define MEM_FLAG_DDR BIT(MEM_DDR) 138 #define MEM_FLAG_RDDR BIT(MEM_RDDR) 139 #define MEM_FLAG_RMBS BIT(MEM_RMBS) 140 141 /* chipset Error Detection and Correction capabilities and mode */ 142 enum edac_type { 143 EDAC_UNKNOWN = 0, /* Unknown if ECC is available */ 144 EDAC_NONE, /* Doesnt support ECC */ 145 EDAC_RESERVED, /* Reserved ECC type */ 146 EDAC_PARITY, /* Detects parity errors */ 147 EDAC_EC, /* Error Checking - no correction */ 148 EDAC_SECDED, /* Single bit error correction, Double detection */ 149 EDAC_S2ECD2ED, /* Chipkill x2 devices - do these exist? */ 150 EDAC_S4ECD4ED, /* Chipkill x4 devices */ 151 EDAC_S8ECD8ED, /* Chipkill x8 devices */ 152 EDAC_S16ECD16ED, /* Chipkill x16 devices */ 153 }; 154 155 #define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN) 156 #define EDAC_FLAG_NONE BIT(EDAC_NONE) 157 #define EDAC_FLAG_PARITY BIT(EDAC_PARITY) 158 #define EDAC_FLAG_EC BIT(EDAC_EC) 159 #define EDAC_FLAG_SECDED BIT(EDAC_SECDED) 160 #define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED) 161 #define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED) 162 #define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED) 163 #define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED) 164 165 /* scrubbing capabilities */ 166 enum scrub_type { 167 SCRUB_UNKNOWN = 0, /* Unknown if scrubber is available */ 168 SCRUB_NONE, /* No scrubber */ 169 SCRUB_SW_PROG, /* SW progressive (sequential) scrubbing */ 170 SCRUB_SW_SRC, /* Software scrub only errors */ 171 SCRUB_SW_PROG_SRC, /* Progressive software scrub from an error */ 172 SCRUB_SW_TUNABLE, /* Software scrub frequency is tunable */ 173 SCRUB_HW_PROG, /* HW progressive (sequential) scrubbing */ 174 SCRUB_HW_SRC, /* Hardware scrub only errors */ 175 SCRUB_HW_PROG_SRC, /* Progressive hardware scrub from an error */ 176 SCRUB_HW_TUNABLE /* Hardware scrub frequency is tunable */ 177 }; 178 179 #define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG) 180 #define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC_CORR) 181 #define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC_CORR) 182 #define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE) 183 #define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG) 184 #define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC_CORR) 185 #define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC_CORR) 186 #define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE) 187 188 /* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */ 189 190 /* 191 * There are several things to be aware of that aren't at all obvious: 192 * 193 * 194 * SOCKETS, SOCKET SETS, BANKS, ROWS, CHIP-SELECT ROWS, CHANNELS, etc.. 195 * 196 * These are some of the many terms that are thrown about that don't always 197 * mean what people think they mean (Inconceivable!). In the interest of 198 * creating a common ground for discussion, terms and their definitions 199 * will be established. 200 * 201 * Memory devices: The individual chip on a memory stick. These devices 202 * commonly output 4 and 8 bits each. Grouping several 203 * of these in parallel provides 64 bits which is common 204 * for a memory stick. 205 * 206 * Memory Stick: A printed circuit board that agregates multiple 207 * memory devices in parallel. This is the atomic 208 * memory component that is purchaseable by Joe consumer 209 * and loaded into a memory socket. 210 * 211 * Socket: A physical connector on the motherboard that accepts 212 * a single memory stick. 213 * 214 * Channel: Set of memory devices on a memory stick that must be 215 * grouped in parallel with one or more additional 216 * channels from other memory sticks. This parallel 217 * grouping of the output from multiple channels are 218 * necessary for the smallest granularity of memory access. 219 * Some memory controllers are capable of single channel - 220 * which means that memory sticks can be loaded 221 * individually. Other memory controllers are only 222 * capable of dual channel - which means that memory 223 * sticks must be loaded as pairs (see "socket set"). 224 * 225 * Chip-select row: All of the memory devices that are selected together. 226 * for a single, minimum grain of memory access. 227 * This selects all of the parallel memory devices across 228 * all of the parallel channels. Common chip-select rows 229 * for single channel are 64 bits, for dual channel 128 230 * bits. 231 * 232 * Single-Ranked stick: A Single-ranked stick has 1 chip-select row of memmory. 233 * Motherboards commonly drive two chip-select pins to 234 * a memory stick. A single-ranked stick, will occupy 235 * only one of those rows. The other will be unused. 236 * 237 * Double-Ranked stick: A double-ranked stick has two chip-select rows which 238 * access different sets of memory devices. The two 239 * rows cannot be accessed concurrently. 240 * 241 * Double-sided stick: DEPRECATED TERM, see Double-Ranked stick. 242 * A double-sided stick has two chip-select rows which 243 * access different sets of memory devices. The two 244 * rows cannot be accessed concurrently. "Double-sided" 245 * is irrespective of the memory devices being mounted 246 * on both sides of the memory stick. 247 * 248 * Socket set: All of the memory sticks that are required for for 249 * a single memory access or all of the memory sticks 250 * spanned by a chip-select row. A single socket set 251 * has two chip-select rows and if double-sided sticks 252 * are used these will occupy those chip-select rows. 253 * 254 * Bank: This term is avoided because it is unclear when 255 * needing to distinguish between chip-select rows and 256 * socket sets. 257 * 258 * Controller pages: 259 * 260 * Physical pages: 261 * 262 * Virtual pages: 263 * 264 * 265 * STRUCTURE ORGANIZATION AND CHOICES 266 * 267 * 268 * 269 * PS - I enjoyed writing all that about as much as you enjoyed reading it. 270 */ 271 272 struct channel_info { 273 int chan_idx; /* channel index */ 274 u32 ce_count; /* Correctable Errors for this CHANNEL */ 275 char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */ 276 struct csrow_info *csrow; /* the parent */ 277 }; 278 279 struct csrow_info { 280 unsigned long first_page; /* first page number in dimm */ 281 unsigned long last_page; /* last page number in dimm */ 282 unsigned long page_mask; /* used for interleaving - 283 * 0UL for non intlv 284 */ 285 u32 nr_pages; /* number of pages in csrow */ 286 u32 grain; /* granularity of reported error in bytes */ 287 int csrow_idx; /* the chip-select row */ 288 enum dev_type dtype; /* memory device type */ 289 u32 ue_count; /* Uncorrectable Errors for this csrow */ 290 u32 ce_count; /* Correctable Errors for this csrow */ 291 enum mem_type mtype; /* memory csrow type */ 292 enum edac_type edac_mode; /* EDAC mode for this csrow */ 293 struct mem_ctl_info *mci; /* the parent */ 294 295 struct kobject kobj; /* sysfs kobject for this csrow */ 296 struct completion kobj_complete; 297 298 /* FIXME the number of CHANNELs might need to become dynamic */ 299 u32 nr_channels; 300 struct channel_info *channels; 301 }; 302 303 struct mem_ctl_info { 304 struct list_head link; /* for global list of mem_ctl_info structs */ 305 unsigned long mtype_cap; /* memory types supported by mc */ 306 unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */ 307 unsigned long edac_cap; /* configuration capabilities - this is 308 * closely related to edac_ctl_cap. The 309 * difference is that the controller may be 310 * capable of s4ecd4ed which would be listed 311 * in edac_ctl_cap, but if channels aren't 312 * capable of s4ecd4ed then the edac_cap would 313 * not have that capability. 314 */ 315 unsigned long scrub_cap; /* chipset scrub capabilities */ 316 enum scrub_type scrub_mode; /* current scrub mode */ 317 318 /* pointer to edac checking routine */ 319 void (*edac_check) (struct mem_ctl_info * mci); 320 /* 321 * Remaps memory pages: controller pages to physical pages. 322 * For most MC's, this will be NULL. 323 */ 324 /* FIXME - why not send the phys page to begin with? */ 325 unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci, 326 unsigned long page); 327 int mc_idx; 328 int nr_csrows; 329 struct csrow_info *csrows; 330 /* 331 * FIXME - what about controllers on other busses? - IDs must be 332 * unique. dev pointer should be sufficiently unique, but 333 * BUS:SLOT.FUNC numbers may not be unique. 334 */ 335 struct device *dev; 336 const char *mod_name; 337 const char *mod_ver; 338 const char *ctl_name; 339 char proc_name[MC_PROC_NAME_MAX_LEN + 1]; 340 void *pvt_info; 341 u32 ue_noinfo_count; /* Uncorrectable Errors w/o info */ 342 u32 ce_noinfo_count; /* Correctable Errors w/o info */ 343 u32 ue_count; /* Total Uncorrectable Errors for this MC */ 344 u32 ce_count; /* Total Correctable Errors for this MC */ 345 unsigned long start_time; /* mci load start time (in jiffies) */ 346 347 /* this stuff is for safe removal of mc devices from global list while 348 * NMI handlers may be traversing list 349 */ 350 struct rcu_head rcu; 351 struct completion complete; 352 353 /* edac sysfs device control */ 354 struct kobject edac_mci_kobj; 355 struct completion kobj_complete; 356 }; 357 358 #ifdef CONFIG_PCI 359 360 /* write all or some bits in a byte-register*/ 361 static inline void pci_write_bits8(struct pci_dev *pdev, int offset, u8 value, 362 u8 mask) 363 { 364 if (mask != 0xff) { 365 u8 buf; 366 367 pci_read_config_byte(pdev, offset, &buf); 368 value &= mask; 369 buf &= ~mask; 370 value |= buf; 371 } 372 373 pci_write_config_byte(pdev, offset, value); 374 } 375 376 /* write all or some bits in a word-register*/ 377 static inline void pci_write_bits16(struct pci_dev *pdev, int offset, 378 u16 value, u16 mask) 379 { 380 if (mask != 0xffff) { 381 u16 buf; 382 383 pci_read_config_word(pdev, offset, &buf); 384 value &= mask; 385 buf &= ~mask; 386 value |= buf; 387 } 388 389 pci_write_config_word(pdev, offset, value); 390 } 391 392 /* write all or some bits in a dword-register*/ 393 static inline void pci_write_bits32(struct pci_dev *pdev, int offset, 394 u32 value, u32 mask) 395 { 396 if (mask != 0xffff) { 397 u32 buf; 398 399 pci_read_config_dword(pdev, offset, &buf); 400 value &= mask; 401 buf &= ~mask; 402 value |= buf; 403 } 404 405 pci_write_config_dword(pdev, offset, value); 406 } 407 408 #endif /* CONFIG_PCI */ 409 410 #ifdef CONFIG_EDAC_DEBUG 411 void edac_mc_dump_channel(struct channel_info *chan); 412 void edac_mc_dump_mci(struct mem_ctl_info *mci); 413 void edac_mc_dump_csrow(struct csrow_info *csrow); 414 #endif /* CONFIG_EDAC_DEBUG */ 415 416 extern int edac_mc_add_mc(struct mem_ctl_info *mci,int mc_idx); 417 extern struct mem_ctl_info * edac_mc_del_mc(struct device *dev); 418 extern int edac_mc_find_csrow_by_page(struct mem_ctl_info *mci, 419 unsigned long page); 420 extern void edac_mc_scrub_block(unsigned long page, unsigned long offset, 421 u32 size); 422 423 /* 424 * The no info errors are used when error overflows are reported. 425 * There are a limited number of error logging registers that can 426 * be exausted. When all registers are exhausted and an additional 427 * error occurs then an error overflow register records that an 428 * error occured and the type of error, but doesn't have any 429 * further information. The ce/ue versions make for cleaner 430 * reporting logic and function interface - reduces conditional 431 * statement clutter and extra function arguments. 432 */ 433 extern void edac_mc_handle_ce(struct mem_ctl_info *mci, 434 unsigned long page_frame_number, unsigned long offset_in_page, 435 unsigned long syndrome, int row, int channel, 436 const char *msg); 437 extern void edac_mc_handle_ce_no_info(struct mem_ctl_info *mci, 438 const char *msg); 439 extern void edac_mc_handle_ue(struct mem_ctl_info *mci, 440 unsigned long page_frame_number, unsigned long offset_in_page, 441 int row, const char *msg); 442 extern void edac_mc_handle_ue_no_info(struct mem_ctl_info *mci, 443 const char *msg); 444 445 /* 446 * This kmalloc's and initializes all the structures. 447 * Can't be used if all structures don't have the same lifetime. 448 */ 449 extern struct mem_ctl_info *edac_mc_alloc(unsigned sz_pvt, unsigned nr_csrows, 450 unsigned nr_chans); 451 452 /* Free an mc previously allocated by edac_mc_alloc() */ 453 extern void edac_mc_free(struct mem_ctl_info *mci); 454 455 #endif /* _EDAC_MC_H_ */ 456