1 /* 2 * Intel e752x Memory Controller kernel module 3 * (C) 2004 Linux Networx (http://lnxi.com) 4 * This file may be distributed under the terms of the 5 * GNU General Public License. 6 * 7 * See "enum e752x_chips" below for supported chipsets 8 * 9 * Written by Tom Zimmerman 10 * 11 * Contributors: 12 * Thayne Harbaugh at realmsys.com (?) 13 * Wang Zhenyu at intel.com 14 * Dave Jiang at mvista.com 15 * 16 * $Id: edac_e752x.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ 17 * 18 */ 19 20 #include <linux/config.h> 21 #include <linux/module.h> 22 #include <linux/init.h> 23 #include <linux/pci.h> 24 #include <linux/pci_ids.h> 25 #include <linux/slab.h> 26 #include "edac_mc.h" 27 28 #define e752x_printk(level, fmt, arg...) \ 29 edac_printk(level, "e752x", fmt, ##arg) 30 31 #define e752x_mc_printk(mci, level, fmt, arg...) \ 32 edac_mc_chipset_printk(mci, level, "e752x", fmt, ##arg) 33 34 #ifndef PCI_DEVICE_ID_INTEL_7520_0 35 #define PCI_DEVICE_ID_INTEL_7520_0 0x3590 36 #endif /* PCI_DEVICE_ID_INTEL_7520_0 */ 37 38 #ifndef PCI_DEVICE_ID_INTEL_7520_1_ERR 39 #define PCI_DEVICE_ID_INTEL_7520_1_ERR 0x3591 40 #endif /* PCI_DEVICE_ID_INTEL_7520_1_ERR */ 41 42 #ifndef PCI_DEVICE_ID_INTEL_7525_0 43 #define PCI_DEVICE_ID_INTEL_7525_0 0x359E 44 #endif /* PCI_DEVICE_ID_INTEL_7525_0 */ 45 46 #ifndef PCI_DEVICE_ID_INTEL_7525_1_ERR 47 #define PCI_DEVICE_ID_INTEL_7525_1_ERR 0x3593 48 #endif /* PCI_DEVICE_ID_INTEL_7525_1_ERR */ 49 50 #ifndef PCI_DEVICE_ID_INTEL_7320_0 51 #define PCI_DEVICE_ID_INTEL_7320_0 0x3592 52 #endif /* PCI_DEVICE_ID_INTEL_7320_0 */ 53 54 #ifndef PCI_DEVICE_ID_INTEL_7320_1_ERR 55 #define PCI_DEVICE_ID_INTEL_7320_1_ERR 0x3593 56 #endif /* PCI_DEVICE_ID_INTEL_7320_1_ERR */ 57 58 #define E752X_NR_CSROWS 8 /* number of csrows */ 59 60 /* E752X register addresses - device 0 function 0 */ 61 #define E752X_DRB 0x60 /* DRAM row boundary register (8b) */ 62 #define E752X_DRA 0x70 /* DRAM row attribute register (8b) */ 63 /* 64 * 31:30 Device width row 7 65 * 01=x8 10=x4 11=x8 DDR2 66 * 27:26 Device width row 6 67 * 23:22 Device width row 5 68 * 19:20 Device width row 4 69 * 15:14 Device width row 3 70 * 11:10 Device width row 2 71 * 7:6 Device width row 1 72 * 3:2 Device width row 0 73 */ 74 #define E752X_DRC 0x7C /* DRAM controller mode reg (32b) */ 75 /* FIXME:IS THIS RIGHT? */ 76 /* 77 * 22 Number channels 0=1,1=2 78 * 19:18 DRB Granularity 32/64MB 79 */ 80 #define E752X_DRM 0x80 /* Dimm mapping register */ 81 #define E752X_DDRCSR 0x9A /* DDR control and status reg (16b) */ 82 /* 83 * 14:12 1 single A, 2 single B, 3 dual 84 */ 85 #define E752X_TOLM 0xC4 /* DRAM top of low memory reg (16b) */ 86 #define E752X_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */ 87 #define E752X_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */ 88 #define E752X_REMAPOFFSET 0xCA /* DRAM remap limit offset reg (16b) */ 89 90 /* E752X register addresses - device 0 function 1 */ 91 #define E752X_FERR_GLOBAL 0x40 /* Global first error register (32b) */ 92 #define E752X_NERR_GLOBAL 0x44 /* Global next error register (32b) */ 93 #define E752X_HI_FERR 0x50 /* Hub interface first error reg (8b) */ 94 #define E752X_HI_NERR 0x52 /* Hub interface next error reg (8b) */ 95 #define E752X_HI_ERRMASK 0x54 /* Hub interface error mask reg (8b) */ 96 #define E752X_HI_SMICMD 0x5A /* Hub interface SMI command reg (8b) */ 97 #define E752X_SYSBUS_FERR 0x60 /* System buss first error reg (16b) */ 98 #define E752X_SYSBUS_NERR 0x62 /* System buss next error reg (16b) */ 99 #define E752X_SYSBUS_ERRMASK 0x64 /* System buss error mask reg (16b) */ 100 #define E752X_SYSBUS_SMICMD 0x6A /* System buss SMI command reg (16b) */ 101 #define E752X_BUF_FERR 0x70 /* Memory buffer first error reg (8b) */ 102 #define E752X_BUF_NERR 0x72 /* Memory buffer next error reg (8b) */ 103 #define E752X_BUF_ERRMASK 0x74 /* Memory buffer error mask reg (8b) */ 104 #define E752X_BUF_SMICMD 0x7A /* Memory buffer SMI command reg (8b) */ 105 #define E752X_DRAM_FERR 0x80 /* DRAM first error register (16b) */ 106 #define E752X_DRAM_NERR 0x82 /* DRAM next error register (16b) */ 107 #define E752X_DRAM_ERRMASK 0x84 /* DRAM error mask register (8b) */ 108 #define E752X_DRAM_SMICMD 0x8A /* DRAM SMI command register (8b) */ 109 #define E752X_DRAM_RETR_ADD 0xAC /* DRAM Retry address register (32b) */ 110 #define E752X_DRAM_SEC1_ADD 0xA0 /* DRAM first correctable memory */ 111 /* error address register (32b) */ 112 /* 113 * 31 Reserved 114 * 30:2 CE address (64 byte block 34:6) 115 * 1 Reserved 116 * 0 HiLoCS 117 */ 118 #define E752X_DRAM_SEC2_ADD 0xC8 /* DRAM first correctable memory */ 119 /* error address register (32b) */ 120 /* 121 * 31 Reserved 122 * 30:2 CE address (64 byte block 34:6) 123 * 1 Reserved 124 * 0 HiLoCS 125 */ 126 #define E752X_DRAM_DED_ADD 0xA4 /* DRAM first uncorrectable memory */ 127 /* error address register (32b) */ 128 /* 129 * 31 Reserved 130 * 30:2 CE address (64 byte block 34:6) 131 * 1 Reserved 132 * 0 HiLoCS 133 */ 134 #define E752X_DRAM_SCRB_ADD 0xA8 /* DRAM first uncorrectable scrub memory */ 135 /* error address register (32b) */ 136 /* 137 * 31 Reserved 138 * 30:2 CE address (64 byte block 34:6) 139 * 1 Reserved 140 * 0 HiLoCS 141 */ 142 #define E752X_DRAM_SEC1_SYNDROME 0xC4 /* DRAM first correctable memory */ 143 /* error syndrome register (16b) */ 144 #define E752X_DRAM_SEC2_SYNDROME 0xC6 /* DRAM second correctable memory */ 145 /* error syndrome register (16b) */ 146 #define E752X_DEVPRES1 0xF4 /* Device Present 1 register (8b) */ 147 148 /* ICH5R register addresses - device 30 function 0 */ 149 #define ICH5R_PCI_STAT 0x06 /* PCI status register (16b) */ 150 #define ICH5R_PCI_2ND_STAT 0x1E /* PCI status secondary reg (16b) */ 151 #define ICH5R_PCI_BRIDGE_CTL 0x3E /* PCI bridge control register (16b) */ 152 153 enum e752x_chips { 154 E7520 = 0, 155 E7525 = 1, 156 E7320 = 2 157 }; 158 159 struct e752x_pvt { 160 struct pci_dev *bridge_ck; 161 struct pci_dev *dev_d0f0; 162 struct pci_dev *dev_d0f1; 163 u32 tolm; 164 u32 remapbase; 165 u32 remaplimit; 166 int mc_symmetric; 167 u8 map[8]; 168 int map_type; 169 const struct e752x_dev_info *dev_info; 170 }; 171 172 struct e752x_dev_info { 173 u16 err_dev; 174 u16 ctl_dev; 175 const char *ctl_name; 176 }; 177 178 struct e752x_error_info { 179 u32 ferr_global; 180 u32 nerr_global; 181 u8 hi_ferr; 182 u8 hi_nerr; 183 u16 sysbus_ferr; 184 u16 sysbus_nerr; 185 u8 buf_ferr; 186 u8 buf_nerr; 187 u16 dram_ferr; 188 u16 dram_nerr; 189 u32 dram_sec1_add; 190 u32 dram_sec2_add; 191 u16 dram_sec1_syndrome; 192 u16 dram_sec2_syndrome; 193 u32 dram_ded_add; 194 u32 dram_scrb_add; 195 u32 dram_retr_add; 196 }; 197 198 static const struct e752x_dev_info e752x_devs[] = { 199 [E7520] = { 200 .err_dev = PCI_DEVICE_ID_INTEL_7520_1_ERR, 201 .ctl_dev = PCI_DEVICE_ID_INTEL_7520_0, 202 .ctl_name = "E7520" 203 }, 204 [E7525] = { 205 .err_dev = PCI_DEVICE_ID_INTEL_7525_1_ERR, 206 .ctl_dev = PCI_DEVICE_ID_INTEL_7525_0, 207 .ctl_name = "E7525" 208 }, 209 [E7320] = { 210 .err_dev = PCI_DEVICE_ID_INTEL_7320_1_ERR, 211 .ctl_dev = PCI_DEVICE_ID_INTEL_7320_0, 212 .ctl_name = "E7320" 213 }, 214 }; 215 216 static unsigned long ctl_page_to_phys(struct mem_ctl_info *mci, 217 unsigned long page) 218 { 219 u32 remap; 220 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 221 222 debugf3("%s()\n", __func__); 223 224 if (page < pvt->tolm) 225 return page; 226 227 if ((page >= 0x100000) && (page < pvt->remapbase)) 228 return page; 229 230 remap = (page - pvt->tolm) + pvt->remapbase; 231 232 if (remap < pvt->remaplimit) 233 return remap; 234 235 e752x_printk(KERN_ERR, "Invalid page %lx - out of range\n", page); 236 return pvt->tolm - 1; 237 } 238 239 static void do_process_ce(struct mem_ctl_info *mci, u16 error_one, 240 u32 sec1_add, u16 sec1_syndrome) 241 { 242 u32 page; 243 int row; 244 int channel; 245 int i; 246 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 247 248 debugf3("%s()\n", __func__); 249 250 /* convert the addr to 4k page */ 251 page = sec1_add >> (PAGE_SHIFT - 4); 252 253 /* FIXME - check for -1 */ 254 if (pvt->mc_symmetric) { 255 /* chip select are bits 14 & 13 */ 256 row = ((page >> 1) & 3); 257 e752x_printk(KERN_WARNING, 258 "Test row %d Table %d %d %d %d %d %d %d %d\n", row, 259 pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3], 260 pvt->map[4], pvt->map[5], pvt->map[6], pvt->map[7]); 261 262 /* test for channel remapping */ 263 for (i = 0; i < 8; i++) { 264 if (pvt->map[i] == row) 265 break; 266 } 267 268 e752x_printk(KERN_WARNING, "Test computed row %d\n", i); 269 270 if (i < 8) 271 row = i; 272 else 273 e752x_mc_printk(mci, KERN_WARNING, 274 "row %d not found in remap table\n", row); 275 } else 276 row = edac_mc_find_csrow_by_page(mci, page); 277 278 /* 0 = channel A, 1 = channel B */ 279 channel = !(error_one & 1); 280 281 if (!pvt->map_type) 282 row = 7 - row; 283 284 edac_mc_handle_ce(mci, page, 0, sec1_syndrome, row, channel, 285 "e752x CE"); 286 } 287 288 static inline void process_ce(struct mem_ctl_info *mci, u16 error_one, 289 u32 sec1_add, u16 sec1_syndrome, int *error_found, 290 int handle_error) 291 { 292 *error_found = 1; 293 294 if (handle_error) 295 do_process_ce(mci, error_one, sec1_add, sec1_syndrome); 296 } 297 298 static void do_process_ue(struct mem_ctl_info *mci, u16 error_one, 299 u32 ded_add, u32 scrb_add) 300 { 301 u32 error_2b, block_page; 302 int row; 303 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 304 305 debugf3("%s()\n", __func__); 306 307 if (error_one & 0x0202) { 308 error_2b = ded_add; 309 310 /* convert to 4k address */ 311 block_page = error_2b >> (PAGE_SHIFT - 4); 312 313 row = pvt->mc_symmetric ? 314 /* chip select are bits 14 & 13 */ 315 ((block_page >> 1) & 3) : 316 edac_mc_find_csrow_by_page(mci, block_page); 317 318 edac_mc_handle_ue(mci, block_page, 0, row, 319 "e752x UE from Read"); 320 } 321 if (error_one & 0x0404) { 322 error_2b = scrb_add; 323 324 /* convert to 4k address */ 325 block_page = error_2b >> (PAGE_SHIFT - 4); 326 327 row = pvt->mc_symmetric ? 328 /* chip select are bits 14 & 13 */ 329 ((block_page >> 1) & 3) : 330 edac_mc_find_csrow_by_page(mci, block_page); 331 332 edac_mc_handle_ue(mci, block_page, 0, row, 333 "e752x UE from Scruber"); 334 } 335 } 336 337 static inline void process_ue(struct mem_ctl_info *mci, u16 error_one, 338 u32 ded_add, u32 scrb_add, int *error_found, int handle_error) 339 { 340 *error_found = 1; 341 342 if (handle_error) 343 do_process_ue(mci, error_one, ded_add, scrb_add); 344 } 345 346 static inline void process_ue_no_info_wr(struct mem_ctl_info *mci, 347 int *error_found, int handle_error) 348 { 349 *error_found = 1; 350 351 if (!handle_error) 352 return; 353 354 debugf3("%s()\n", __func__); 355 edac_mc_handle_ue_no_info(mci, "e752x UE log memory write"); 356 } 357 358 static void do_process_ded_retry(struct mem_ctl_info *mci, u16 error, 359 u32 retry_add) 360 { 361 u32 error_1b, page; 362 int row; 363 struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info; 364 365 error_1b = retry_add; 366 page = error_1b >> (PAGE_SHIFT - 4); /* convert the addr to 4k page */ 367 row = pvt->mc_symmetric ? 368 ((page >> 1) & 3) : /* chip select are bits 14 & 13 */ 369 edac_mc_find_csrow_by_page(mci, page); 370 e752x_mc_printk(mci, KERN_WARNING, 371 "CE page 0x%lx, row %d : Memory read retry\n", 372 (long unsigned int) page, row); 373 } 374 375 static inline void process_ded_retry(struct mem_ctl_info *mci, u16 error, 376 u32 retry_add, int *error_found, int handle_error) 377 { 378 *error_found = 1; 379 380 if (handle_error) 381 do_process_ded_retry(mci, error, retry_add); 382 } 383 384 static inline void process_threshold_ce(struct mem_ctl_info *mci, u16 error, 385 int *error_found, int handle_error) 386 { 387 *error_found = 1; 388 389 if (handle_error) 390 e752x_mc_printk(mci, KERN_WARNING, "Memory threshold CE\n"); 391 } 392 393 static char *global_message[11] = { 394 "PCI Express C1", "PCI Express C", "PCI Express B1", 395 "PCI Express B", "PCI Express A1", "PCI Express A", 396 "DMA Controler", "HUB Interface", "System Bus", 397 "DRAM Controler", "Internal Buffer" 398 }; 399 400 static char *fatal_message[2] = { "Non-Fatal ", "Fatal " }; 401 402 static void do_global_error(int fatal, u32 errors) 403 { 404 int i; 405 406 for (i = 0; i < 11; i++) { 407 if (errors & (1 << i)) 408 e752x_printk(KERN_WARNING, "%sError %s\n", 409 fatal_message[fatal], global_message[i]); 410 } 411 } 412 413 static inline void global_error(int fatal, u32 errors, int *error_found, 414 int handle_error) 415 { 416 *error_found = 1; 417 418 if (handle_error) 419 do_global_error(fatal, errors); 420 } 421 422 static char *hub_message[7] = { 423 "HI Address or Command Parity", "HI Illegal Access", 424 "HI Internal Parity", "Out of Range Access", 425 "HI Data Parity", "Enhanced Config Access", 426 "Hub Interface Target Abort" 427 }; 428 429 static void do_hub_error(int fatal, u8 errors) 430 { 431 int i; 432 433 for (i = 0; i < 7; i++) { 434 if (errors & (1 << i)) 435 e752x_printk(KERN_WARNING, "%sError %s\n", 436 fatal_message[fatal], hub_message[i]); 437 } 438 } 439 440 static inline void hub_error(int fatal, u8 errors, int *error_found, 441 int handle_error) 442 { 443 *error_found = 1; 444 445 if (handle_error) 446 do_hub_error(fatal, errors); 447 } 448 449 static char *membuf_message[4] = { 450 "Internal PMWB to DRAM parity", 451 "Internal PMWB to System Bus Parity", 452 "Internal System Bus or IO to PMWB Parity", 453 "Internal DRAM to PMWB Parity" 454 }; 455 456 static void do_membuf_error(u8 errors) 457 { 458 int i; 459 460 for (i = 0; i < 4; i++) { 461 if (errors & (1 << i)) 462 e752x_printk(KERN_WARNING, "Non-Fatal Error %s\n", 463 membuf_message[i]); 464 } 465 } 466 467 static inline void membuf_error(u8 errors, int *error_found, int handle_error) 468 { 469 *error_found = 1; 470 471 if (handle_error) 472 do_membuf_error(errors); 473 } 474 475 static char *sysbus_message[10] = { 476 "Addr or Request Parity", 477 "Data Strobe Glitch", 478 "Addr Strobe Glitch", 479 "Data Parity", 480 "Addr Above TOM", 481 "Non DRAM Lock Error", 482 "MCERR", "BINIT", 483 "Memory Parity", 484 "IO Subsystem Parity" 485 }; 486 487 static void do_sysbus_error(int fatal, u32 errors) 488 { 489 int i; 490 491 for (i = 0; i < 10; i++) { 492 if (errors & (1 << i)) 493 e752x_printk(KERN_WARNING, "%sError System Bus %s\n", 494 fatal_message[fatal], sysbus_message[i]); 495 } 496 } 497 498 static inline void sysbus_error(int fatal, u32 errors, int *error_found, 499 int handle_error) 500 { 501 *error_found = 1; 502 503 if (handle_error) 504 do_sysbus_error(fatal, errors); 505 } 506 507 static void e752x_check_hub_interface(struct e752x_error_info *info, 508 int *error_found, int handle_error) 509 { 510 u8 stat8; 511 512 //pci_read_config_byte(dev,E752X_HI_FERR,&stat8); 513 514 stat8 = info->hi_ferr; 515 516 if(stat8 & 0x7f) { /* Error, so process */ 517 stat8 &= 0x7f; 518 519 if(stat8 & 0x2b) 520 hub_error(1, stat8 & 0x2b, error_found, handle_error); 521 522 if(stat8 & 0x54) 523 hub_error(0, stat8 & 0x54, error_found, handle_error); 524 } 525 526 //pci_read_config_byte(dev,E752X_HI_NERR,&stat8); 527 528 stat8 = info->hi_nerr; 529 530 if(stat8 & 0x7f) { /* Error, so process */ 531 stat8 &= 0x7f; 532 533 if (stat8 & 0x2b) 534 hub_error(1, stat8 & 0x2b, error_found, handle_error); 535 536 if(stat8 & 0x54) 537 hub_error(0, stat8 & 0x54, error_found, handle_error); 538 } 539 } 540 541 static void e752x_check_sysbus(struct e752x_error_info *info, 542 int *error_found, int handle_error) 543 { 544 u32 stat32, error32; 545 546 //pci_read_config_dword(dev,E752X_SYSBUS_FERR,&stat32); 547 stat32 = info->sysbus_ferr + (info->sysbus_nerr << 16); 548 549 if (stat32 == 0) 550 return; /* no errors */ 551 552 error32 = (stat32 >> 16) & 0x3ff; 553 stat32 = stat32 & 0x3ff; 554 555 if(stat32 & 0x083) 556 sysbus_error(1, stat32 & 0x083, error_found, handle_error); 557 558 if(stat32 & 0x37c) 559 sysbus_error(0, stat32 & 0x37c, error_found, handle_error); 560 561 if(error32 & 0x083) 562 sysbus_error(1, error32 & 0x083, error_found, handle_error); 563 564 if(error32 & 0x37c) 565 sysbus_error(0, error32 & 0x37c, error_found, handle_error); 566 } 567 568 static void e752x_check_membuf (struct e752x_error_info *info, 569 int *error_found, int handle_error) 570 { 571 u8 stat8; 572 573 stat8 = info->buf_ferr; 574 575 if (stat8 & 0x0f) { /* Error, so process */ 576 stat8 &= 0x0f; 577 membuf_error(stat8, error_found, handle_error); 578 } 579 580 stat8 = info->buf_nerr; 581 582 if (stat8 & 0x0f) { /* Error, so process */ 583 stat8 &= 0x0f; 584 membuf_error(stat8, error_found, handle_error); 585 } 586 } 587 588 static void e752x_check_dram (struct mem_ctl_info *mci, 589 struct e752x_error_info *info, int *error_found, 590 int handle_error) 591 { 592 u16 error_one, error_next; 593 594 error_one = info->dram_ferr; 595 error_next = info->dram_nerr; 596 597 /* decode and report errors */ 598 if(error_one & 0x0101) /* check first error correctable */ 599 process_ce(mci, error_one, info->dram_sec1_add, 600 info->dram_sec1_syndrome, error_found, 601 handle_error); 602 603 if(error_next & 0x0101) /* check next error correctable */ 604 process_ce(mci, error_next, info->dram_sec2_add, 605 info->dram_sec2_syndrome, error_found, 606 handle_error); 607 608 if(error_one & 0x4040) 609 process_ue_no_info_wr(mci, error_found, handle_error); 610 611 if(error_next & 0x4040) 612 process_ue_no_info_wr(mci, error_found, handle_error); 613 614 if(error_one & 0x2020) 615 process_ded_retry(mci, error_one, info->dram_retr_add, 616 error_found, handle_error); 617 618 if(error_next & 0x2020) 619 process_ded_retry(mci, error_next, info->dram_retr_add, 620 error_found, handle_error); 621 622 if(error_one & 0x0808) 623 process_threshold_ce(mci, error_one, error_found, 624 handle_error); 625 626 if(error_next & 0x0808) 627 process_threshold_ce(mci, error_next, error_found, 628 handle_error); 629 630 if(error_one & 0x0606) 631 process_ue(mci, error_one, info->dram_ded_add, 632 info->dram_scrb_add, error_found, handle_error); 633 634 if(error_next & 0x0606) 635 process_ue(mci, error_next, info->dram_ded_add, 636 info->dram_scrb_add, error_found, handle_error); 637 } 638 639 static void e752x_get_error_info (struct mem_ctl_info *mci, 640 struct e752x_error_info *info) 641 { 642 struct pci_dev *dev; 643 struct e752x_pvt *pvt; 644 645 memset(info, 0, sizeof(*info)); 646 pvt = (struct e752x_pvt *) mci->pvt_info; 647 dev = pvt->dev_d0f1; 648 pci_read_config_dword(dev, E752X_FERR_GLOBAL, &info->ferr_global); 649 650 if (info->ferr_global) { 651 pci_read_config_byte(dev, E752X_HI_FERR, &info->hi_ferr); 652 pci_read_config_word(dev, E752X_SYSBUS_FERR, 653 &info->sysbus_ferr); 654 pci_read_config_byte(dev, E752X_BUF_FERR, &info->buf_ferr); 655 pci_read_config_word(dev, E752X_DRAM_FERR, 656 &info->dram_ferr); 657 pci_read_config_dword(dev, E752X_DRAM_SEC1_ADD, 658 &info->dram_sec1_add); 659 pci_read_config_word(dev, E752X_DRAM_SEC1_SYNDROME, 660 &info->dram_sec1_syndrome); 661 pci_read_config_dword(dev, E752X_DRAM_DED_ADD, 662 &info->dram_ded_add); 663 pci_read_config_dword(dev, E752X_DRAM_SCRB_ADD, 664 &info->dram_scrb_add); 665 pci_read_config_dword(dev, E752X_DRAM_RETR_ADD, 666 &info->dram_retr_add); 667 668 if (info->hi_ferr & 0x7f) 669 pci_write_config_byte(dev, E752X_HI_FERR, 670 info->hi_ferr); 671 672 if (info->sysbus_ferr) 673 pci_write_config_word(dev, E752X_SYSBUS_FERR, 674 info->sysbus_ferr); 675 676 if (info->buf_ferr & 0x0f) 677 pci_write_config_byte(dev, E752X_BUF_FERR, 678 info->buf_ferr); 679 680 if (info->dram_ferr) 681 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_FERR, 682 info->dram_ferr, info->dram_ferr); 683 684 pci_write_config_dword(dev, E752X_FERR_GLOBAL, 685 info->ferr_global); 686 } 687 688 pci_read_config_dword(dev, E752X_NERR_GLOBAL, &info->nerr_global); 689 690 if (info->nerr_global) { 691 pci_read_config_byte(dev, E752X_HI_NERR, &info->hi_nerr); 692 pci_read_config_word(dev, E752X_SYSBUS_NERR, 693 &info->sysbus_nerr); 694 pci_read_config_byte(dev, E752X_BUF_NERR, &info->buf_nerr); 695 pci_read_config_word(dev, E752X_DRAM_NERR, 696 &info->dram_nerr); 697 pci_read_config_dword(dev, E752X_DRAM_SEC2_ADD, 698 &info->dram_sec2_add); 699 pci_read_config_word(dev, E752X_DRAM_SEC2_SYNDROME, 700 &info->dram_sec2_syndrome); 701 702 if (info->hi_nerr & 0x7f) 703 pci_write_config_byte(dev, E752X_HI_NERR, 704 info->hi_nerr); 705 706 if (info->sysbus_nerr) 707 pci_write_config_word(dev, E752X_SYSBUS_NERR, 708 info->sysbus_nerr); 709 710 if (info->buf_nerr & 0x0f) 711 pci_write_config_byte(dev, E752X_BUF_NERR, 712 info->buf_nerr); 713 714 if (info->dram_nerr) 715 pci_write_bits16(pvt->bridge_ck, E752X_DRAM_NERR, 716 info->dram_nerr, info->dram_nerr); 717 718 pci_write_config_dword(dev, E752X_NERR_GLOBAL, 719 info->nerr_global); 720 } 721 } 722 723 static int e752x_process_error_info (struct mem_ctl_info *mci, 724 struct e752x_error_info *info, int handle_errors) 725 { 726 u32 error32, stat32; 727 int error_found; 728 729 error_found = 0; 730 error32 = (info->ferr_global >> 18) & 0x3ff; 731 stat32 = (info->ferr_global >> 4) & 0x7ff; 732 733 if (error32) 734 global_error(1, error32, &error_found, handle_errors); 735 736 if (stat32) 737 global_error(0, stat32, &error_found, handle_errors); 738 739 error32 = (info->nerr_global >> 18) & 0x3ff; 740 stat32 = (info->nerr_global >> 4) & 0x7ff; 741 742 if (error32) 743 global_error(1, error32, &error_found, handle_errors); 744 745 if (stat32) 746 global_error(0, stat32, &error_found, handle_errors); 747 748 e752x_check_hub_interface(info, &error_found, handle_errors); 749 e752x_check_sysbus(info, &error_found, handle_errors); 750 e752x_check_membuf(info, &error_found, handle_errors); 751 e752x_check_dram(mci, info, &error_found, handle_errors); 752 return error_found; 753 } 754 755 static void e752x_check(struct mem_ctl_info *mci) 756 { 757 struct e752x_error_info info; 758 759 debugf3("%s()\n", __func__); 760 e752x_get_error_info(mci, &info); 761 e752x_process_error_info(mci, &info, 1); 762 } 763 764 static int e752x_probe1(struct pci_dev *pdev, int dev_idx) 765 { 766 int rc = -ENODEV; 767 int index; 768 u16 pci_data; 769 u8 stat8; 770 struct mem_ctl_info *mci = NULL; 771 struct e752x_pvt *pvt = NULL; 772 u16 ddrcsr; 773 u32 drc; 774 int drc_chan; /* Number of channels 0=1chan,1=2chan */ 775 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */ 776 int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */ 777 u32 dra; 778 unsigned long last_cumul_size; 779 struct pci_dev *dev = NULL; 780 struct e752x_error_info discard; 781 782 debugf0("%s(): mci\n", __func__); 783 debugf0("Starting Probe1\n"); 784 785 /* enable device 0 function 1 */ 786 pci_read_config_byte(pdev, E752X_DEVPRES1, &stat8); 787 stat8 |= (1 << 5); 788 pci_write_config_byte(pdev, E752X_DEVPRES1, stat8); 789 790 /* need to find out the number of channels */ 791 pci_read_config_dword(pdev, E752X_DRC, &drc); 792 pci_read_config_word(pdev, E752X_DDRCSR, &ddrcsr); 793 /* FIXME: should check >>12 or 0xf, true for all? */ 794 /* Dual channel = 1, Single channel = 0 */ 795 drc_chan = (((ddrcsr >> 12) & 3) == 3); 796 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */ 797 drc_ddim = (drc >> 20) & 0x3; 798 799 mci = edac_mc_alloc(sizeof(*pvt), E752X_NR_CSROWS, drc_chan + 1); 800 801 if (mci == NULL) { 802 rc = -ENOMEM; 803 goto fail; 804 } 805 806 debugf3("%s(): init mci\n", __func__); 807 mci->mtype_cap = MEM_FLAG_RDDR; 808 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED | 809 EDAC_FLAG_S4ECD4ED; 810 /* FIXME - what if different memory types are in different csrows? */ 811 mci->mod_name = EDAC_MOD_STR; 812 mci->mod_ver = "$Revision: 1.5.2.11 $"; 813 mci->pdev = pdev; 814 815 debugf3("%s(): init pvt\n", __func__); 816 pvt = (struct e752x_pvt *) mci->pvt_info; 817 pvt->dev_info = &e752x_devs[dev_idx]; 818 pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL, 819 pvt->dev_info->err_dev, 820 pvt->bridge_ck); 821 822 if (pvt->bridge_ck == NULL) 823 pvt->bridge_ck = pci_scan_single_device(pdev->bus, 824 PCI_DEVFN(0, 1)); 825 826 if (pvt->bridge_ck == NULL) { 827 e752x_printk(KERN_ERR, "error reporting device not found:" 828 "vendor %x device 0x%x (broken BIOS?)\n", 829 PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].err_dev); 830 goto fail; 831 } 832 833 pvt->mc_symmetric = ((ddrcsr & 0x10) != 0); 834 debugf3("%s(): more mci init\n", __func__); 835 mci->ctl_name = pvt->dev_info->ctl_name; 836 mci->edac_check = e752x_check; 837 mci->ctl_page_to_phys = ctl_page_to_phys; 838 839 /* find out the device types */ 840 pci_read_config_dword(pdev, E752X_DRA, &dra); 841 842 /* 843 * The dram row boundary (DRB) reg values are boundary address for 844 * each DRAM row with a granularity of 64 or 128MB (single/dual 845 * channel operation). DRB regs are cumulative; therefore DRB7 will 846 * contain the total memory contained in all eight rows. 847 */ 848 for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) { 849 u8 value; 850 u32 cumul_size; 851 852 /* mem_dev 0=x8, 1=x4 */ 853 int mem_dev = (dra >> (index * 4 + 2)) & 0x3; 854 struct csrow_info *csrow = &mci->csrows[index]; 855 856 mem_dev = (mem_dev == 2); 857 pci_read_config_byte(mci->pdev, E752X_DRB + index, &value); 858 /* convert a 128 or 64 MiB DRB to a page size. */ 859 cumul_size = value << (25 + drc_drbg - PAGE_SHIFT); 860 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index, 861 cumul_size); 862 863 if (cumul_size == last_cumul_size) 864 continue; /* not populated */ 865 866 csrow->first_page = last_cumul_size; 867 csrow->last_page = cumul_size - 1; 868 csrow->nr_pages = cumul_size - last_cumul_size; 869 last_cumul_size = cumul_size; 870 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */ 871 csrow->mtype = MEM_RDDR; /* only one type supported */ 872 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8; 873 874 /* 875 * if single channel or x8 devices then SECDED 876 * if dual channel and x4 then S4ECD4ED 877 */ 878 if (drc_ddim) { 879 if (drc_chan && mem_dev) { 880 csrow->edac_mode = EDAC_S4ECD4ED; 881 mci->edac_cap |= EDAC_FLAG_S4ECD4ED; 882 } else { 883 csrow->edac_mode = EDAC_SECDED; 884 mci->edac_cap |= EDAC_FLAG_SECDED; 885 } 886 } else 887 csrow->edac_mode = EDAC_NONE; 888 } 889 890 /* Fill in the memory map table */ 891 { 892 u8 value; 893 u8 last = 0; 894 u8 row = 0; 895 896 for (index = 0; index < 8; index += 2) { 897 pci_read_config_byte(mci->pdev, E752X_DRB + index, 898 &value); 899 900 /* test if there is a dimm in this slot */ 901 if (value == last) { 902 /* no dimm in the slot, so flag it as empty */ 903 pvt->map[index] = 0xff; 904 pvt->map[index + 1] = 0xff; 905 } else { /* there is a dimm in the slot */ 906 pvt->map[index] = row; 907 row++; 908 last = value; 909 /* test the next value to see if the dimm is 910 double sided */ 911 pci_read_config_byte(mci->pdev, 912 E752X_DRB + index + 1, 913 &value); 914 pvt->map[index + 1] = (value == last) ? 915 0xff : /* the dimm is single sided, 916 * so flag as empty 917 */ 918 row; /* this is a double sided dimm 919 * to save the next row # 920 */ 921 row++; 922 last = value; 923 } 924 } 925 } 926 927 /* set the map type. 1 = normal, 0 = reversed */ 928 pci_read_config_byte(mci->pdev, E752X_DRM, &stat8); 929 pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f)); 930 931 mci->edac_cap |= EDAC_FLAG_NONE; 932 debugf3("%s(): tolm, remapbase, remaplimit\n", __func__); 933 934 /* load the top of low memory, remap base, and remap limit vars */ 935 pci_read_config_word(mci->pdev, E752X_TOLM, &pci_data); 936 pvt->tolm = ((u32) pci_data) << 4; 937 pci_read_config_word(mci->pdev, E752X_REMAPBASE, &pci_data); 938 pvt->remapbase = ((u32) pci_data) << 14; 939 pci_read_config_word(mci->pdev, E752X_REMAPLIMIT, &pci_data); 940 pvt->remaplimit = ((u32) pci_data) << 14; 941 e752x_printk(KERN_INFO, 942 "tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm, 943 pvt->remapbase, pvt->remaplimit); 944 945 if (edac_mc_add_mc(mci)) { 946 debugf3("%s(): failed edac_mc_add_mc()\n", __func__); 947 goto fail; 948 } 949 950 dev = pci_get_device(PCI_VENDOR_ID_INTEL, e752x_devs[dev_idx].ctl_dev, 951 NULL); 952 pvt->dev_d0f0 = dev; 953 /* find the error reporting device and clear errors */ 954 dev = pvt->dev_d0f1 = pci_dev_get(pvt->bridge_ck); 955 /* Turn off error disable & SMI in case the BIOS turned it on */ 956 pci_write_config_byte(dev, E752X_HI_ERRMASK, 0x00); 957 pci_write_config_byte(dev, E752X_HI_SMICMD, 0x00); 958 pci_write_config_word(dev, E752X_SYSBUS_ERRMASK, 0x00); 959 pci_write_config_word(dev, E752X_SYSBUS_SMICMD, 0x00); 960 pci_write_config_byte(dev, E752X_BUF_ERRMASK, 0x00); 961 pci_write_config_byte(dev, E752X_BUF_SMICMD, 0x00); 962 pci_write_config_byte(dev, E752X_DRAM_ERRMASK, 0x00); 963 pci_write_config_byte(dev, E752X_DRAM_SMICMD, 0x00); 964 965 e752x_get_error_info(mci, &discard); /* clear other MCH errors */ 966 967 /* get this far and it's successful */ 968 debugf3("%s(): success\n", __func__); 969 return 0; 970 971 fail: 972 if (mci) { 973 if (pvt->dev_d0f0) 974 pci_dev_put(pvt->dev_d0f0); 975 976 if (pvt->dev_d0f1) 977 pci_dev_put(pvt->dev_d0f1); 978 979 if (pvt->bridge_ck) 980 pci_dev_put(pvt->bridge_ck); 981 982 edac_mc_free(mci); 983 } 984 985 return rc; 986 } 987 988 /* returns count (>= 0), or negative on error */ 989 static int __devinit e752x_init_one(struct pci_dev *pdev, 990 const struct pci_device_id *ent) 991 { 992 debugf0("%s()\n", __func__); 993 994 /* wake up and enable device */ 995 if(pci_enable_device(pdev) < 0) 996 return -EIO; 997 998 return e752x_probe1(pdev, ent->driver_data); 999 } 1000 1001 static void __devexit e752x_remove_one(struct pci_dev *pdev) 1002 { 1003 struct mem_ctl_info *mci; 1004 struct e752x_pvt *pvt; 1005 1006 debugf0("%s()\n", __func__); 1007 1008 if ((mci = edac_mc_del_mc(pdev)) == NULL) 1009 return; 1010 1011 pvt = (struct e752x_pvt *) mci->pvt_info; 1012 pci_dev_put(pvt->dev_d0f0); 1013 pci_dev_put(pvt->dev_d0f1); 1014 pci_dev_put(pvt->bridge_ck); 1015 edac_mc_free(mci); 1016 } 1017 1018 static const struct pci_device_id e752x_pci_tbl[] __devinitdata = { 1019 { 1020 PCI_VEND_DEV(INTEL, 7520_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1021 E7520 1022 }, 1023 { 1024 PCI_VEND_DEV(INTEL, 7525_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1025 E7525 1026 }, 1027 { 1028 PCI_VEND_DEV(INTEL, 7320_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1029 E7320 1030 }, 1031 { 1032 0, 1033 } /* 0 terminated list. */ 1034 }; 1035 1036 MODULE_DEVICE_TABLE(pci, e752x_pci_tbl); 1037 1038 static struct pci_driver e752x_driver = { 1039 .name = EDAC_MOD_STR, 1040 .probe = e752x_init_one, 1041 .remove = __devexit_p(e752x_remove_one), 1042 .id_table = e752x_pci_tbl, 1043 }; 1044 1045 static int __init e752x_init(void) 1046 { 1047 int pci_rc; 1048 1049 debugf3("%s()\n", __func__); 1050 pci_rc = pci_register_driver(&e752x_driver); 1051 return (pci_rc < 0) ? pci_rc : 0; 1052 } 1053 1054 static void __exit e752x_exit(void) 1055 { 1056 debugf3("%s()\n", __func__); 1057 pci_unregister_driver(&e752x_driver); 1058 } 1059 1060 module_init(e752x_init); 1061 module_exit(e752x_exit); 1062 1063 MODULE_LICENSE("GPL"); 1064 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Tom Zimmerman\n"); 1065 MODULE_DESCRIPTION("MC support for Intel e752x memory controllers"); 1066