1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved 4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved. 5 * Copyright 2011-2012 Calxeda, Inc. 6 */ 7 8 #include <asm/cacheflush.h> 9 #include <linux/ctype.h> 10 #include <linux/delay.h> 11 #include <linux/edac.h> 12 #include <linux/firmware/intel/stratix10-smc.h> 13 #include <linux/genalloc.h> 14 #include <linux/interrupt.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/kernel.h> 17 #include <linux/mfd/altera-sysmgr.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/notifier.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/panic_notifier.h> 24 #include <linux/platform_device.h> 25 #include <linux/property.h> 26 #include <linux/regmap.h> 27 #include <linux/types.h> 28 #include <linux/uaccess.h> 29 30 #include "altera_edac.h" 31 #include "edac_module.h" 32 33 #define EDAC_MOD_STR "altera_edac" 34 #define EDAC_DEVICE "Altera" 35 36 #ifdef CONFIG_EDAC_ALTERA_SDRAM 37 static const struct altr_sdram_prv_data c5_data = { 38 .ecc_ctrl_offset = CV_CTLCFG_OFST, 39 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, 40 .ecc_stat_offset = CV_DRAMSTS_OFST, 41 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, 42 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, 43 .ecc_saddr_offset = CV_ERRADDR_OFST, 44 .ecc_daddr_offset = CV_ERRADDR_OFST, 45 .ecc_cecnt_offset = CV_SBECOUNT_OFST, 46 .ecc_uecnt_offset = CV_DBECOUNT_OFST, 47 .ecc_irq_en_offset = CV_DRAMINTR_OFST, 48 .ecc_irq_en_mask = CV_DRAMINTR_INTREN, 49 .ecc_irq_clr_offset = CV_DRAMINTR_OFST, 50 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), 51 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, 52 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, 53 .ce_ue_trgr_offset = CV_CTLCFG_OFST, 54 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, 55 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, 56 }; 57 58 static const struct altr_sdram_prv_data a10_data = { 59 .ecc_ctrl_offset = A10_ECCCTRL1_OFST, 60 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, 61 .ecc_stat_offset = A10_INTSTAT_OFST, 62 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, 63 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, 64 .ecc_saddr_offset = A10_SERRADDR_OFST, 65 .ecc_daddr_offset = A10_DERRADDR_OFST, 66 .ecc_irq_en_offset = A10_ERRINTEN_OFST, 67 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, 68 .ecc_irq_clr_offset = A10_INTSTAT_OFST, 69 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), 70 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, 71 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, 72 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, 73 .ce_set_mask = A10_DIAGINT_TSERRA_MASK, 74 .ue_set_mask = A10_DIAGINT_TDERRA_MASK, 75 }; 76 77 /*********************** EDAC Memory Controller Functions ****************/ 78 79 /* The SDRAM controller uses the EDAC Memory Controller framework. */ 80 81 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) 82 { 83 struct mem_ctl_info *mci = dev_id; 84 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 85 const struct altr_sdram_prv_data *priv = drvdata->data; 86 u32 status, err_count = 1, err_addr; 87 88 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); 89 90 if (status & priv->ecc_stat_ue_mask) { 91 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, 92 &err_addr); 93 if (priv->ecc_uecnt_offset) 94 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, 95 &err_count); 96 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", 97 err_count, err_addr); 98 } 99 if (status & priv->ecc_stat_ce_mask) { 100 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, 101 &err_addr); 102 if (priv->ecc_uecnt_offset) 103 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, 104 &err_count); 105 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, 106 err_addr >> PAGE_SHIFT, 107 err_addr & ~PAGE_MASK, 0, 108 0, 0, -1, mci->ctl_name, ""); 109 /* Clear IRQ to resume */ 110 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, 111 priv->ecc_irq_clr_mask); 112 113 return IRQ_HANDLED; 114 } 115 return IRQ_NONE; 116 } 117 118 static ssize_t altr_sdr_mc_err_inject_write(struct file *file, 119 const char __user *data, 120 size_t count, loff_t *ppos) 121 { 122 struct mem_ctl_info *mci = file->private_data; 123 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 124 const struct altr_sdram_prv_data *priv = drvdata->data; 125 u32 *ptemp; 126 dma_addr_t dma_handle; 127 u32 reg, read_reg; 128 129 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); 130 if (!ptemp) { 131 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 132 edac_printk(KERN_ERR, EDAC_MC, 133 "Inject: Buffer Allocation error\n"); 134 return -ENOMEM; 135 } 136 137 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 138 &read_reg); 139 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); 140 141 /* Error are injected by writing a word while the SBE or DBE 142 * bit in the CTLCFG register is set. Reading the word will 143 * trigger the SBE or DBE error and the corresponding IRQ. 144 */ 145 if (count == 3) { 146 edac_printk(KERN_ALERT, EDAC_MC, 147 "Inject Double bit error\n"); 148 local_irq_disable(); 149 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 150 (read_reg | priv->ue_set_mask)); 151 local_irq_enable(); 152 } else { 153 edac_printk(KERN_ALERT, EDAC_MC, 154 "Inject Single bit error\n"); 155 local_irq_disable(); 156 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 157 (read_reg | priv->ce_set_mask)); 158 local_irq_enable(); 159 } 160 161 ptemp[0] = 0x5A5A5A5A; 162 ptemp[1] = 0xA5A5A5A5; 163 164 /* Clear the error injection bits */ 165 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); 166 /* Ensure it has been written out */ 167 wmb(); 168 169 /* 170 * To trigger the error, we need to read the data back 171 * (the data was written with errors above). 172 * The READ_ONCE macros and printk are used to prevent the 173 * the compiler optimizing these reads out. 174 */ 175 reg = READ_ONCE(ptemp[0]); 176 read_reg = READ_ONCE(ptemp[1]); 177 /* Force Read */ 178 rmb(); 179 180 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", 181 reg, read_reg); 182 183 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 184 185 return count; 186 } 187 188 static const struct file_operations altr_sdr_mc_debug_inject_fops = { 189 .open = simple_open, 190 .write = altr_sdr_mc_err_inject_write, 191 .llseek = generic_file_llseek, 192 }; 193 194 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) 195 { 196 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 197 return; 198 199 if (!mci->debugfs) 200 return; 201 202 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci, 203 &altr_sdr_mc_debug_inject_fops); 204 } 205 206 /* Get total memory size from Open Firmware DTB */ 207 static unsigned long get_total_mem(void) 208 { 209 struct device_node *np = NULL; 210 struct resource res; 211 int ret; 212 unsigned long total_mem = 0; 213 214 for_each_node_by_type(np, "memory") { 215 ret = of_address_to_resource(np, 0, &res); 216 if (ret) 217 continue; 218 219 total_mem += resource_size(&res); 220 } 221 edac_dbg(0, "total_mem 0x%lx\n", total_mem); 222 return total_mem; 223 } 224 225 static const struct of_device_id altr_sdram_ctrl_of_match[] = { 226 { .compatible = "altr,sdram-edac", .data = &c5_data}, 227 { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, 228 {}, 229 }; 230 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); 231 232 static int a10_init(struct regmap *mc_vbase) 233 { 234 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, 235 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { 236 edac_printk(KERN_ERR, EDAC_MC, 237 "Error setting SB IRQ mode\n"); 238 return -ENODEV; 239 } 240 241 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { 242 edac_printk(KERN_ERR, EDAC_MC, 243 "Error setting trigger count\n"); 244 return -ENODEV; 245 } 246 247 return 0; 248 } 249 250 static int a10_unmask_irq(struct platform_device *pdev, u32 mask) 251 { 252 void __iomem *sm_base; 253 int ret = 0; 254 255 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), 256 dev_name(&pdev->dev))) { 257 edac_printk(KERN_ERR, EDAC_MC, 258 "Unable to request mem region\n"); 259 return -EBUSY; 260 } 261 262 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 263 if (!sm_base) { 264 edac_printk(KERN_ERR, EDAC_MC, 265 "Unable to ioremap device\n"); 266 267 ret = -ENOMEM; 268 goto release; 269 } 270 271 iowrite32(mask, sm_base); 272 273 iounmap(sm_base); 274 275 release: 276 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 277 278 return ret; 279 } 280 281 static int altr_sdram_probe(struct platform_device *pdev) 282 { 283 struct edac_mc_layer layers[2]; 284 struct mem_ctl_info *mci; 285 struct altr_sdram_mc_data *drvdata; 286 const struct altr_sdram_prv_data *priv; 287 struct regmap *mc_vbase; 288 struct dimm_info *dimm; 289 u32 read_reg; 290 int irq, irq2, res = 0; 291 unsigned long mem_size, irqflags = 0; 292 293 /* Grab the register range from the sdr controller in device tree */ 294 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 295 "altr,sdr-syscon"); 296 if (IS_ERR(mc_vbase)) { 297 edac_printk(KERN_ERR, EDAC_MC, 298 "regmap for altr,sdr-syscon lookup failed.\n"); 299 return -ENODEV; 300 } 301 302 /* Check specific dependencies for the module */ 303 priv = device_get_match_data(&pdev->dev); 304 305 /* Validate the SDRAM controller has ECC enabled */ 306 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || 307 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { 308 edac_printk(KERN_ERR, EDAC_MC, 309 "No ECC/ECC disabled [0x%08X]\n", read_reg); 310 return -ENODEV; 311 } 312 313 /* Grab memory size from device tree. */ 314 mem_size = get_total_mem(); 315 if (!mem_size) { 316 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); 317 return -ENODEV; 318 } 319 320 /* Ensure the SDRAM Interrupt is disabled */ 321 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, 322 priv->ecc_irq_en_mask, 0)) { 323 edac_printk(KERN_ERR, EDAC_MC, 324 "Error disabling SDRAM ECC IRQ\n"); 325 return -ENODEV; 326 } 327 328 /* Toggle to clear the SDRAM Error count */ 329 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 330 priv->ecc_cnt_rst_mask, 331 priv->ecc_cnt_rst_mask)) { 332 edac_printk(KERN_ERR, EDAC_MC, 333 "Error clearing SDRAM ECC count\n"); 334 return -ENODEV; 335 } 336 337 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 338 priv->ecc_cnt_rst_mask, 0)) { 339 edac_printk(KERN_ERR, EDAC_MC, 340 "Error clearing SDRAM ECC count\n"); 341 return -ENODEV; 342 } 343 344 irq = platform_get_irq(pdev, 0); 345 if (irq < 0) { 346 edac_printk(KERN_ERR, EDAC_MC, 347 "No irq %d in DT\n", irq); 348 return irq; 349 } 350 351 /* Arria10 has a 2nd IRQ */ 352 irq2 = platform_get_irq(pdev, 1); 353 354 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 355 layers[0].size = 1; 356 layers[0].is_virt_csrow = true; 357 layers[1].type = EDAC_MC_LAYER_CHANNEL; 358 layers[1].size = 1; 359 layers[1].is_virt_csrow = false; 360 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 361 sizeof(struct altr_sdram_mc_data)); 362 if (!mci) 363 return -ENOMEM; 364 365 mci->pdev = &pdev->dev; 366 drvdata = mci->pvt_info; 367 drvdata->mc_vbase = mc_vbase; 368 drvdata->data = priv; 369 platform_set_drvdata(pdev, mci); 370 371 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 372 edac_printk(KERN_ERR, EDAC_MC, 373 "Unable to get managed device resource\n"); 374 res = -ENOMEM; 375 goto free; 376 } 377 378 mci->mtype_cap = MEM_FLAG_DDR3; 379 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 380 mci->edac_cap = EDAC_FLAG_SECDED; 381 mci->mod_name = EDAC_MOD_STR; 382 mci->ctl_name = dev_name(&pdev->dev); 383 mci->scrub_mode = SCRUB_SW_SRC; 384 mci->dev_name = dev_name(&pdev->dev); 385 386 dimm = *mci->dimms; 387 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; 388 dimm->grain = 8; 389 dimm->dtype = DEV_X8; 390 dimm->mtype = MEM_DDR3; 391 dimm->edac_mode = EDAC_SECDED; 392 393 res = edac_mc_add_mc(mci); 394 if (res < 0) 395 goto err; 396 397 /* Only the Arria10 has separate IRQs */ 398 if (of_machine_is_compatible("altr,socfpga-arria10")) { 399 /* Arria10 specific initialization */ 400 res = a10_init(mc_vbase); 401 if (res < 0) 402 goto err2; 403 404 res = devm_request_irq(&pdev->dev, irq2, 405 altr_sdram_mc_err_handler, 406 IRQF_SHARED, dev_name(&pdev->dev), mci); 407 if (res < 0) { 408 edac_mc_printk(mci, KERN_ERR, 409 "Unable to request irq %d\n", irq2); 410 res = -ENODEV; 411 goto err2; 412 } 413 414 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); 415 if (res < 0) 416 goto err2; 417 418 irqflags = IRQF_SHARED; 419 } 420 421 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, 422 irqflags, dev_name(&pdev->dev), mci); 423 if (res < 0) { 424 edac_mc_printk(mci, KERN_ERR, 425 "Unable to request irq %d\n", irq); 426 res = -ENODEV; 427 goto err2; 428 } 429 430 /* Infrastructure ready - enable the IRQ */ 431 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, 432 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { 433 edac_mc_printk(mci, KERN_ERR, 434 "Error enabling SDRAM ECC IRQ\n"); 435 res = -ENODEV; 436 goto err2; 437 } 438 439 altr_sdr_mc_create_debugfs_nodes(mci); 440 441 devres_close_group(&pdev->dev, NULL); 442 443 return 0; 444 445 err2: 446 edac_mc_del_mc(&pdev->dev); 447 err: 448 devres_release_group(&pdev->dev, NULL); 449 free: 450 edac_mc_free(mci); 451 edac_printk(KERN_ERR, EDAC_MC, 452 "EDAC Probe Failed; Error %d\n", res); 453 454 return res; 455 } 456 457 static void altr_sdram_remove(struct platform_device *pdev) 458 { 459 struct mem_ctl_info *mci = platform_get_drvdata(pdev); 460 461 edac_mc_del_mc(&pdev->dev); 462 edac_mc_free(mci); 463 platform_set_drvdata(pdev, NULL); 464 } 465 466 /* 467 * If you want to suspend, need to disable EDAC by removing it 468 * from the device tree or defconfig. 469 */ 470 #ifdef CONFIG_PM 471 static int altr_sdram_prepare(struct device *dev) 472 { 473 pr_err("Suspend not allowed when EDAC is enabled.\n"); 474 475 return -EPERM; 476 } 477 478 static const struct dev_pm_ops altr_sdram_pm_ops = { 479 .prepare = altr_sdram_prepare, 480 }; 481 #endif 482 483 static struct platform_driver altr_sdram_edac_driver = { 484 .probe = altr_sdram_probe, 485 .remove_new = altr_sdram_remove, 486 .driver = { 487 .name = "altr_sdram_edac", 488 #ifdef CONFIG_PM 489 .pm = &altr_sdram_pm_ops, 490 #endif 491 .of_match_table = altr_sdram_ctrl_of_match, 492 }, 493 }; 494 495 module_platform_driver(altr_sdram_edac_driver); 496 497 #endif /* CONFIG_EDAC_ALTERA_SDRAM */ 498 499 /************************* EDAC Parent Probe *************************/ 500 501 static const struct of_device_id altr_edac_device_of_match[]; 502 503 static const struct of_device_id altr_edac_of_match[] = { 504 { .compatible = "altr,socfpga-ecc-manager" }, 505 {}, 506 }; 507 MODULE_DEVICE_TABLE(of, altr_edac_of_match); 508 509 static int altr_edac_probe(struct platform_device *pdev) 510 { 511 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, 512 NULL, &pdev->dev); 513 return 0; 514 } 515 516 static struct platform_driver altr_edac_driver = { 517 .probe = altr_edac_probe, 518 .driver = { 519 .name = "socfpga_ecc_manager", 520 .of_match_table = altr_edac_of_match, 521 }, 522 }; 523 module_platform_driver(altr_edac_driver); 524 525 /************************* EDAC Device Functions *************************/ 526 527 /* 528 * EDAC Device Functions (shared between various IPs). 529 * The discrete memories use the EDAC Device framework. The probe 530 * and error handling functions are very similar between memories 531 * so they are shared. The memory allocation and freeing for EDAC 532 * trigger testing are different for each memory. 533 */ 534 535 #ifdef CONFIG_EDAC_ALTERA_OCRAM 536 static const struct edac_device_prv_data ocramecc_data; 537 #endif 538 #ifdef CONFIG_EDAC_ALTERA_L2C 539 static const struct edac_device_prv_data l2ecc_data; 540 #endif 541 #ifdef CONFIG_EDAC_ALTERA_OCRAM 542 static const struct edac_device_prv_data a10_ocramecc_data; 543 #endif 544 #ifdef CONFIG_EDAC_ALTERA_L2C 545 static const struct edac_device_prv_data a10_l2ecc_data; 546 #endif 547 548 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) 549 { 550 irqreturn_t ret_value = IRQ_NONE; 551 struct edac_device_ctl_info *dci = dev_id; 552 struct altr_edac_device_dev *drvdata = dci->pvt_info; 553 const struct edac_device_prv_data *priv = drvdata->data; 554 555 if (irq == drvdata->sb_irq) { 556 if (priv->ce_clear_mask) 557 writel(priv->ce_clear_mask, drvdata->base); 558 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); 559 ret_value = IRQ_HANDLED; 560 } else if (irq == drvdata->db_irq) { 561 if (priv->ue_clear_mask) 562 writel(priv->ue_clear_mask, drvdata->base); 563 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); 564 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 565 ret_value = IRQ_HANDLED; 566 } else { 567 WARN_ON(1); 568 } 569 570 return ret_value; 571 } 572 573 static ssize_t __maybe_unused 574 altr_edac_device_trig(struct file *file, const char __user *user_buf, 575 size_t count, loff_t *ppos) 576 577 { 578 u32 *ptemp, i, error_mask; 579 int result = 0; 580 u8 trig_type; 581 unsigned long flags; 582 struct edac_device_ctl_info *edac_dci = file->private_data; 583 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 584 const struct edac_device_prv_data *priv = drvdata->data; 585 void *generic_ptr = edac_dci->dev; 586 587 if (!user_buf || get_user(trig_type, user_buf)) 588 return -EFAULT; 589 590 if (!priv->alloc_mem) 591 return -ENOMEM; 592 593 /* 594 * Note that generic_ptr is initialized to the device * but in 595 * some alloc_functions, this is overridden and returns data. 596 */ 597 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); 598 if (!ptemp) { 599 edac_printk(KERN_ERR, EDAC_DEVICE, 600 "Inject: Buffer Allocation error\n"); 601 return -ENOMEM; 602 } 603 604 if (trig_type == ALTR_UE_TRIGGER_CHAR) 605 error_mask = priv->ue_set_mask; 606 else 607 error_mask = priv->ce_set_mask; 608 609 edac_printk(KERN_ALERT, EDAC_DEVICE, 610 "Trigger Error Mask (0x%X)\n", error_mask); 611 612 local_irq_save(flags); 613 /* write ECC corrupted data out. */ 614 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { 615 /* Read data so we're in the correct state */ 616 rmb(); 617 if (READ_ONCE(ptemp[i])) 618 result = -1; 619 /* Toggle Error bit (it is latched), leave ECC enabled */ 620 writel(error_mask, (drvdata->base + priv->set_err_ofst)); 621 writel(priv->ecc_enable_mask, (drvdata->base + 622 priv->set_err_ofst)); 623 ptemp[i] = i; 624 } 625 /* Ensure it has been written out */ 626 wmb(); 627 local_irq_restore(flags); 628 629 if (result) 630 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); 631 632 /* Read out written data. ECC error caused here */ 633 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) 634 if (READ_ONCE(ptemp[i]) != i) 635 edac_printk(KERN_ERR, EDAC_DEVICE, 636 "Read doesn't match written data\n"); 637 638 if (priv->free_mem) 639 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); 640 641 return count; 642 } 643 644 static const struct file_operations altr_edac_device_inject_fops __maybe_unused = { 645 .open = simple_open, 646 .write = altr_edac_device_trig, 647 .llseek = generic_file_llseek, 648 }; 649 650 static ssize_t __maybe_unused 651 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf, 652 size_t count, loff_t *ppos); 653 654 static const struct file_operations altr_edac_a10_device_inject_fops __maybe_unused = { 655 .open = simple_open, 656 .write = altr_edac_a10_device_trig, 657 .llseek = generic_file_llseek, 658 }; 659 660 static ssize_t __maybe_unused 661 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf, 662 size_t count, loff_t *ppos); 663 664 static const struct file_operations altr_edac_a10_device_inject2_fops __maybe_unused = { 665 .open = simple_open, 666 .write = altr_edac_a10_device_trig2, 667 .llseek = generic_file_llseek, 668 }; 669 670 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, 671 const struct edac_device_prv_data *priv) 672 { 673 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 674 675 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 676 return; 677 678 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); 679 if (!drvdata->debugfs_dir) 680 return; 681 682 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR, 683 drvdata->debugfs_dir, edac_dci, 684 priv->inject_fops)) 685 debugfs_remove_recursive(drvdata->debugfs_dir); 686 } 687 688 static const struct of_device_id altr_edac_device_of_match[] = { 689 #ifdef CONFIG_EDAC_ALTERA_L2C 690 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, 691 #endif 692 #ifdef CONFIG_EDAC_ALTERA_OCRAM 693 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, 694 #endif 695 {}, 696 }; 697 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); 698 699 /* 700 * altr_edac_device_probe() 701 * This is a generic EDAC device driver that will support 702 * various Altera memory devices such as the L2 cache ECC and 703 * OCRAM ECC as well as the memories for other peripherals. 704 * Module specific initialization is done by passing the 705 * function index in the device tree. 706 */ 707 static int altr_edac_device_probe(struct platform_device *pdev) 708 { 709 struct edac_device_ctl_info *dci; 710 struct altr_edac_device_dev *drvdata; 711 struct resource *r; 712 int res = 0; 713 struct device_node *np = pdev->dev.of_node; 714 char *ecc_name = (char *)np->name; 715 static int dev_instance; 716 717 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 718 edac_printk(KERN_ERR, EDAC_DEVICE, 719 "Unable to open devm\n"); 720 return -ENOMEM; 721 } 722 723 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 724 if (!r) { 725 edac_printk(KERN_ERR, EDAC_DEVICE, 726 "Unable to get mem resource\n"); 727 res = -ENODEV; 728 goto fail; 729 } 730 731 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), 732 dev_name(&pdev->dev))) { 733 edac_printk(KERN_ERR, EDAC_DEVICE, 734 "%s:Error requesting mem region\n", ecc_name); 735 res = -EBUSY; 736 goto fail; 737 } 738 739 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, 740 1, ecc_name, 1, 0, NULL, 0, 741 dev_instance++); 742 743 if (!dci) { 744 edac_printk(KERN_ERR, EDAC_DEVICE, 745 "%s: Unable to allocate EDAC device\n", ecc_name); 746 res = -ENOMEM; 747 goto fail; 748 } 749 750 drvdata = dci->pvt_info; 751 dci->dev = &pdev->dev; 752 platform_set_drvdata(pdev, dci); 753 drvdata->edac_dev_name = ecc_name; 754 755 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 756 if (!drvdata->base) { 757 res = -ENOMEM; 758 goto fail1; 759 } 760 761 /* Get driver specific data for this EDAC device */ 762 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; 763 764 /* Check specific dependencies for the module */ 765 if (drvdata->data->setup) { 766 res = drvdata->data->setup(drvdata); 767 if (res) 768 goto fail1; 769 } 770 771 drvdata->sb_irq = platform_get_irq(pdev, 0); 772 res = devm_request_irq(&pdev->dev, drvdata->sb_irq, 773 altr_edac_device_handler, 774 0, dev_name(&pdev->dev), dci); 775 if (res) 776 goto fail1; 777 778 drvdata->db_irq = platform_get_irq(pdev, 1); 779 res = devm_request_irq(&pdev->dev, drvdata->db_irq, 780 altr_edac_device_handler, 781 0, dev_name(&pdev->dev), dci); 782 if (res) 783 goto fail1; 784 785 dci->mod_name = "Altera ECC Manager"; 786 dci->dev_name = drvdata->edac_dev_name; 787 788 res = edac_device_add_device(dci); 789 if (res) 790 goto fail1; 791 792 altr_create_edacdev_dbgfs(dci, drvdata->data); 793 794 devres_close_group(&pdev->dev, NULL); 795 796 return 0; 797 798 fail1: 799 edac_device_free_ctl_info(dci); 800 fail: 801 devres_release_group(&pdev->dev, NULL); 802 edac_printk(KERN_ERR, EDAC_DEVICE, 803 "%s:Error setting up EDAC device: %d\n", ecc_name, res); 804 805 return res; 806 } 807 808 static void altr_edac_device_remove(struct platform_device *pdev) 809 { 810 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev); 811 struct altr_edac_device_dev *drvdata = dci->pvt_info; 812 813 debugfs_remove_recursive(drvdata->debugfs_dir); 814 edac_device_del_device(&pdev->dev); 815 edac_device_free_ctl_info(dci); 816 } 817 818 static struct platform_driver altr_edac_device_driver = { 819 .probe = altr_edac_device_probe, 820 .remove_new = altr_edac_device_remove, 821 .driver = { 822 .name = "altr_edac_device", 823 .of_match_table = altr_edac_device_of_match, 824 }, 825 }; 826 module_platform_driver(altr_edac_device_driver); 827 828 /******************* Arria10 Device ECC Shared Functions *****************/ 829 830 /* 831 * Test for memory's ECC dependencies upon entry because platform specific 832 * startup should have initialized the memory and enabled the ECC. 833 * Can't turn on ECC here because accessing un-initialized memory will 834 * cause CE/UE errors possibly causing an ABORT. 835 */ 836 static int __maybe_unused 837 altr_check_ecc_deps(struct altr_edac_device_dev *device) 838 { 839 void __iomem *base = device->base; 840 const struct edac_device_prv_data *prv = device->data; 841 842 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) 843 return 0; 844 845 edac_printk(KERN_ERR, EDAC_DEVICE, 846 "%s: No ECC present or ECC disabled.\n", 847 device->edac_dev_name); 848 return -ENODEV; 849 } 850 851 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id) 852 { 853 struct altr_edac_device_dev *dci = dev_id; 854 void __iomem *base = dci->base; 855 856 if (irq == dci->sb_irq) { 857 writel(ALTR_A10_ECC_SERRPENA, 858 base + ALTR_A10_ECC_INTSTAT_OFST); 859 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 860 861 return IRQ_HANDLED; 862 } else if (irq == dci->db_irq) { 863 writel(ALTR_A10_ECC_DERRPENA, 864 base + ALTR_A10_ECC_INTSTAT_OFST); 865 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 866 if (dci->data->panic) 867 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 868 869 return IRQ_HANDLED; 870 } 871 872 WARN_ON(1); 873 874 return IRQ_NONE; 875 } 876 877 /******************* Arria10 Memory Buffer Functions *********************/ 878 879 static inline int a10_get_irq_mask(struct device_node *np) 880 { 881 int irq; 882 const u32 *handle = of_get_property(np, "interrupts", NULL); 883 884 if (!handle) 885 return -ENODEV; 886 irq = be32_to_cpup(handle); 887 return irq; 888 } 889 890 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) 891 { 892 u32 value = readl(ioaddr); 893 894 value |= bit_mask; 895 writel(value, ioaddr); 896 } 897 898 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) 899 { 900 u32 value = readl(ioaddr); 901 902 value &= ~bit_mask; 903 writel(value, ioaddr); 904 } 905 906 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) 907 { 908 u32 value = readl(ioaddr); 909 910 return (value & bit_mask) ? 1 : 0; 911 } 912 913 /* 914 * This function uses the memory initialization block in the Arria10 ECC 915 * controller to initialize/clear the entire memory data and ECC data. 916 */ 917 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port) 918 { 919 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; 920 u32 init_mask, stat_mask, clear_mask; 921 int ret = 0; 922 923 if (port) { 924 init_mask = ALTR_A10_ECC_INITB; 925 stat_mask = ALTR_A10_ECC_INITCOMPLETEB; 926 clear_mask = ALTR_A10_ECC_ERRPENB_MASK; 927 } else { 928 init_mask = ALTR_A10_ECC_INITA; 929 stat_mask = ALTR_A10_ECC_INITCOMPLETEA; 930 clear_mask = ALTR_A10_ECC_ERRPENA_MASK; 931 } 932 933 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); 934 while (limit--) { 935 if (ecc_test_bits(stat_mask, 936 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) 937 break; 938 udelay(1); 939 } 940 if (limit < 0) 941 ret = -EBUSY; 942 943 /* Clear any pending ECC interrupts */ 944 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); 945 946 return ret; 947 } 948 949 static __init int __maybe_unused 950 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, 951 u32 ecc_ctrl_en_mask, bool dual_port) 952 { 953 int ret = 0; 954 void __iomem *ecc_block_base; 955 struct regmap *ecc_mgr_map; 956 char *ecc_name; 957 struct device_node *np_eccmgr; 958 959 ecc_name = (char *)np->name; 960 961 /* Get the ECC Manager - parent of the device EDACs */ 962 np_eccmgr = of_get_parent(np); 963 964 ecc_mgr_map = 965 altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr, 966 "altr,sysmgr-syscon"); 967 968 of_node_put(np_eccmgr); 969 if (IS_ERR(ecc_mgr_map)) { 970 edac_printk(KERN_ERR, EDAC_DEVICE, 971 "Unable to get syscon altr,sysmgr-syscon\n"); 972 return -ENODEV; 973 } 974 975 /* Map the ECC Block */ 976 ecc_block_base = of_iomap(np, 0); 977 if (!ecc_block_base) { 978 edac_printk(KERN_ERR, EDAC_DEVICE, 979 "Unable to map %s ECC block\n", ecc_name); 980 return -ENODEV; 981 } 982 983 /* Disable ECC */ 984 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask); 985 writel(ALTR_A10_ECC_SERRINTEN, 986 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST)); 987 ecc_clear_bits(ecc_ctrl_en_mask, 988 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); 989 /* Ensure all writes complete */ 990 wmb(); 991 /* Use HW initialization block to initialize memory for ECC */ 992 ret = altr_init_memory_port(ecc_block_base, 0); 993 if (ret) { 994 edac_printk(KERN_ERR, EDAC_DEVICE, 995 "ECC: cannot init %s PORTA memory\n", ecc_name); 996 goto out; 997 } 998 999 if (dual_port) { 1000 ret = altr_init_memory_port(ecc_block_base, 1); 1001 if (ret) { 1002 edac_printk(KERN_ERR, EDAC_DEVICE, 1003 "ECC: cannot init %s PORTB memory\n", 1004 ecc_name); 1005 goto out; 1006 } 1007 } 1008 1009 /* Interrupt mode set to every SBERR */ 1010 regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST, 1011 ALTR_A10_ECC_INTMODE); 1012 /* Enable ECC */ 1013 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base + 1014 ALTR_A10_ECC_CTRL_OFST)); 1015 writel(ALTR_A10_ECC_SERRINTEN, 1016 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST)); 1017 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask); 1018 /* Ensure all writes complete */ 1019 wmb(); 1020 out: 1021 iounmap(ecc_block_base); 1022 return ret; 1023 } 1024 1025 static int validate_parent_available(struct device_node *np); 1026 static const struct of_device_id altr_edac_a10_device_of_match[]; 1027 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat) 1028 { 1029 int irq; 1030 struct device_node *child, *np; 1031 1032 np = of_find_compatible_node(NULL, NULL, 1033 "altr,socfpga-a10-ecc-manager"); 1034 if (!np) { 1035 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n"); 1036 return -ENODEV; 1037 } 1038 1039 for_each_child_of_node(np, child) { 1040 const struct of_device_id *pdev_id; 1041 const struct edac_device_prv_data *prv; 1042 1043 if (!of_device_is_available(child)) 1044 continue; 1045 if (!of_device_is_compatible(child, compat)) 1046 continue; 1047 1048 if (validate_parent_available(child)) 1049 continue; 1050 1051 irq = a10_get_irq_mask(child); 1052 if (irq < 0) 1053 continue; 1054 1055 /* Get matching node and check for valid result */ 1056 pdev_id = of_match_node(altr_edac_a10_device_of_match, child); 1057 if (IS_ERR_OR_NULL(pdev_id)) 1058 continue; 1059 1060 /* Validate private data pointer before dereferencing */ 1061 prv = pdev_id->data; 1062 if (!prv) 1063 continue; 1064 1065 altr_init_a10_ecc_block(child, BIT(irq), 1066 prv->ecc_enable_mask, 0); 1067 } 1068 1069 of_node_put(np); 1070 return 0; 1071 } 1072 1073 /*********************** SDRAM EDAC Device Functions *********************/ 1074 1075 #ifdef CONFIG_EDAC_ALTERA_SDRAM 1076 1077 /* 1078 * A legacy U-Boot bug only enabled memory mapped access to the ECC Enable 1079 * register if ECC is enabled. Linux checks the ECC Enable register to 1080 * determine ECC status. 1081 * Use an SMC call (which always works) to determine ECC enablement. 1082 */ 1083 static int altr_s10_sdram_check_ecc_deps(struct altr_edac_device_dev *device) 1084 { 1085 const struct edac_device_prv_data *prv = device->data; 1086 unsigned long sdram_ecc_addr; 1087 struct arm_smccc_res result; 1088 struct device_node *np; 1089 phys_addr_t sdram_addr; 1090 u32 read_reg; 1091 int ret; 1092 1093 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl"); 1094 if (!np) 1095 goto sdram_err; 1096 1097 sdram_addr = of_translate_address(np, of_get_address(np, 0, 1098 NULL, NULL)); 1099 of_node_put(np); 1100 sdram_ecc_addr = (unsigned long)sdram_addr + prv->ecc_en_ofst; 1101 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sdram_ecc_addr, 1102 0, 0, 0, 0, 0, 0, &result); 1103 read_reg = (unsigned int)result.a1; 1104 ret = (int)result.a0; 1105 if (!ret && (read_reg & prv->ecc_enable_mask)) 1106 return 0; 1107 1108 sdram_err: 1109 edac_printk(KERN_ERR, EDAC_DEVICE, 1110 "%s: No ECC present or ECC disabled.\n", 1111 device->edac_dev_name); 1112 return -ENODEV; 1113 } 1114 1115 static const struct edac_device_prv_data s10_sdramecc_data = { 1116 .setup = altr_s10_sdram_check_ecc_deps, 1117 .ce_clear_mask = ALTR_S10_ECC_SERRPENA, 1118 .ue_clear_mask = ALTR_S10_ECC_DERRPENA, 1119 .ecc_enable_mask = ALTR_S10_ECC_EN, 1120 .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST, 1121 .ce_set_mask = ALTR_S10_ECC_TSERRA, 1122 .ue_set_mask = ALTR_S10_ECC_TDERRA, 1123 .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST, 1124 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1125 .inject_fops = &altr_edac_a10_device_inject_fops, 1126 }; 1127 #endif /* CONFIG_EDAC_ALTERA_SDRAM */ 1128 1129 /*********************** OCRAM EDAC Device Functions *********************/ 1130 1131 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1132 1133 static void *ocram_alloc_mem(size_t size, void **other) 1134 { 1135 struct device_node *np; 1136 struct gen_pool *gp; 1137 void *sram_addr; 1138 1139 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); 1140 if (!np) 1141 return NULL; 1142 1143 gp = of_gen_pool_get(np, "iram", 0); 1144 of_node_put(np); 1145 if (!gp) 1146 return NULL; 1147 1148 sram_addr = (void *)gen_pool_alloc(gp, size); 1149 if (!sram_addr) 1150 return NULL; 1151 1152 memset(sram_addr, 0, size); 1153 /* Ensure data is written out */ 1154 wmb(); 1155 1156 /* Remember this handle for freeing later */ 1157 *other = gp; 1158 1159 return sram_addr; 1160 } 1161 1162 static void ocram_free_mem(void *p, size_t size, void *other) 1163 { 1164 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size); 1165 } 1166 1167 static const struct edac_device_prv_data ocramecc_data = { 1168 .setup = altr_check_ecc_deps, 1169 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), 1170 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), 1171 .alloc_mem = ocram_alloc_mem, 1172 .free_mem = ocram_free_mem, 1173 .ecc_enable_mask = ALTR_OCR_ECC_EN, 1174 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, 1175 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), 1176 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), 1177 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, 1178 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, 1179 .inject_fops = &altr_edac_device_inject_fops, 1180 }; 1181 1182 static int __maybe_unused 1183 altr_check_ocram_deps_init(struct altr_edac_device_dev *device) 1184 { 1185 void __iomem *base = device->base; 1186 int ret; 1187 1188 ret = altr_check_ecc_deps(device); 1189 if (ret) 1190 return ret; 1191 1192 /* Verify OCRAM has been initialized */ 1193 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA, 1194 (base + ALTR_A10_ECC_INITSTAT_OFST))) 1195 return -ENODEV; 1196 1197 /* Enable IRQ on Single Bit Error */ 1198 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST)); 1199 /* Ensure all writes complete */ 1200 wmb(); 1201 1202 return 0; 1203 } 1204 1205 static const struct edac_device_prv_data a10_ocramecc_data = { 1206 .setup = altr_check_ocram_deps_init, 1207 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1208 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1209 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, 1210 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, 1211 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1212 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1213 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1214 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1215 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1216 .inject_fops = &altr_edac_a10_device_inject2_fops, 1217 /* 1218 * OCRAM panic on uncorrectable error because sleep/resume 1219 * functions and FPGA contents are stored in OCRAM. Prefer 1220 * a kernel panic over executing/loading corrupted data. 1221 */ 1222 .panic = true, 1223 }; 1224 1225 #endif /* CONFIG_EDAC_ALTERA_OCRAM */ 1226 1227 /********************* L2 Cache EDAC Device Functions ********************/ 1228 1229 #ifdef CONFIG_EDAC_ALTERA_L2C 1230 1231 static void *l2_alloc_mem(size_t size, void **other) 1232 { 1233 struct device *dev = *other; 1234 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); 1235 1236 if (!ptemp) 1237 return NULL; 1238 1239 /* Make sure everything is written out */ 1240 wmb(); 1241 1242 /* 1243 * Clean all cache levels up to LoC (includes L2) 1244 * This ensures the corrupted data is written into 1245 * L2 cache for readback test (which causes ECC error). 1246 */ 1247 flush_cache_all(); 1248 1249 return ptemp; 1250 } 1251 1252 static void l2_free_mem(void *p, size_t size, void *other) 1253 { 1254 struct device *dev = other; 1255 1256 if (dev && p) 1257 devm_kfree(dev, p); 1258 } 1259 1260 /* 1261 * altr_l2_check_deps() 1262 * Test for L2 cache ECC dependencies upon entry because 1263 * platform specific startup should have initialized the L2 1264 * memory and enabled the ECC. 1265 * Bail if ECC is not enabled. 1266 * Note that L2 Cache Enable is forced at build time. 1267 */ 1268 static int altr_l2_check_deps(struct altr_edac_device_dev *device) 1269 { 1270 void __iomem *base = device->base; 1271 const struct edac_device_prv_data *prv = device->data; 1272 1273 if ((readl(base) & prv->ecc_enable_mask) == 1274 prv->ecc_enable_mask) 1275 return 0; 1276 1277 edac_printk(KERN_ERR, EDAC_DEVICE, 1278 "L2: No ECC present, or ECC disabled\n"); 1279 return -ENODEV; 1280 } 1281 1282 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) 1283 { 1284 struct altr_edac_device_dev *dci = dev_id; 1285 1286 if (irq == dci->sb_irq) { 1287 regmap_write(dci->edac->ecc_mgr_map, 1288 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1289 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); 1290 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 1291 1292 return IRQ_HANDLED; 1293 } else if (irq == dci->db_irq) { 1294 regmap_write(dci->edac->ecc_mgr_map, 1295 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1296 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); 1297 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 1298 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 1299 1300 return IRQ_HANDLED; 1301 } 1302 1303 WARN_ON(1); 1304 1305 return IRQ_NONE; 1306 } 1307 1308 static const struct edac_device_prv_data l2ecc_data = { 1309 .setup = altr_l2_check_deps, 1310 .ce_clear_mask = 0, 1311 .ue_clear_mask = 0, 1312 .alloc_mem = l2_alloc_mem, 1313 .free_mem = l2_free_mem, 1314 .ecc_enable_mask = ALTR_L2_ECC_EN, 1315 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), 1316 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), 1317 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, 1318 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1319 .inject_fops = &altr_edac_device_inject_fops, 1320 }; 1321 1322 static const struct edac_device_prv_data a10_l2ecc_data = { 1323 .setup = altr_l2_check_deps, 1324 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, 1325 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, 1326 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, 1327 .alloc_mem = l2_alloc_mem, 1328 .free_mem = l2_free_mem, 1329 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, 1330 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, 1331 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, 1332 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, 1333 .ecc_irq_handler = altr_edac_a10_l2_irq, 1334 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1335 .inject_fops = &altr_edac_device_inject_fops, 1336 }; 1337 1338 #endif /* CONFIG_EDAC_ALTERA_L2C */ 1339 1340 /********************* Ethernet Device Functions ********************/ 1341 1342 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1343 1344 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev) 1345 { 1346 int ret; 1347 1348 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); 1349 if (ret) 1350 return ret; 1351 1352 return altr_check_ecc_deps(dev); 1353 } 1354 1355 static const struct edac_device_prv_data a10_enetecc_data = { 1356 .setup = socfpga_init_ethernet_ecc, 1357 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1358 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1359 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1360 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1361 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1362 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1363 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1364 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1365 .inject_fops = &altr_edac_a10_device_inject2_fops, 1366 }; 1367 1368 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ 1369 1370 /********************** NAND Device Functions **********************/ 1371 1372 #ifdef CONFIG_EDAC_ALTERA_NAND 1373 1374 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device) 1375 { 1376 int ret; 1377 1378 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); 1379 if (ret) 1380 return ret; 1381 1382 return altr_check_ecc_deps(device); 1383 } 1384 1385 static const struct edac_device_prv_data a10_nandecc_data = { 1386 .setup = socfpga_init_nand_ecc, 1387 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1388 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1389 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1390 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1391 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1392 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1393 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1394 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1395 .inject_fops = &altr_edac_a10_device_inject_fops, 1396 }; 1397 1398 #endif /* CONFIG_EDAC_ALTERA_NAND */ 1399 1400 /********************** DMA Device Functions **********************/ 1401 1402 #ifdef CONFIG_EDAC_ALTERA_DMA 1403 1404 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device) 1405 { 1406 int ret; 1407 1408 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); 1409 if (ret) 1410 return ret; 1411 1412 return altr_check_ecc_deps(device); 1413 } 1414 1415 static const struct edac_device_prv_data a10_dmaecc_data = { 1416 .setup = socfpga_init_dma_ecc, 1417 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1418 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1419 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1420 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1421 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1422 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1423 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1424 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1425 .inject_fops = &altr_edac_a10_device_inject_fops, 1426 }; 1427 1428 #endif /* CONFIG_EDAC_ALTERA_DMA */ 1429 1430 /********************** USB Device Functions **********************/ 1431 1432 #ifdef CONFIG_EDAC_ALTERA_USB 1433 1434 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device) 1435 { 1436 int ret; 1437 1438 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); 1439 if (ret) 1440 return ret; 1441 1442 return altr_check_ecc_deps(device); 1443 } 1444 1445 static const struct edac_device_prv_data a10_usbecc_data = { 1446 .setup = socfpga_init_usb_ecc, 1447 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1448 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1449 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1450 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1451 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1452 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1453 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1454 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1455 .inject_fops = &altr_edac_a10_device_inject2_fops, 1456 }; 1457 1458 #endif /* CONFIG_EDAC_ALTERA_USB */ 1459 1460 /********************** QSPI Device Functions **********************/ 1461 1462 #ifdef CONFIG_EDAC_ALTERA_QSPI 1463 1464 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device) 1465 { 1466 int ret; 1467 1468 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); 1469 if (ret) 1470 return ret; 1471 1472 return altr_check_ecc_deps(device); 1473 } 1474 1475 static const struct edac_device_prv_data a10_qspiecc_data = { 1476 .setup = socfpga_init_qspi_ecc, 1477 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1478 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1479 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1480 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1481 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1482 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1483 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1484 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1485 .inject_fops = &altr_edac_a10_device_inject_fops, 1486 }; 1487 1488 #endif /* CONFIG_EDAC_ALTERA_QSPI */ 1489 1490 /********************* SDMMC Device Functions **********************/ 1491 1492 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1493 1494 static const struct edac_device_prv_data a10_sdmmceccb_data; 1495 static int altr_portb_setup(struct altr_edac_device_dev *device) 1496 { 1497 struct edac_device_ctl_info *dci; 1498 struct altr_edac_device_dev *altdev; 1499 char *ecc_name = "sdmmcb-ecc"; 1500 int edac_idx, rc; 1501 struct device_node *np; 1502 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; 1503 1504 rc = altr_check_ecc_deps(device); 1505 if (rc) 1506 return rc; 1507 1508 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1509 if (!np) { 1510 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); 1511 return -ENODEV; 1512 } 1513 1514 /* Create the PortB EDAC device */ 1515 edac_idx = edac_device_alloc_index(); 1516 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, 1517 ecc_name, 1, 0, NULL, 0, edac_idx); 1518 if (!dci) { 1519 edac_printk(KERN_ERR, EDAC_DEVICE, 1520 "%s: Unable to allocate PortB EDAC device\n", 1521 ecc_name); 1522 return -ENOMEM; 1523 } 1524 1525 /* Initialize the PortB EDAC device structure from PortA structure */ 1526 altdev = dci->pvt_info; 1527 *altdev = *device; 1528 1529 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL)) 1530 return -ENOMEM; 1531 1532 /* Update PortB specific values */ 1533 altdev->edac_dev_name = ecc_name; 1534 altdev->edac_idx = edac_idx; 1535 altdev->edac_dev = dci; 1536 altdev->data = prv; 1537 dci->dev = &altdev->ddev; 1538 dci->ctl_name = "Altera ECC Manager"; 1539 dci->mod_name = ecc_name; 1540 dci->dev_name = ecc_name; 1541 1542 /* 1543 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly 1544 * 1545 * FIXME: Instead of ifdefs with different architectures the driver 1546 * should properly use compatibles. 1547 */ 1548 #ifdef CONFIG_64BIT 1549 altdev->sb_irq = irq_of_parse_and_map(np, 1); 1550 #else 1551 altdev->sb_irq = irq_of_parse_and_map(np, 2); 1552 #endif 1553 if (!altdev->sb_irq) { 1554 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); 1555 rc = -ENODEV; 1556 goto err_release_group_1; 1557 } 1558 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq, 1559 prv->ecc_irq_handler, 1560 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1561 ecc_name, altdev); 1562 if (rc) { 1563 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); 1564 goto err_release_group_1; 1565 } 1566 1567 #ifdef CONFIG_64BIT 1568 /* Use IRQ to determine SError origin instead of assigning IRQ */ 1569 rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq); 1570 if (rc) { 1571 edac_printk(KERN_ERR, EDAC_DEVICE, 1572 "Error PortB DBIRQ alloc\n"); 1573 goto err_release_group_1; 1574 } 1575 #else 1576 altdev->db_irq = irq_of_parse_and_map(np, 3); 1577 if (!altdev->db_irq) { 1578 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); 1579 rc = -ENODEV; 1580 goto err_release_group_1; 1581 } 1582 rc = devm_request_irq(&altdev->ddev, altdev->db_irq, 1583 prv->ecc_irq_handler, 1584 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1585 ecc_name, altdev); 1586 if (rc) { 1587 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); 1588 goto err_release_group_1; 1589 } 1590 #endif 1591 1592 rc = edac_device_add_device(dci); 1593 if (rc) { 1594 edac_printk(KERN_ERR, EDAC_DEVICE, 1595 "edac_device_add_device portB failed\n"); 1596 rc = -ENOMEM; 1597 goto err_release_group_1; 1598 } 1599 altr_create_edacdev_dbgfs(dci, prv); 1600 1601 list_add(&altdev->next, &altdev->edac->a10_ecc_devices); 1602 1603 devres_remove_group(&altdev->ddev, altr_portb_setup); 1604 1605 return 0; 1606 1607 err_release_group_1: 1608 edac_device_free_ctl_info(dci); 1609 devres_release_group(&altdev->ddev, altr_portb_setup); 1610 edac_printk(KERN_ERR, EDAC_DEVICE, 1611 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 1612 return rc; 1613 } 1614 1615 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device) 1616 { 1617 int rc = -ENODEV; 1618 struct device_node *child; 1619 1620 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1621 if (!child) 1622 return -ENODEV; 1623 1624 if (!of_device_is_available(child)) 1625 goto exit; 1626 1627 if (validate_parent_available(child)) 1628 goto exit; 1629 1630 /* Init portB */ 1631 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, 1632 a10_sdmmceccb_data.ecc_enable_mask, 1); 1633 if (rc) 1634 goto exit; 1635 1636 /* Setup portB */ 1637 return altr_portb_setup(device); 1638 1639 exit: 1640 of_node_put(child); 1641 return rc; 1642 } 1643 1644 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) 1645 { 1646 struct altr_edac_device_dev *ad = dev_id; 1647 void __iomem *base = ad->base; 1648 const struct edac_device_prv_data *priv = ad->data; 1649 1650 if (irq == ad->sb_irq) { 1651 writel(priv->ce_clear_mask, 1652 base + ALTR_A10_ECC_INTSTAT_OFST); 1653 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); 1654 return IRQ_HANDLED; 1655 } else if (irq == ad->db_irq) { 1656 writel(priv->ue_clear_mask, 1657 base + ALTR_A10_ECC_INTSTAT_OFST); 1658 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); 1659 return IRQ_HANDLED; 1660 } 1661 1662 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); 1663 1664 return IRQ_NONE; 1665 } 1666 1667 static const struct edac_device_prv_data a10_sdmmcecca_data = { 1668 .setup = socfpga_init_sdmmc_ecc, 1669 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1670 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1671 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1672 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1673 .ce_set_mask = ALTR_A10_ECC_SERRPENA, 1674 .ue_set_mask = ALTR_A10_ECC_DERRPENA, 1675 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1676 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1677 .inject_fops = &altr_edac_a10_device_inject_fops, 1678 }; 1679 1680 static const struct edac_device_prv_data a10_sdmmceccb_data = { 1681 .setup = socfpga_init_sdmmc_ecc, 1682 .ce_clear_mask = ALTR_A10_ECC_SERRPENB, 1683 .ue_clear_mask = ALTR_A10_ECC_DERRPENB, 1684 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1685 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1686 .ce_set_mask = ALTR_A10_ECC_TSERRB, 1687 .ue_set_mask = ALTR_A10_ECC_TDERRB, 1688 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1689 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, 1690 .inject_fops = &altr_edac_a10_device_inject_fops, 1691 }; 1692 1693 #endif /* CONFIG_EDAC_ALTERA_SDMMC */ 1694 1695 /********************* Arria10 EDAC Device Functions *************************/ 1696 static const struct of_device_id altr_edac_a10_device_of_match[] = { 1697 #ifdef CONFIG_EDAC_ALTERA_L2C 1698 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, 1699 #endif 1700 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1701 { .compatible = "altr,socfpga-a10-ocram-ecc", 1702 .data = &a10_ocramecc_data }, 1703 #endif 1704 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1705 { .compatible = "altr,socfpga-eth-mac-ecc", 1706 .data = &a10_enetecc_data }, 1707 #endif 1708 #ifdef CONFIG_EDAC_ALTERA_NAND 1709 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, 1710 #endif 1711 #ifdef CONFIG_EDAC_ALTERA_DMA 1712 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, 1713 #endif 1714 #ifdef CONFIG_EDAC_ALTERA_USB 1715 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, 1716 #endif 1717 #ifdef CONFIG_EDAC_ALTERA_QSPI 1718 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, 1719 #endif 1720 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1721 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, 1722 #endif 1723 #ifdef CONFIG_EDAC_ALTERA_SDRAM 1724 { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data }, 1725 #endif 1726 {}, 1727 }; 1728 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); 1729 1730 /* 1731 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 1732 * because 2 IRQs are shared among the all ECC peripherals. The ECC 1733 * manager manages the IRQs and the children. 1734 * Based on xgene_edac.c peripheral code. 1735 */ 1736 1737 static ssize_t __maybe_unused 1738 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf, 1739 size_t count, loff_t *ppos) 1740 { 1741 struct edac_device_ctl_info *edac_dci = file->private_data; 1742 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 1743 const struct edac_device_prv_data *priv = drvdata->data; 1744 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); 1745 unsigned long flags; 1746 u8 trig_type; 1747 1748 if (!user_buf || get_user(trig_type, user_buf)) 1749 return -EFAULT; 1750 1751 local_irq_save(flags); 1752 if (trig_type == ALTR_UE_TRIGGER_CHAR) 1753 writel(priv->ue_set_mask, set_addr); 1754 else 1755 writel(priv->ce_set_mask, set_addr); 1756 1757 /* Ensure the interrupt test bits are set */ 1758 wmb(); 1759 local_irq_restore(flags); 1760 1761 return count; 1762 } 1763 1764 /* 1765 * The Stratix10 EDAC Error Injection Functions differ from Arria10 1766 * slightly. A few Arria10 peripherals can use this injection function. 1767 * Inject the error into the memory and then readback to trigger the IRQ. 1768 */ 1769 static ssize_t __maybe_unused 1770 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf, 1771 size_t count, loff_t *ppos) 1772 { 1773 struct edac_device_ctl_info *edac_dci = file->private_data; 1774 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 1775 const struct edac_device_prv_data *priv = drvdata->data; 1776 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); 1777 unsigned long flags; 1778 u8 trig_type; 1779 1780 if (!user_buf || get_user(trig_type, user_buf)) 1781 return -EFAULT; 1782 1783 local_irq_save(flags); 1784 if (trig_type == ALTR_UE_TRIGGER_CHAR) { 1785 writel(priv->ue_set_mask, set_addr); 1786 } else { 1787 /* Setup read/write of 4 bytes */ 1788 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST); 1789 /* Setup Address to 0 */ 1790 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST); 1791 /* Setup accctrl to read & ecc & data override */ 1792 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1793 /* Kick it. */ 1794 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1795 /* Setup write for single bit change */ 1796 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1, 1797 drvdata->base + ECC_BLK_WDATA0_OFST); 1798 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST), 1799 drvdata->base + ECC_BLK_WDATA1_OFST); 1800 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST), 1801 drvdata->base + ECC_BLK_WDATA2_OFST); 1802 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST), 1803 drvdata->base + ECC_BLK_WDATA3_OFST); 1804 1805 /* Copy Read ECC to Write ECC */ 1806 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST), 1807 drvdata->base + ECC_BLK_WECC0_OFST); 1808 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST), 1809 drvdata->base + ECC_BLK_WECC1_OFST); 1810 /* Setup accctrl to write & ecc override & data override */ 1811 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1812 /* Kick it. */ 1813 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1814 /* Setup accctrl to read & ecc overwrite & data overwrite */ 1815 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1816 /* Kick it. */ 1817 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1818 } 1819 1820 /* Ensure the interrupt test bits are set */ 1821 wmb(); 1822 local_irq_restore(flags); 1823 1824 return count; 1825 } 1826 1827 static void altr_edac_a10_irq_handler(struct irq_desc *desc) 1828 { 1829 int dberr, bit, sm_offset, irq_status; 1830 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); 1831 struct irq_chip *chip = irq_desc_get_chip(desc); 1832 int irq = irq_desc_get_irq(desc); 1833 unsigned long bits; 1834 1835 dberr = (irq == edac->db_irq) ? 1 : 0; 1836 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : 1837 A10_SYSMGR_ECC_INTSTAT_SERR_OFST; 1838 1839 chained_irq_enter(chip, desc); 1840 1841 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); 1842 1843 bits = irq_status; 1844 for_each_set_bit(bit, &bits, 32) 1845 generic_handle_domain_irq(edac->domain, dberr * 32 + bit); 1846 1847 chained_irq_exit(chip, desc); 1848 } 1849 1850 static int validate_parent_available(struct device_node *np) 1851 { 1852 struct device_node *parent; 1853 int ret = 0; 1854 1855 /* SDRAM must be present for Linux (implied parent) */ 1856 if (of_device_is_compatible(np, "altr,sdram-edac-s10")) 1857 return 0; 1858 1859 /* Ensure parent device is enabled if parent node exists */ 1860 parent = of_parse_phandle(np, "altr,ecc-parent", 0); 1861 if (parent && !of_device_is_available(parent)) 1862 ret = -ENODEV; 1863 1864 of_node_put(parent); 1865 return ret; 1866 } 1867 1868 static int get_s10_sdram_edac_resource(struct device_node *np, 1869 struct resource *res) 1870 { 1871 struct device_node *parent; 1872 int ret; 1873 1874 parent = of_parse_phandle(np, "altr,sdr-syscon", 0); 1875 if (!parent) 1876 return -ENODEV; 1877 1878 ret = of_address_to_resource(parent, 0, res); 1879 of_node_put(parent); 1880 1881 return ret; 1882 } 1883 1884 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, 1885 struct device_node *np) 1886 { 1887 struct edac_device_ctl_info *dci; 1888 struct altr_edac_device_dev *altdev; 1889 char *ecc_name = (char *)np->name; 1890 struct resource res; 1891 int edac_idx; 1892 int rc = 0; 1893 const struct edac_device_prv_data *prv; 1894 /* Get matching node and check for valid result */ 1895 const struct of_device_id *pdev_id = 1896 of_match_node(altr_edac_a10_device_of_match, np); 1897 if (IS_ERR_OR_NULL(pdev_id)) 1898 return -ENODEV; 1899 1900 /* Get driver specific data for this EDAC device */ 1901 prv = pdev_id->data; 1902 if (IS_ERR_OR_NULL(prv)) 1903 return -ENODEV; 1904 1905 if (validate_parent_available(np)) 1906 return -ENODEV; 1907 1908 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) 1909 return -ENOMEM; 1910 1911 if (of_device_is_compatible(np, "altr,sdram-edac-s10")) 1912 rc = get_s10_sdram_edac_resource(np, &res); 1913 else 1914 rc = of_address_to_resource(np, 0, &res); 1915 1916 if (rc < 0) { 1917 edac_printk(KERN_ERR, EDAC_DEVICE, 1918 "%s: no resource address\n", ecc_name); 1919 goto err_release_group; 1920 } 1921 1922 edac_idx = edac_device_alloc_index(); 1923 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1924 1, ecc_name, 1, 0, NULL, 0, 1925 edac_idx); 1926 1927 if (!dci) { 1928 edac_printk(KERN_ERR, EDAC_DEVICE, 1929 "%s: Unable to allocate EDAC device\n", ecc_name); 1930 rc = -ENOMEM; 1931 goto err_release_group; 1932 } 1933 1934 altdev = dci->pvt_info; 1935 dci->dev = edac->dev; 1936 altdev->edac_dev_name = ecc_name; 1937 altdev->edac_idx = edac_idx; 1938 altdev->edac = edac; 1939 altdev->edac_dev = dci; 1940 altdev->data = prv; 1941 altdev->ddev = *edac->dev; 1942 dci->dev = &altdev->ddev; 1943 dci->ctl_name = "Altera ECC Manager"; 1944 dci->mod_name = ecc_name; 1945 dci->dev_name = ecc_name; 1946 1947 altdev->base = devm_ioremap_resource(edac->dev, &res); 1948 if (IS_ERR(altdev->base)) { 1949 rc = PTR_ERR(altdev->base); 1950 goto err_release_group1; 1951 } 1952 1953 /* Check specific dependencies for the module */ 1954 if (altdev->data->setup) { 1955 rc = altdev->data->setup(altdev); 1956 if (rc) 1957 goto err_release_group1; 1958 } 1959 1960 altdev->sb_irq = irq_of_parse_and_map(np, 0); 1961 if (!altdev->sb_irq) { 1962 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); 1963 rc = -ENODEV; 1964 goto err_release_group1; 1965 } 1966 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler, 1967 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1968 ecc_name, altdev); 1969 if (rc) { 1970 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n"); 1971 goto err_release_group1; 1972 } 1973 1974 #ifdef CONFIG_64BIT 1975 /* Use IRQ to determine SError origin instead of assigning IRQ */ 1976 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq); 1977 if (rc) { 1978 edac_printk(KERN_ERR, EDAC_DEVICE, 1979 "Unable to parse DB IRQ index\n"); 1980 goto err_release_group1; 1981 } 1982 #else 1983 altdev->db_irq = irq_of_parse_and_map(np, 1); 1984 if (!altdev->db_irq) { 1985 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); 1986 rc = -ENODEV; 1987 goto err_release_group1; 1988 } 1989 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler, 1990 IRQF_ONESHOT | IRQF_TRIGGER_HIGH, 1991 ecc_name, altdev); 1992 if (rc) { 1993 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); 1994 goto err_release_group1; 1995 } 1996 #endif 1997 1998 rc = edac_device_add_device(dci); 1999 if (rc) { 2000 dev_err(edac->dev, "edac_device_add_device failed\n"); 2001 rc = -ENOMEM; 2002 goto err_release_group1; 2003 } 2004 2005 altr_create_edacdev_dbgfs(dci, prv); 2006 2007 list_add(&altdev->next, &edac->a10_ecc_devices); 2008 2009 devres_remove_group(edac->dev, altr_edac_a10_device_add); 2010 2011 return 0; 2012 2013 err_release_group1: 2014 edac_device_free_ctl_info(dci); 2015 err_release_group: 2016 devres_release_group(edac->dev, NULL); 2017 edac_printk(KERN_ERR, EDAC_DEVICE, 2018 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 2019 2020 return rc; 2021 } 2022 2023 static void a10_eccmgr_irq_mask(struct irq_data *d) 2024 { 2025 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 2026 2027 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, 2028 BIT(d->hwirq)); 2029 } 2030 2031 static void a10_eccmgr_irq_unmask(struct irq_data *d) 2032 { 2033 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 2034 2035 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, 2036 BIT(d->hwirq)); 2037 } 2038 2039 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, 2040 irq_hw_number_t hwirq) 2041 { 2042 struct altr_arria10_edac *edac = d->host_data; 2043 2044 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); 2045 irq_set_chip_data(irq, edac); 2046 irq_set_noprobe(irq); 2047 2048 return 0; 2049 } 2050 2051 static const struct irq_domain_ops a10_eccmgr_ic_ops = { 2052 .map = a10_eccmgr_irqdomain_map, 2053 .xlate = irq_domain_xlate_twocell, 2054 }; 2055 2056 /************** Stratix 10 EDAC Double Bit Error Handler ************/ 2057 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m) 2058 2059 #ifdef CONFIG_64BIT 2060 /* panic routine issues reboot on non-zero panic_timeout */ 2061 extern int panic_timeout; 2062 2063 /* 2064 * The double bit error is handled through SError which is fatal. This is 2065 * called as a panic notifier to printout ECC error info as part of the panic. 2066 */ 2067 static int s10_edac_dberr_handler(struct notifier_block *this, 2068 unsigned long event, void *ptr) 2069 { 2070 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier); 2071 int err_addr, dberror; 2072 2073 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST, 2074 &dberror); 2075 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror); 2076 if (dberror & S10_DBE_IRQ_MASK) { 2077 struct list_head *position; 2078 struct altr_edac_device_dev *ed; 2079 struct arm_smccc_res result; 2080 2081 /* Find the matching DBE in the list of devices */ 2082 list_for_each(position, &edac->a10_ecc_devices) { 2083 ed = list_entry(position, struct altr_edac_device_dev, 2084 next); 2085 if (!(BIT(ed->db_irq) & dberror)) 2086 continue; 2087 2088 writel(ALTR_A10_ECC_DERRPENA, 2089 ed->base + ALTR_A10_ECC_INTSTAT_OFST); 2090 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST); 2091 regmap_write(edac->ecc_mgr_map, 2092 S10_SYSMGR_UE_ADDR_OFST, err_addr); 2093 edac_printk(KERN_ERR, EDAC_DEVICE, 2094 "EDAC: [Fatal DBE on %s @ 0x%08X]\n", 2095 ed->edac_dev_name, err_addr); 2096 break; 2097 } 2098 /* Notify the System through SMC. Reboot delay = 1 second */ 2099 panic_timeout = 1; 2100 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0, 2101 0, 0, &result); 2102 } 2103 2104 return NOTIFY_DONE; 2105 } 2106 #endif 2107 2108 /****************** Arria 10 EDAC Probe Function *********************/ 2109 static int altr_edac_a10_probe(struct platform_device *pdev) 2110 { 2111 struct altr_arria10_edac *edac; 2112 struct device_node *child; 2113 2114 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); 2115 if (!edac) 2116 return -ENOMEM; 2117 2118 edac->dev = &pdev->dev; 2119 platform_set_drvdata(pdev, edac); 2120 INIT_LIST_HEAD(&edac->a10_ecc_devices); 2121 2122 edac->ecc_mgr_map = 2123 altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node, 2124 "altr,sysmgr-syscon"); 2125 2126 if (IS_ERR(edac->ecc_mgr_map)) { 2127 edac_printk(KERN_ERR, EDAC_DEVICE, 2128 "Unable to get syscon altr,sysmgr-syscon\n"); 2129 return PTR_ERR(edac->ecc_mgr_map); 2130 } 2131 2132 edac->irq_chip.name = pdev->dev.of_node->name; 2133 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; 2134 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; 2135 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64, 2136 &a10_eccmgr_ic_ops, edac); 2137 if (!edac->domain) { 2138 dev_err(&pdev->dev, "Error adding IRQ domain\n"); 2139 return -ENOMEM; 2140 } 2141 2142 edac->sb_irq = platform_get_irq(pdev, 0); 2143 if (edac->sb_irq < 0) 2144 return edac->sb_irq; 2145 2146 irq_set_chained_handler_and_data(edac->sb_irq, 2147 altr_edac_a10_irq_handler, 2148 edac); 2149 2150 #ifdef CONFIG_64BIT 2151 { 2152 int dberror, err_addr; 2153 2154 edac->panic_notifier.notifier_call = s10_edac_dberr_handler; 2155 atomic_notifier_chain_register(&panic_notifier_list, 2156 &edac->panic_notifier); 2157 2158 /* Printout a message if uncorrectable error previously. */ 2159 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, 2160 &dberror); 2161 if (dberror) { 2162 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST, 2163 &err_addr); 2164 edac_printk(KERN_ERR, EDAC_DEVICE, 2165 "Previous Boot UE detected[0x%X] @ 0x%X\n", 2166 dberror, err_addr); 2167 /* Reset the sticky registers */ 2168 regmap_write(edac->ecc_mgr_map, 2169 S10_SYSMGR_UE_VAL_OFST, 0); 2170 regmap_write(edac->ecc_mgr_map, 2171 S10_SYSMGR_UE_ADDR_OFST, 0); 2172 } 2173 } 2174 #else 2175 edac->db_irq = platform_get_irq(pdev, 1); 2176 if (edac->db_irq < 0) 2177 return edac->db_irq; 2178 2179 irq_set_chained_handler_and_data(edac->db_irq, 2180 altr_edac_a10_irq_handler, edac); 2181 #endif 2182 2183 for_each_child_of_node(pdev->dev.of_node, child) { 2184 if (!of_device_is_available(child)) 2185 continue; 2186 2187 if (of_match_node(altr_edac_a10_device_of_match, child)) 2188 altr_edac_a10_device_add(edac, child); 2189 2190 #ifdef CONFIG_EDAC_ALTERA_SDRAM 2191 else if (of_device_is_compatible(child, "altr,sdram-edac-a10")) 2192 of_platform_populate(pdev->dev.of_node, 2193 altr_sdram_ctrl_of_match, 2194 NULL, &pdev->dev); 2195 #endif 2196 } 2197 2198 return 0; 2199 } 2200 2201 static const struct of_device_id altr_edac_a10_of_match[] = { 2202 { .compatible = "altr,socfpga-a10-ecc-manager" }, 2203 { .compatible = "altr,socfpga-s10-ecc-manager" }, 2204 {}, 2205 }; 2206 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); 2207 2208 static struct platform_driver altr_edac_a10_driver = { 2209 .probe = altr_edac_a10_probe, 2210 .driver = { 2211 .name = "socfpga_a10_ecc_manager", 2212 .of_match_table = altr_edac_a10_of_match, 2213 }, 2214 }; 2215 module_platform_driver(altr_edac_a10_driver); 2216 2217 MODULE_AUTHOR("Thor Thayer"); 2218 MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); 2219