1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved 4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved. 5 * Copyright 2011-2012 Calxeda, Inc. 6 */ 7 8 #include <asm/cacheflush.h> 9 #include <linux/ctype.h> 10 #include <linux/delay.h> 11 #include <linux/edac.h> 12 #include <linux/firmware/intel/stratix10-smc.h> 13 #include <linux/genalloc.h> 14 #include <linux/interrupt.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/kernel.h> 17 #include <linux/mfd/altera-sysmgr.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/notifier.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/panic_notifier.h> 24 #include <linux/platform_device.h> 25 #include <linux/property.h> 26 #include <linux/regmap.h> 27 #include <linux/types.h> 28 #include <linux/uaccess.h> 29 30 #include "altera_edac.h" 31 #include "edac_module.h" 32 33 #define EDAC_MOD_STR "altera_edac" 34 #define EDAC_DEVICE "Altera" 35 36 #ifdef CONFIG_EDAC_ALTERA_SDRAM 37 static const struct altr_sdram_prv_data c5_data = { 38 .ecc_ctrl_offset = CV_CTLCFG_OFST, 39 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN, 40 .ecc_stat_offset = CV_DRAMSTS_OFST, 41 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR, 42 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR, 43 .ecc_saddr_offset = CV_ERRADDR_OFST, 44 .ecc_daddr_offset = CV_ERRADDR_OFST, 45 .ecc_cecnt_offset = CV_SBECOUNT_OFST, 46 .ecc_uecnt_offset = CV_DBECOUNT_OFST, 47 .ecc_irq_en_offset = CV_DRAMINTR_OFST, 48 .ecc_irq_en_mask = CV_DRAMINTR_INTREN, 49 .ecc_irq_clr_offset = CV_DRAMINTR_OFST, 50 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN), 51 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST, 52 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR, 53 .ce_ue_trgr_offset = CV_CTLCFG_OFST, 54 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR, 55 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR, 56 }; 57 58 static const struct altr_sdram_prv_data a10_data = { 59 .ecc_ctrl_offset = A10_ECCCTRL1_OFST, 60 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN, 61 .ecc_stat_offset = A10_INTSTAT_OFST, 62 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR, 63 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR, 64 .ecc_saddr_offset = A10_SERRADDR_OFST, 65 .ecc_daddr_offset = A10_DERRADDR_OFST, 66 .ecc_irq_en_offset = A10_ERRINTEN_OFST, 67 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK, 68 .ecc_irq_clr_offset = A10_INTSTAT_OFST, 69 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR), 70 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST, 71 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK, 72 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST, 73 .ce_set_mask = A10_DIAGINT_TSERRA_MASK, 74 .ue_set_mask = A10_DIAGINT_TDERRA_MASK, 75 }; 76 77 /*********************** EDAC Memory Controller Functions ****************/ 78 79 /* The SDRAM controller uses the EDAC Memory Controller framework. */ 80 81 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id) 82 { 83 struct mem_ctl_info *mci = dev_id; 84 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 85 const struct altr_sdram_prv_data *priv = drvdata->data; 86 u32 status, err_count = 1, err_addr; 87 88 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status); 89 90 if (status & priv->ecc_stat_ue_mask) { 91 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset, 92 &err_addr); 93 if (priv->ecc_uecnt_offset) 94 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset, 95 &err_count); 96 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n", 97 err_count, err_addr); 98 } 99 if (status & priv->ecc_stat_ce_mask) { 100 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset, 101 &err_addr); 102 if (priv->ecc_cecnt_offset) 103 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset, 104 &err_count); 105 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count, 106 err_addr >> PAGE_SHIFT, 107 err_addr & ~PAGE_MASK, 0, 108 0, 0, -1, mci->ctl_name, ""); 109 /* Clear IRQ to resume */ 110 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset, 111 priv->ecc_irq_clr_mask); 112 113 return IRQ_HANDLED; 114 } 115 return IRQ_NONE; 116 } 117 118 static ssize_t altr_sdr_mc_err_inject_write(struct file *file, 119 const char __user *data, 120 size_t count, loff_t *ppos) 121 { 122 struct mem_ctl_info *mci = file->private_data; 123 struct altr_sdram_mc_data *drvdata = mci->pvt_info; 124 const struct altr_sdram_prv_data *priv = drvdata->data; 125 u32 *ptemp; 126 dma_addr_t dma_handle; 127 u32 reg, read_reg; 128 129 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL); 130 if (!ptemp) { 131 edac_printk(KERN_ERR, EDAC_MC, 132 "Inject: Buffer Allocation error\n"); 133 return -ENOMEM; 134 } 135 136 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 137 &read_reg); 138 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask); 139 140 /* Error are injected by writing a word while the SBE or DBE 141 * bit in the CTLCFG register is set. Reading the word will 142 * trigger the SBE or DBE error and the corresponding IRQ. 143 */ 144 if (count == 3) { 145 edac_printk(KERN_ALERT, EDAC_MC, 146 "Inject Double bit error\n"); 147 local_irq_disable(); 148 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 149 (read_reg | priv->ue_set_mask)); 150 local_irq_enable(); 151 } else { 152 edac_printk(KERN_ALERT, EDAC_MC, 153 "Inject Single bit error\n"); 154 local_irq_disable(); 155 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, 156 (read_reg | priv->ce_set_mask)); 157 local_irq_enable(); 158 } 159 160 ptemp[0] = 0x5A5A5A5A; 161 ptemp[1] = 0xA5A5A5A5; 162 163 /* Clear the error injection bits */ 164 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg); 165 /* Ensure it has been written out */ 166 wmb(); 167 168 /* 169 * To trigger the error, we need to read the data back 170 * (the data was written with errors above). 171 * The READ_ONCE macros and printk are used to prevent the 172 * the compiler optimizing these reads out. 173 */ 174 reg = READ_ONCE(ptemp[0]); 175 read_reg = READ_ONCE(ptemp[1]); 176 /* Force Read */ 177 rmb(); 178 179 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n", 180 reg, read_reg); 181 182 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle); 183 184 return count; 185 } 186 187 static const struct file_operations altr_sdr_mc_debug_inject_fops = { 188 .open = simple_open, 189 .write = altr_sdr_mc_err_inject_write, 190 .llseek = generic_file_llseek, 191 }; 192 193 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci) 194 { 195 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 196 return; 197 198 if (!mci->debugfs) 199 return; 200 201 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci, 202 &altr_sdr_mc_debug_inject_fops); 203 } 204 205 /* Get total memory size from Open Firmware DTB */ 206 static unsigned long get_total_mem(void) 207 { 208 struct device_node *np = NULL; 209 struct resource res; 210 int ret; 211 unsigned long total_mem = 0; 212 213 for_each_node_by_type(np, "memory") { 214 ret = of_address_to_resource(np, 0, &res); 215 if (ret) 216 continue; 217 218 total_mem += resource_size(&res); 219 } 220 edac_dbg(0, "total_mem 0x%lx\n", total_mem); 221 return total_mem; 222 } 223 224 static const struct of_device_id altr_sdram_ctrl_of_match[] = { 225 { .compatible = "altr,sdram-edac", .data = &c5_data}, 226 { .compatible = "altr,sdram-edac-a10", .data = &a10_data}, 227 {}, 228 }; 229 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match); 230 231 static int a10_init(struct regmap *mc_vbase) 232 { 233 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST, 234 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) { 235 edac_printk(KERN_ERR, EDAC_MC, 236 "Error setting SB IRQ mode\n"); 237 return -ENODEV; 238 } 239 240 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) { 241 edac_printk(KERN_ERR, EDAC_MC, 242 "Error setting trigger count\n"); 243 return -ENODEV; 244 } 245 246 return 0; 247 } 248 249 static int a10_unmask_irq(struct platform_device *pdev, u32 mask) 250 { 251 void __iomem *sm_base; 252 int ret = 0; 253 254 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32), 255 dev_name(&pdev->dev))) { 256 edac_printk(KERN_ERR, EDAC_MC, 257 "Unable to request mem region\n"); 258 return -EBUSY; 259 } 260 261 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 262 if (!sm_base) { 263 edac_printk(KERN_ERR, EDAC_MC, 264 "Unable to ioremap device\n"); 265 266 ret = -ENOMEM; 267 goto release; 268 } 269 270 iowrite32(mask, sm_base); 271 272 iounmap(sm_base); 273 274 release: 275 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32)); 276 277 return ret; 278 } 279 280 static int altr_sdram_probe(struct platform_device *pdev) 281 { 282 struct edac_mc_layer layers[2]; 283 struct mem_ctl_info *mci; 284 struct altr_sdram_mc_data *drvdata; 285 const struct altr_sdram_prv_data *priv; 286 struct regmap *mc_vbase; 287 struct dimm_info *dimm; 288 u32 read_reg; 289 int irq, irq2, res = 0; 290 unsigned long mem_size, irqflags = 0; 291 292 /* Grab the register range from the sdr controller in device tree */ 293 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, 294 "altr,sdr-syscon"); 295 if (IS_ERR(mc_vbase)) { 296 edac_printk(KERN_ERR, EDAC_MC, 297 "regmap for altr,sdr-syscon lookup failed.\n"); 298 return -ENODEV; 299 } 300 301 /* Check specific dependencies for the module */ 302 priv = device_get_match_data(&pdev->dev); 303 304 /* Validate the SDRAM controller has ECC enabled */ 305 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) || 306 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) { 307 edac_printk(KERN_ERR, EDAC_MC, 308 "No ECC/ECC disabled [0x%08X]\n", read_reg); 309 return -ENODEV; 310 } 311 312 /* Grab memory size from device tree. */ 313 mem_size = get_total_mem(); 314 if (!mem_size) { 315 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n"); 316 return -ENODEV; 317 } 318 319 /* Ensure the SDRAM Interrupt is disabled */ 320 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset, 321 priv->ecc_irq_en_mask, 0)) { 322 edac_printk(KERN_ERR, EDAC_MC, 323 "Error disabling SDRAM ECC IRQ\n"); 324 return -ENODEV; 325 } 326 327 /* Toggle to clear the SDRAM Error count */ 328 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 329 priv->ecc_cnt_rst_mask, 330 priv->ecc_cnt_rst_mask)) { 331 edac_printk(KERN_ERR, EDAC_MC, 332 "Error clearing SDRAM ECC count\n"); 333 return -ENODEV; 334 } 335 336 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset, 337 priv->ecc_cnt_rst_mask, 0)) { 338 edac_printk(KERN_ERR, EDAC_MC, 339 "Error clearing SDRAM ECC count\n"); 340 return -ENODEV; 341 } 342 343 irq = platform_get_irq(pdev, 0); 344 if (irq < 0) { 345 edac_printk(KERN_ERR, EDAC_MC, 346 "No irq %d in DT\n", irq); 347 return irq; 348 } 349 350 /* Arria10 has a 2nd IRQ */ 351 irq2 = platform_get_irq(pdev, 1); 352 353 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 354 layers[0].size = 1; 355 layers[0].is_virt_csrow = true; 356 layers[1].type = EDAC_MC_LAYER_CHANNEL; 357 layers[1].size = 1; 358 layers[1].is_virt_csrow = false; 359 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 360 sizeof(struct altr_sdram_mc_data)); 361 if (!mci) 362 return -ENOMEM; 363 364 mci->pdev = &pdev->dev; 365 drvdata = mci->pvt_info; 366 drvdata->mc_vbase = mc_vbase; 367 drvdata->data = priv; 368 platform_set_drvdata(pdev, mci); 369 370 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 371 edac_printk(KERN_ERR, EDAC_MC, 372 "Unable to get managed device resource\n"); 373 res = -ENOMEM; 374 goto free; 375 } 376 377 mci->mtype_cap = MEM_FLAG_DDR3; 378 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; 379 mci->edac_cap = EDAC_FLAG_SECDED; 380 mci->mod_name = EDAC_MOD_STR; 381 mci->ctl_name = dev_name(&pdev->dev); 382 mci->scrub_mode = SCRUB_SW_SRC; 383 mci->dev_name = dev_name(&pdev->dev); 384 385 dimm = *mci->dimms; 386 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1; 387 dimm->grain = 8; 388 dimm->dtype = DEV_X8; 389 dimm->mtype = MEM_DDR3; 390 dimm->edac_mode = EDAC_SECDED; 391 392 res = edac_mc_add_mc(mci); 393 if (res < 0) 394 goto err; 395 396 /* Only the Arria10 has separate IRQs */ 397 if (of_machine_is_compatible("altr,socfpga-arria10")) { 398 /* Arria10 specific initialization */ 399 res = a10_init(mc_vbase); 400 if (res < 0) 401 goto err2; 402 403 res = devm_request_irq(&pdev->dev, irq2, 404 altr_sdram_mc_err_handler, 405 IRQF_SHARED, dev_name(&pdev->dev), mci); 406 if (res < 0) { 407 edac_mc_printk(mci, KERN_ERR, 408 "Unable to request irq %d\n", irq2); 409 res = -ENODEV; 410 goto err2; 411 } 412 413 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK); 414 if (res < 0) 415 goto err2; 416 417 irqflags = IRQF_SHARED; 418 } 419 420 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler, 421 irqflags, dev_name(&pdev->dev), mci); 422 if (res < 0) { 423 edac_mc_printk(mci, KERN_ERR, 424 "Unable to request irq %d\n", irq); 425 res = -ENODEV; 426 goto err2; 427 } 428 429 /* Infrastructure ready - enable the IRQ */ 430 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset, 431 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) { 432 edac_mc_printk(mci, KERN_ERR, 433 "Error enabling SDRAM ECC IRQ\n"); 434 res = -ENODEV; 435 goto err2; 436 } 437 438 altr_sdr_mc_create_debugfs_nodes(mci); 439 440 devres_close_group(&pdev->dev, NULL); 441 442 return 0; 443 444 err2: 445 edac_mc_del_mc(&pdev->dev); 446 err: 447 devres_release_group(&pdev->dev, NULL); 448 free: 449 edac_mc_free(mci); 450 edac_printk(KERN_ERR, EDAC_MC, 451 "EDAC Probe Failed; Error %d\n", res); 452 453 return res; 454 } 455 456 /* 457 * If you want to suspend, need to disable EDAC by removing it 458 * from the device tree or defconfig. 459 */ 460 #ifdef CONFIG_PM 461 static int altr_sdram_prepare(struct device *dev) 462 { 463 pr_err("Suspend not allowed when EDAC is enabled.\n"); 464 465 return -EPERM; 466 } 467 468 static const struct dev_pm_ops altr_sdram_pm_ops = { 469 .prepare = altr_sdram_prepare, 470 }; 471 #endif 472 473 static struct platform_driver altr_sdram_edac_driver = { 474 .probe = altr_sdram_probe, 475 .driver = { 476 .name = "altr_sdram_edac", 477 #ifdef CONFIG_PM 478 .pm = &altr_sdram_pm_ops, 479 #endif 480 .of_match_table = altr_sdram_ctrl_of_match, 481 .suppress_bind_attrs = true, 482 }, 483 }; 484 485 module_platform_driver(altr_sdram_edac_driver); 486 487 #endif /* CONFIG_EDAC_ALTERA_SDRAM */ 488 489 /************************* EDAC Parent Probe *************************/ 490 491 static const struct of_device_id altr_edac_device_of_match[]; 492 493 static const struct of_device_id altr_edac_of_match[] = { 494 { .compatible = "altr,socfpga-ecc-manager" }, 495 {}, 496 }; 497 MODULE_DEVICE_TABLE(of, altr_edac_of_match); 498 499 static int altr_edac_probe(struct platform_device *pdev) 500 { 501 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match, 502 NULL, &pdev->dev); 503 return 0; 504 } 505 506 static struct platform_driver altr_edac_driver = { 507 .probe = altr_edac_probe, 508 .driver = { 509 .name = "socfpga_ecc_manager", 510 .of_match_table = altr_edac_of_match, 511 .suppress_bind_attrs = true, 512 }, 513 }; 514 module_platform_driver(altr_edac_driver); 515 516 /************************* EDAC Device Functions *************************/ 517 518 /* 519 * EDAC Device Functions (shared between various IPs). 520 * The discrete memories use the EDAC Device framework. The probe 521 * and error handling functions are very similar between memories 522 * so they are shared. The memory allocation and freeing for EDAC 523 * trigger testing are different for each memory. 524 */ 525 526 #ifdef CONFIG_EDAC_ALTERA_OCRAM 527 static const struct edac_device_prv_data ocramecc_data; 528 #endif 529 #ifdef CONFIG_EDAC_ALTERA_L2C 530 static const struct edac_device_prv_data l2ecc_data; 531 #endif 532 #ifdef CONFIG_EDAC_ALTERA_OCRAM 533 static const struct edac_device_prv_data a10_ocramecc_data; 534 #endif 535 #ifdef CONFIG_EDAC_ALTERA_L2C 536 static const struct edac_device_prv_data a10_l2ecc_data; 537 #endif 538 539 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id) 540 { 541 irqreturn_t ret_value = IRQ_NONE; 542 struct edac_device_ctl_info *dci = dev_id; 543 struct altr_edac_device_dev *drvdata = dci->pvt_info; 544 const struct edac_device_prv_data *priv = drvdata->data; 545 546 if (irq == drvdata->sb_irq) { 547 if (priv->ce_clear_mask) 548 writel(priv->ce_clear_mask, drvdata->base); 549 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name); 550 ret_value = IRQ_HANDLED; 551 } else if (irq == drvdata->db_irq) { 552 if (priv->ue_clear_mask) 553 writel(priv->ue_clear_mask, drvdata->base); 554 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name); 555 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 556 ret_value = IRQ_HANDLED; 557 } else { 558 WARN_ON(1); 559 } 560 561 return ret_value; 562 } 563 564 static ssize_t __maybe_unused 565 altr_edac_device_trig(struct file *file, const char __user *user_buf, 566 size_t count, loff_t *ppos) 567 568 { 569 u32 *ptemp, i, error_mask; 570 int result = 0; 571 u8 trig_type; 572 unsigned long flags; 573 struct edac_device_ctl_info *edac_dci = file->private_data; 574 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 575 const struct edac_device_prv_data *priv = drvdata->data; 576 void *generic_ptr = edac_dci->dev; 577 578 if (!user_buf || get_user(trig_type, user_buf)) 579 return -EFAULT; 580 581 if (!priv->alloc_mem) 582 return -ENOMEM; 583 584 /* 585 * Note that generic_ptr is initialized to the device * but in 586 * some alloc_functions, this is overridden and returns data. 587 */ 588 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr); 589 if (!ptemp) { 590 edac_printk(KERN_ERR, EDAC_DEVICE, 591 "Inject: Buffer Allocation error\n"); 592 return -ENOMEM; 593 } 594 595 if (trig_type == ALTR_UE_TRIGGER_CHAR) 596 error_mask = priv->ue_set_mask; 597 else 598 error_mask = priv->ce_set_mask; 599 600 edac_printk(KERN_ALERT, EDAC_DEVICE, 601 "Trigger Error Mask (0x%X)\n", error_mask); 602 603 local_irq_save(flags); 604 /* write ECC corrupted data out. */ 605 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) { 606 /* Read data so we're in the correct state */ 607 rmb(); 608 if (READ_ONCE(ptemp[i])) 609 result = -1; 610 /* Toggle Error bit (it is latched), leave ECC enabled */ 611 writel(error_mask, (drvdata->base + priv->set_err_ofst)); 612 writel(priv->ecc_enable_mask, (drvdata->base + 613 priv->set_err_ofst)); 614 ptemp[i] = i; 615 } 616 /* Ensure it has been written out */ 617 wmb(); 618 local_irq_restore(flags); 619 620 if (result) 621 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n"); 622 623 /* Read out written data. ECC error caused here */ 624 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++) 625 if (READ_ONCE(ptemp[i]) != i) 626 edac_printk(KERN_ERR, EDAC_DEVICE, 627 "Read doesn't match written data\n"); 628 629 if (priv->free_mem) 630 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr); 631 632 return count; 633 } 634 635 static const struct file_operations altr_edac_device_inject_fops __maybe_unused = { 636 .open = simple_open, 637 .write = altr_edac_device_trig, 638 .llseek = generic_file_llseek, 639 }; 640 641 static ssize_t __maybe_unused 642 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf, 643 size_t count, loff_t *ppos); 644 645 static const struct file_operations altr_edac_a10_device_inject_fops __maybe_unused = { 646 .open = simple_open, 647 .write = altr_edac_a10_device_trig, 648 .llseek = generic_file_llseek, 649 }; 650 651 static ssize_t __maybe_unused 652 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf, 653 size_t count, loff_t *ppos); 654 655 static const struct file_operations altr_edac_a10_device_inject2_fops __maybe_unused = { 656 .open = simple_open, 657 .write = altr_edac_a10_device_trig2, 658 .llseek = generic_file_llseek, 659 }; 660 661 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci, 662 const struct edac_device_prv_data *priv) 663 { 664 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 665 666 if (!IS_ENABLED(CONFIG_EDAC_DEBUG)) 667 return; 668 669 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name); 670 if (!drvdata->debugfs_dir) 671 return; 672 673 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR, 674 drvdata->debugfs_dir, edac_dci, 675 priv->inject_fops)) 676 debugfs_remove_recursive(drvdata->debugfs_dir); 677 } 678 679 static const struct of_device_id altr_edac_device_of_match[] = { 680 #ifdef CONFIG_EDAC_ALTERA_L2C 681 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data }, 682 #endif 683 #ifdef CONFIG_EDAC_ALTERA_OCRAM 684 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data }, 685 #endif 686 {}, 687 }; 688 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match); 689 690 /* 691 * altr_edac_device_probe() 692 * This is a generic EDAC device driver that will support 693 * various Altera memory devices such as the L2 cache ECC and 694 * OCRAM ECC as well as the memories for other peripherals. 695 * Module specific initialization is done by passing the 696 * function index in the device tree. 697 */ 698 static int altr_edac_device_probe(struct platform_device *pdev) 699 { 700 struct edac_device_ctl_info *dci; 701 struct altr_edac_device_dev *drvdata; 702 struct resource *r; 703 int res = 0; 704 struct device_node *np = pdev->dev.of_node; 705 char *ecc_name = (char *)np->name; 706 static int dev_instance; 707 708 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) { 709 edac_printk(KERN_ERR, EDAC_DEVICE, 710 "Unable to open devm\n"); 711 return -ENOMEM; 712 } 713 714 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 715 if (!r) { 716 edac_printk(KERN_ERR, EDAC_DEVICE, 717 "Unable to get mem resource\n"); 718 res = -ENODEV; 719 goto fail; 720 } 721 722 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r), 723 dev_name(&pdev->dev))) { 724 edac_printk(KERN_ERR, EDAC_DEVICE, 725 "%s:Error requesting mem region\n", ecc_name); 726 res = -EBUSY; 727 goto fail; 728 } 729 730 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name, 731 1, ecc_name, 1, 0, dev_instance++); 732 733 if (!dci) { 734 edac_printk(KERN_ERR, EDAC_DEVICE, 735 "%s: Unable to allocate EDAC device\n", ecc_name); 736 res = -ENOMEM; 737 goto fail; 738 } 739 740 drvdata = dci->pvt_info; 741 dci->dev = &pdev->dev; 742 platform_set_drvdata(pdev, dci); 743 drvdata->edac_dev_name = ecc_name; 744 745 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r)); 746 if (!drvdata->base) { 747 res = -ENOMEM; 748 goto fail1; 749 } 750 751 /* Get driver specific data for this EDAC device */ 752 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data; 753 754 /* Check specific dependencies for the module */ 755 if (drvdata->data->setup) { 756 res = drvdata->data->setup(drvdata); 757 if (res) 758 goto fail1; 759 } 760 761 drvdata->sb_irq = platform_get_irq(pdev, 0); 762 res = devm_request_irq(&pdev->dev, drvdata->sb_irq, 763 altr_edac_device_handler, 764 0, dev_name(&pdev->dev), dci); 765 if (res) 766 goto fail1; 767 768 drvdata->db_irq = platform_get_irq(pdev, 1); 769 res = devm_request_irq(&pdev->dev, drvdata->db_irq, 770 altr_edac_device_handler, 771 0, dev_name(&pdev->dev), dci); 772 if (res) 773 goto fail1; 774 775 dci->mod_name = "Altera ECC Manager"; 776 dci->dev_name = drvdata->edac_dev_name; 777 778 res = edac_device_add_device(dci); 779 if (res) 780 goto fail1; 781 782 altr_create_edacdev_dbgfs(dci, drvdata->data); 783 784 devres_close_group(&pdev->dev, NULL); 785 786 return 0; 787 788 fail1: 789 edac_device_free_ctl_info(dci); 790 fail: 791 devres_release_group(&pdev->dev, NULL); 792 edac_printk(KERN_ERR, EDAC_DEVICE, 793 "%s:Error setting up EDAC device: %d\n", ecc_name, res); 794 795 return res; 796 } 797 798 static struct platform_driver altr_edac_device_driver = { 799 .probe = altr_edac_device_probe, 800 .driver = { 801 .name = "altr_edac_device", 802 .of_match_table = altr_edac_device_of_match, 803 .suppress_bind_attrs = true, 804 }, 805 }; 806 module_platform_driver(altr_edac_device_driver); 807 808 /******************* Arria10 Device ECC Shared Functions *****************/ 809 810 /* 811 * Test for memory's ECC dependencies upon entry because platform specific 812 * startup should have initialized the memory and enabled the ECC. 813 * Can't turn on ECC here because accessing un-initialized memory will 814 * cause CE/UE errors possibly causing an ABORT. 815 */ 816 static int __maybe_unused 817 altr_check_ecc_deps(struct altr_edac_device_dev *device) 818 { 819 void __iomem *base = device->base; 820 const struct edac_device_prv_data *prv = device->data; 821 822 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask) 823 return 0; 824 825 edac_printk(KERN_ERR, EDAC_DEVICE, 826 "%s: No ECC present or ECC disabled.\n", 827 device->edac_dev_name); 828 return -ENODEV; 829 } 830 831 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id) 832 { 833 struct altr_edac_device_dev *dci = dev_id; 834 void __iomem *base = dci->base; 835 836 if (irq == dci->sb_irq) { 837 writel(ALTR_A10_ECC_SERRPENA, 838 base + ALTR_A10_ECC_INTSTAT_OFST); 839 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 840 841 return IRQ_HANDLED; 842 } else if (irq == dci->db_irq) { 843 writel(ALTR_A10_ECC_DERRPENA, 844 base + ALTR_A10_ECC_INTSTAT_OFST); 845 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 846 if (dci->data->panic) 847 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 848 849 return IRQ_HANDLED; 850 } 851 852 WARN_ON(1); 853 854 return IRQ_NONE; 855 } 856 857 /******************* Arria10 Memory Buffer Functions *********************/ 858 859 static inline int a10_get_irq_mask(struct device_node *np) 860 { 861 int irq; 862 const u32 *handle = of_get_property(np, "interrupts", NULL); 863 864 if (!handle) 865 return -ENODEV; 866 irq = be32_to_cpup(handle); 867 return irq; 868 } 869 870 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr) 871 { 872 u32 value = readl(ioaddr); 873 874 value |= bit_mask; 875 writel(value, ioaddr); 876 } 877 878 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr) 879 { 880 u32 value = readl(ioaddr); 881 882 value &= ~bit_mask; 883 writel(value, ioaddr); 884 } 885 886 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr) 887 { 888 u32 value = readl(ioaddr); 889 890 return (value & bit_mask) ? 1 : 0; 891 } 892 893 /* 894 * This function uses the memory initialization block in the Arria10 ECC 895 * controller to initialize/clear the entire memory data and ECC data. 896 */ 897 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port) 898 { 899 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US; 900 u32 init_mask, stat_mask, clear_mask; 901 int ret = 0; 902 903 if (port) { 904 init_mask = ALTR_A10_ECC_INITB; 905 stat_mask = ALTR_A10_ECC_INITCOMPLETEB; 906 clear_mask = ALTR_A10_ECC_ERRPENB_MASK; 907 } else { 908 init_mask = ALTR_A10_ECC_INITA; 909 stat_mask = ALTR_A10_ECC_INITCOMPLETEA; 910 clear_mask = ALTR_A10_ECC_ERRPENA_MASK; 911 } 912 913 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST)); 914 while (limit--) { 915 if (ecc_test_bits(stat_mask, 916 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST))) 917 break; 918 udelay(1); 919 } 920 if (limit < 0) 921 ret = -EBUSY; 922 923 /* Clear any pending ECC interrupts */ 924 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST)); 925 926 return ret; 927 } 928 929 static int __maybe_unused 930 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask, 931 u32 ecc_ctrl_en_mask, bool dual_port) 932 { 933 int ret = 0; 934 void __iomem *ecc_block_base; 935 struct regmap *ecc_mgr_map; 936 char *ecc_name; 937 struct device_node *np_eccmgr; 938 939 ecc_name = (char *)np->name; 940 941 /* Get the ECC Manager - parent of the device EDACs */ 942 np_eccmgr = of_get_parent(np); 943 944 ecc_mgr_map = 945 altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr, 946 "altr,sysmgr-syscon"); 947 948 of_node_put(np_eccmgr); 949 if (IS_ERR(ecc_mgr_map)) { 950 edac_printk(KERN_ERR, EDAC_DEVICE, 951 "Unable to get syscon altr,sysmgr-syscon\n"); 952 return -ENODEV; 953 } 954 955 /* Map the ECC Block */ 956 ecc_block_base = of_iomap(np, 0); 957 if (!ecc_block_base) { 958 edac_printk(KERN_ERR, EDAC_DEVICE, 959 "Unable to map %s ECC block\n", ecc_name); 960 return -ENODEV; 961 } 962 963 /* Disable ECC */ 964 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask); 965 writel(ALTR_A10_ECC_SERRINTEN, 966 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST)); 967 ecc_clear_bits(ecc_ctrl_en_mask, 968 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST)); 969 /* Ensure all writes complete */ 970 wmb(); 971 /* Use HW initialization block to initialize memory for ECC */ 972 ret = altr_init_memory_port(ecc_block_base, 0); 973 if (ret) { 974 edac_printk(KERN_ERR, EDAC_DEVICE, 975 "ECC: cannot init %s PORTA memory\n", ecc_name); 976 goto out; 977 } 978 979 if (dual_port) { 980 ret = altr_init_memory_port(ecc_block_base, 1); 981 if (ret) { 982 edac_printk(KERN_ERR, EDAC_DEVICE, 983 "ECC: cannot init %s PORTB memory\n", 984 ecc_name); 985 goto out; 986 } 987 } 988 989 /* Enable ECC */ 990 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base + 991 ALTR_A10_ECC_CTRL_OFST)); 992 writel(ALTR_A10_ECC_SERRINTEN, 993 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST)); 994 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask); 995 /* Ensure all writes complete */ 996 wmb(); 997 out: 998 iounmap(ecc_block_base); 999 return ret; 1000 } 1001 1002 static int validate_parent_available(struct device_node *np); 1003 static const struct of_device_id altr_edac_a10_device_of_match[]; 1004 static int __maybe_unused altr_init_a10_ecc_device_type(char *compat) 1005 { 1006 int irq; 1007 struct device_node *child, *np; 1008 1009 np = of_find_compatible_node(NULL, NULL, 1010 "altr,socfpga-a10-ecc-manager"); 1011 if (!np) { 1012 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n"); 1013 return -ENODEV; 1014 } 1015 1016 for_each_child_of_node(np, child) { 1017 const struct of_device_id *pdev_id; 1018 const struct edac_device_prv_data *prv; 1019 1020 if (!of_device_is_available(child)) 1021 continue; 1022 if (!of_device_is_compatible(child, compat)) 1023 continue; 1024 1025 if (validate_parent_available(child)) 1026 continue; 1027 1028 irq = a10_get_irq_mask(child); 1029 if (irq < 0) 1030 continue; 1031 1032 /* Get matching node and check for valid result */ 1033 pdev_id = of_match_node(altr_edac_a10_device_of_match, child); 1034 if (IS_ERR_OR_NULL(pdev_id)) 1035 continue; 1036 1037 /* Validate private data pointer before dereferencing */ 1038 prv = pdev_id->data; 1039 if (!prv) 1040 continue; 1041 1042 altr_init_a10_ecc_block(child, BIT(irq), 1043 prv->ecc_enable_mask, 0); 1044 } 1045 1046 of_node_put(np); 1047 return 0; 1048 } 1049 1050 /*********************** SDRAM EDAC Device Functions *********************/ 1051 1052 #ifdef CONFIG_EDAC_ALTERA_SDRAM 1053 1054 /* 1055 * A legacy U-Boot bug only enabled memory mapped access to the ECC Enable 1056 * register if ECC is enabled. Linux checks the ECC Enable register to 1057 * determine ECC status. 1058 * Use an SMC call (which always works) to determine ECC enablement. 1059 */ 1060 static int altr_s10_sdram_check_ecc_deps(struct altr_edac_device_dev *device) 1061 { 1062 const struct edac_device_prv_data *prv = device->data; 1063 unsigned long sdram_ecc_addr; 1064 struct arm_smccc_res result; 1065 struct device_node *np; 1066 phys_addr_t sdram_addr; 1067 u32 read_reg; 1068 int ret; 1069 1070 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl"); 1071 if (!np) 1072 goto sdram_err; 1073 1074 sdram_addr = of_translate_address(np, of_get_address(np, 0, 1075 NULL, NULL)); 1076 of_node_put(np); 1077 sdram_ecc_addr = (unsigned long)sdram_addr + prv->ecc_en_ofst; 1078 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sdram_ecc_addr, 1079 0, 0, 0, 0, 0, 0, &result); 1080 read_reg = (unsigned int)result.a1; 1081 ret = (int)result.a0; 1082 if (!ret && (read_reg & prv->ecc_enable_mask)) 1083 return 0; 1084 1085 sdram_err: 1086 edac_printk(KERN_ERR, EDAC_DEVICE, 1087 "%s: No ECC present or ECC disabled.\n", 1088 device->edac_dev_name); 1089 return -ENODEV; 1090 } 1091 1092 static const struct edac_device_prv_data s10_sdramecc_data = { 1093 .setup = altr_s10_sdram_check_ecc_deps, 1094 .ce_clear_mask = ALTR_S10_ECC_SERRPENA, 1095 .ue_clear_mask = ALTR_S10_ECC_DERRPENA, 1096 .ecc_enable_mask = ALTR_S10_ECC_EN, 1097 .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST, 1098 .ce_set_mask = ALTR_S10_ECC_TSERRA, 1099 .ue_set_mask = ALTR_S10_ECC_TDERRA, 1100 .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST, 1101 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1102 .inject_fops = &altr_edac_a10_device_inject_fops, 1103 }; 1104 #endif /* CONFIG_EDAC_ALTERA_SDRAM */ 1105 1106 /*********************** OCRAM EDAC Device Functions *********************/ 1107 1108 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1109 1110 static void *ocram_alloc_mem(size_t size, void **other) 1111 { 1112 struct device_node *np; 1113 struct gen_pool *gp; 1114 void *sram_addr; 1115 1116 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc"); 1117 if (!np) 1118 return NULL; 1119 1120 gp = of_gen_pool_get(np, "iram", 0); 1121 of_node_put(np); 1122 if (!gp) 1123 return NULL; 1124 1125 sram_addr = (void *)gen_pool_alloc(gp, size); 1126 if (!sram_addr) 1127 return NULL; 1128 1129 memset(sram_addr, 0, size); 1130 /* Ensure data is written out */ 1131 wmb(); 1132 1133 /* Remember this handle for freeing later */ 1134 *other = gp; 1135 1136 return sram_addr; 1137 } 1138 1139 static void ocram_free_mem(void *p, size_t size, void *other) 1140 { 1141 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size); 1142 } 1143 1144 static const struct edac_device_prv_data ocramecc_data = { 1145 .setup = altr_check_ecc_deps, 1146 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR), 1147 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR), 1148 .alloc_mem = ocram_alloc_mem, 1149 .free_mem = ocram_free_mem, 1150 .ecc_enable_mask = ALTR_OCR_ECC_EN, 1151 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET, 1152 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS), 1153 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD), 1154 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET, 1155 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE, 1156 .inject_fops = &altr_edac_device_inject_fops, 1157 }; 1158 1159 static int __maybe_unused 1160 altr_check_ocram_deps_init(struct altr_edac_device_dev *device) 1161 { 1162 void __iomem *base = device->base; 1163 int ret; 1164 1165 ret = altr_check_ecc_deps(device); 1166 if (ret) 1167 return ret; 1168 1169 /* 1170 * Verify that OCRAM has been initialized. 1171 * During a warm reset, OCRAM contents are retained, but the control 1172 * and status registers are reset to their default values. Therefore, 1173 * ECC must be explicitly re-enabled in the control register. 1174 * Error condition: if INITCOMPLETEA is clear and ECC_EN is already set. 1175 */ 1176 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA, 1177 (base + ALTR_A10_ECC_INITSTAT_OFST))) { 1178 if (!ecc_test_bits(ALTR_A10_ECC_EN, 1179 (base + ALTR_A10_ECC_CTRL_OFST))) 1180 ecc_set_bits(ALTR_A10_ECC_EN, 1181 (base + ALTR_A10_ECC_CTRL_OFST)); 1182 else 1183 return -ENODEV; 1184 } 1185 1186 /* Enable IRQ on Single Bit Error */ 1187 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST)); 1188 /* Ensure all writes complete */ 1189 wmb(); 1190 1191 return 0; 1192 } 1193 1194 static const struct edac_device_prv_data a10_ocramecc_data = { 1195 .setup = altr_check_ocram_deps_init, 1196 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1197 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1198 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM, 1199 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL, 1200 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1201 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1202 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1203 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1204 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1205 .inject_fops = &altr_edac_a10_device_inject2_fops, 1206 /* 1207 * OCRAM panic on uncorrectable error because sleep/resume 1208 * functions and FPGA contents are stored in OCRAM. Prefer 1209 * a kernel panic over executing/loading corrupted data. 1210 */ 1211 .panic = true, 1212 }; 1213 1214 #endif /* CONFIG_EDAC_ALTERA_OCRAM */ 1215 1216 /********************* L2 Cache EDAC Device Functions ********************/ 1217 1218 #ifdef CONFIG_EDAC_ALTERA_L2C 1219 1220 static void *l2_alloc_mem(size_t size, void **other) 1221 { 1222 struct device *dev = *other; 1223 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL); 1224 1225 if (!ptemp) 1226 return NULL; 1227 1228 /* Make sure everything is written out */ 1229 wmb(); 1230 1231 /* 1232 * Clean all cache levels up to LoC (includes L2) 1233 * This ensures the corrupted data is written into 1234 * L2 cache for readback test (which causes ECC error). 1235 */ 1236 flush_cache_all(); 1237 1238 return ptemp; 1239 } 1240 1241 static void l2_free_mem(void *p, size_t size, void *other) 1242 { 1243 struct device *dev = other; 1244 1245 if (dev && p) 1246 devm_kfree(dev, p); 1247 } 1248 1249 /* 1250 * altr_l2_check_deps() 1251 * Test for L2 cache ECC dependencies upon entry because 1252 * platform specific startup should have initialized the L2 1253 * memory and enabled the ECC. 1254 * Bail if ECC is not enabled. 1255 * Note that L2 Cache Enable is forced at build time. 1256 */ 1257 static int altr_l2_check_deps(struct altr_edac_device_dev *device) 1258 { 1259 void __iomem *base = device->base; 1260 const struct edac_device_prv_data *prv = device->data; 1261 1262 if ((readl(base) & prv->ecc_enable_mask) == 1263 prv->ecc_enable_mask) 1264 return 0; 1265 1266 edac_printk(KERN_ERR, EDAC_DEVICE, 1267 "L2: No ECC present, or ECC disabled\n"); 1268 return -ENODEV; 1269 } 1270 1271 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id) 1272 { 1273 struct altr_edac_device_dev *dci = dev_id; 1274 1275 if (irq == dci->sb_irq) { 1276 regmap_write(dci->edac->ecc_mgr_map, 1277 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1278 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB); 1279 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name); 1280 1281 return IRQ_HANDLED; 1282 } else if (irq == dci->db_irq) { 1283 regmap_write(dci->edac->ecc_mgr_map, 1284 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST, 1285 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB); 1286 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name); 1287 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n"); 1288 1289 return IRQ_HANDLED; 1290 } 1291 1292 WARN_ON(1); 1293 1294 return IRQ_NONE; 1295 } 1296 1297 static const struct edac_device_prv_data l2ecc_data = { 1298 .setup = altr_l2_check_deps, 1299 .ce_clear_mask = 0, 1300 .ue_clear_mask = 0, 1301 .alloc_mem = l2_alloc_mem, 1302 .free_mem = l2_free_mem, 1303 .ecc_enable_mask = ALTR_L2_ECC_EN, 1304 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS), 1305 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD), 1306 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET, 1307 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1308 .inject_fops = &altr_edac_device_inject_fops, 1309 }; 1310 1311 static const struct edac_device_prv_data a10_l2ecc_data = { 1312 .setup = altr_l2_check_deps, 1313 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR, 1314 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR, 1315 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2, 1316 .alloc_mem = l2_alloc_mem, 1317 .free_mem = l2_free_mem, 1318 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL, 1319 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK, 1320 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK, 1321 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST, 1322 .ecc_irq_handler = altr_edac_a10_l2_irq, 1323 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE, 1324 .inject_fops = &altr_edac_device_inject_fops, 1325 }; 1326 1327 #endif /* CONFIG_EDAC_ALTERA_L2C */ 1328 1329 /********************* Ethernet Device Functions ********************/ 1330 1331 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1332 1333 static int socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev) 1334 { 1335 int ret; 1336 1337 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc"); 1338 if (ret) 1339 return ret; 1340 1341 return altr_check_ecc_deps(dev); 1342 } 1343 1344 static const struct edac_device_prv_data a10_enetecc_data = { 1345 .setup = socfpga_init_ethernet_ecc, 1346 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1347 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1348 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1349 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1350 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1351 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1352 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1353 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1354 .inject_fops = &altr_edac_a10_device_inject_fops, 1355 }; 1356 1357 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */ 1358 1359 /********************** NAND Device Functions **********************/ 1360 1361 #ifdef CONFIG_EDAC_ALTERA_NAND 1362 1363 static int socfpga_init_nand_ecc(struct altr_edac_device_dev *device) 1364 { 1365 int ret; 1366 1367 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc"); 1368 if (ret) 1369 return ret; 1370 1371 return altr_check_ecc_deps(device); 1372 } 1373 1374 static const struct edac_device_prv_data a10_nandecc_data = { 1375 .setup = socfpga_init_nand_ecc, 1376 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1377 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1378 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1379 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1380 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1381 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1382 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1383 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1384 .inject_fops = &altr_edac_a10_device_inject_fops, 1385 }; 1386 1387 #endif /* CONFIG_EDAC_ALTERA_NAND */ 1388 1389 /********************** DMA Device Functions **********************/ 1390 1391 #ifdef CONFIG_EDAC_ALTERA_DMA 1392 1393 static int socfpga_init_dma_ecc(struct altr_edac_device_dev *device) 1394 { 1395 int ret; 1396 1397 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc"); 1398 if (ret) 1399 return ret; 1400 1401 return altr_check_ecc_deps(device); 1402 } 1403 1404 static const struct edac_device_prv_data a10_dmaecc_data = { 1405 .setup = socfpga_init_dma_ecc, 1406 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1407 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1408 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1409 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1410 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1411 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1412 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1413 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1414 .inject_fops = &altr_edac_a10_device_inject_fops, 1415 }; 1416 1417 #endif /* CONFIG_EDAC_ALTERA_DMA */ 1418 1419 /********************** USB Device Functions **********************/ 1420 1421 #ifdef CONFIG_EDAC_ALTERA_USB 1422 1423 static int socfpga_init_usb_ecc(struct altr_edac_device_dev *device) 1424 { 1425 int ret; 1426 1427 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc"); 1428 if (ret) 1429 return ret; 1430 1431 return altr_check_ecc_deps(device); 1432 } 1433 1434 static const struct edac_device_prv_data a10_usbecc_data = { 1435 .setup = socfpga_init_usb_ecc, 1436 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1437 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1438 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1439 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1440 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1441 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1442 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1443 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1444 .inject_fops = &altr_edac_a10_device_inject_fops, 1445 }; 1446 1447 #endif /* CONFIG_EDAC_ALTERA_USB */ 1448 1449 /********************** QSPI Device Functions **********************/ 1450 1451 #ifdef CONFIG_EDAC_ALTERA_QSPI 1452 1453 static int socfpga_init_qspi_ecc(struct altr_edac_device_dev *device) 1454 { 1455 int ret; 1456 1457 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc"); 1458 if (ret) 1459 return ret; 1460 1461 return altr_check_ecc_deps(device); 1462 } 1463 1464 static const struct edac_device_prv_data a10_qspiecc_data = { 1465 .setup = socfpga_init_qspi_ecc, 1466 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1467 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1468 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1469 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1470 .ce_set_mask = ALTR_A10_ECC_TSERRA, 1471 .ue_set_mask = ALTR_A10_ECC_TDERRA, 1472 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1473 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1474 .inject_fops = &altr_edac_a10_device_inject_fops, 1475 }; 1476 1477 #endif /* CONFIG_EDAC_ALTERA_QSPI */ 1478 1479 /********************* SDMMC Device Functions **********************/ 1480 1481 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1482 1483 static const struct edac_device_prv_data a10_sdmmceccb_data; 1484 static int altr_portb_setup(struct altr_edac_device_dev *device) 1485 { 1486 struct edac_device_ctl_info *dci; 1487 struct altr_edac_device_dev *altdev; 1488 char *ecc_name = "sdmmcb-ecc"; 1489 int edac_idx, rc; 1490 struct device_node *np; 1491 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data; 1492 bool is_s10 = device->edac->is_s10; 1493 1494 rc = altr_check_ecc_deps(device); 1495 if (rc) 1496 return rc; 1497 1498 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1499 if (!np) { 1500 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n"); 1501 return -ENODEV; 1502 } 1503 1504 /* Create the PortB EDAC device */ 1505 edac_idx = edac_device_alloc_index(); 1506 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1, 1507 ecc_name, 1, 0, edac_idx); 1508 if (!dci) { 1509 of_node_put(np); 1510 edac_printk(KERN_ERR, EDAC_DEVICE, 1511 "%s: Unable to allocate PortB EDAC device\n", 1512 ecc_name); 1513 return -ENOMEM; 1514 } 1515 1516 /* Initialize the PortB EDAC device structure from PortA structure */ 1517 altdev = dci->pvt_info; 1518 *altdev = *device; 1519 1520 if (!devres_open_group(device->edac->dev, altr_portb_setup, GFP_KERNEL)) { 1521 edac_device_free_ctl_info(dci); 1522 of_node_put(np); 1523 return -ENOMEM; 1524 } 1525 1526 /* Update PortB specific values */ 1527 altdev->edac_dev_name = ecc_name; 1528 altdev->edac_idx = edac_idx; 1529 altdev->edac_dev = dci; 1530 altdev->data = prv; 1531 dci->dev = &altdev->ddev; 1532 dci->ctl_name = "Altera ECC Manager"; 1533 dci->mod_name = ecc_name; 1534 dci->dev_name = ecc_name; 1535 1536 /* 1537 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly 1538 */ 1539 1540 /* Using compatibles to determine the IRQ Index */ 1541 if (is_s10) 1542 altdev->sb_irq = irq_of_parse_and_map(np, 1); 1543 else 1544 altdev->sb_irq = irq_of_parse_and_map(np, 2); 1545 1546 if (!altdev->sb_irq) { 1547 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n"); 1548 rc = -ENODEV; 1549 goto err_release_group_1; 1550 } 1551 rc = devm_request_irq(device->edac->dev, altdev->sb_irq, 1552 prv->ecc_irq_handler, IRQF_TRIGGER_HIGH, 1553 ecc_name, altdev); 1554 if (rc) { 1555 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n"); 1556 goto err_release_group_1; 1557 } 1558 1559 if (is_s10) { 1560 /* Use IRQ to determine SError origin instead of assigning IRQ */ 1561 rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq); 1562 if (rc) { 1563 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); 1564 goto err_release_group_1; 1565 } 1566 } else { 1567 altdev->db_irq = irq_of_parse_and_map(np, 3); 1568 if (!altdev->db_irq) { 1569 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n"); 1570 rc = -ENODEV; 1571 goto err_release_group_1; 1572 } 1573 rc = devm_request_irq(device->edac->dev, altdev->db_irq, 1574 prv->ecc_irq_handler, IRQF_TRIGGER_HIGH, 1575 ecc_name, altdev); 1576 if (rc) { 1577 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n"); 1578 goto err_release_group_1; 1579 } 1580 } 1581 1582 rc = edac_device_add_device(dci); 1583 if (rc) { 1584 edac_printk(KERN_ERR, EDAC_DEVICE, 1585 "edac_device_add_device portB failed\n"); 1586 rc = -ENOMEM; 1587 goto err_release_group_1; 1588 } 1589 of_node_put(np); 1590 1591 altr_create_edacdev_dbgfs(dci, prv); 1592 1593 list_add(&altdev->next, &altdev->edac->a10_ecc_devices); 1594 1595 devres_remove_group(device->edac->dev, altr_portb_setup); 1596 1597 return 0; 1598 1599 err_release_group_1: 1600 /* 1601 * Release the devres group first so the managed IRQs are 1602 * unregistered before dci (which contains the IRQ handler's 1603 * data via dci->pvt_info) is freed, avoiding a use-after-free. 1604 */ 1605 devres_release_group(device->edac->dev, altr_portb_setup); 1606 edac_device_free_ctl_info(dci); 1607 of_node_put(np); 1608 edac_printk(KERN_ERR, EDAC_DEVICE, 1609 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 1610 return rc; 1611 } 1612 1613 static int socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device) 1614 { 1615 int rc = -ENODEV; 1616 struct device_node *child; 1617 1618 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc"); 1619 if (!child) 1620 return -ENODEV; 1621 1622 if (!of_device_is_available(child)) 1623 goto exit; 1624 1625 if (validate_parent_available(child)) 1626 goto exit; 1627 1628 /* Init portB */ 1629 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK, 1630 a10_sdmmceccb_data.ecc_enable_mask, 1); 1631 if (rc) 1632 goto exit; 1633 1634 /* Setup portB */ 1635 rc = altr_portb_setup(device); 1636 1637 exit: 1638 of_node_put(child); 1639 return rc; 1640 } 1641 1642 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id) 1643 { 1644 struct altr_edac_device_dev *ad = dev_id; 1645 void __iomem *base = ad->base; 1646 const struct edac_device_prv_data *priv = ad->data; 1647 1648 if (irq == ad->sb_irq) { 1649 writel(priv->ce_clear_mask, 1650 base + ALTR_A10_ECC_INTSTAT_OFST); 1651 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name); 1652 return IRQ_HANDLED; 1653 } else if (irq == ad->db_irq) { 1654 writel(priv->ue_clear_mask, 1655 base + ALTR_A10_ECC_INTSTAT_OFST); 1656 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name); 1657 return IRQ_HANDLED; 1658 } 1659 1660 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq); 1661 1662 return IRQ_NONE; 1663 } 1664 1665 static const struct edac_device_prv_data a10_sdmmcecca_data = { 1666 .setup = socfpga_init_sdmmc_ecc, 1667 .ce_clear_mask = ALTR_A10_ECC_SERRPENA, 1668 .ue_clear_mask = ALTR_A10_ECC_DERRPENA, 1669 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1670 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1671 .ce_set_mask = ALTR_A10_ECC_SERRPENA, 1672 .ue_set_mask = ALTR_A10_ECC_DERRPENA, 1673 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1674 .ecc_irq_handler = altr_edac_a10_ecc_irq, 1675 .inject_fops = &altr_edac_a10_device_inject_fops, 1676 }; 1677 1678 static const struct edac_device_prv_data a10_sdmmceccb_data = { 1679 .setup = socfpga_init_sdmmc_ecc, 1680 .ce_clear_mask = ALTR_A10_ECC_SERRPENB, 1681 .ue_clear_mask = ALTR_A10_ECC_DERRPENB, 1682 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL, 1683 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST, 1684 .ce_set_mask = ALTR_A10_ECC_TSERRB, 1685 .ue_set_mask = ALTR_A10_ECC_TDERRB, 1686 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST, 1687 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb, 1688 .inject_fops = &altr_edac_a10_device_inject_fops, 1689 }; 1690 1691 #endif /* CONFIG_EDAC_ALTERA_SDMMC */ 1692 1693 /********************* Arria10 EDAC Device Functions *************************/ 1694 static const struct of_device_id altr_edac_a10_device_of_match[] = { 1695 #ifdef CONFIG_EDAC_ALTERA_L2C 1696 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data }, 1697 #endif 1698 #ifdef CONFIG_EDAC_ALTERA_OCRAM 1699 { .compatible = "altr,socfpga-a10-ocram-ecc", 1700 .data = &a10_ocramecc_data }, 1701 #endif 1702 #ifdef CONFIG_EDAC_ALTERA_ETHERNET 1703 { .compatible = "altr,socfpga-eth-mac-ecc", 1704 .data = &a10_enetecc_data }, 1705 #endif 1706 #ifdef CONFIG_EDAC_ALTERA_NAND 1707 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data }, 1708 #endif 1709 #ifdef CONFIG_EDAC_ALTERA_DMA 1710 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data }, 1711 #endif 1712 #ifdef CONFIG_EDAC_ALTERA_USB 1713 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data }, 1714 #endif 1715 #ifdef CONFIG_EDAC_ALTERA_QSPI 1716 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data }, 1717 #endif 1718 #ifdef CONFIG_EDAC_ALTERA_SDMMC 1719 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data }, 1720 #endif 1721 #ifdef CONFIG_EDAC_ALTERA_SDRAM 1722 { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data }, 1723 #endif 1724 {}, 1725 }; 1726 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match); 1727 1728 /* 1729 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5 1730 * because 2 IRQs are shared among the all ECC peripherals. The ECC 1731 * manager manages the IRQs and the children. 1732 * Based on xgene_edac.c peripheral code. 1733 */ 1734 1735 static ssize_t __maybe_unused 1736 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf, 1737 size_t count, loff_t *ppos) 1738 { 1739 struct edac_device_ctl_info *edac_dci = file->private_data; 1740 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 1741 const struct edac_device_prv_data *priv = drvdata->data; 1742 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); 1743 unsigned long flags; 1744 u8 trig_type; 1745 1746 if (!user_buf || get_user(trig_type, user_buf)) 1747 return -EFAULT; 1748 1749 local_irq_save(flags); 1750 if (trig_type == ALTR_UE_TRIGGER_CHAR) 1751 writew(priv->ue_set_mask, set_addr); 1752 else 1753 writew(priv->ce_set_mask, set_addr); 1754 1755 /* Ensure the interrupt test bits are set */ 1756 wmb(); 1757 local_irq_restore(flags); 1758 1759 return count; 1760 } 1761 1762 /* 1763 * The Stratix10 EDAC Error Injection Functions differ from Arria10 1764 * slightly. A few Arria10 peripherals can use this injection function. 1765 * Inject the error into the memory and then readback to trigger the IRQ. 1766 */ 1767 static ssize_t __maybe_unused 1768 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf, 1769 size_t count, loff_t *ppos) 1770 { 1771 struct edac_device_ctl_info *edac_dci = file->private_data; 1772 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info; 1773 const struct edac_device_prv_data *priv = drvdata->data; 1774 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst); 1775 unsigned long flags; 1776 u8 trig_type; 1777 1778 if (!user_buf || get_user(trig_type, user_buf)) 1779 return -EFAULT; 1780 1781 local_irq_save(flags); 1782 if (trig_type == ALTR_UE_TRIGGER_CHAR) { 1783 writew(priv->ue_set_mask, set_addr); 1784 } else { 1785 /* Setup read/write of 4 bytes */ 1786 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST); 1787 /* Setup Address to 0 */ 1788 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST); 1789 /* Setup accctrl to read & ecc & data override */ 1790 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1791 /* Kick it. */ 1792 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1793 /* Setup write for single bit change */ 1794 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1, 1795 drvdata->base + ECC_BLK_WDATA0_OFST); 1796 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST), 1797 drvdata->base + ECC_BLK_WDATA1_OFST); 1798 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST), 1799 drvdata->base + ECC_BLK_WDATA2_OFST); 1800 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST), 1801 drvdata->base + ECC_BLK_WDATA3_OFST); 1802 1803 /* Copy Read ECC to Write ECC */ 1804 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST), 1805 drvdata->base + ECC_BLK_WECC0_OFST); 1806 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST), 1807 drvdata->base + ECC_BLK_WECC1_OFST); 1808 /* Setup accctrl to write & ecc override & data override */ 1809 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1810 /* Kick it. */ 1811 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1812 /* Setup accctrl to read & ecc overwrite & data overwrite */ 1813 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST); 1814 /* Kick it. */ 1815 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST); 1816 } 1817 1818 /* Ensure the interrupt test bits are set */ 1819 wmb(); 1820 local_irq_restore(flags); 1821 1822 return count; 1823 } 1824 1825 static void altr_edac_a10_irq_handler(struct irq_desc *desc) 1826 { 1827 int dberr, bit, sm_offset, irq_status; 1828 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc); 1829 struct irq_chip *chip = irq_desc_get_chip(desc); 1830 int irq = irq_desc_get_irq(desc); 1831 unsigned long bits; 1832 1833 dberr = (irq == edac->db_irq) ? 1 : 0; 1834 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST : 1835 A10_SYSMGR_ECC_INTSTAT_SERR_OFST; 1836 1837 chained_irq_enter(chip, desc); 1838 1839 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status); 1840 1841 bits = irq_status; 1842 for_each_set_bit(bit, &bits, 32) 1843 generic_handle_domain_irq(edac->domain, dberr * 32 + bit); 1844 1845 chained_irq_exit(chip, desc); 1846 } 1847 1848 static int validate_parent_available(struct device_node *np) 1849 { 1850 struct device_node *parent; 1851 int ret = 0; 1852 1853 /* SDRAM must be present for Linux (implied parent) */ 1854 if (of_device_is_compatible(np, "altr,sdram-edac-s10")) 1855 return 0; 1856 1857 /* Ensure parent device is enabled if parent node exists */ 1858 parent = of_parse_phandle(np, "altr,ecc-parent", 0); 1859 if (parent && !of_device_is_available(parent)) 1860 ret = -ENODEV; 1861 1862 of_node_put(parent); 1863 return ret; 1864 } 1865 1866 static int get_s10_sdram_edac_resource(struct device_node *np, 1867 struct resource *res) 1868 { 1869 struct device_node *parent; 1870 int ret; 1871 1872 parent = of_parse_phandle(np, "altr,sdr-syscon", 0); 1873 if (!parent) 1874 return -ENODEV; 1875 1876 ret = of_address_to_resource(parent, 0, res); 1877 of_node_put(parent); 1878 1879 return ret; 1880 } 1881 1882 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac, 1883 struct device_node *np) 1884 { 1885 struct edac_device_ctl_info *dci; 1886 struct altr_edac_device_dev *altdev; 1887 char *ecc_name = (char *)np->name; 1888 struct resource res; 1889 int edac_idx; 1890 int rc = 0; 1891 const struct edac_device_prv_data *prv; 1892 /* Get matching node and check for valid result */ 1893 const struct of_device_id *pdev_id = 1894 of_match_node(altr_edac_a10_device_of_match, np); 1895 if (IS_ERR_OR_NULL(pdev_id)) 1896 return -ENODEV; 1897 1898 /* Get driver specific data for this EDAC device */ 1899 prv = pdev_id->data; 1900 if (IS_ERR_OR_NULL(prv)) 1901 return -ENODEV; 1902 1903 if (validate_parent_available(np)) 1904 return -ENODEV; 1905 1906 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL)) 1907 return -ENOMEM; 1908 1909 if (of_device_is_compatible(np, "altr,sdram-edac-s10")) 1910 rc = get_s10_sdram_edac_resource(np, &res); 1911 else 1912 rc = of_address_to_resource(np, 0, &res); 1913 1914 if (rc < 0) { 1915 edac_printk(KERN_ERR, EDAC_DEVICE, 1916 "%s: no resource address\n", ecc_name); 1917 goto err_release_group; 1918 } 1919 1920 edac_idx = edac_device_alloc_index(); 1921 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1922 1, ecc_name, 1, 0, edac_idx); 1923 1924 if (!dci) { 1925 edac_printk(KERN_ERR, EDAC_DEVICE, 1926 "%s: Unable to allocate EDAC device\n", ecc_name); 1927 rc = -ENOMEM; 1928 goto err_release_group; 1929 } 1930 1931 altdev = dci->pvt_info; 1932 dci->dev = edac->dev; 1933 altdev->edac_dev_name = ecc_name; 1934 altdev->edac_idx = edac_idx; 1935 altdev->edac = edac; 1936 altdev->edac_dev = dci; 1937 altdev->data = prv; 1938 altdev->ddev = *edac->dev; 1939 dci->dev = &altdev->ddev; 1940 dci->ctl_name = "Altera ECC Manager"; 1941 dci->mod_name = ecc_name; 1942 dci->dev_name = ecc_name; 1943 1944 altdev->base = devm_ioremap_resource(edac->dev, &res); 1945 if (IS_ERR(altdev->base)) { 1946 rc = PTR_ERR(altdev->base); 1947 goto err_release_group1; 1948 } 1949 1950 /* Check specific dependencies for the module */ 1951 if (altdev->data->setup) { 1952 rc = altdev->data->setup(altdev); 1953 if (rc) 1954 goto err_release_group1; 1955 } 1956 1957 altdev->sb_irq = irq_of_parse_and_map(np, 0); 1958 if (!altdev->sb_irq) { 1959 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n"); 1960 rc = -ENODEV; 1961 goto err_release_group1; 1962 } 1963 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler, 1964 IRQF_TRIGGER_HIGH, ecc_name, altdev); 1965 if (rc) { 1966 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n"); 1967 goto err_release_group1; 1968 } 1969 1970 if (edac->is_s10) { 1971 /* Use IRQ to determine SError origin instead of assigning IRQ */ 1972 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq); 1973 if (rc) { 1974 edac_printk(KERN_ERR, EDAC_DEVICE, 1975 "Unable to parse DB IRQ index\n"); 1976 goto err_release_group1; 1977 } 1978 } else { 1979 altdev->db_irq = irq_of_parse_and_map(np, 1); 1980 if (!altdev->db_irq) { 1981 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n"); 1982 rc = -ENODEV; 1983 goto err_release_group1; 1984 } 1985 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler, 1986 IRQF_TRIGGER_HIGH, 1987 ecc_name, altdev); 1988 if (rc) { 1989 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n"); 1990 goto err_release_group1; 1991 } 1992 } 1993 1994 rc = edac_device_add_device(dci); 1995 if (rc) { 1996 dev_err(edac->dev, "edac_device_add_device failed\n"); 1997 rc = -ENOMEM; 1998 goto err_release_group1; 1999 } 2000 2001 altr_create_edacdev_dbgfs(dci, prv); 2002 2003 list_add(&altdev->next, &edac->a10_ecc_devices); 2004 2005 devres_remove_group(edac->dev, altr_edac_a10_device_add); 2006 2007 return 0; 2008 2009 err_release_group1: 2010 /* 2011 * Release the devres group first so the managed IRQs are 2012 * unregistered before dci (which contains the IRQ handler's 2013 * data via dci->pvt_info) is freed, avoiding a use-after-free. 2014 */ 2015 devres_release_group(edac->dev, NULL); 2016 edac_device_free_ctl_info(dci); 2017 goto err_print; 2018 err_release_group: 2019 devres_release_group(edac->dev, NULL); 2020 err_print: 2021 edac_printk(KERN_ERR, EDAC_DEVICE, 2022 "%s:Error setting up EDAC device: %d\n", ecc_name, rc); 2023 2024 return rc; 2025 } 2026 2027 static void a10_eccmgr_irq_mask(struct irq_data *d) 2028 { 2029 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 2030 2031 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, 2032 BIT(d->hwirq)); 2033 } 2034 2035 static void a10_eccmgr_irq_unmask(struct irq_data *d) 2036 { 2037 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d); 2038 2039 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, 2040 BIT(d->hwirq)); 2041 } 2042 2043 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq, 2044 irq_hw_number_t hwirq) 2045 { 2046 struct altr_arria10_edac *edac = d->host_data; 2047 2048 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq); 2049 irq_set_chip_data(irq, edac); 2050 irq_set_noprobe(irq); 2051 2052 return 0; 2053 } 2054 2055 static const struct irq_domain_ops a10_eccmgr_ic_ops = { 2056 .map = a10_eccmgr_irqdomain_map, 2057 .xlate = irq_domain_xlate_twocell, 2058 }; 2059 2060 /************** Stratix 10 EDAC Double Bit Error Handler ************/ 2061 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m) 2062 2063 /* panic routine issues reboot on non-zero panic_timeout */ 2064 extern int panic_timeout; 2065 2066 /* 2067 * The double bit error is handled through SError which is fatal. This is 2068 * called as a panic notifier to printout ECC error info as part of the panic. 2069 */ 2070 static int s10_edac_dberr_handler(struct notifier_block *this, 2071 unsigned long event, void *ptr) 2072 { 2073 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier); 2074 int err_addr, dberror; 2075 2076 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST, 2077 &dberror); 2078 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror); 2079 if (dberror & S10_DBE_IRQ_MASK) { 2080 struct list_head *position; 2081 struct altr_edac_device_dev *ed; 2082 struct arm_smccc_res result; 2083 2084 /* Find the matching DBE in the list of devices */ 2085 list_for_each(position, &edac->a10_ecc_devices) { 2086 ed = list_entry(position, struct altr_edac_device_dev, 2087 next); 2088 if (!(BIT(ed->db_irq) & dberror)) 2089 continue; 2090 2091 writel(ALTR_A10_ECC_DERRPENA, 2092 ed->base + ALTR_A10_ECC_INTSTAT_OFST); 2093 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST); 2094 regmap_write(edac->ecc_mgr_map, 2095 S10_SYSMGR_UE_ADDR_OFST, err_addr); 2096 edac_printk(KERN_ERR, EDAC_DEVICE, 2097 "EDAC: [Fatal DBE on %s @ 0x%08X]\n", 2098 ed->edac_dev_name, err_addr); 2099 break; 2100 } 2101 /* Notify the System through SMC. Reboot delay = 1 second */ 2102 panic_timeout = 1; 2103 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0, 2104 0, 0, &result); 2105 } 2106 2107 return NOTIFY_DONE; 2108 } 2109 2110 /****************** Arria 10 EDAC Probe Function *********************/ 2111 static int altr_edac_a10_probe(struct platform_device *pdev) 2112 { 2113 struct altr_arria10_edac *edac; 2114 struct device_node *child; 2115 2116 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL); 2117 if (!edac) 2118 return -ENOMEM; 2119 2120 edac->dev = &pdev->dev; 2121 platform_set_drvdata(pdev, edac); 2122 INIT_LIST_HEAD(&edac->a10_ecc_devices); 2123 2124 edac->is_s10 = !!device_get_match_data(&pdev->dev); 2125 2126 edac->ecc_mgr_map = 2127 altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node, 2128 "altr,sysmgr-syscon"); 2129 2130 if (IS_ERR(edac->ecc_mgr_map)) { 2131 edac_printk(KERN_ERR, EDAC_DEVICE, 2132 "Unable to get syscon altr,sysmgr-syscon\n"); 2133 return PTR_ERR(edac->ecc_mgr_map); 2134 } 2135 2136 /* Set irq mask for DDR SBE to avoid any pending irq before registration */ 2137 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, 2138 (A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0)); 2139 2140 edac->irq_chip.name = pdev->dev.of_node->name; 2141 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask; 2142 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask; 2143 edac->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), 64, &a10_eccmgr_ic_ops, 2144 edac); 2145 if (!edac->domain) { 2146 dev_err(&pdev->dev, "Error adding IRQ domain\n"); 2147 return -ENOMEM; 2148 } 2149 2150 edac->sb_irq = platform_get_irq(pdev, 0); 2151 if (edac->sb_irq < 0) 2152 return edac->sb_irq; 2153 2154 irq_set_chained_handler_and_data(edac->sb_irq, 2155 altr_edac_a10_irq_handler, 2156 edac); 2157 if (edac->is_s10) 2158 { 2159 int dberror, err_addr; 2160 2161 edac->panic_notifier.notifier_call = s10_edac_dberr_handler; 2162 atomic_notifier_chain_register(&panic_notifier_list, 2163 &edac->panic_notifier); 2164 2165 /* Printout a message if uncorrectable error previously. */ 2166 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, 2167 &dberror); 2168 if (dberror) { 2169 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST, 2170 &err_addr); 2171 edac_printk(KERN_ERR, EDAC_DEVICE, 2172 "Previous Boot UE detected[0x%X] @ 0x%X\n", 2173 dberror, err_addr); 2174 /* Reset the sticky registers */ 2175 regmap_write(edac->ecc_mgr_map, 2176 S10_SYSMGR_UE_VAL_OFST, 0); 2177 regmap_write(edac->ecc_mgr_map, 2178 S10_SYSMGR_UE_ADDR_OFST, 0); 2179 } 2180 } else { 2181 edac->db_irq = platform_get_irq(pdev, 1); 2182 if (edac->db_irq < 0) 2183 return edac->db_irq; 2184 2185 irq_set_chained_handler_and_data(edac->db_irq, 2186 altr_edac_a10_irq_handler, edac); 2187 } 2188 2189 for_each_child_of_node(pdev->dev.of_node, child) { 2190 if (!of_device_is_available(child)) 2191 continue; 2192 2193 if (of_match_node(altr_edac_a10_device_of_match, child)) 2194 altr_edac_a10_device_add(edac, child); 2195 2196 #ifdef CONFIG_EDAC_ALTERA_SDRAM 2197 else if (of_device_is_compatible(child, "altr,sdram-edac-a10")) 2198 of_platform_populate(pdev->dev.of_node, 2199 altr_sdram_ctrl_of_match, 2200 NULL, &pdev->dev); 2201 #endif 2202 } 2203 2204 return 0; 2205 } 2206 2207 static const struct of_device_id altr_edac_a10_of_match[] = { 2208 { .compatible = "altr,socfpga-a10-ecc-manager" }, 2209 { .compatible = "altr,socfpga-s10-ecc-manager", .data = (void *)1 }, 2210 {}, 2211 }; 2212 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match); 2213 2214 static struct platform_driver altr_edac_a10_driver = { 2215 .probe = altr_edac_a10_probe, 2216 .driver = { 2217 .name = "socfpga_a10_ecc_manager", 2218 .of_match_table = altr_edac_a10_of_match, 2219 .suppress_bind_attrs = true, 2220 }, 2221 }; 2222 module_platform_driver(altr_edac_a10_driver); 2223 2224 MODULE_AUTHOR("Thor Thayer"); 2225 MODULE_DESCRIPTION("EDAC Driver for Altera Memories"); 2226