xref: /linux/drivers/edac/altera_edac.c (revision 0750b8fcf313845b21c71344b4bea8ad7d3cee84)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4  *  Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5  *  Copyright 2011-2012 Calxeda, Inc.
6  */
7 
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/firmware/intel/stratix10-smc.h>
13 #include <linux/genalloc.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/altera-sysmgr.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/notifier.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/panic_notifier.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/types.h>
27 #include <linux/uaccess.h>
28 
29 #include "altera_edac.h"
30 #include "edac_module.h"
31 
32 #define EDAC_MOD_STR		"altera_edac"
33 #define EDAC_DEVICE		"Altera"
34 
35 #ifdef CONFIG_EDAC_ALTERA_SDRAM
36 static const struct altr_sdram_prv_data c5_data = {
37 	.ecc_ctrl_offset    = CV_CTLCFG_OFST,
38 	.ecc_ctl_en_mask    = CV_CTLCFG_ECC_AUTO_EN,
39 	.ecc_stat_offset    = CV_DRAMSTS_OFST,
40 	.ecc_stat_ce_mask   = CV_DRAMSTS_SBEERR,
41 	.ecc_stat_ue_mask   = CV_DRAMSTS_DBEERR,
42 	.ecc_saddr_offset   = CV_ERRADDR_OFST,
43 	.ecc_daddr_offset   = CV_ERRADDR_OFST,
44 	.ecc_cecnt_offset   = CV_SBECOUNT_OFST,
45 	.ecc_uecnt_offset   = CV_DBECOUNT_OFST,
46 	.ecc_irq_en_offset  = CV_DRAMINTR_OFST,
47 	.ecc_irq_en_mask    = CV_DRAMINTR_INTREN,
48 	.ecc_irq_clr_offset = CV_DRAMINTR_OFST,
49 	.ecc_irq_clr_mask   = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
50 	.ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
51 	.ecc_cnt_rst_mask   = CV_DRAMINTR_INTRCLR,
52 	.ce_ue_trgr_offset  = CV_CTLCFG_OFST,
53 	.ce_set_mask        = CV_CTLCFG_GEN_SB_ERR,
54 	.ue_set_mask        = CV_CTLCFG_GEN_DB_ERR,
55 };
56 
57 static const struct altr_sdram_prv_data a10_data = {
58 	.ecc_ctrl_offset    = A10_ECCCTRL1_OFST,
59 	.ecc_ctl_en_mask    = A10_ECCCTRL1_ECC_EN,
60 	.ecc_stat_offset    = A10_INTSTAT_OFST,
61 	.ecc_stat_ce_mask   = A10_INTSTAT_SBEERR,
62 	.ecc_stat_ue_mask   = A10_INTSTAT_DBEERR,
63 	.ecc_saddr_offset   = A10_SERRADDR_OFST,
64 	.ecc_daddr_offset   = A10_DERRADDR_OFST,
65 	.ecc_irq_en_offset  = A10_ERRINTEN_OFST,
66 	.ecc_irq_en_mask    = A10_ECC_IRQ_EN_MASK,
67 	.ecc_irq_clr_offset = A10_INTSTAT_OFST,
68 	.ecc_irq_clr_mask   = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
69 	.ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
70 	.ecc_cnt_rst_mask   = A10_ECC_CNT_RESET_MASK,
71 	.ce_ue_trgr_offset  = A10_DIAGINTTEST_OFST,
72 	.ce_set_mask        = A10_DIAGINT_TSERRA_MASK,
73 	.ue_set_mask        = A10_DIAGINT_TDERRA_MASK,
74 };
75 
76 /*********************** EDAC Memory Controller Functions ****************/
77 
78 /* The SDRAM controller uses the EDAC Memory Controller framework.       */
79 
80 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
81 {
82 	struct mem_ctl_info *mci = dev_id;
83 	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
84 	const struct altr_sdram_prv_data *priv = drvdata->data;
85 	u32 status, err_count = 1, err_addr;
86 
87 	regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
88 
89 	if (status & priv->ecc_stat_ue_mask) {
90 		regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
91 			    &err_addr);
92 		if (priv->ecc_uecnt_offset)
93 			regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
94 				    &err_count);
95 		panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
96 		      err_count, err_addr);
97 	}
98 	if (status & priv->ecc_stat_ce_mask) {
99 		regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
100 			    &err_addr);
101 		if (priv->ecc_uecnt_offset)
102 			regmap_read(drvdata->mc_vbase,  priv->ecc_cecnt_offset,
103 				    &err_count);
104 		edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
105 				     err_addr >> PAGE_SHIFT,
106 				     err_addr & ~PAGE_MASK, 0,
107 				     0, 0, -1, mci->ctl_name, "");
108 		/* Clear IRQ to resume */
109 		regmap_write(drvdata->mc_vbase,	priv->ecc_irq_clr_offset,
110 			     priv->ecc_irq_clr_mask);
111 
112 		return IRQ_HANDLED;
113 	}
114 	return IRQ_NONE;
115 }
116 
117 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
118 					    const char __user *data,
119 					    size_t count, loff_t *ppos)
120 {
121 	struct mem_ctl_info *mci = file->private_data;
122 	struct altr_sdram_mc_data *drvdata = mci->pvt_info;
123 	const struct altr_sdram_prv_data *priv = drvdata->data;
124 	u32 *ptemp;
125 	dma_addr_t dma_handle;
126 	u32 reg, read_reg;
127 
128 	ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
129 	if (!ptemp) {
130 		dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
131 		edac_printk(KERN_ERR, EDAC_MC,
132 			    "Inject: Buffer Allocation error\n");
133 		return -ENOMEM;
134 	}
135 
136 	regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
137 		    &read_reg);
138 	read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
139 
140 	/* Error are injected by writing a word while the SBE or DBE
141 	 * bit in the CTLCFG register is set. Reading the word will
142 	 * trigger the SBE or DBE error and the corresponding IRQ.
143 	 */
144 	if (count == 3) {
145 		edac_printk(KERN_ALERT, EDAC_MC,
146 			    "Inject Double bit error\n");
147 		local_irq_disable();
148 		regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
149 			     (read_reg | priv->ue_set_mask));
150 		local_irq_enable();
151 	} else {
152 		edac_printk(KERN_ALERT, EDAC_MC,
153 			    "Inject Single bit error\n");
154 		local_irq_disable();
155 		regmap_write(drvdata->mc_vbase,	priv->ce_ue_trgr_offset,
156 			     (read_reg | priv->ce_set_mask));
157 		local_irq_enable();
158 	}
159 
160 	ptemp[0] = 0x5A5A5A5A;
161 	ptemp[1] = 0xA5A5A5A5;
162 
163 	/* Clear the error injection bits */
164 	regmap_write(drvdata->mc_vbase,	priv->ce_ue_trgr_offset, read_reg);
165 	/* Ensure it has been written out */
166 	wmb();
167 
168 	/*
169 	 * To trigger the error, we need to read the data back
170 	 * (the data was written with errors above).
171 	 * The READ_ONCE macros and printk are used to prevent the
172 	 * the compiler optimizing these reads out.
173 	 */
174 	reg = READ_ONCE(ptemp[0]);
175 	read_reg = READ_ONCE(ptemp[1]);
176 	/* Force Read */
177 	rmb();
178 
179 	edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
180 		    reg, read_reg);
181 
182 	dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
183 
184 	return count;
185 }
186 
187 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
188 	.open = simple_open,
189 	.write = altr_sdr_mc_err_inject_write,
190 	.llseek = generic_file_llseek,
191 };
192 
193 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
194 {
195 	if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
196 		return;
197 
198 	if (!mci->debugfs)
199 		return;
200 
201 	edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
202 				 &altr_sdr_mc_debug_inject_fops);
203 }
204 
205 /* Get total memory size from Open Firmware DTB */
206 static unsigned long get_total_mem(void)
207 {
208 	struct device_node *np = NULL;
209 	struct resource res;
210 	int ret;
211 	unsigned long total_mem = 0;
212 
213 	for_each_node_by_type(np, "memory") {
214 		ret = of_address_to_resource(np, 0, &res);
215 		if (ret)
216 			continue;
217 
218 		total_mem += resource_size(&res);
219 	}
220 	edac_dbg(0, "total_mem 0x%lx\n", total_mem);
221 	return total_mem;
222 }
223 
224 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
225 	{ .compatible = "altr,sdram-edac", .data = &c5_data},
226 	{ .compatible = "altr,sdram-edac-a10", .data = &a10_data},
227 	{},
228 };
229 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
230 
231 static int a10_init(struct regmap *mc_vbase)
232 {
233 	if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
234 			       A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
235 		edac_printk(KERN_ERR, EDAC_MC,
236 			    "Error setting SB IRQ mode\n");
237 		return -ENODEV;
238 	}
239 
240 	if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
241 		edac_printk(KERN_ERR, EDAC_MC,
242 			    "Error setting trigger count\n");
243 		return -ENODEV;
244 	}
245 
246 	return 0;
247 }
248 
249 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
250 {
251 	void __iomem  *sm_base;
252 	int  ret = 0;
253 
254 	if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
255 				dev_name(&pdev->dev))) {
256 		edac_printk(KERN_ERR, EDAC_MC,
257 			    "Unable to request mem region\n");
258 		return -EBUSY;
259 	}
260 
261 	sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
262 	if (!sm_base) {
263 		edac_printk(KERN_ERR, EDAC_MC,
264 			    "Unable to ioremap device\n");
265 
266 		ret = -ENOMEM;
267 		goto release;
268 	}
269 
270 	iowrite32(mask, sm_base);
271 
272 	iounmap(sm_base);
273 
274 release:
275 	release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
276 
277 	return ret;
278 }
279 
280 static int altr_sdram_probe(struct platform_device *pdev)
281 {
282 	const struct of_device_id *id;
283 	struct edac_mc_layer layers[2];
284 	struct mem_ctl_info *mci;
285 	struct altr_sdram_mc_data *drvdata;
286 	const struct altr_sdram_prv_data *priv;
287 	struct regmap *mc_vbase;
288 	struct dimm_info *dimm;
289 	u32 read_reg;
290 	int irq, irq2, res = 0;
291 	unsigned long mem_size, irqflags = 0;
292 
293 	id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
294 	if (!id)
295 		return -ENODEV;
296 
297 	/* Grab the register range from the sdr controller in device tree */
298 	mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
299 						   "altr,sdr-syscon");
300 	if (IS_ERR(mc_vbase)) {
301 		edac_printk(KERN_ERR, EDAC_MC,
302 			    "regmap for altr,sdr-syscon lookup failed.\n");
303 		return -ENODEV;
304 	}
305 
306 	/* Check specific dependencies for the module */
307 	priv = of_match_node(altr_sdram_ctrl_of_match,
308 			     pdev->dev.of_node)->data;
309 
310 	/* Validate the SDRAM controller has ECC enabled */
311 	if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
312 	    ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
313 		edac_printk(KERN_ERR, EDAC_MC,
314 			    "No ECC/ECC disabled [0x%08X]\n", read_reg);
315 		return -ENODEV;
316 	}
317 
318 	/* Grab memory size from device tree. */
319 	mem_size = get_total_mem();
320 	if (!mem_size) {
321 		edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
322 		return -ENODEV;
323 	}
324 
325 	/* Ensure the SDRAM Interrupt is disabled */
326 	if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
327 			       priv->ecc_irq_en_mask, 0)) {
328 		edac_printk(KERN_ERR, EDAC_MC,
329 			    "Error disabling SDRAM ECC IRQ\n");
330 		return -ENODEV;
331 	}
332 
333 	/* Toggle to clear the SDRAM Error count */
334 	if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
335 			       priv->ecc_cnt_rst_mask,
336 			       priv->ecc_cnt_rst_mask)) {
337 		edac_printk(KERN_ERR, EDAC_MC,
338 			    "Error clearing SDRAM ECC count\n");
339 		return -ENODEV;
340 	}
341 
342 	if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
343 			       priv->ecc_cnt_rst_mask, 0)) {
344 		edac_printk(KERN_ERR, EDAC_MC,
345 			    "Error clearing SDRAM ECC count\n");
346 		return -ENODEV;
347 	}
348 
349 	irq = platform_get_irq(pdev, 0);
350 	if (irq < 0) {
351 		edac_printk(KERN_ERR, EDAC_MC,
352 			    "No irq %d in DT\n", irq);
353 		return irq;
354 	}
355 
356 	/* Arria10 has a 2nd IRQ */
357 	irq2 = platform_get_irq(pdev, 1);
358 
359 	layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
360 	layers[0].size = 1;
361 	layers[0].is_virt_csrow = true;
362 	layers[1].type = EDAC_MC_LAYER_CHANNEL;
363 	layers[1].size = 1;
364 	layers[1].is_virt_csrow = false;
365 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
366 			    sizeof(struct altr_sdram_mc_data));
367 	if (!mci)
368 		return -ENOMEM;
369 
370 	mci->pdev = &pdev->dev;
371 	drvdata = mci->pvt_info;
372 	drvdata->mc_vbase = mc_vbase;
373 	drvdata->data = priv;
374 	platform_set_drvdata(pdev, mci);
375 
376 	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
377 		edac_printk(KERN_ERR, EDAC_MC,
378 			    "Unable to get managed device resource\n");
379 		res = -ENOMEM;
380 		goto free;
381 	}
382 
383 	mci->mtype_cap = MEM_FLAG_DDR3;
384 	mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
385 	mci->edac_cap = EDAC_FLAG_SECDED;
386 	mci->mod_name = EDAC_MOD_STR;
387 	mci->ctl_name = dev_name(&pdev->dev);
388 	mci->scrub_mode = SCRUB_SW_SRC;
389 	mci->dev_name = dev_name(&pdev->dev);
390 
391 	dimm = *mci->dimms;
392 	dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
393 	dimm->grain = 8;
394 	dimm->dtype = DEV_X8;
395 	dimm->mtype = MEM_DDR3;
396 	dimm->edac_mode = EDAC_SECDED;
397 
398 	res = edac_mc_add_mc(mci);
399 	if (res < 0)
400 		goto err;
401 
402 	/* Only the Arria10 has separate IRQs */
403 	if (of_machine_is_compatible("altr,socfpga-arria10")) {
404 		/* Arria10 specific initialization */
405 		res = a10_init(mc_vbase);
406 		if (res < 0)
407 			goto err2;
408 
409 		res = devm_request_irq(&pdev->dev, irq2,
410 				       altr_sdram_mc_err_handler,
411 				       IRQF_SHARED, dev_name(&pdev->dev), mci);
412 		if (res < 0) {
413 			edac_mc_printk(mci, KERN_ERR,
414 				       "Unable to request irq %d\n", irq2);
415 			res = -ENODEV;
416 			goto err2;
417 		}
418 
419 		res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
420 		if (res < 0)
421 			goto err2;
422 
423 		irqflags = IRQF_SHARED;
424 	}
425 
426 	res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
427 			       irqflags, dev_name(&pdev->dev), mci);
428 	if (res < 0) {
429 		edac_mc_printk(mci, KERN_ERR,
430 			       "Unable to request irq %d\n", irq);
431 		res = -ENODEV;
432 		goto err2;
433 	}
434 
435 	/* Infrastructure ready - enable the IRQ */
436 	if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
437 			       priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
438 		edac_mc_printk(mci, KERN_ERR,
439 			       "Error enabling SDRAM ECC IRQ\n");
440 		res = -ENODEV;
441 		goto err2;
442 	}
443 
444 	altr_sdr_mc_create_debugfs_nodes(mci);
445 
446 	devres_close_group(&pdev->dev, NULL);
447 
448 	return 0;
449 
450 err2:
451 	edac_mc_del_mc(&pdev->dev);
452 err:
453 	devres_release_group(&pdev->dev, NULL);
454 free:
455 	edac_mc_free(mci);
456 	edac_printk(KERN_ERR, EDAC_MC,
457 		    "EDAC Probe Failed; Error %d\n", res);
458 
459 	return res;
460 }
461 
462 static int altr_sdram_remove(struct platform_device *pdev)
463 {
464 	struct mem_ctl_info *mci = platform_get_drvdata(pdev);
465 
466 	edac_mc_del_mc(&pdev->dev);
467 	edac_mc_free(mci);
468 	platform_set_drvdata(pdev, NULL);
469 
470 	return 0;
471 }
472 
473 /*
474  * If you want to suspend, need to disable EDAC by removing it
475  * from the device tree or defconfig.
476  */
477 #ifdef CONFIG_PM
478 static int altr_sdram_prepare(struct device *dev)
479 {
480 	pr_err("Suspend not allowed when EDAC is enabled.\n");
481 
482 	return -EPERM;
483 }
484 
485 static const struct dev_pm_ops altr_sdram_pm_ops = {
486 	.prepare = altr_sdram_prepare,
487 };
488 #endif
489 
490 static struct platform_driver altr_sdram_edac_driver = {
491 	.probe = altr_sdram_probe,
492 	.remove = altr_sdram_remove,
493 	.driver = {
494 		.name = "altr_sdram_edac",
495 #ifdef CONFIG_PM
496 		.pm = &altr_sdram_pm_ops,
497 #endif
498 		.of_match_table = altr_sdram_ctrl_of_match,
499 	},
500 };
501 
502 module_platform_driver(altr_sdram_edac_driver);
503 
504 #endif	/* CONFIG_EDAC_ALTERA_SDRAM */
505 
506 /************************* EDAC Parent Probe *************************/
507 
508 static const struct of_device_id altr_edac_device_of_match[];
509 
510 static const struct of_device_id altr_edac_of_match[] = {
511 	{ .compatible = "altr,socfpga-ecc-manager" },
512 	{},
513 };
514 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
515 
516 static int altr_edac_probe(struct platform_device *pdev)
517 {
518 	of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
519 			     NULL, &pdev->dev);
520 	return 0;
521 }
522 
523 static struct platform_driver altr_edac_driver = {
524 	.probe =  altr_edac_probe,
525 	.driver = {
526 		.name = "socfpga_ecc_manager",
527 		.of_match_table = altr_edac_of_match,
528 	},
529 };
530 module_platform_driver(altr_edac_driver);
531 
532 /************************* EDAC Device Functions *************************/
533 
534 /*
535  * EDAC Device Functions (shared between various IPs).
536  * The discrete memories use the EDAC Device framework. The probe
537  * and error handling functions are very similar between memories
538  * so they are shared. The memory allocation and freeing for EDAC
539  * trigger testing are different for each memory.
540  */
541 
542 #ifdef CONFIG_EDAC_ALTERA_OCRAM
543 static const struct edac_device_prv_data ocramecc_data;
544 #endif
545 #ifdef CONFIG_EDAC_ALTERA_L2C
546 static const struct edac_device_prv_data l2ecc_data;
547 #endif
548 #ifdef CONFIG_EDAC_ALTERA_OCRAM
549 static const struct edac_device_prv_data a10_ocramecc_data;
550 #endif
551 #ifdef CONFIG_EDAC_ALTERA_L2C
552 static const struct edac_device_prv_data a10_l2ecc_data;
553 #endif
554 
555 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
556 {
557 	irqreturn_t ret_value = IRQ_NONE;
558 	struct edac_device_ctl_info *dci = dev_id;
559 	struct altr_edac_device_dev *drvdata = dci->pvt_info;
560 	const struct edac_device_prv_data *priv = drvdata->data;
561 
562 	if (irq == drvdata->sb_irq) {
563 		if (priv->ce_clear_mask)
564 			writel(priv->ce_clear_mask, drvdata->base);
565 		edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
566 		ret_value = IRQ_HANDLED;
567 	} else if (irq == drvdata->db_irq) {
568 		if (priv->ue_clear_mask)
569 			writel(priv->ue_clear_mask, drvdata->base);
570 		edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
571 		panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
572 		ret_value = IRQ_HANDLED;
573 	} else {
574 		WARN_ON(1);
575 	}
576 
577 	return ret_value;
578 }
579 
580 static ssize_t __maybe_unused
581 altr_edac_device_trig(struct file *file, const char __user *user_buf,
582 		      size_t count, loff_t *ppos)
583 
584 {
585 	u32 *ptemp, i, error_mask;
586 	int result = 0;
587 	u8 trig_type;
588 	unsigned long flags;
589 	struct edac_device_ctl_info *edac_dci = file->private_data;
590 	struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
591 	const struct edac_device_prv_data *priv = drvdata->data;
592 	void *generic_ptr = edac_dci->dev;
593 
594 	if (!user_buf || get_user(trig_type, user_buf))
595 		return -EFAULT;
596 
597 	if (!priv->alloc_mem)
598 		return -ENOMEM;
599 
600 	/*
601 	 * Note that generic_ptr is initialized to the device * but in
602 	 * some alloc_functions, this is overridden and returns data.
603 	 */
604 	ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
605 	if (!ptemp) {
606 		edac_printk(KERN_ERR, EDAC_DEVICE,
607 			    "Inject: Buffer Allocation error\n");
608 		return -ENOMEM;
609 	}
610 
611 	if (trig_type == ALTR_UE_TRIGGER_CHAR)
612 		error_mask = priv->ue_set_mask;
613 	else
614 		error_mask = priv->ce_set_mask;
615 
616 	edac_printk(KERN_ALERT, EDAC_DEVICE,
617 		    "Trigger Error Mask (0x%X)\n", error_mask);
618 
619 	local_irq_save(flags);
620 	/* write ECC corrupted data out. */
621 	for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
622 		/* Read data so we're in the correct state */
623 		rmb();
624 		if (READ_ONCE(ptemp[i]))
625 			result = -1;
626 		/* Toggle Error bit (it is latched), leave ECC enabled */
627 		writel(error_mask, (drvdata->base + priv->set_err_ofst));
628 		writel(priv->ecc_enable_mask, (drvdata->base +
629 					       priv->set_err_ofst));
630 		ptemp[i] = i;
631 	}
632 	/* Ensure it has been written out */
633 	wmb();
634 	local_irq_restore(flags);
635 
636 	if (result)
637 		edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
638 
639 	/* Read out written data. ECC error caused here */
640 	for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
641 		if (READ_ONCE(ptemp[i]) != i)
642 			edac_printk(KERN_ERR, EDAC_DEVICE,
643 				    "Read doesn't match written data\n");
644 
645 	if (priv->free_mem)
646 		priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
647 
648 	return count;
649 }
650 
651 static const struct file_operations altr_edac_device_inject_fops __maybe_unused = {
652 	.open = simple_open,
653 	.write = altr_edac_device_trig,
654 	.llseek = generic_file_llseek,
655 };
656 
657 static ssize_t __maybe_unused
658 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
659 			  size_t count, loff_t *ppos);
660 
661 static const struct file_operations altr_edac_a10_device_inject_fops __maybe_unused = {
662 	.open = simple_open,
663 	.write = altr_edac_a10_device_trig,
664 	.llseek = generic_file_llseek,
665 };
666 
667 static ssize_t __maybe_unused
668 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
669 			   size_t count, loff_t *ppos);
670 
671 static const struct file_operations altr_edac_a10_device_inject2_fops __maybe_unused = {
672 	.open = simple_open,
673 	.write = altr_edac_a10_device_trig2,
674 	.llseek = generic_file_llseek,
675 };
676 
677 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
678 				      const struct edac_device_prv_data *priv)
679 {
680 	struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
681 
682 	if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
683 		return;
684 
685 	drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
686 	if (!drvdata->debugfs_dir)
687 		return;
688 
689 	if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
690 				      drvdata->debugfs_dir, edac_dci,
691 				      priv->inject_fops))
692 		debugfs_remove_recursive(drvdata->debugfs_dir);
693 }
694 
695 static const struct of_device_id altr_edac_device_of_match[] = {
696 #ifdef CONFIG_EDAC_ALTERA_L2C
697 	{ .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
698 #endif
699 #ifdef CONFIG_EDAC_ALTERA_OCRAM
700 	{ .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
701 #endif
702 	{},
703 };
704 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
705 
706 /*
707  * altr_edac_device_probe()
708  *	This is a generic EDAC device driver that will support
709  *	various Altera memory devices such as the L2 cache ECC and
710  *	OCRAM ECC as well as the memories for other peripherals.
711  *	Module specific initialization is done by passing the
712  *	function index in the device tree.
713  */
714 static int altr_edac_device_probe(struct platform_device *pdev)
715 {
716 	struct edac_device_ctl_info *dci;
717 	struct altr_edac_device_dev *drvdata;
718 	struct resource *r;
719 	int res = 0;
720 	struct device_node *np = pdev->dev.of_node;
721 	char *ecc_name = (char *)np->name;
722 	static int dev_instance;
723 
724 	if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
725 		edac_printk(KERN_ERR, EDAC_DEVICE,
726 			    "Unable to open devm\n");
727 		return -ENOMEM;
728 	}
729 
730 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
731 	if (!r) {
732 		edac_printk(KERN_ERR, EDAC_DEVICE,
733 			    "Unable to get mem resource\n");
734 		res = -ENODEV;
735 		goto fail;
736 	}
737 
738 	if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
739 				     dev_name(&pdev->dev))) {
740 		edac_printk(KERN_ERR, EDAC_DEVICE,
741 			    "%s:Error requesting mem region\n", ecc_name);
742 		res = -EBUSY;
743 		goto fail;
744 	}
745 
746 	dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
747 					 1, ecc_name, 1, 0, NULL, 0,
748 					 dev_instance++);
749 
750 	if (!dci) {
751 		edac_printk(KERN_ERR, EDAC_DEVICE,
752 			    "%s: Unable to allocate EDAC device\n", ecc_name);
753 		res = -ENOMEM;
754 		goto fail;
755 	}
756 
757 	drvdata = dci->pvt_info;
758 	dci->dev = &pdev->dev;
759 	platform_set_drvdata(pdev, dci);
760 	drvdata->edac_dev_name = ecc_name;
761 
762 	drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
763 	if (!drvdata->base) {
764 		res = -ENOMEM;
765 		goto fail1;
766 	}
767 
768 	/* Get driver specific data for this EDAC device */
769 	drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
770 
771 	/* Check specific dependencies for the module */
772 	if (drvdata->data->setup) {
773 		res = drvdata->data->setup(drvdata);
774 		if (res)
775 			goto fail1;
776 	}
777 
778 	drvdata->sb_irq = platform_get_irq(pdev, 0);
779 	res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
780 			       altr_edac_device_handler,
781 			       0, dev_name(&pdev->dev), dci);
782 	if (res)
783 		goto fail1;
784 
785 	drvdata->db_irq = platform_get_irq(pdev, 1);
786 	res = devm_request_irq(&pdev->dev, drvdata->db_irq,
787 			       altr_edac_device_handler,
788 			       0, dev_name(&pdev->dev), dci);
789 	if (res)
790 		goto fail1;
791 
792 	dci->mod_name = "Altera ECC Manager";
793 	dci->dev_name = drvdata->edac_dev_name;
794 
795 	res = edac_device_add_device(dci);
796 	if (res)
797 		goto fail1;
798 
799 	altr_create_edacdev_dbgfs(dci, drvdata->data);
800 
801 	devres_close_group(&pdev->dev, NULL);
802 
803 	return 0;
804 
805 fail1:
806 	edac_device_free_ctl_info(dci);
807 fail:
808 	devres_release_group(&pdev->dev, NULL);
809 	edac_printk(KERN_ERR, EDAC_DEVICE,
810 		    "%s:Error setting up EDAC device: %d\n", ecc_name, res);
811 
812 	return res;
813 }
814 
815 static int altr_edac_device_remove(struct platform_device *pdev)
816 {
817 	struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
818 	struct altr_edac_device_dev *drvdata = dci->pvt_info;
819 
820 	debugfs_remove_recursive(drvdata->debugfs_dir);
821 	edac_device_del_device(&pdev->dev);
822 	edac_device_free_ctl_info(dci);
823 
824 	return 0;
825 }
826 
827 static struct platform_driver altr_edac_device_driver = {
828 	.probe =  altr_edac_device_probe,
829 	.remove = altr_edac_device_remove,
830 	.driver = {
831 		.name = "altr_edac_device",
832 		.of_match_table = altr_edac_device_of_match,
833 	},
834 };
835 module_platform_driver(altr_edac_device_driver);
836 
837 /******************* Arria10 Device ECC Shared Functions *****************/
838 
839 /*
840  *  Test for memory's ECC dependencies upon entry because platform specific
841  *  startup should have initialized the memory and enabled the ECC.
842  *  Can't turn on ECC here because accessing un-initialized memory will
843  *  cause CE/UE errors possibly causing an ABORT.
844  */
845 static int __maybe_unused
846 altr_check_ecc_deps(struct altr_edac_device_dev *device)
847 {
848 	void __iomem  *base = device->base;
849 	const struct edac_device_prv_data *prv = device->data;
850 
851 	if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
852 		return 0;
853 
854 	edac_printk(KERN_ERR, EDAC_DEVICE,
855 		    "%s: No ECC present or ECC disabled.\n",
856 		    device->edac_dev_name);
857 	return -ENODEV;
858 }
859 
860 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
861 {
862 	struct altr_edac_device_dev *dci = dev_id;
863 	void __iomem  *base = dci->base;
864 
865 	if (irq == dci->sb_irq) {
866 		writel(ALTR_A10_ECC_SERRPENA,
867 		       base + ALTR_A10_ECC_INTSTAT_OFST);
868 		edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
869 
870 		return IRQ_HANDLED;
871 	} else if (irq == dci->db_irq) {
872 		writel(ALTR_A10_ECC_DERRPENA,
873 		       base + ALTR_A10_ECC_INTSTAT_OFST);
874 		edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
875 		if (dci->data->panic)
876 			panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
877 
878 		return IRQ_HANDLED;
879 	}
880 
881 	WARN_ON(1);
882 
883 	return IRQ_NONE;
884 }
885 
886 /******************* Arria10 Memory Buffer Functions *********************/
887 
888 static inline int a10_get_irq_mask(struct device_node *np)
889 {
890 	int irq;
891 	const u32 *handle = of_get_property(np, "interrupts", NULL);
892 
893 	if (!handle)
894 		return -ENODEV;
895 	irq = be32_to_cpup(handle);
896 	return irq;
897 }
898 
899 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
900 {
901 	u32 value = readl(ioaddr);
902 
903 	value |= bit_mask;
904 	writel(value, ioaddr);
905 }
906 
907 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
908 {
909 	u32 value = readl(ioaddr);
910 
911 	value &= ~bit_mask;
912 	writel(value, ioaddr);
913 }
914 
915 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
916 {
917 	u32 value = readl(ioaddr);
918 
919 	return (value & bit_mask) ? 1 : 0;
920 }
921 
922 /*
923  * This function uses the memory initialization block in the Arria10 ECC
924  * controller to initialize/clear the entire memory data and ECC data.
925  */
926 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
927 {
928 	int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
929 	u32 init_mask, stat_mask, clear_mask;
930 	int ret = 0;
931 
932 	if (port) {
933 		init_mask = ALTR_A10_ECC_INITB;
934 		stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
935 		clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
936 	} else {
937 		init_mask = ALTR_A10_ECC_INITA;
938 		stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
939 		clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
940 	}
941 
942 	ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
943 	while (limit--) {
944 		if (ecc_test_bits(stat_mask,
945 				  (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
946 			break;
947 		udelay(1);
948 	}
949 	if (limit < 0)
950 		ret = -EBUSY;
951 
952 	/* Clear any pending ECC interrupts */
953 	writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
954 
955 	return ret;
956 }
957 
958 static __init int __maybe_unused
959 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
960 			u32 ecc_ctrl_en_mask, bool dual_port)
961 {
962 	int ret = 0;
963 	void __iomem *ecc_block_base;
964 	struct regmap *ecc_mgr_map;
965 	char *ecc_name;
966 	struct device_node *np_eccmgr;
967 
968 	ecc_name = (char *)np->name;
969 
970 	/* Get the ECC Manager - parent of the device EDACs */
971 	np_eccmgr = of_get_parent(np);
972 
973 	ecc_mgr_map =
974 		altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,
975 						     "altr,sysmgr-syscon");
976 
977 	of_node_put(np_eccmgr);
978 	if (IS_ERR(ecc_mgr_map)) {
979 		edac_printk(KERN_ERR, EDAC_DEVICE,
980 			    "Unable to get syscon altr,sysmgr-syscon\n");
981 		return -ENODEV;
982 	}
983 
984 	/* Map the ECC Block */
985 	ecc_block_base = of_iomap(np, 0);
986 	if (!ecc_block_base) {
987 		edac_printk(KERN_ERR, EDAC_DEVICE,
988 			    "Unable to map %s ECC block\n", ecc_name);
989 		return -ENODEV;
990 	}
991 
992 	/* Disable ECC */
993 	regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
994 	writel(ALTR_A10_ECC_SERRINTEN,
995 	       (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
996 	ecc_clear_bits(ecc_ctrl_en_mask,
997 		       (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
998 	/* Ensure all writes complete */
999 	wmb();
1000 	/* Use HW initialization block to initialize memory for ECC */
1001 	ret = altr_init_memory_port(ecc_block_base, 0);
1002 	if (ret) {
1003 		edac_printk(KERN_ERR, EDAC_DEVICE,
1004 			    "ECC: cannot init %s PORTA memory\n", ecc_name);
1005 		goto out;
1006 	}
1007 
1008 	if (dual_port) {
1009 		ret = altr_init_memory_port(ecc_block_base, 1);
1010 		if (ret) {
1011 			edac_printk(KERN_ERR, EDAC_DEVICE,
1012 				    "ECC: cannot init %s PORTB memory\n",
1013 				    ecc_name);
1014 			goto out;
1015 		}
1016 	}
1017 
1018 	/* Interrupt mode set to every SBERR */
1019 	regmap_write(ecc_mgr_map, ALTR_A10_ECC_INTMODE_OFST,
1020 		     ALTR_A10_ECC_INTMODE);
1021 	/* Enable ECC */
1022 	ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1023 					ALTR_A10_ECC_CTRL_OFST));
1024 	writel(ALTR_A10_ECC_SERRINTEN,
1025 	       (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1026 	regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1027 	/* Ensure all writes complete */
1028 	wmb();
1029 out:
1030 	iounmap(ecc_block_base);
1031 	return ret;
1032 }
1033 
1034 static int validate_parent_available(struct device_node *np);
1035 static const struct of_device_id altr_edac_a10_device_of_match[];
1036 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1037 {
1038 	int irq;
1039 	struct device_node *child, *np;
1040 
1041 	np = of_find_compatible_node(NULL, NULL,
1042 				     "altr,socfpga-a10-ecc-manager");
1043 	if (!np) {
1044 		edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1045 		return -ENODEV;
1046 	}
1047 
1048 	for_each_child_of_node(np, child) {
1049 		const struct of_device_id *pdev_id;
1050 		const struct edac_device_prv_data *prv;
1051 
1052 		if (!of_device_is_available(child))
1053 			continue;
1054 		if (!of_device_is_compatible(child, compat))
1055 			continue;
1056 
1057 		if (validate_parent_available(child))
1058 			continue;
1059 
1060 		irq = a10_get_irq_mask(child);
1061 		if (irq < 0)
1062 			continue;
1063 
1064 		/* Get matching node and check for valid result */
1065 		pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1066 		if (IS_ERR_OR_NULL(pdev_id))
1067 			continue;
1068 
1069 		/* Validate private data pointer before dereferencing */
1070 		prv = pdev_id->data;
1071 		if (!prv)
1072 			continue;
1073 
1074 		altr_init_a10_ecc_block(child, BIT(irq),
1075 					prv->ecc_enable_mask, 0);
1076 	}
1077 
1078 	of_node_put(np);
1079 	return 0;
1080 }
1081 
1082 /*********************** SDRAM EDAC Device Functions *********************/
1083 
1084 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1085 
1086 static const struct edac_device_prv_data s10_sdramecc_data = {
1087 	.setup = altr_check_ecc_deps,
1088 	.ce_clear_mask = ALTR_S10_ECC_SERRPENA,
1089 	.ue_clear_mask = ALTR_S10_ECC_DERRPENA,
1090 	.ecc_enable_mask = ALTR_S10_ECC_EN,
1091 	.ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
1092 	.ce_set_mask = ALTR_S10_ECC_TSERRA,
1093 	.ue_set_mask = ALTR_S10_ECC_TDERRA,
1094 	.set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
1095 	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1096 	.inject_fops = &altr_edac_a10_device_inject_fops,
1097 };
1098 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
1099 
1100 /*********************** OCRAM EDAC Device Functions *********************/
1101 
1102 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1103 
1104 static void *ocram_alloc_mem(size_t size, void **other)
1105 {
1106 	struct device_node *np;
1107 	struct gen_pool *gp;
1108 	void *sram_addr;
1109 
1110 	np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1111 	if (!np)
1112 		return NULL;
1113 
1114 	gp = of_gen_pool_get(np, "iram", 0);
1115 	of_node_put(np);
1116 	if (!gp)
1117 		return NULL;
1118 
1119 	sram_addr = (void *)gen_pool_alloc(gp, size);
1120 	if (!sram_addr)
1121 		return NULL;
1122 
1123 	memset(sram_addr, 0, size);
1124 	/* Ensure data is written out */
1125 	wmb();
1126 
1127 	/* Remember this handle for freeing  later */
1128 	*other = gp;
1129 
1130 	return sram_addr;
1131 }
1132 
1133 static void ocram_free_mem(void *p, size_t size, void *other)
1134 {
1135 	gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1136 }
1137 
1138 static const struct edac_device_prv_data ocramecc_data = {
1139 	.setup = altr_check_ecc_deps,
1140 	.ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1141 	.ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1142 	.alloc_mem = ocram_alloc_mem,
1143 	.free_mem = ocram_free_mem,
1144 	.ecc_enable_mask = ALTR_OCR_ECC_EN,
1145 	.ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1146 	.ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1147 	.ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1148 	.set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1149 	.trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1150 	.inject_fops = &altr_edac_device_inject_fops,
1151 };
1152 
1153 static int __maybe_unused
1154 altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
1155 {
1156 	void __iomem  *base = device->base;
1157 	int ret;
1158 
1159 	ret = altr_check_ecc_deps(device);
1160 	if (ret)
1161 		return ret;
1162 
1163 	/* Verify OCRAM has been initialized */
1164 	if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
1165 			   (base + ALTR_A10_ECC_INITSTAT_OFST)))
1166 		return -ENODEV;
1167 
1168 	/* Enable IRQ on Single Bit Error */
1169 	writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
1170 	/* Ensure all writes complete */
1171 	wmb();
1172 
1173 	return 0;
1174 }
1175 
1176 static const struct edac_device_prv_data a10_ocramecc_data = {
1177 	.setup = altr_check_ocram_deps_init,
1178 	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1179 	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1180 	.irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1181 	.ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1182 	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1183 	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1184 	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1185 	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1186 	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1187 	.inject_fops = &altr_edac_a10_device_inject2_fops,
1188 	/*
1189 	 * OCRAM panic on uncorrectable error because sleep/resume
1190 	 * functions and FPGA contents are stored in OCRAM. Prefer
1191 	 * a kernel panic over executing/loading corrupted data.
1192 	 */
1193 	.panic = true,
1194 };
1195 
1196 #endif	/* CONFIG_EDAC_ALTERA_OCRAM */
1197 
1198 /********************* L2 Cache EDAC Device Functions ********************/
1199 
1200 #ifdef CONFIG_EDAC_ALTERA_L2C
1201 
1202 static void *l2_alloc_mem(size_t size, void **other)
1203 {
1204 	struct device *dev = *other;
1205 	void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1206 
1207 	if (!ptemp)
1208 		return NULL;
1209 
1210 	/* Make sure everything is written out */
1211 	wmb();
1212 
1213 	/*
1214 	 * Clean all cache levels up to LoC (includes L2)
1215 	 * This ensures the corrupted data is written into
1216 	 * L2 cache for readback test (which causes ECC error).
1217 	 */
1218 	flush_cache_all();
1219 
1220 	return ptemp;
1221 }
1222 
1223 static void l2_free_mem(void *p, size_t size, void *other)
1224 {
1225 	struct device *dev = other;
1226 
1227 	if (dev && p)
1228 		devm_kfree(dev, p);
1229 }
1230 
1231 /*
1232  * altr_l2_check_deps()
1233  *	Test for L2 cache ECC dependencies upon entry because
1234  *	platform specific startup should have initialized the L2
1235  *	memory and enabled the ECC.
1236  *	Bail if ECC is not enabled.
1237  *	Note that L2 Cache Enable is forced at build time.
1238  */
1239 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1240 {
1241 	void __iomem *base = device->base;
1242 	const struct edac_device_prv_data *prv = device->data;
1243 
1244 	if ((readl(base) & prv->ecc_enable_mask) ==
1245 	     prv->ecc_enable_mask)
1246 		return 0;
1247 
1248 	edac_printk(KERN_ERR, EDAC_DEVICE,
1249 		    "L2: No ECC present, or ECC disabled\n");
1250 	return -ENODEV;
1251 }
1252 
1253 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1254 {
1255 	struct altr_edac_device_dev *dci = dev_id;
1256 
1257 	if (irq == dci->sb_irq) {
1258 		regmap_write(dci->edac->ecc_mgr_map,
1259 			     A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1260 			     A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1261 		edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1262 
1263 		return IRQ_HANDLED;
1264 	} else if (irq == dci->db_irq) {
1265 		regmap_write(dci->edac->ecc_mgr_map,
1266 			     A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1267 			     A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1268 		edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1269 		panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1270 
1271 		return IRQ_HANDLED;
1272 	}
1273 
1274 	WARN_ON(1);
1275 
1276 	return IRQ_NONE;
1277 }
1278 
1279 static const struct edac_device_prv_data l2ecc_data = {
1280 	.setup = altr_l2_check_deps,
1281 	.ce_clear_mask = 0,
1282 	.ue_clear_mask = 0,
1283 	.alloc_mem = l2_alloc_mem,
1284 	.free_mem = l2_free_mem,
1285 	.ecc_enable_mask = ALTR_L2_ECC_EN,
1286 	.ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1287 	.ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1288 	.set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1289 	.trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1290 	.inject_fops = &altr_edac_device_inject_fops,
1291 };
1292 
1293 static const struct edac_device_prv_data a10_l2ecc_data = {
1294 	.setup = altr_l2_check_deps,
1295 	.ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1296 	.ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1297 	.irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1298 	.alloc_mem = l2_alloc_mem,
1299 	.free_mem = l2_free_mem,
1300 	.ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1301 	.ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1302 	.ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1303 	.set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1304 	.ecc_irq_handler = altr_edac_a10_l2_irq,
1305 	.trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1306 	.inject_fops = &altr_edac_device_inject_fops,
1307 };
1308 
1309 #endif	/* CONFIG_EDAC_ALTERA_L2C */
1310 
1311 /********************* Ethernet Device Functions ********************/
1312 
1313 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1314 
1315 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1316 {
1317 	int ret;
1318 
1319 	ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1320 	if (ret)
1321 		return ret;
1322 
1323 	return altr_check_ecc_deps(dev);
1324 }
1325 
1326 static const struct edac_device_prv_data a10_enetecc_data = {
1327 	.setup = socfpga_init_ethernet_ecc,
1328 	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1329 	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1330 	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1331 	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1332 	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1333 	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1334 	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1335 	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1336 	.inject_fops = &altr_edac_a10_device_inject2_fops,
1337 };
1338 
1339 #endif	/* CONFIG_EDAC_ALTERA_ETHERNET */
1340 
1341 /********************** NAND Device Functions **********************/
1342 
1343 #ifdef CONFIG_EDAC_ALTERA_NAND
1344 
1345 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1346 {
1347 	int ret;
1348 
1349 	ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1350 	if (ret)
1351 		return ret;
1352 
1353 	return altr_check_ecc_deps(device);
1354 }
1355 
1356 static const struct edac_device_prv_data a10_nandecc_data = {
1357 	.setup = socfpga_init_nand_ecc,
1358 	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1359 	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1360 	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1361 	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1362 	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1363 	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1364 	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1365 	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1366 	.inject_fops = &altr_edac_a10_device_inject_fops,
1367 };
1368 
1369 #endif	/* CONFIG_EDAC_ALTERA_NAND */
1370 
1371 /********************** DMA Device Functions **********************/
1372 
1373 #ifdef CONFIG_EDAC_ALTERA_DMA
1374 
1375 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1376 {
1377 	int ret;
1378 
1379 	ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1380 	if (ret)
1381 		return ret;
1382 
1383 	return altr_check_ecc_deps(device);
1384 }
1385 
1386 static const struct edac_device_prv_data a10_dmaecc_data = {
1387 	.setup = socfpga_init_dma_ecc,
1388 	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1389 	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1390 	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1391 	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1392 	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1393 	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1394 	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1395 	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1396 	.inject_fops = &altr_edac_a10_device_inject_fops,
1397 };
1398 
1399 #endif	/* CONFIG_EDAC_ALTERA_DMA */
1400 
1401 /********************** USB Device Functions **********************/
1402 
1403 #ifdef CONFIG_EDAC_ALTERA_USB
1404 
1405 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1406 {
1407 	int ret;
1408 
1409 	ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1410 	if (ret)
1411 		return ret;
1412 
1413 	return altr_check_ecc_deps(device);
1414 }
1415 
1416 static const struct edac_device_prv_data a10_usbecc_data = {
1417 	.setup = socfpga_init_usb_ecc,
1418 	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1419 	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1420 	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1421 	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1422 	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1423 	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1424 	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1425 	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1426 	.inject_fops = &altr_edac_a10_device_inject2_fops,
1427 };
1428 
1429 #endif	/* CONFIG_EDAC_ALTERA_USB */
1430 
1431 /********************** QSPI Device Functions **********************/
1432 
1433 #ifdef CONFIG_EDAC_ALTERA_QSPI
1434 
1435 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1436 {
1437 	int ret;
1438 
1439 	ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1440 	if (ret)
1441 		return ret;
1442 
1443 	return altr_check_ecc_deps(device);
1444 }
1445 
1446 static const struct edac_device_prv_data a10_qspiecc_data = {
1447 	.setup = socfpga_init_qspi_ecc,
1448 	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1449 	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1450 	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1451 	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1452 	.ce_set_mask = ALTR_A10_ECC_TSERRA,
1453 	.ue_set_mask = ALTR_A10_ECC_TDERRA,
1454 	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1455 	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1456 	.inject_fops = &altr_edac_a10_device_inject_fops,
1457 };
1458 
1459 #endif	/* CONFIG_EDAC_ALTERA_QSPI */
1460 
1461 /********************* SDMMC Device Functions **********************/
1462 
1463 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1464 
1465 static const struct edac_device_prv_data a10_sdmmceccb_data;
1466 static int altr_portb_setup(struct altr_edac_device_dev *device)
1467 {
1468 	struct edac_device_ctl_info *dci;
1469 	struct altr_edac_device_dev *altdev;
1470 	char *ecc_name = "sdmmcb-ecc";
1471 	int edac_idx, rc;
1472 	struct device_node *np;
1473 	const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1474 
1475 	rc = altr_check_ecc_deps(device);
1476 	if (rc)
1477 		return rc;
1478 
1479 	np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1480 	if (!np) {
1481 		edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1482 		return -ENODEV;
1483 	}
1484 
1485 	/* Create the PortB EDAC device */
1486 	edac_idx = edac_device_alloc_index();
1487 	dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1488 					 ecc_name, 1, 0, NULL, 0, edac_idx);
1489 	if (!dci) {
1490 		edac_printk(KERN_ERR, EDAC_DEVICE,
1491 			    "%s: Unable to allocate PortB EDAC device\n",
1492 			    ecc_name);
1493 		return -ENOMEM;
1494 	}
1495 
1496 	/* Initialize the PortB EDAC device structure from PortA structure */
1497 	altdev = dci->pvt_info;
1498 	*altdev = *device;
1499 
1500 	if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1501 		return -ENOMEM;
1502 
1503 	/* Update PortB specific values */
1504 	altdev->edac_dev_name = ecc_name;
1505 	altdev->edac_idx = edac_idx;
1506 	altdev->edac_dev = dci;
1507 	altdev->data = prv;
1508 	dci->dev = &altdev->ddev;
1509 	dci->ctl_name = "Altera ECC Manager";
1510 	dci->mod_name = ecc_name;
1511 	dci->dev_name = ecc_name;
1512 
1513 	/*
1514 	 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly
1515 	 *
1516 	 * FIXME: Instead of ifdefs with different architectures the driver
1517 	 *        should properly use compatibles.
1518 	 */
1519 #ifdef CONFIG_64BIT
1520 	altdev->sb_irq = irq_of_parse_and_map(np, 1);
1521 #else
1522 	altdev->sb_irq = irq_of_parse_and_map(np, 2);
1523 #endif
1524 	if (!altdev->sb_irq) {
1525 		edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1526 		rc = -ENODEV;
1527 		goto err_release_group_1;
1528 	}
1529 	rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1530 			      prv->ecc_irq_handler,
1531 			      IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1532 			      ecc_name, altdev);
1533 	if (rc) {
1534 		edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1535 		goto err_release_group_1;
1536 	}
1537 
1538 #ifdef CONFIG_64BIT
1539 	/* Use IRQ to determine SError origin instead of assigning IRQ */
1540 	rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
1541 	if (rc) {
1542 		edac_printk(KERN_ERR, EDAC_DEVICE,
1543 			    "Error PortB DBIRQ alloc\n");
1544 		goto err_release_group_1;
1545 	}
1546 #else
1547 	altdev->db_irq = irq_of_parse_and_map(np, 3);
1548 	if (!altdev->db_irq) {
1549 		edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1550 		rc = -ENODEV;
1551 		goto err_release_group_1;
1552 	}
1553 	rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1554 			      prv->ecc_irq_handler,
1555 			      IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1556 			      ecc_name, altdev);
1557 	if (rc) {
1558 		edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1559 		goto err_release_group_1;
1560 	}
1561 #endif
1562 
1563 	rc = edac_device_add_device(dci);
1564 	if (rc) {
1565 		edac_printk(KERN_ERR, EDAC_DEVICE,
1566 			    "edac_device_add_device portB failed\n");
1567 		rc = -ENOMEM;
1568 		goto err_release_group_1;
1569 	}
1570 	altr_create_edacdev_dbgfs(dci, prv);
1571 
1572 	list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1573 
1574 	devres_remove_group(&altdev->ddev, altr_portb_setup);
1575 
1576 	return 0;
1577 
1578 err_release_group_1:
1579 	edac_device_free_ctl_info(dci);
1580 	devres_release_group(&altdev->ddev, altr_portb_setup);
1581 	edac_printk(KERN_ERR, EDAC_DEVICE,
1582 		    "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1583 	return rc;
1584 }
1585 
1586 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1587 {
1588 	int rc = -ENODEV;
1589 	struct device_node *child;
1590 
1591 	child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1592 	if (!child)
1593 		return -ENODEV;
1594 
1595 	if (!of_device_is_available(child))
1596 		goto exit;
1597 
1598 	if (validate_parent_available(child))
1599 		goto exit;
1600 
1601 	/* Init portB */
1602 	rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1603 				     a10_sdmmceccb_data.ecc_enable_mask, 1);
1604 	if (rc)
1605 		goto exit;
1606 
1607 	/* Setup portB */
1608 	return altr_portb_setup(device);
1609 
1610 exit:
1611 	of_node_put(child);
1612 	return rc;
1613 }
1614 
1615 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1616 {
1617 	struct altr_edac_device_dev *ad = dev_id;
1618 	void __iomem  *base = ad->base;
1619 	const struct edac_device_prv_data *priv = ad->data;
1620 
1621 	if (irq == ad->sb_irq) {
1622 		writel(priv->ce_clear_mask,
1623 		       base + ALTR_A10_ECC_INTSTAT_OFST);
1624 		edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1625 		return IRQ_HANDLED;
1626 	} else if (irq == ad->db_irq) {
1627 		writel(priv->ue_clear_mask,
1628 		       base + ALTR_A10_ECC_INTSTAT_OFST);
1629 		edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1630 		return IRQ_HANDLED;
1631 	}
1632 
1633 	WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1634 
1635 	return IRQ_NONE;
1636 }
1637 
1638 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1639 	.setup = socfpga_init_sdmmc_ecc,
1640 	.ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1641 	.ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1642 	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1643 	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1644 	.ce_set_mask = ALTR_A10_ECC_SERRPENA,
1645 	.ue_set_mask = ALTR_A10_ECC_DERRPENA,
1646 	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1647 	.ecc_irq_handler = altr_edac_a10_ecc_irq,
1648 	.inject_fops = &altr_edac_a10_device_inject_fops,
1649 };
1650 
1651 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1652 	.setup = socfpga_init_sdmmc_ecc,
1653 	.ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1654 	.ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1655 	.ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1656 	.ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1657 	.ce_set_mask = ALTR_A10_ECC_TSERRB,
1658 	.ue_set_mask = ALTR_A10_ECC_TDERRB,
1659 	.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1660 	.ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1661 	.inject_fops = &altr_edac_a10_device_inject_fops,
1662 };
1663 
1664 #endif	/* CONFIG_EDAC_ALTERA_SDMMC */
1665 
1666 /********************* Arria10 EDAC Device Functions *************************/
1667 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1668 #ifdef CONFIG_EDAC_ALTERA_L2C
1669 	{ .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1670 #endif
1671 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1672 	{ .compatible = "altr,socfpga-a10-ocram-ecc",
1673 	  .data = &a10_ocramecc_data },
1674 #endif
1675 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1676 	{ .compatible = "altr,socfpga-eth-mac-ecc",
1677 	  .data = &a10_enetecc_data },
1678 #endif
1679 #ifdef CONFIG_EDAC_ALTERA_NAND
1680 	{ .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1681 #endif
1682 #ifdef CONFIG_EDAC_ALTERA_DMA
1683 	{ .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1684 #endif
1685 #ifdef CONFIG_EDAC_ALTERA_USB
1686 	{ .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1687 #endif
1688 #ifdef CONFIG_EDAC_ALTERA_QSPI
1689 	{ .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1690 #endif
1691 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1692 	{ .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1693 #endif
1694 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1695 	{ .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1696 #endif
1697 	{},
1698 };
1699 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1700 
1701 /*
1702  * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1703  * because 2 IRQs are shared among the all ECC peripherals. The ECC
1704  * manager manages the IRQs and the children.
1705  * Based on xgene_edac.c peripheral code.
1706  */
1707 
1708 static ssize_t __maybe_unused
1709 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
1710 			  size_t count, loff_t *ppos)
1711 {
1712 	struct edac_device_ctl_info *edac_dci = file->private_data;
1713 	struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1714 	const struct edac_device_prv_data *priv = drvdata->data;
1715 	void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1716 	unsigned long flags;
1717 	u8 trig_type;
1718 
1719 	if (!user_buf || get_user(trig_type, user_buf))
1720 		return -EFAULT;
1721 
1722 	local_irq_save(flags);
1723 	if (trig_type == ALTR_UE_TRIGGER_CHAR)
1724 		writel(priv->ue_set_mask, set_addr);
1725 	else
1726 		writel(priv->ce_set_mask, set_addr);
1727 
1728 	/* Ensure the interrupt test bits are set */
1729 	wmb();
1730 	local_irq_restore(flags);
1731 
1732 	return count;
1733 }
1734 
1735 /*
1736  * The Stratix10 EDAC Error Injection Functions differ from Arria10
1737  * slightly. A few Arria10 peripherals can use this injection function.
1738  * Inject the error into the memory and then readback to trigger the IRQ.
1739  */
1740 static ssize_t __maybe_unused
1741 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
1742 			   size_t count, loff_t *ppos)
1743 {
1744 	struct edac_device_ctl_info *edac_dci = file->private_data;
1745 	struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1746 	const struct edac_device_prv_data *priv = drvdata->data;
1747 	void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1748 	unsigned long flags;
1749 	u8 trig_type;
1750 
1751 	if (!user_buf || get_user(trig_type, user_buf))
1752 		return -EFAULT;
1753 
1754 	local_irq_save(flags);
1755 	if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1756 		writel(priv->ue_set_mask, set_addr);
1757 	} else {
1758 		/* Setup read/write of 4 bytes */
1759 		writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1760 		/* Setup Address to 0 */
1761 		writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1762 		/* Setup accctrl to read & ecc & data override */
1763 		writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1764 		/* Kick it. */
1765 		writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1766 		/* Setup write for single bit change */
1767 		writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1768 		       drvdata->base + ECC_BLK_WDATA0_OFST);
1769 		writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1770 		       drvdata->base + ECC_BLK_WDATA1_OFST);
1771 		writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1772 		       drvdata->base + ECC_BLK_WDATA2_OFST);
1773 		writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1774 		       drvdata->base + ECC_BLK_WDATA3_OFST);
1775 
1776 		/* Copy Read ECC to Write ECC */
1777 		writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1778 		       drvdata->base + ECC_BLK_WECC0_OFST);
1779 		writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1780 		       drvdata->base + ECC_BLK_WECC1_OFST);
1781 		/* Setup accctrl to write & ecc override & data override */
1782 		writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1783 		/* Kick it. */
1784 		writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1785 		/* Setup accctrl to read & ecc overwrite & data overwrite */
1786 		writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1787 		/* Kick it. */
1788 		writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1789 	}
1790 
1791 	/* Ensure the interrupt test bits are set */
1792 	wmb();
1793 	local_irq_restore(flags);
1794 
1795 	return count;
1796 }
1797 
1798 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1799 {
1800 	int dberr, bit, sm_offset, irq_status;
1801 	struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1802 	struct irq_chip *chip = irq_desc_get_chip(desc);
1803 	int irq = irq_desc_get_irq(desc);
1804 	unsigned long bits;
1805 
1806 	dberr = (irq == edac->db_irq) ? 1 : 0;
1807 	sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1808 			    A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1809 
1810 	chained_irq_enter(chip, desc);
1811 
1812 	regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1813 
1814 	bits = irq_status;
1815 	for_each_set_bit(bit, &bits, 32)
1816 		generic_handle_domain_irq(edac->domain, dberr * 32 + bit);
1817 
1818 	chained_irq_exit(chip, desc);
1819 }
1820 
1821 static int validate_parent_available(struct device_node *np)
1822 {
1823 	struct device_node *parent;
1824 	int ret = 0;
1825 
1826 	/* SDRAM must be present for Linux (implied parent) */
1827 	if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1828 		return 0;
1829 
1830 	/* Ensure parent device is enabled if parent node exists */
1831 	parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1832 	if (parent && !of_device_is_available(parent))
1833 		ret = -ENODEV;
1834 
1835 	of_node_put(parent);
1836 	return ret;
1837 }
1838 
1839 static int get_s10_sdram_edac_resource(struct device_node *np,
1840 				       struct resource *res)
1841 {
1842 	struct device_node *parent;
1843 	int ret;
1844 
1845 	parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
1846 	if (!parent)
1847 		return -ENODEV;
1848 
1849 	ret = of_address_to_resource(parent, 0, res);
1850 	of_node_put(parent);
1851 
1852 	return ret;
1853 }
1854 
1855 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1856 				    struct device_node *np)
1857 {
1858 	struct edac_device_ctl_info *dci;
1859 	struct altr_edac_device_dev *altdev;
1860 	char *ecc_name = (char *)np->name;
1861 	struct resource res;
1862 	int edac_idx;
1863 	int rc = 0;
1864 	const struct edac_device_prv_data *prv;
1865 	/* Get matching node and check for valid result */
1866 	const struct of_device_id *pdev_id =
1867 		of_match_node(altr_edac_a10_device_of_match, np);
1868 	if (IS_ERR_OR_NULL(pdev_id))
1869 		return -ENODEV;
1870 
1871 	/* Get driver specific data for this EDAC device */
1872 	prv = pdev_id->data;
1873 	if (IS_ERR_OR_NULL(prv))
1874 		return -ENODEV;
1875 
1876 	if (validate_parent_available(np))
1877 		return -ENODEV;
1878 
1879 	if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1880 		return -ENOMEM;
1881 
1882 	if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1883 		rc = get_s10_sdram_edac_resource(np, &res);
1884 	else
1885 		rc = of_address_to_resource(np, 0, &res);
1886 
1887 	if (rc < 0) {
1888 		edac_printk(KERN_ERR, EDAC_DEVICE,
1889 			    "%s: no resource address\n", ecc_name);
1890 		goto err_release_group;
1891 	}
1892 
1893 	edac_idx = edac_device_alloc_index();
1894 	dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1895 					 1, ecc_name, 1, 0, NULL, 0,
1896 					 edac_idx);
1897 
1898 	if (!dci) {
1899 		edac_printk(KERN_ERR, EDAC_DEVICE,
1900 			    "%s: Unable to allocate EDAC device\n", ecc_name);
1901 		rc = -ENOMEM;
1902 		goto err_release_group;
1903 	}
1904 
1905 	altdev = dci->pvt_info;
1906 	dci->dev = edac->dev;
1907 	altdev->edac_dev_name = ecc_name;
1908 	altdev->edac_idx = edac_idx;
1909 	altdev->edac = edac;
1910 	altdev->edac_dev = dci;
1911 	altdev->data = prv;
1912 	altdev->ddev = *edac->dev;
1913 	dci->dev = &altdev->ddev;
1914 	dci->ctl_name = "Altera ECC Manager";
1915 	dci->mod_name = ecc_name;
1916 	dci->dev_name = ecc_name;
1917 
1918 	altdev->base = devm_ioremap_resource(edac->dev, &res);
1919 	if (IS_ERR(altdev->base)) {
1920 		rc = PTR_ERR(altdev->base);
1921 		goto err_release_group1;
1922 	}
1923 
1924 	/* Check specific dependencies for the module */
1925 	if (altdev->data->setup) {
1926 		rc = altdev->data->setup(altdev);
1927 		if (rc)
1928 			goto err_release_group1;
1929 	}
1930 
1931 	altdev->sb_irq = irq_of_parse_and_map(np, 0);
1932 	if (!altdev->sb_irq) {
1933 		edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1934 		rc = -ENODEV;
1935 		goto err_release_group1;
1936 	}
1937 	rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1938 			      IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1939 			      ecc_name, altdev);
1940 	if (rc) {
1941 		edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1942 		goto err_release_group1;
1943 	}
1944 
1945 #ifdef CONFIG_64BIT
1946 	/* Use IRQ to determine SError origin instead of assigning IRQ */
1947 	rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
1948 	if (rc) {
1949 		edac_printk(KERN_ERR, EDAC_DEVICE,
1950 			    "Unable to parse DB IRQ index\n");
1951 		goto err_release_group1;
1952 	}
1953 #else
1954 	altdev->db_irq = irq_of_parse_and_map(np, 1);
1955 	if (!altdev->db_irq) {
1956 		edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1957 		rc = -ENODEV;
1958 		goto err_release_group1;
1959 	}
1960 	rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1961 			      IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1962 			      ecc_name, altdev);
1963 	if (rc) {
1964 		edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
1965 		goto err_release_group1;
1966 	}
1967 #endif
1968 
1969 	rc = edac_device_add_device(dci);
1970 	if (rc) {
1971 		dev_err(edac->dev, "edac_device_add_device failed\n");
1972 		rc = -ENOMEM;
1973 		goto err_release_group1;
1974 	}
1975 
1976 	altr_create_edacdev_dbgfs(dci, prv);
1977 
1978 	list_add(&altdev->next, &edac->a10_ecc_devices);
1979 
1980 	devres_remove_group(edac->dev, altr_edac_a10_device_add);
1981 
1982 	return 0;
1983 
1984 err_release_group1:
1985 	edac_device_free_ctl_info(dci);
1986 err_release_group:
1987 	devres_release_group(edac->dev, NULL);
1988 	edac_printk(KERN_ERR, EDAC_DEVICE,
1989 		    "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1990 
1991 	return rc;
1992 }
1993 
1994 static void a10_eccmgr_irq_mask(struct irq_data *d)
1995 {
1996 	struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
1997 
1998 	regmap_write(edac->ecc_mgr_map,	A10_SYSMGR_ECC_INTMASK_SET_OFST,
1999 		     BIT(d->hwirq));
2000 }
2001 
2002 static void a10_eccmgr_irq_unmask(struct irq_data *d)
2003 {
2004 	struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2005 
2006 	regmap_write(edac->ecc_mgr_map,	A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2007 		     BIT(d->hwirq));
2008 }
2009 
2010 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2011 				    irq_hw_number_t hwirq)
2012 {
2013 	struct altr_arria10_edac *edac = d->host_data;
2014 
2015 	irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2016 	irq_set_chip_data(irq, edac);
2017 	irq_set_noprobe(irq);
2018 
2019 	return 0;
2020 }
2021 
2022 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2023 	.map = a10_eccmgr_irqdomain_map,
2024 	.xlate = irq_domain_xlate_twocell,
2025 };
2026 
2027 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2028 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2029 
2030 #ifdef CONFIG_64BIT
2031 /* panic routine issues reboot on non-zero panic_timeout */
2032 extern int panic_timeout;
2033 
2034 /*
2035  * The double bit error is handled through SError which is fatal. This is
2036  * called as a panic notifier to printout ECC error info as part of the panic.
2037  */
2038 static int s10_edac_dberr_handler(struct notifier_block *this,
2039 				  unsigned long event, void *ptr)
2040 {
2041 	struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2042 	int err_addr, dberror;
2043 
2044 	regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2045 		    &dberror);
2046 	regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2047 	if (dberror & S10_DBE_IRQ_MASK) {
2048 		struct list_head *position;
2049 		struct altr_edac_device_dev *ed;
2050 		struct arm_smccc_res result;
2051 
2052 		/* Find the matching DBE in the list of devices */
2053 		list_for_each(position, &edac->a10_ecc_devices) {
2054 			ed = list_entry(position, struct altr_edac_device_dev,
2055 					next);
2056 			if (!(BIT(ed->db_irq) & dberror))
2057 				continue;
2058 
2059 			writel(ALTR_A10_ECC_DERRPENA,
2060 			       ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2061 			err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2062 			regmap_write(edac->ecc_mgr_map,
2063 				     S10_SYSMGR_UE_ADDR_OFST, err_addr);
2064 			edac_printk(KERN_ERR, EDAC_DEVICE,
2065 				    "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2066 				    ed->edac_dev_name, err_addr);
2067 			break;
2068 		}
2069 		/* Notify the System through SMC. Reboot delay = 1 second */
2070 		panic_timeout = 1;
2071 		arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2072 			      0, 0, &result);
2073 	}
2074 
2075 	return NOTIFY_DONE;
2076 }
2077 #endif
2078 
2079 /****************** Arria 10 EDAC Probe Function *********************/
2080 static int altr_edac_a10_probe(struct platform_device *pdev)
2081 {
2082 	struct altr_arria10_edac *edac;
2083 	struct device_node *child;
2084 
2085 	edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2086 	if (!edac)
2087 		return -ENOMEM;
2088 
2089 	edac->dev = &pdev->dev;
2090 	platform_set_drvdata(pdev, edac);
2091 	INIT_LIST_HEAD(&edac->a10_ecc_devices);
2092 
2093 	edac->ecc_mgr_map =
2094 		altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,
2095 						     "altr,sysmgr-syscon");
2096 
2097 	if (IS_ERR(edac->ecc_mgr_map)) {
2098 		edac_printk(KERN_ERR, EDAC_DEVICE,
2099 			    "Unable to get syscon altr,sysmgr-syscon\n");
2100 		return PTR_ERR(edac->ecc_mgr_map);
2101 	}
2102 
2103 	edac->irq_chip.name = pdev->dev.of_node->name;
2104 	edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2105 	edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2106 	edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2107 					     &a10_eccmgr_ic_ops, edac);
2108 	if (!edac->domain) {
2109 		dev_err(&pdev->dev, "Error adding IRQ domain\n");
2110 		return -ENOMEM;
2111 	}
2112 
2113 	edac->sb_irq = platform_get_irq(pdev, 0);
2114 	if (edac->sb_irq < 0) {
2115 		dev_err(&pdev->dev, "No SBERR IRQ resource\n");
2116 		return edac->sb_irq;
2117 	}
2118 
2119 	irq_set_chained_handler_and_data(edac->sb_irq,
2120 					 altr_edac_a10_irq_handler,
2121 					 edac);
2122 
2123 #ifdef CONFIG_64BIT
2124 	{
2125 		int dberror, err_addr;
2126 
2127 		edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2128 		atomic_notifier_chain_register(&panic_notifier_list,
2129 					       &edac->panic_notifier);
2130 
2131 		/* Printout a message if uncorrectable error previously. */
2132 		regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2133 			    &dberror);
2134 		if (dberror) {
2135 			regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2136 				    &err_addr);
2137 			edac_printk(KERN_ERR, EDAC_DEVICE,
2138 				    "Previous Boot UE detected[0x%X] @ 0x%X\n",
2139 				    dberror, err_addr);
2140 			/* Reset the sticky registers */
2141 			regmap_write(edac->ecc_mgr_map,
2142 				     S10_SYSMGR_UE_VAL_OFST, 0);
2143 			regmap_write(edac->ecc_mgr_map,
2144 				     S10_SYSMGR_UE_ADDR_OFST, 0);
2145 		}
2146 	}
2147 #else
2148 	edac->db_irq = platform_get_irq(pdev, 1);
2149 	if (edac->db_irq < 0) {
2150 		dev_err(&pdev->dev, "No DBERR IRQ resource\n");
2151 		return edac->db_irq;
2152 	}
2153 	irq_set_chained_handler_and_data(edac->db_irq,
2154 					 altr_edac_a10_irq_handler, edac);
2155 #endif
2156 
2157 	for_each_child_of_node(pdev->dev.of_node, child) {
2158 		if (!of_device_is_available(child))
2159 			continue;
2160 
2161 		if (of_match_node(altr_edac_a10_device_of_match, child))
2162 			altr_edac_a10_device_add(edac, child);
2163 
2164 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2165 		else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2166 			of_platform_populate(pdev->dev.of_node,
2167 					     altr_sdram_ctrl_of_match,
2168 					     NULL, &pdev->dev);
2169 #endif
2170 	}
2171 
2172 	return 0;
2173 }
2174 
2175 static const struct of_device_id altr_edac_a10_of_match[] = {
2176 	{ .compatible = "altr,socfpga-a10-ecc-manager" },
2177 	{ .compatible = "altr,socfpga-s10-ecc-manager" },
2178 	{},
2179 };
2180 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2181 
2182 static struct platform_driver altr_edac_a10_driver = {
2183 	.probe =  altr_edac_a10_probe,
2184 	.driver = {
2185 		.name = "socfpga_a10_ecc_manager",
2186 		.of_match_table = altr_edac_a10_of_match,
2187 	},
2188 };
2189 module_platform_driver(altr_edac_a10_driver);
2190 
2191 MODULE_LICENSE("GPL v2");
2192 MODULE_AUTHOR("Thor Thayer");
2193 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
2194