1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _ZL3073X_REGS_H 4 #define _ZL3073X_REGS_H 5 6 #include <linux/bitfield.h> 7 #include <linux/bits.h> 8 9 /* 10 * Register address structure: 11 * =========================== 12 * 25 19 18 16 15 7 6 0 13 * +------------------------------------------+ 14 * | max_offset | size | page | page_offset | 15 * +------------------------------------------+ 16 * 17 * page_offset ... <0x00..0x7F> 18 * page .......... HW page number 19 * size .......... register byte size (1, 2, 4 or 6) 20 * max_offset .... maximal offset for indexed registers 21 * (for non-indexed regs max_offset == page_offset) 22 */ 23 24 #define ZL_REG_OFFSET_MASK GENMASK(6, 0) 25 #define ZL_REG_PAGE_MASK GENMASK(15, 7) 26 #define ZL_REG_SIZE_MASK GENMASK(18, 16) 27 #define ZL_REG_MAX_OFFSET_MASK GENMASK(25, 19) 28 #define ZL_REG_ADDR_MASK GENMASK(15, 0) 29 30 #define ZL_REG_OFFSET(_reg) FIELD_GET(ZL_REG_OFFSET_MASK, _reg) 31 #define ZL_REG_PAGE(_reg) FIELD_GET(ZL_REG_PAGE_MASK, _reg) 32 #define ZL_REG_MAX_OFFSET(_reg) FIELD_GET(ZL_REG_MAX_OFFSET_MASK, _reg) 33 #define ZL_REG_SIZE(_reg) FIELD_GET(ZL_REG_SIZE_MASK, _reg) 34 #define ZL_REG_ADDR(_reg) FIELD_GET(ZL_REG_ADDR_MASK, _reg) 35 36 /** 37 * ZL_REG_IDX - define indexed register 38 * @_idx: index of register to access 39 * @_page: register page 40 * @_offset: register offset in page 41 * @_size: register byte size (1, 2, 4 or 6) 42 * @_items: number of register indices 43 * @_stride: stride between items in bytes 44 * 45 * All parameters except @_idx should be constant. 46 */ 47 #define ZL_REG_IDX(_idx, _page, _offset, _size, _items, _stride) \ 48 (FIELD_PREP(ZL_REG_OFFSET_MASK, \ 49 (_offset) + (_idx) * (_stride)) | \ 50 FIELD_PREP_CONST(ZL_REG_PAGE_MASK, _page) | \ 51 FIELD_PREP_CONST(ZL_REG_SIZE_MASK, _size) | \ 52 FIELD_PREP_CONST(ZL_REG_MAX_OFFSET_MASK, \ 53 (_offset) + ((_items) - 1) * (_stride))) 54 55 /** 56 * ZL_REG - define simple (non-indexed) register 57 * @_page: register page 58 * @_offset: register offset in page 59 * @_size: register byte size (1, 2, 4 or 6) 60 * 61 * All parameters should be constant. 62 */ 63 #define ZL_REG(_page, _offset, _size) \ 64 ZL_REG_IDX(0, _page, _offset, _size, 1, 0) 65 66 /************************** 67 * Register Page 0, General 68 **************************/ 69 70 #define ZL_REG_ID ZL_REG(0, 0x01, 2) 71 #define ZL_REG_REVISION ZL_REG(0, 0x03, 2) 72 #define ZL_REG_FW_VER ZL_REG(0, 0x05, 2) 73 #define ZL_REG_CUSTOM_CONFIG_VER ZL_REG(0, 0x07, 4) 74 75 /************************* 76 * Register Page 2, Status 77 *************************/ 78 79 #define ZL_REG_REF_MON_STATUS(_idx) \ 80 ZL_REG_IDX(_idx, 2, 0x02, 1, ZL3073X_NUM_REFS, 1) 81 #define ZL_REF_MON_STATUS_OK 0 /* all bits zeroed */ 82 83 #define ZL_REG_DPLL_MON_STATUS(_idx) \ 84 ZL_REG_IDX(_idx, 2, 0x10, 1, ZL3073X_MAX_CHANNELS, 1) 85 #define ZL_DPLL_MON_STATUS_STATE GENMASK(1, 0) 86 #define ZL_DPLL_MON_STATUS_STATE_ACQUIRING 0 87 #define ZL_DPLL_MON_STATUS_STATE_LOCK 1 88 #define ZL_DPLL_MON_STATUS_STATE_HOLDOVER 2 89 #define ZL_DPLL_MON_STATUS_HO_READY BIT(2) 90 91 #define ZL_REG_DPLL_REFSEL_STATUS(_idx) \ 92 ZL_REG_IDX(_idx, 2, 0x30, 1, ZL3073X_MAX_CHANNELS, 1) 93 #define ZL_DPLL_REFSEL_STATUS_REFSEL GENMASK(3, 0) 94 #define ZL_DPLL_REFSEL_STATUS_STATE GENMASK(6, 4) 95 #define ZL_DPLL_REFSEL_STATUS_STATE_LOCK 4 96 97 /*********************** 98 * Register Page 5, DPLL 99 ***********************/ 100 101 #define ZL_REG_DPLL_MODE_REFSEL(_idx) \ 102 ZL_REG_IDX(_idx, 5, 0x04, 1, ZL3073X_MAX_CHANNELS, 4) 103 #define ZL_DPLL_MODE_REFSEL_MODE GENMASK(2, 0) 104 #define ZL_DPLL_MODE_REFSEL_MODE_FREERUN 0 105 #define ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER 1 106 #define ZL_DPLL_MODE_REFSEL_MODE_REFLOCK 2 107 #define ZL_DPLL_MODE_REFSEL_MODE_AUTO 3 108 #define ZL_DPLL_MODE_REFSEL_MODE_NCO 4 109 #define ZL_DPLL_MODE_REFSEL_REF GENMASK(7, 4) 110 111 /*********************************** 112 * Register Page 9, Synth and Output 113 ***********************************/ 114 115 #define ZL_REG_SYNTH_CTRL(_idx) \ 116 ZL_REG_IDX(_idx, 9, 0x00, 1, ZL3073X_NUM_SYNTHS, 1) 117 #define ZL_SYNTH_CTRL_EN BIT(0) 118 #define ZL_SYNTH_CTRL_DPLL_SEL GENMASK(6, 4) 119 120 #define ZL_REG_SYNTH_PHASE_SHIFT_CTRL ZL_REG(9, 0x1e, 1) 121 #define ZL_REG_SYNTH_PHASE_SHIFT_MASK ZL_REG(9, 0x1f, 1) 122 #define ZL_REG_SYNTH_PHASE_SHIFT_INTVL ZL_REG(9, 0x20, 1) 123 #define ZL_REG_SYNTH_PHASE_SHIFT_DATA ZL_REG(9, 0x21, 2) 124 125 #define ZL_REG_OUTPUT_CTRL(_idx) \ 126 ZL_REG_IDX(_idx, 9, 0x28, 1, ZL3073X_NUM_OUTS, 1) 127 #define ZL_OUTPUT_CTRL_EN BIT(0) 128 #define ZL_OUTPUT_CTRL_SYNTH_SEL GENMASK(6, 4) 129 130 /******************************* 131 * Register Page 10, Ref Mailbox 132 *******************************/ 133 134 #define ZL_REG_REF_MB_MASK ZL_REG(10, 0x02, 2) 135 136 #define ZL_REG_REF_MB_SEM ZL_REG(10, 0x04, 1) 137 #define ZL_REF_MB_SEM_WR BIT(0) 138 #define ZL_REF_MB_SEM_RD BIT(1) 139 140 #define ZL_REG_REF_FREQ_BASE ZL_REG(10, 0x05, 2) 141 #define ZL_REG_REF_FREQ_MULT ZL_REG(10, 0x07, 2) 142 #define ZL_REG_REF_RATIO_M ZL_REG(10, 0x09, 2) 143 #define ZL_REG_REF_RATIO_N ZL_REG(10, 0x0b, 2) 144 145 #define ZL_REG_REF_CONFIG ZL_REG(10, 0x0d, 1) 146 #define ZL_REF_CONFIG_ENABLE BIT(0) 147 #define ZL_REF_CONFIG_DIFF_EN BIT(2) 148 149 /******************************** 150 * Register Page 12, DPLL Mailbox 151 ********************************/ 152 153 #define ZL_REG_DPLL_MB_MASK ZL_REG(12, 0x02, 2) 154 155 #define ZL_REG_DPLL_MB_SEM ZL_REG(12, 0x04, 1) 156 #define ZL_DPLL_MB_SEM_WR BIT(0) 157 #define ZL_DPLL_MB_SEM_RD BIT(1) 158 159 #define ZL_REG_DPLL_REF_PRIO(_idx) \ 160 ZL_REG_IDX(_idx, 12, 0x52, 1, ZL3073X_NUM_REFS / 2, 1) 161 #define ZL_DPLL_REF_PRIO_REF_P GENMASK(3, 0) 162 #define ZL_DPLL_REF_PRIO_REF_N GENMASK(7, 4) 163 #define ZL_DPLL_REF_PRIO_MAX 14 164 #define ZL_DPLL_REF_PRIO_NONE 15 165 166 /********************************* 167 * Register Page 13, Synth Mailbox 168 *********************************/ 169 170 #define ZL_REG_SYNTH_MB_MASK ZL_REG(13, 0x02, 2) 171 172 #define ZL_REG_SYNTH_MB_SEM ZL_REG(13, 0x04, 1) 173 #define ZL_SYNTH_MB_SEM_WR BIT(0) 174 #define ZL_SYNTH_MB_SEM_RD BIT(1) 175 176 #define ZL_REG_SYNTH_FREQ_BASE ZL_REG(13, 0x06, 2) 177 #define ZL_REG_SYNTH_FREQ_MULT ZL_REG(13, 0x08, 4) 178 #define ZL_REG_SYNTH_FREQ_M ZL_REG(13, 0x0c, 2) 179 #define ZL_REG_SYNTH_FREQ_N ZL_REG(13, 0x0e, 2) 180 181 /********************************** 182 * Register Page 14, Output Mailbox 183 **********************************/ 184 #define ZL_REG_OUTPUT_MB_MASK ZL_REG(14, 0x02, 2) 185 186 #define ZL_REG_OUTPUT_MB_SEM ZL_REG(14, 0x04, 1) 187 #define ZL_OUTPUT_MB_SEM_WR BIT(0) 188 #define ZL_OUTPUT_MB_SEM_RD BIT(1) 189 190 #define ZL_REG_OUTPUT_MODE ZL_REG(14, 0x05, 1) 191 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT GENMASK(7, 4) 192 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DISABLED 0 193 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LVDS 1 194 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_DIFF 2 195 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_LOWVCM 3 196 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2 4 197 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1P 5 198 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_1N 6 199 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_INV 7 200 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV 12 201 #define ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV 15 202 203 #define ZL_REG_OUTPUT_DIV ZL_REG(14, 0x0c, 4) 204 #define ZL_REG_OUTPUT_WIDTH ZL_REG(14, 0x10, 4) 205 #define ZL_REG_OUTPUT_ESYNC_PERIOD ZL_REG(14, 0x14, 4) 206 #define ZL_REG_OUTPUT_ESYNC_WIDTH ZL_REG(14, 0x18, 4) 207 208 #endif /* _ZL3073X_REGS_H */ 209