1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bits.h> 4 #include <linux/bitfield.h> 5 #include <linux/bug.h> 6 #include <linux/container_of.h> 7 #include <linux/dev_printk.h> 8 #include <linux/dpll.h> 9 #include <linux/err.h> 10 #include <linux/kthread.h> 11 #include <linux/math64.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/netlink.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/sprintf.h> 18 19 #include "core.h" 20 #include "dpll.h" 21 #include "prop.h" 22 #include "regs.h" 23 24 #define ZL3073X_DPLL_REF_NONE ZL3073X_NUM_REFS 25 #define ZL3073X_DPLL_REF_IS_VALID(_ref) ((_ref) != ZL3073X_DPLL_REF_NONE) 26 27 /** 28 * struct zl3073x_dpll_pin - DPLL pin 29 * @list: this DPLL pin list entry 30 * @dpll: DPLL the pin is registered to 31 * @dpll_pin: pointer to registered dpll_pin 32 * @tracker: tracking object for the acquired reference 33 * @label: package label 34 * @dir: pin direction 35 * @id: pin id 36 * @prio: pin priority <0, 14> 37 * @selectable: pin is selectable in automatic mode 38 * @esync_control: embedded sync is controllable 39 * @phase_gran: phase adjustment granularity 40 * @pin_state: last saved pin state 41 * @phase_offset: last saved pin phase offset 42 * @freq_offset: last saved fractional frequency offset 43 */ 44 struct zl3073x_dpll_pin { 45 struct list_head list; 46 struct zl3073x_dpll *dpll; 47 struct dpll_pin *dpll_pin; 48 dpll_tracker tracker; 49 char label[8]; 50 enum dpll_pin_direction dir; 51 u8 id; 52 u8 prio; 53 bool selectable; 54 bool esync_control; 55 s32 phase_gran; 56 enum dpll_pin_state pin_state; 57 s64 phase_offset; 58 s64 freq_offset; 59 }; 60 61 /* 62 * Supported esync ranges for input and for output per output pair type 63 */ 64 static const struct dpll_pin_frequency esync_freq_ranges[] = { 65 DPLL_PIN_FREQUENCY_RANGE(0, 1), 66 }; 67 68 /** 69 * zl3073x_dpll_is_input_pin - check if the pin is input one 70 * @pin: pin to check 71 * 72 * Return: true if pin is input, false if pin is output. 73 */ 74 static bool 75 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin) 76 { 77 return pin->dir == DPLL_PIN_DIRECTION_INPUT; 78 } 79 80 /** 81 * zl3073x_dpll_is_p_pin - check if the pin is P-pin 82 * @pin: pin to check 83 * 84 * Return: true if the pin is P-pin, false if it is N-pin 85 */ 86 static bool 87 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin) 88 { 89 return zl3073x_is_p_pin(pin->id); 90 } 91 92 static int 93 zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv, 94 const struct dpll_device *dpll, void *dpll_priv, 95 enum dpll_pin_direction *direction, 96 struct netlink_ext_ack *extack) 97 { 98 struct zl3073x_dpll_pin *pin = pin_priv; 99 100 *direction = pin->dir; 101 102 return 0; 103 } 104 105 static struct zl3073x_dpll_pin * 106 zl3073x_dpll_pin_get_by_ref(struct zl3073x_dpll *zldpll, u8 ref_id) 107 { 108 struct zl3073x_dpll_pin *pin; 109 110 list_for_each_entry(pin, &zldpll->pins, list) { 111 if (zl3073x_dpll_is_input_pin(pin) && 112 zl3073x_input_pin_ref_get(pin->id) == ref_id) 113 return pin; 114 } 115 116 return NULL; 117 } 118 119 static int 120 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, 121 void *pin_priv, 122 const struct dpll_device *dpll, 123 void *dpll_priv, 124 struct dpll_pin_esync *esync, 125 struct netlink_ext_ack *extack) 126 { 127 struct zl3073x_dpll *zldpll = dpll_priv; 128 struct zl3073x_dev *zldev = zldpll->dev; 129 struct zl3073x_dpll_pin *pin = pin_priv; 130 const struct zl3073x_ref *ref; 131 u8 ref_id; 132 133 ref_id = zl3073x_input_pin_ref_get(pin->id); 134 ref = zl3073x_ref_state_get(zldev, ref_id); 135 136 switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) { 137 case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: 138 esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0; 139 esync->pulse = 25; 140 break; 141 default: 142 esync->freq = 0; 143 esync->pulse = 0; 144 break; 145 } 146 147 /* If the pin supports esync control expose its range but only 148 * if the current reference frequency is > 1 Hz. 149 */ 150 if (pin->esync_control && zl3073x_ref_freq_get(ref) > 1) { 151 esync->range = esync_freq_ranges; 152 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 153 } else { 154 esync->range = NULL; 155 esync->range_num = 0; 156 } 157 158 return 0; 159 } 160 161 static int 162 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin, 163 void *pin_priv, 164 const struct dpll_device *dpll, 165 void *dpll_priv, u64 freq, 166 struct netlink_ext_ack *extack) 167 { 168 struct zl3073x_dpll *zldpll = dpll_priv; 169 struct zl3073x_dev *zldev = zldpll->dev; 170 struct zl3073x_dpll_pin *pin = pin_priv; 171 struct zl3073x_ref ref; 172 u8 ref_id, sync_mode; 173 174 ref_id = zl3073x_input_pin_ref_get(pin->id); 175 ref = *zl3073x_ref_state_get(zldev, ref_id); 176 177 /* Use freq == 0 to disable esync */ 178 if (!freq) 179 sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF; 180 else 181 sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75; 182 183 ref.sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE; 184 ref.sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode); 185 186 if (freq) { 187 /* 1 Hz is only supported frequency now */ 188 ref.esync_n_div = ZL_REF_ESYNC_DIV_1HZ; 189 } 190 191 /* Update reference configuration */ 192 return zl3073x_ref_state_set(zldev, ref_id, &ref); 193 } 194 195 static int 196 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv, 197 const struct dpll_device *dpll, void *dpll_priv, 198 s64 *ffo, struct netlink_ext_ack *extack) 199 { 200 struct zl3073x_dpll_pin *pin = pin_priv; 201 202 *ffo = pin->freq_offset; 203 204 return 0; 205 } 206 207 static int 208 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin, 209 void *pin_priv, 210 const struct dpll_device *dpll, 211 void *dpll_priv, u64 *frequency, 212 struct netlink_ext_ack *extack) 213 { 214 struct zl3073x_dpll *zldpll = dpll_priv; 215 struct zl3073x_dpll_pin *pin = pin_priv; 216 u8 ref_id; 217 218 ref_id = zl3073x_input_pin_ref_get(pin->id); 219 *frequency = zl3073x_dev_ref_freq_get(zldpll->dev, ref_id); 220 221 return 0; 222 } 223 224 static int 225 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin, 226 void *pin_priv, 227 const struct dpll_device *dpll, 228 void *dpll_priv, u64 frequency, 229 struct netlink_ext_ack *extack) 230 { 231 struct zl3073x_dpll *zldpll = dpll_priv; 232 struct zl3073x_dev *zldev = zldpll->dev; 233 struct zl3073x_dpll_pin *pin = pin_priv; 234 struct zl3073x_ref ref; 235 u8 ref_id; 236 237 /* Get reference state */ 238 ref_id = zl3073x_input_pin_ref_get(pin->id); 239 ref = *zl3073x_ref_state_get(zldev, ref_id); 240 241 /* Update frequency */ 242 zl3073x_ref_freq_set(&ref, frequency); 243 244 /* Commit reference state */ 245 return zl3073x_ref_state_set(zldev, ref_id, &ref); 246 } 247 248 /** 249 * zl3073x_dpll_selected_ref_get - get currently selected reference 250 * @zldpll: pointer to zl3073x_dpll 251 * @ref: place to store selected reference 252 * 253 * Check for currently selected reference the DPLL should be locked to 254 * and stores its index to given @ref. 255 * 256 * Return: 0 on success, <0 on error 257 */ 258 static int 259 zl3073x_dpll_selected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 260 { 261 struct zl3073x_dev *zldev = zldpll->dev; 262 u8 state, value; 263 int rc; 264 265 switch (zldpll->refsel_mode) { 266 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 267 /* For automatic mode read refsel_status register */ 268 rc = zl3073x_read_u8(zldev, 269 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id), 270 &value); 271 if (rc) 272 return rc; 273 274 /* Extract reference state */ 275 state = FIELD_GET(ZL_DPLL_REFSEL_STATUS_STATE, value); 276 277 /* Return the reference only if the DPLL is locked to it */ 278 if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK) 279 *ref = FIELD_GET(ZL_DPLL_REFSEL_STATUS_REFSEL, value); 280 else 281 *ref = ZL3073X_DPLL_REF_NONE; 282 break; 283 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 284 /* For manual mode return stored value */ 285 *ref = zldpll->forced_ref; 286 break; 287 default: 288 /* For other modes like NCO, freerun... there is no input ref */ 289 *ref = ZL3073X_DPLL_REF_NONE; 290 break; 291 } 292 293 return 0; 294 } 295 296 /** 297 * zl3073x_dpll_selected_ref_set - select reference in manual mode 298 * @zldpll: pointer to zl3073x_dpll 299 * @ref: input reference to be selected 300 * 301 * Selects the given reference for the DPLL channel it should be 302 * locked to. 303 * 304 * Return: 0 on success, <0 on error 305 */ 306 static int 307 zl3073x_dpll_selected_ref_set(struct zl3073x_dpll *zldpll, u8 ref) 308 { 309 struct zl3073x_dev *zldev = zldpll->dev; 310 u8 mode, mode_refsel; 311 int rc; 312 313 mode = zldpll->refsel_mode; 314 315 switch (mode) { 316 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 317 /* Manual mode with ref selected */ 318 if (ref == ZL3073X_DPLL_REF_NONE) { 319 switch (zldpll->lock_status) { 320 case DPLL_LOCK_STATUS_LOCKED_HO_ACQ: 321 case DPLL_LOCK_STATUS_HOLDOVER: 322 /* Switch to forced holdover */ 323 mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 324 break; 325 default: 326 /* Switch to freerun */ 327 mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 328 break; 329 } 330 /* Keep selected reference */ 331 ref = zldpll->forced_ref; 332 } else if (ref == zldpll->forced_ref) { 333 /* No register update - same mode and same ref */ 334 return 0; 335 } 336 break; 337 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 338 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 339 /* Manual mode without no ref */ 340 if (ref == ZL3073X_DPLL_REF_NONE) 341 /* No register update - keep current mode */ 342 return 0; 343 344 /* Switch to reflock mode and update ref selection */ 345 mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 346 break; 347 default: 348 /* For other modes like automatic or NCO ref cannot be selected 349 * manually 350 */ 351 return -EOPNOTSUPP; 352 } 353 354 /* Build mode_refsel value */ 355 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode) | 356 FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 357 358 /* Update dpll_mode_refsel register */ 359 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 360 mode_refsel); 361 if (rc) 362 return rc; 363 364 /* Store new mode and forced reference */ 365 zldpll->refsel_mode = mode; 366 zldpll->forced_ref = ref; 367 368 return rc; 369 } 370 371 /** 372 * zl3073x_dpll_connected_ref_get - get currently connected reference 373 * @zldpll: pointer to zl3073x_dpll 374 * @ref: place to store selected reference 375 * 376 * Looks for currently connected the DPLL is locked to and stores its index 377 * to given @ref. 378 * 379 * Return: 0 on success, <0 on error 380 */ 381 static int 382 zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 383 { 384 struct zl3073x_dev *zldev = zldpll->dev; 385 int rc; 386 387 /* Get currently selected input reference */ 388 rc = zl3073x_dpll_selected_ref_get(zldpll, ref); 389 if (rc) 390 return rc; 391 392 /* If the monitor indicates an error nothing is connected */ 393 if (ZL3073X_DPLL_REF_IS_VALID(*ref) && 394 !zl3073x_dev_ref_is_status_ok(zldev, *ref)) 395 *ref = ZL3073X_DPLL_REF_NONE; 396 397 return 0; 398 } 399 400 static int 401 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin, 402 void *pin_priv, 403 const struct dpll_device *dpll, 404 void *dpll_priv, s64 *phase_offset, 405 struct netlink_ext_ack *extack) 406 { 407 struct zl3073x_dpll *zldpll = dpll_priv; 408 struct zl3073x_dev *zldev = zldpll->dev; 409 struct zl3073x_dpll_pin *pin = pin_priv; 410 const struct zl3073x_ref *ref; 411 u8 conn_id, ref_id; 412 s64 ref_phase; 413 int rc; 414 415 /* Get currently connected reference */ 416 rc = zl3073x_dpll_connected_ref_get(zldpll, &conn_id); 417 if (rc) 418 return rc; 419 420 /* Report phase offset only for currently connected pin if the phase 421 * monitor feature is disabled and only if the input pin signal is 422 * present. 423 */ 424 ref_id = zl3073x_input_pin_ref_get(pin->id); 425 ref = zl3073x_ref_state_get(zldev, ref_id); 426 if ((!zldpll->phase_monitor && ref_id != conn_id) || 427 !zl3073x_ref_is_status_ok(ref)) { 428 *phase_offset = 0; 429 return 0; 430 } 431 432 ref_phase = pin->phase_offset; 433 434 /* The DPLL being locked to a higher freq than the current ref 435 * the phase offset is modded to the period of the signal 436 * the dpll is locked to. 437 */ 438 if (ZL3073X_DPLL_REF_IS_VALID(conn_id) && conn_id != ref_id) { 439 u32 conn_freq, ref_freq; 440 441 /* Get frequency of connected and given ref */ 442 conn_freq = zl3073x_dev_ref_freq_get(zldev, conn_id); 443 ref_freq = zl3073x_ref_freq_get(ref); 444 445 if (conn_freq > ref_freq) { 446 s64 conn_period, div_factor; 447 448 conn_period = div_s64(PSEC_PER_SEC, conn_freq); 449 div_factor = div64_s64(ref_phase, conn_period); 450 ref_phase -= conn_period * div_factor; 451 } 452 } 453 454 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER; 455 456 return rc; 457 } 458 459 static int 460 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 461 void *pin_priv, 462 const struct dpll_device *dpll, 463 void *dpll_priv, 464 s32 *phase_adjust, 465 struct netlink_ext_ack *extack) 466 { 467 struct zl3073x_dpll *zldpll = dpll_priv; 468 struct zl3073x_dev *zldev = zldpll->dev; 469 struct zl3073x_dpll_pin *pin = pin_priv; 470 const struct zl3073x_ref *ref; 471 s64 phase_comp; 472 u8 ref_id; 473 474 /* Read reference configuration */ 475 ref_id = zl3073x_input_pin_ref_get(pin->id); 476 ref = zl3073x_ref_state_get(zldev, ref_id); 477 478 /* Perform sign extension for 48bit signed value */ 479 phase_comp = sign_extend64(ref->phase_comp, 47); 480 481 /* Reverse two's complement negation applied during set and convert 482 * to 32bit signed int 483 */ 484 *phase_adjust = (s32)-phase_comp; 485 486 return 0; 487 } 488 489 static int 490 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 491 void *pin_priv, 492 const struct dpll_device *dpll, 493 void *dpll_priv, 494 s32 phase_adjust, 495 struct netlink_ext_ack *extack) 496 { 497 struct zl3073x_dpll *zldpll = dpll_priv; 498 struct zl3073x_dev *zldev = zldpll->dev; 499 struct zl3073x_dpll_pin *pin = pin_priv; 500 struct zl3073x_ref ref; 501 u8 ref_id; 502 503 /* Read reference configuration */ 504 ref_id = zl3073x_input_pin_ref_get(pin->id); 505 ref = *zl3073x_ref_state_get(zldev, ref_id); 506 507 /* The value in the register is stored as two's complement negation 508 * of requested value. 509 */ 510 ref.phase_comp = -phase_adjust; 511 512 /* Update reference configuration */ 513 return zl3073x_ref_state_set(zldev, ref_id, &ref); 514 } 515 516 /** 517 * zl3073x_dpll_ref_prio_get - get priority for given input pin 518 * @pin: pointer to pin 519 * @prio: place to store priority 520 * 521 * Reads current priority for the given input pin and stores the value 522 * to @prio. 523 * 524 * Return: 0 on success, <0 on error 525 */ 526 static int 527 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio) 528 { 529 struct zl3073x_dpll *zldpll = pin->dpll; 530 struct zl3073x_dev *zldev = zldpll->dev; 531 u8 ref, ref_prio; 532 int rc; 533 534 guard(mutex)(&zldev->multiop_lock); 535 536 /* Read DPLL configuration */ 537 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 538 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 539 if (rc) 540 return rc; 541 542 /* Read reference priority - one value for P&N pins (4 bits/pin) */ 543 ref = zl3073x_input_pin_ref_get(pin->id); 544 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), 545 &ref_prio); 546 if (rc) 547 return rc; 548 549 /* Select nibble according pin type */ 550 if (zl3073x_dpll_is_p_pin(pin)) 551 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_P, ref_prio); 552 else 553 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_N, ref_prio); 554 555 return rc; 556 } 557 558 /** 559 * zl3073x_dpll_ref_prio_set - set priority for given input pin 560 * @pin: pointer to pin 561 * @prio: place to store priority 562 * 563 * Sets priority for the given input pin. 564 * 565 * Return: 0 on success, <0 on error 566 */ 567 static int 568 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio) 569 { 570 struct zl3073x_dpll *zldpll = pin->dpll; 571 struct zl3073x_dev *zldev = zldpll->dev; 572 u8 ref, ref_prio; 573 int rc; 574 575 guard(mutex)(&zldev->multiop_lock); 576 577 /* Read DPLL configuration into mailbox */ 578 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 579 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 580 if (rc) 581 return rc; 582 583 /* Read reference priority - one value shared between P&N pins */ 584 ref = zl3073x_input_pin_ref_get(pin->id); 585 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio); 586 if (rc) 587 return rc; 588 589 /* Update nibble according pin type */ 590 if (zl3073x_dpll_is_p_pin(pin)) { 591 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_P; 592 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio); 593 } else { 594 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_N; 595 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio); 596 } 597 598 /* Update reference priority */ 599 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio); 600 if (rc) 601 return rc; 602 603 /* Commit configuration */ 604 return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR, 605 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 606 } 607 608 /** 609 * zl3073x_dpll_ref_state_get - get status for given input pin 610 * @pin: pointer to pin 611 * @state: place to store status 612 * 613 * Checks current status for the given input pin and stores the value 614 * to @state. 615 * 616 * Return: 0 on success, <0 on error 617 */ 618 static int 619 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin, 620 enum dpll_pin_state *state) 621 { 622 struct zl3073x_dpll *zldpll = pin->dpll; 623 struct zl3073x_dev *zldev = zldpll->dev; 624 u8 ref, ref_conn; 625 int rc; 626 627 ref = zl3073x_input_pin_ref_get(pin->id); 628 629 /* Get currently connected reference */ 630 rc = zl3073x_dpll_connected_ref_get(zldpll, &ref_conn); 631 if (rc) 632 return rc; 633 634 if (ref == ref_conn) { 635 *state = DPLL_PIN_STATE_CONNECTED; 636 return 0; 637 } 638 639 /* If the DPLL is running in automatic mode and the reference is 640 * selectable and its monitor does not report any error then report 641 * pin as selectable. 642 */ 643 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO && 644 zl3073x_dev_ref_is_status_ok(zldev, ref) && pin->selectable) { 645 *state = DPLL_PIN_STATE_SELECTABLE; 646 return 0; 647 } 648 649 /* Otherwise report the pin as disconnected */ 650 *state = DPLL_PIN_STATE_DISCONNECTED; 651 652 return 0; 653 } 654 655 static int 656 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 657 void *pin_priv, 658 const struct dpll_device *dpll, 659 void *dpll_priv, 660 enum dpll_pin_state *state, 661 struct netlink_ext_ack *extack) 662 { 663 struct zl3073x_dpll_pin *pin = pin_priv; 664 665 return zl3073x_dpll_ref_state_get(pin, state); 666 } 667 668 static int 669 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin, 670 void *pin_priv, 671 const struct dpll_device *dpll, 672 void *dpll_priv, 673 enum dpll_pin_state state, 674 struct netlink_ext_ack *extack) 675 { 676 struct zl3073x_dpll *zldpll = dpll_priv; 677 struct zl3073x_dpll_pin *pin = pin_priv; 678 u8 new_ref; 679 int rc; 680 681 switch (zldpll->refsel_mode) { 682 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 683 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 684 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 685 if (state == DPLL_PIN_STATE_CONNECTED) { 686 /* Choose the pin as new selected reference */ 687 new_ref = zl3073x_input_pin_ref_get(pin->id); 688 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 689 /* No reference */ 690 new_ref = ZL3073X_DPLL_REF_NONE; 691 } else { 692 NL_SET_ERR_MSG_MOD(extack, 693 "Invalid pin state for manual mode"); 694 return -EINVAL; 695 } 696 697 rc = zl3073x_dpll_selected_ref_set(zldpll, new_ref); 698 break; 699 700 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 701 if (state == DPLL_PIN_STATE_SELECTABLE) { 702 if (pin->selectable) 703 return 0; /* Pin is already selectable */ 704 705 /* Restore pin priority in HW */ 706 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 707 if (rc) 708 return rc; 709 710 /* Mark pin as selectable */ 711 pin->selectable = true; 712 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 713 if (!pin->selectable) 714 return 0; /* Pin is already disconnected */ 715 716 /* Set pin priority to none in HW */ 717 rc = zl3073x_dpll_ref_prio_set(pin, 718 ZL_DPLL_REF_PRIO_NONE); 719 if (rc) 720 return rc; 721 722 /* Mark pin as non-selectable */ 723 pin->selectable = false; 724 } else { 725 NL_SET_ERR_MSG(extack, 726 "Invalid pin state for automatic mode"); 727 return -EINVAL; 728 } 729 break; 730 731 default: 732 /* In other modes we cannot change input reference */ 733 NL_SET_ERR_MSG(extack, 734 "Pin state cannot be changed in current mode"); 735 rc = -EOPNOTSUPP; 736 break; 737 } 738 739 return rc; 740 } 741 742 static int 743 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv, 744 const struct dpll_device *dpll, void *dpll_priv, 745 u32 *prio, struct netlink_ext_ack *extack) 746 { 747 struct zl3073x_dpll_pin *pin = pin_priv; 748 749 *prio = pin->prio; 750 751 return 0; 752 } 753 754 static int 755 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv, 756 const struct dpll_device *dpll, void *dpll_priv, 757 u32 prio, struct netlink_ext_ack *extack) 758 { 759 struct zl3073x_dpll_pin *pin = pin_priv; 760 int rc; 761 762 if (prio > ZL_DPLL_REF_PRIO_MAX) 763 return -EINVAL; 764 765 /* If the pin is selectable then update HW registers */ 766 if (pin->selectable) { 767 rc = zl3073x_dpll_ref_prio_set(pin, prio); 768 if (rc) 769 return rc; 770 } 771 772 /* Save priority */ 773 pin->prio = prio; 774 775 return 0; 776 } 777 778 static int 779 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, 780 void *pin_priv, 781 const struct dpll_device *dpll, 782 void *dpll_priv, 783 struct dpll_pin_esync *esync, 784 struct netlink_ext_ack *extack) 785 { 786 struct zl3073x_dpll *zldpll = dpll_priv; 787 struct zl3073x_dev *zldev = zldpll->dev; 788 struct zl3073x_dpll_pin *pin = pin_priv; 789 const struct zl3073x_synth *synth; 790 const struct zl3073x_out *out; 791 u8 clock_type, out_id; 792 u32 synth_freq; 793 794 out_id = zl3073x_output_pin_out_get(pin->id); 795 out = zl3073x_out_state_get(zldev, out_id); 796 797 /* If N-division is enabled, esync is not supported. The register used 798 * for N-division is also used for the esync divider so both cannot 799 * be used. 800 */ 801 switch (zl3073x_out_signal_format_get(out)) { 802 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 803 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 804 return -EOPNOTSUPP; 805 default: 806 break; 807 } 808 809 /* Get attached synth frequency */ 810 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out)); 811 synth_freq = zl3073x_synth_freq_get(synth); 812 813 clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode); 814 if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { 815 /* No need to read esync data if it is not enabled */ 816 esync->freq = 0; 817 esync->pulse = 0; 818 819 goto finish; 820 } 821 822 /* Compute esync frequency */ 823 esync->freq = synth_freq / out->div / out->esync_n_period; 824 825 /* By comparing the esync_pulse_width to the half of the pulse width 826 * the esync pulse percentage can be determined. 827 * Note that half pulse width is in units of half synth cycles, which 828 * is why it reduces down to be output_div. 829 */ 830 esync->pulse = (50 * out->esync_n_width) / out->div; 831 832 finish: 833 /* Set supported esync ranges if the pin supports esync control and 834 * if the output frequency is > 1 Hz. 835 */ 836 if (pin->esync_control && (synth_freq / out->div) > 1) { 837 esync->range = esync_freq_ranges; 838 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 839 } else { 840 esync->range = NULL; 841 esync->range_num = 0; 842 } 843 844 return 0; 845 } 846 847 static int 848 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin, 849 void *pin_priv, 850 const struct dpll_device *dpll, 851 void *dpll_priv, u64 freq, 852 struct netlink_ext_ack *extack) 853 { 854 struct zl3073x_dpll *zldpll = dpll_priv; 855 struct zl3073x_dev *zldev = zldpll->dev; 856 struct zl3073x_dpll_pin *pin = pin_priv; 857 const struct zl3073x_synth *synth; 858 struct zl3073x_out out; 859 u8 clock_type, out_id; 860 u32 synth_freq; 861 862 out_id = zl3073x_output_pin_out_get(pin->id); 863 out = *zl3073x_out_state_get(zldev, out_id); 864 865 /* If N-division is enabled, esync is not supported. The register used 866 * for N-division is also used for the esync divider so both cannot 867 * be used. 868 */ 869 switch (zl3073x_out_signal_format_get(&out)) { 870 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 871 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 872 return -EOPNOTSUPP; 873 default: 874 break; 875 } 876 877 /* Select clock type */ 878 if (freq) 879 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC; 880 else 881 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL; 882 883 /* Update clock type in output mode */ 884 out.mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE; 885 out.mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type); 886 887 /* If esync is being disabled just write mailbox and finish */ 888 if (!freq) 889 goto write_mailbox; 890 891 /* Get attached synth frequency */ 892 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 893 synth_freq = zl3073x_synth_freq_get(synth); 894 895 /* Compute and update esync period */ 896 out.esync_n_period = synth_freq / (u32)freq / out.div; 897 898 /* Half of the period in units of 1/2 synth cycle can be represented by 899 * the output_div. To get the supported esync pulse width of 25% of the 900 * period the output_div can just be divided by 2. Note that this 901 * assumes that output_div is even, otherwise some resolution will be 902 * lost. 903 */ 904 out.esync_n_width = out.div / 2; 905 906 write_mailbox: 907 /* Commit output configuration */ 908 return zl3073x_out_state_set(zldev, out_id, &out); 909 } 910 911 static int 912 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin, 913 void *pin_priv, 914 const struct dpll_device *dpll, 915 void *dpll_priv, u64 *frequency, 916 struct netlink_ext_ack *extack) 917 { 918 struct zl3073x_dpll *zldpll = dpll_priv; 919 struct zl3073x_dpll_pin *pin = pin_priv; 920 921 *frequency = zl3073x_dev_output_pin_freq_get(zldpll->dev, pin->id); 922 923 return 0; 924 } 925 926 static int 927 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, 928 void *pin_priv, 929 const struct dpll_device *dpll, 930 void *dpll_priv, u64 frequency, 931 struct netlink_ext_ack *extack) 932 { 933 struct zl3073x_dpll *zldpll = dpll_priv; 934 struct zl3073x_dev *zldev = zldpll->dev; 935 struct zl3073x_dpll_pin *pin = pin_priv; 936 const struct zl3073x_synth *synth; 937 u8 out_id, signal_format; 938 u32 new_div, synth_freq; 939 struct zl3073x_out out; 940 941 out_id = zl3073x_output_pin_out_get(pin->id); 942 out = *zl3073x_out_state_get(zldev, out_id); 943 944 /* Get attached synth frequency and compute new divisor */ 945 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 946 synth_freq = zl3073x_synth_freq_get(synth); 947 new_div = synth_freq / (u32)frequency; 948 949 /* Get used signal format for the given output */ 950 signal_format = zl3073x_out_signal_format_get(&out); 951 952 /* Check signal format */ 953 if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV && 954 signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) { 955 /* For non N-divided signal formats the frequency is computed 956 * as division of synth frequency and output divisor. 957 */ 958 out.div = new_div; 959 960 /* For 50/50 duty cycle the divisor is equal to width */ 961 out.width = new_div; 962 963 /* Commit output configuration */ 964 return zl3073x_out_state_set(zldev, out_id, &out); 965 } 966 967 if (zl3073x_dpll_is_p_pin(pin)) { 968 /* We are going to change output frequency for P-pin but 969 * if the requested frequency is less than current N-pin 970 * frequency then indicate a failure as we are not able 971 * to compute N-pin divisor to keep its frequency unchanged. 972 * 973 * Update divisor for N-pin to keep N-pin frequency. 974 */ 975 out.esync_n_period = (out.esync_n_period * out.div) / new_div; 976 if (!out.esync_n_period) 977 return -EINVAL; 978 979 /* Update the output divisor */ 980 out.div = new_div; 981 982 /* For 50/50 duty cycle the divisor is equal to width */ 983 out.width = out.div; 984 } else { 985 /* We are going to change frequency of N-pin but if 986 * the requested freq is greater or equal than freq of P-pin 987 * in the output pair we cannot compute divisor for the N-pin. 988 * In this case indicate a failure. 989 * 990 * Update divisor for N-pin 991 */ 992 out.esync_n_period = div64_u64(synth_freq, frequency * out.div); 993 if (!out.esync_n_period) 994 return -EINVAL; 995 } 996 997 /* For 50/50 duty cycle the divisor is equal to width */ 998 out.esync_n_width = out.esync_n_period; 999 1000 /* Commit output configuration */ 1001 return zl3073x_out_state_set(zldev, out_id, &out); 1002 } 1003 1004 static int 1005 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 1006 void *pin_priv, 1007 const struct dpll_device *dpll, 1008 void *dpll_priv, 1009 s32 *phase_adjust, 1010 struct netlink_ext_ack *extack) 1011 { 1012 struct zl3073x_dpll *zldpll = dpll_priv; 1013 struct zl3073x_dev *zldev = zldpll->dev; 1014 struct zl3073x_dpll_pin *pin = pin_priv; 1015 const struct zl3073x_out *out; 1016 u8 out_id; 1017 1018 out_id = zl3073x_output_pin_out_get(pin->id); 1019 out = zl3073x_out_state_get(zldev, out_id); 1020 1021 /* Convert value to ps and reverse two's complement negation applied 1022 * during 'set' 1023 */ 1024 *phase_adjust = -out->phase_comp * pin->phase_gran; 1025 1026 return 0; 1027 } 1028 1029 static int 1030 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 1031 void *pin_priv, 1032 const struct dpll_device *dpll, 1033 void *dpll_priv, 1034 s32 phase_adjust, 1035 struct netlink_ext_ack *extack) 1036 { 1037 struct zl3073x_dpll *zldpll = dpll_priv; 1038 struct zl3073x_dev *zldev = zldpll->dev; 1039 struct zl3073x_dpll_pin *pin = pin_priv; 1040 struct zl3073x_out out; 1041 u8 out_id; 1042 1043 out_id = zl3073x_output_pin_out_get(pin->id); 1044 out = *zl3073x_out_state_get(zldev, out_id); 1045 1046 /* The value in the register is stored as two's complement negation 1047 * of requested value and expressed in half synth clock cycles. 1048 */ 1049 out.phase_comp = -phase_adjust / pin->phase_gran; 1050 1051 /* Update output configuration from mailbox */ 1052 return zl3073x_out_state_set(zldev, out_id, &out); 1053 } 1054 1055 static int 1056 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 1057 void *pin_priv, 1058 const struct dpll_device *dpll, 1059 void *dpll_priv, 1060 enum dpll_pin_state *state, 1061 struct netlink_ext_ack *extack) 1062 { 1063 /* If the output pin is registered then it is always connected */ 1064 *state = DPLL_PIN_STATE_CONNECTED; 1065 1066 return 0; 1067 } 1068 1069 static int 1070 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, 1071 enum dpll_lock_status *status, 1072 enum dpll_lock_status_error *status_error, 1073 struct netlink_ext_ack *extack) 1074 { 1075 struct zl3073x_dpll *zldpll = dpll_priv; 1076 struct zl3073x_dev *zldev = zldpll->dev; 1077 u8 mon_status, state; 1078 int rc; 1079 1080 switch (zldpll->refsel_mode) { 1081 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1082 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1083 /* In FREERUN and NCO modes the DPLL is always unlocked */ 1084 *status = DPLL_LOCK_STATUS_UNLOCKED; 1085 1086 return 0; 1087 default: 1088 break; 1089 } 1090 1091 /* Read DPLL monitor status */ 1092 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id), 1093 &mon_status); 1094 if (rc) 1095 return rc; 1096 state = FIELD_GET(ZL_DPLL_MON_STATUS_STATE, mon_status); 1097 1098 switch (state) { 1099 case ZL_DPLL_MON_STATUS_STATE_LOCK: 1100 if (FIELD_GET(ZL_DPLL_MON_STATUS_HO_READY, mon_status)) 1101 *status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 1102 else 1103 *status = DPLL_LOCK_STATUS_LOCKED; 1104 break; 1105 case ZL_DPLL_MON_STATUS_STATE_HOLDOVER: 1106 case ZL_DPLL_MON_STATUS_STATE_ACQUIRING: 1107 *status = DPLL_LOCK_STATUS_HOLDOVER; 1108 break; 1109 default: 1110 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n", 1111 mon_status); 1112 *status = DPLL_LOCK_STATUS_UNLOCKED; 1113 break; 1114 } 1115 1116 return 0; 1117 } 1118 1119 static int 1120 zl3073x_dpll_supported_modes_get(const struct dpll_device *dpll, 1121 void *dpll_priv, unsigned long *modes, 1122 struct netlink_ext_ack *extack) 1123 { 1124 struct zl3073x_dpll *zldpll = dpll_priv; 1125 1126 /* We support switching between automatic and manual mode, except in 1127 * a case where the DPLL channel is configured to run in NCO mode. 1128 * In this case, report only the manual mode to which the NCO is mapped 1129 * as the only supported one. 1130 */ 1131 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_NCO) 1132 __set_bit(DPLL_MODE_AUTOMATIC, modes); 1133 1134 __set_bit(DPLL_MODE_MANUAL, modes); 1135 1136 return 0; 1137 } 1138 1139 static int 1140 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, 1141 enum dpll_mode *mode, struct netlink_ext_ack *extack) 1142 { 1143 struct zl3073x_dpll *zldpll = dpll_priv; 1144 1145 switch (zldpll->refsel_mode) { 1146 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1147 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 1148 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1149 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 1150 /* Use MANUAL for device FREERUN, HOLDOVER, NCO and 1151 * REFLOCK modes 1152 */ 1153 *mode = DPLL_MODE_MANUAL; 1154 break; 1155 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 1156 /* Use AUTO for device AUTO mode */ 1157 *mode = DPLL_MODE_AUTOMATIC; 1158 break; 1159 default: 1160 return -EINVAL; 1161 } 1162 1163 return 0; 1164 } 1165 1166 static int 1167 zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device *dpll, 1168 void *dpll_priv, u32 *factor, 1169 struct netlink_ext_ack *extack) 1170 { 1171 struct zl3073x_dpll *zldpll = dpll_priv; 1172 1173 *factor = zl3073x_dev_phase_avg_factor_get(zldpll->dev); 1174 1175 return 0; 1176 } 1177 1178 static void 1179 zl3073x_dpll_change_work(struct work_struct *work) 1180 { 1181 struct zl3073x_dpll *zldpll; 1182 1183 zldpll = container_of(work, struct zl3073x_dpll, change_work); 1184 dpll_device_change_ntf(zldpll->dpll_dev); 1185 } 1186 1187 static int 1188 zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device *dpll, 1189 void *dpll_priv, u32 factor, 1190 struct netlink_ext_ack *extack) 1191 { 1192 struct zl3073x_dpll *item, *zldpll = dpll_priv; 1193 int rc; 1194 1195 if (factor > 15) { 1196 NL_SET_ERR_MSG_FMT(extack, 1197 "Phase offset average factor has to be from range <0,15>"); 1198 return -EINVAL; 1199 } 1200 1201 rc = zl3073x_dev_phase_avg_factor_set(zldpll->dev, factor); 1202 if (rc) { 1203 NL_SET_ERR_MSG_FMT(extack, 1204 "Failed to set phase offset averaging factor"); 1205 return rc; 1206 } 1207 1208 /* The averaging factor is common for all DPLL channels so after change 1209 * we have to send a notification for other DPLL devices. 1210 */ 1211 list_for_each_entry(item, &zldpll->dev->dplls, list) { 1212 if (item != zldpll) 1213 schedule_work(&item->change_work); 1214 } 1215 1216 return 0; 1217 } 1218 1219 static int 1220 zl3073x_dpll_mode_set(const struct dpll_device *dpll, void *dpll_priv, 1221 enum dpll_mode mode, struct netlink_ext_ack *extack) 1222 { 1223 struct zl3073x_dpll *zldpll = dpll_priv; 1224 u8 hw_mode, mode_refsel, ref; 1225 int rc; 1226 1227 rc = zl3073x_dpll_selected_ref_get(zldpll, &ref); 1228 if (rc) { 1229 NL_SET_ERR_MSG_MOD(extack, "failed to get selected reference"); 1230 return rc; 1231 } 1232 1233 if (mode == DPLL_MODE_MANUAL) { 1234 /* We are switching from automatic to manual mode: 1235 * - if we have a valid reference selected during auto mode then 1236 * we will switch to forced reference lock mode and use this 1237 * reference for selection 1238 * - if NO valid reference is selected, we will switch to forced 1239 * holdover mode or freerun mode, depending on the current 1240 * lock status 1241 */ 1242 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1243 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 1244 else if (zldpll->lock_status == DPLL_LOCK_STATUS_UNLOCKED) 1245 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 1246 else 1247 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 1248 } else { 1249 /* We are switching from manual to automatic mode: 1250 * - if there is a valid reference selected then ensure that 1251 * it is selectable after switch to automatic mode 1252 * - switch to automatic mode 1253 */ 1254 struct zl3073x_dpll_pin *pin; 1255 1256 pin = zl3073x_dpll_pin_get_by_ref(zldpll, ref); 1257 if (pin && !pin->selectable) { 1258 /* Restore pin priority in HW */ 1259 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 1260 if (rc) { 1261 NL_SET_ERR_MSG_MOD(extack, 1262 "failed to restore pin priority"); 1263 return rc; 1264 } 1265 1266 pin->selectable = true; 1267 } 1268 1269 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_AUTO; 1270 } 1271 1272 /* Build mode_refsel value */ 1273 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, hw_mode); 1274 1275 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1276 mode_refsel |= FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 1277 1278 /* Update dpll_mode_refsel register */ 1279 rc = zl3073x_write_u8(zldpll->dev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1280 mode_refsel); 1281 if (rc) { 1282 NL_SET_ERR_MSG_MOD(extack, 1283 "failed to set reference selection mode"); 1284 return rc; 1285 } 1286 1287 zldpll->refsel_mode = hw_mode; 1288 1289 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1290 zldpll->forced_ref = ref; 1291 1292 return 0; 1293 } 1294 1295 static int 1296 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll, 1297 void *dpll_priv, 1298 enum dpll_feature_state *state, 1299 struct netlink_ext_ack *extack) 1300 { 1301 struct zl3073x_dpll *zldpll = dpll_priv; 1302 1303 if (zldpll->phase_monitor) 1304 *state = DPLL_FEATURE_STATE_ENABLE; 1305 else 1306 *state = DPLL_FEATURE_STATE_DISABLE; 1307 1308 return 0; 1309 } 1310 1311 static int 1312 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll, 1313 void *dpll_priv, 1314 enum dpll_feature_state state, 1315 struct netlink_ext_ack *extack) 1316 { 1317 struct zl3073x_dpll *zldpll = dpll_priv; 1318 1319 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE); 1320 1321 return 0; 1322 } 1323 1324 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = { 1325 .direction_get = zl3073x_dpll_pin_direction_get, 1326 .esync_get = zl3073x_dpll_input_pin_esync_get, 1327 .esync_set = zl3073x_dpll_input_pin_esync_set, 1328 .ffo_get = zl3073x_dpll_input_pin_ffo_get, 1329 .frequency_get = zl3073x_dpll_input_pin_frequency_get, 1330 .frequency_set = zl3073x_dpll_input_pin_frequency_set, 1331 .phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get, 1332 .phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get, 1333 .phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set, 1334 .prio_get = zl3073x_dpll_input_pin_prio_get, 1335 .prio_set = zl3073x_dpll_input_pin_prio_set, 1336 .state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get, 1337 .state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set, 1338 }; 1339 1340 static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = { 1341 .direction_get = zl3073x_dpll_pin_direction_get, 1342 .esync_get = zl3073x_dpll_output_pin_esync_get, 1343 .esync_set = zl3073x_dpll_output_pin_esync_set, 1344 .frequency_get = zl3073x_dpll_output_pin_frequency_get, 1345 .frequency_set = zl3073x_dpll_output_pin_frequency_set, 1346 .phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get, 1347 .phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set, 1348 .state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get, 1349 }; 1350 1351 static const struct dpll_device_ops zl3073x_dpll_device_ops = { 1352 .lock_status_get = zl3073x_dpll_lock_status_get, 1353 .mode_get = zl3073x_dpll_mode_get, 1354 .mode_set = zl3073x_dpll_mode_set, 1355 .phase_offset_avg_factor_get = zl3073x_dpll_phase_offset_avg_factor_get, 1356 .phase_offset_avg_factor_set = zl3073x_dpll_phase_offset_avg_factor_set, 1357 .phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get, 1358 .phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set, 1359 .supported_modes_get = zl3073x_dpll_supported_modes_get, 1360 }; 1361 1362 /** 1363 * zl3073x_dpll_pin_alloc - allocate DPLL pin 1364 * @zldpll: pointer to zl3073x_dpll 1365 * @dir: pin direction 1366 * @id: pin id 1367 * 1368 * Allocates and initializes zl3073x_dpll_pin structure for given 1369 * pin id and direction. 1370 * 1371 * Return: pointer to allocated structure on success, error pointer on error 1372 */ 1373 static struct zl3073x_dpll_pin * 1374 zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir, 1375 u8 id) 1376 { 1377 struct zl3073x_dpll_pin *pin; 1378 1379 pin = kzalloc(sizeof(*pin), GFP_KERNEL); 1380 if (!pin) 1381 return ERR_PTR(-ENOMEM); 1382 1383 pin->dpll = zldpll; 1384 pin->dir = dir; 1385 pin->id = id; 1386 1387 return pin; 1388 } 1389 1390 /** 1391 * zl3073x_dpll_pin_free - deallocate DPLL pin 1392 * @pin: pin to free 1393 * 1394 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc. 1395 */ 1396 static void 1397 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin) 1398 { 1399 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); 1400 1401 kfree(pin); 1402 } 1403 1404 /** 1405 * zl3073x_dpll_pin_register - register DPLL pin 1406 * @pin: pointer to DPLL pin 1407 * @index: absolute pin index for registration 1408 * 1409 * Registers given DPLL pin into DPLL sub-system. 1410 * 1411 * Return: 0 on success, <0 on error 1412 */ 1413 static int 1414 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index) 1415 { 1416 struct zl3073x_dpll *zldpll = pin->dpll; 1417 struct zl3073x_pin_props *props; 1418 const struct dpll_pin_ops *ops; 1419 int rc; 1420 1421 /* Get pin properties */ 1422 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); 1423 if (IS_ERR(props)) 1424 return PTR_ERR(props); 1425 1426 /* Save package label, esync capability and phase adjust granularity */ 1427 strscpy(pin->label, props->package_label); 1428 pin->esync_control = props->esync_control; 1429 pin->phase_gran = props->dpll_props.phase_gran; 1430 1431 if (zl3073x_dpll_is_input_pin(pin)) { 1432 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); 1433 if (rc) 1434 goto err_prio_get; 1435 1436 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) { 1437 /* Clamp prio to max value & mark pin non-selectable */ 1438 pin->prio = ZL_DPLL_REF_PRIO_MAX; 1439 pin->selectable = false; 1440 } else { 1441 /* Mark pin as selectable */ 1442 pin->selectable = true; 1443 } 1444 } 1445 1446 /* Create or get existing DPLL pin */ 1447 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, 1448 &props->dpll_props, &pin->tracker); 1449 if (IS_ERR(pin->dpll_pin)) { 1450 rc = PTR_ERR(pin->dpll_pin); 1451 goto err_pin_get; 1452 } 1453 dpll_pin_fwnode_set(pin->dpll_pin, props->fwnode); 1454 1455 if (zl3073x_dpll_is_input_pin(pin)) 1456 ops = &zl3073x_dpll_input_pin_ops; 1457 else 1458 ops = &zl3073x_dpll_output_pin_ops; 1459 1460 /* Register the pin */ 1461 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1462 if (rc) 1463 goto err_register; 1464 1465 /* Free pin properties */ 1466 zl3073x_pin_props_put(props); 1467 1468 return 0; 1469 1470 err_register: 1471 dpll_pin_put(pin->dpll_pin, &pin->tracker); 1472 err_prio_get: 1473 pin->dpll_pin = NULL; 1474 err_pin_get: 1475 zl3073x_pin_props_put(props); 1476 1477 return rc; 1478 } 1479 1480 /** 1481 * zl3073x_dpll_pin_unregister - unregister DPLL pin 1482 * @pin: pointer to DPLL pin 1483 * 1484 * Unregisters pin previously registered by @zl3073x_dpll_pin_register. 1485 */ 1486 static void 1487 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin) 1488 { 1489 struct zl3073x_dpll *zldpll = pin->dpll; 1490 const struct dpll_pin_ops *ops; 1491 1492 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); 1493 1494 if (zl3073x_dpll_is_input_pin(pin)) 1495 ops = &zl3073x_dpll_input_pin_ops; 1496 else 1497 ops = &zl3073x_dpll_output_pin_ops; 1498 1499 /* Unregister the pin */ 1500 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1501 1502 dpll_pin_put(pin->dpll_pin, &pin->tracker); 1503 pin->dpll_pin = NULL; 1504 } 1505 1506 /** 1507 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins 1508 * @zldpll: pointer to zl3073x_dpll structure 1509 * 1510 * Enumerates all DPLL pins registered to given DPLL device and 1511 * unregisters them. 1512 */ 1513 static void 1514 zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll) 1515 { 1516 struct zl3073x_dpll_pin *pin, *next; 1517 1518 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { 1519 zl3073x_dpll_pin_unregister(pin); 1520 list_del(&pin->list); 1521 zl3073x_dpll_pin_free(pin); 1522 } 1523 } 1524 1525 /** 1526 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable 1527 * @zldpll: pointer to zl3073x_dpll structure 1528 * @dir: pin direction 1529 * @index: pin index 1530 * 1531 * Checks if the given pin can be registered to given DPLL. For both 1532 * directions the pin can be registered if it is enabled. In case of 1533 * differential signal type only P-pin is reported as registrable. 1534 * And additionally for the output pin, the pin can be registered only 1535 * if it is connected to synthesizer that is driven by given DPLL. 1536 * 1537 * Return: true if the pin is registrable, false if not 1538 */ 1539 static bool 1540 zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll, 1541 enum dpll_pin_direction dir, u8 index) 1542 { 1543 struct zl3073x_dev *zldev = zldpll->dev; 1544 bool is_diff, is_enabled; 1545 const char *name; 1546 1547 if (dir == DPLL_PIN_DIRECTION_INPUT) { 1548 u8 ref_id = zl3073x_input_pin_ref_get(index); 1549 const struct zl3073x_ref *ref; 1550 1551 /* Skip the pin if the DPLL is running in NCO mode */ 1552 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO) 1553 return false; 1554 1555 name = "REF"; 1556 ref = zl3073x_ref_state_get(zldev, ref_id); 1557 is_diff = zl3073x_ref_is_diff(ref); 1558 is_enabled = zl3073x_ref_is_enabled(ref); 1559 } else { 1560 /* Output P&N pair shares single HW output */ 1561 u8 out = zl3073x_output_pin_out_get(index); 1562 1563 /* Skip the pin if it is connected to different DPLL channel */ 1564 if (zl3073x_dev_out_dpll_get(zldev, out) != zldpll->id) { 1565 dev_dbg(zldev->dev, 1566 "OUT%u is driven by different DPLL\n", out); 1567 1568 return false; 1569 } 1570 1571 name = "OUT"; 1572 is_diff = zl3073x_dev_out_is_diff(zldev, out); 1573 is_enabled = zl3073x_dev_output_pin_is_enabled(zldev, index); 1574 } 1575 1576 /* Skip N-pin if the corresponding input/output is differential */ 1577 if (is_diff && zl3073x_is_n_pin(index)) { 1578 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", 1579 name, index / 2); 1580 1581 return false; 1582 } 1583 1584 /* Skip the pin if it is disabled */ 1585 if (!is_enabled) { 1586 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, 1587 zl3073x_is_p_pin(index) ? 'P' : 'N'); 1588 1589 return false; 1590 } 1591 1592 return true; 1593 } 1594 1595 /** 1596 * zl3073x_dpll_pins_register - register all registerable DPLL pins 1597 * @zldpll: pointer to zl3073x_dpll structure 1598 * 1599 * Enumerates all possible input/output pins and registers all of them 1600 * that are registrable. 1601 * 1602 * Return: 0 on success, <0 on error 1603 */ 1604 static int 1605 zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll) 1606 { 1607 struct zl3073x_dpll_pin *pin; 1608 enum dpll_pin_direction dir; 1609 u8 id, index; 1610 int rc; 1611 1612 /* Process input pins */ 1613 for (index = 0; index < ZL3073X_NUM_PINS; index++) { 1614 /* First input pins and then output pins */ 1615 if (index < ZL3073X_NUM_INPUT_PINS) { 1616 id = index; 1617 dir = DPLL_PIN_DIRECTION_INPUT; 1618 } else { 1619 id = index - ZL3073X_NUM_INPUT_PINS; 1620 dir = DPLL_PIN_DIRECTION_OUTPUT; 1621 } 1622 1623 /* Check if the pin registrable to this DPLL */ 1624 if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id)) 1625 continue; 1626 1627 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id); 1628 if (IS_ERR(pin)) { 1629 rc = PTR_ERR(pin); 1630 goto error; 1631 } 1632 1633 rc = zl3073x_dpll_pin_register(pin, index); 1634 if (rc) 1635 goto error; 1636 1637 list_add(&pin->list, &zldpll->pins); 1638 } 1639 1640 return 0; 1641 1642 error: 1643 zl3073x_dpll_pins_unregister(zldpll); 1644 1645 return rc; 1646 } 1647 1648 /** 1649 * zl3073x_dpll_device_register - register DPLL device 1650 * @zldpll: pointer to zl3073x_dpll structure 1651 * 1652 * Registers given DPLL device into DPLL sub-system. 1653 * 1654 * Return: 0 on success, <0 on error 1655 */ 1656 static int 1657 zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll) 1658 { 1659 struct zl3073x_dev *zldev = zldpll->dev; 1660 u8 dpll_mode_refsel; 1661 int rc; 1662 1663 /* Read DPLL mode and forcibly selected reference */ 1664 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1665 &dpll_mode_refsel); 1666 if (rc) 1667 return rc; 1668 1669 /* Extract mode and selected input reference */ 1670 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE, 1671 dpll_mode_refsel); 1672 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF, 1673 dpll_mode_refsel); 1674 1675 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, 1676 THIS_MODULE, &zldpll->tracker); 1677 if (IS_ERR(zldpll->dpll_dev)) { 1678 rc = PTR_ERR(zldpll->dpll_dev); 1679 zldpll->dpll_dev = NULL; 1680 1681 return rc; 1682 } 1683 1684 rc = dpll_device_register(zldpll->dpll_dev, 1685 zl3073x_prop_dpll_type_get(zldev, zldpll->id), 1686 &zl3073x_dpll_device_ops, zldpll); 1687 if (rc) { 1688 dpll_device_put(zldpll->dpll_dev, &zldpll->tracker); 1689 zldpll->dpll_dev = NULL; 1690 } 1691 1692 return rc; 1693 } 1694 1695 /** 1696 * zl3073x_dpll_device_unregister - unregister DPLL device 1697 * @zldpll: pointer to zl3073x_dpll structure 1698 * 1699 * Unregisters given DPLL device from DPLL sub-system previously registered 1700 * by @zl3073x_dpll_device_register. 1701 */ 1702 static void 1703 zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll) 1704 { 1705 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n"); 1706 1707 cancel_work_sync(&zldpll->change_work); 1708 1709 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, 1710 zldpll); 1711 dpll_device_put(zldpll->dpll_dev, &zldpll->tracker); 1712 zldpll->dpll_dev = NULL; 1713 } 1714 1715 /** 1716 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change 1717 * @pin: pin to check 1718 * 1719 * Check for the change of DPLL to connected pin phase offset change. 1720 * 1721 * Return: true on phase offset change, false otherwise 1722 */ 1723 static bool 1724 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin) 1725 { 1726 struct zl3073x_dpll *zldpll = pin->dpll; 1727 struct zl3073x_dev *zldev = zldpll->dev; 1728 unsigned int reg; 1729 s64 phase_offset; 1730 u8 ref_id; 1731 int rc; 1732 1733 /* No phase offset if the ref monitor reports signal errors */ 1734 ref_id = zl3073x_input_pin_ref_get(pin->id); 1735 if (!zl3073x_dev_ref_is_status_ok(zldev, ref_id)) 1736 return false; 1737 1738 /* Select register to read phase offset value depending on pin and 1739 * phase monitor state: 1740 * 1) For connected pin use dpll_phase_err_data register 1741 * 2) For other pins use appropriate ref_phase register if the phase 1742 * monitor feature is enabled. 1743 */ 1744 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) 1745 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); 1746 else if (zldpll->phase_monitor) 1747 reg = ZL_REG_REF_PHASE(ref_id); 1748 else 1749 return false; 1750 1751 /* Read measured phase offset value */ 1752 rc = zl3073x_read_u48(zldev, reg, &phase_offset); 1753 if (rc) { 1754 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n", 1755 ERR_PTR(rc)); 1756 1757 return false; 1758 } 1759 1760 /* Convert to ps */ 1761 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100); 1762 1763 /* Compare with previous value */ 1764 if (phase_offset != pin->phase_offset) { 1765 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n", 1766 pin->label, pin->phase_offset, phase_offset); 1767 pin->phase_offset = phase_offset; 1768 1769 return true; 1770 } 1771 1772 return false; 1773 } 1774 1775 /** 1776 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change 1777 * @pin: pin to check 1778 * 1779 * Check for the given pin's fractional frequency change. 1780 * 1781 * Return: true on fractional frequency offset change, false otherwise 1782 */ 1783 static bool 1784 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin) 1785 { 1786 struct zl3073x_dpll *zldpll = pin->dpll; 1787 struct zl3073x_dev *zldev = zldpll->dev; 1788 const struct zl3073x_ref *ref; 1789 u8 ref_id; 1790 1791 /* Get reference monitor status */ 1792 ref_id = zl3073x_input_pin_ref_get(pin->id); 1793 ref = zl3073x_ref_state_get(zldev, ref_id); 1794 1795 /* Do not report ffo changes if the reference monitor report errors */ 1796 if (!zl3073x_ref_is_status_ok(ref)) 1797 return false; 1798 1799 /* Compare with previous value */ 1800 if (pin->freq_offset != ref->ffo) { 1801 dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n", 1802 pin->label, pin->freq_offset, ref->ffo); 1803 pin->freq_offset = ref->ffo; 1804 1805 return true; 1806 } 1807 1808 return false; 1809 } 1810 1811 /** 1812 * zl3073x_dpll_changes_check - check for changes and send notifications 1813 * @zldpll: pointer to zl3073x_dpll structure 1814 * 1815 * Checks for changes on given DPLL device and its registered DPLL pins 1816 * and sends notifications about them. 1817 * 1818 * This function is periodically called from @zl3073x_dev_periodic_work. 1819 */ 1820 void 1821 zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll) 1822 { 1823 struct zl3073x_dev *zldev = zldpll->dev; 1824 enum dpll_lock_status lock_status; 1825 struct device *dev = zldev->dev; 1826 struct zl3073x_dpll_pin *pin; 1827 int rc; 1828 1829 zldpll->check_count++; 1830 1831 /* Get current lock status for the DPLL */ 1832 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, 1833 &lock_status, NULL, NULL); 1834 if (rc) { 1835 dev_err(dev, "Failed to get DPLL%u lock status: %pe\n", 1836 zldpll->id, ERR_PTR(rc)); 1837 return; 1838 } 1839 1840 /* If lock status was changed then notify DPLL core */ 1841 if (zldpll->lock_status != lock_status) { 1842 zldpll->lock_status = lock_status; 1843 dpll_device_change_ntf(zldpll->dpll_dev); 1844 } 1845 1846 /* Input pin monitoring does make sense only in automatic 1847 * or forced reference modes. 1848 */ 1849 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO && 1850 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK) 1851 return; 1852 1853 /* Update phase offset latch registers for this DPLL if the phase 1854 * offset monitor feature is enabled. 1855 */ 1856 if (zldpll->phase_monitor) { 1857 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id); 1858 if (rc) { 1859 dev_err(zldev->dev, 1860 "Failed to update phase offsets: %pe\n", 1861 ERR_PTR(rc)); 1862 return; 1863 } 1864 } 1865 1866 list_for_each_entry(pin, &zldpll->pins, list) { 1867 enum dpll_pin_state state; 1868 bool pin_changed = false; 1869 1870 /* Output pins change checks are not necessary because output 1871 * states are constant. 1872 */ 1873 if (!zl3073x_dpll_is_input_pin(pin)) 1874 continue; 1875 1876 rc = zl3073x_dpll_ref_state_get(pin, &state); 1877 if (rc) { 1878 dev_err(dev, 1879 "Failed to get %s on DPLL%u state: %pe\n", 1880 pin->label, zldpll->id, ERR_PTR(rc)); 1881 return; 1882 } 1883 1884 if (state != pin->pin_state) { 1885 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, 1886 pin->pin_state, state); 1887 pin->pin_state = state; 1888 pin_changed = true; 1889 } 1890 1891 /* Check for phase offset and ffo change once per second */ 1892 if (zldpll->check_count % 2 == 0) { 1893 if (zl3073x_dpll_pin_phase_offset_check(pin)) 1894 pin_changed = true; 1895 1896 if (zl3073x_dpll_pin_ffo_check(pin)) 1897 pin_changed = true; 1898 } 1899 1900 if (pin_changed) 1901 dpll_pin_change_ntf(pin->dpll_pin); 1902 } 1903 } 1904 1905 /** 1906 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments 1907 * @zldev: pointer to zl3073x device 1908 * 1909 * Performs initial fine phase adjustments needed per datasheet. 1910 * 1911 * Return: 0 on success, <0 on error 1912 */ 1913 int 1914 zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev) 1915 { 1916 int rc; 1917 1918 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); 1919 if (rc) 1920 return rc; 1921 1922 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); 1923 if (rc) 1924 return rc; 1925 1926 rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff); 1927 if (rc) 1928 return rc; 1929 1930 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); 1931 if (rc) 1932 return rc; 1933 1934 return rc; 1935 } 1936 1937 /** 1938 * zl3073x_dpll_alloc - allocate DPLL device 1939 * @zldev: pointer to zl3073x device 1940 * @ch: DPLL channel number 1941 * 1942 * Allocates DPLL device structure for given DPLL channel. 1943 * 1944 * Return: pointer to DPLL device on success, error pointer on error 1945 */ 1946 struct zl3073x_dpll * 1947 zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch) 1948 { 1949 struct zl3073x_dpll *zldpll; 1950 1951 zldpll = kzalloc(sizeof(*zldpll), GFP_KERNEL); 1952 if (!zldpll) 1953 return ERR_PTR(-ENOMEM); 1954 1955 zldpll->dev = zldev; 1956 zldpll->id = ch; 1957 INIT_LIST_HEAD(&zldpll->pins); 1958 INIT_WORK(&zldpll->change_work, zl3073x_dpll_change_work); 1959 1960 return zldpll; 1961 } 1962 1963 /** 1964 * zl3073x_dpll_free - free DPLL device 1965 * @zldpll: pointer to zl3073x_dpll structure 1966 * 1967 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc. 1968 */ 1969 void 1970 zl3073x_dpll_free(struct zl3073x_dpll *zldpll) 1971 { 1972 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); 1973 1974 kfree(zldpll); 1975 } 1976 1977 /** 1978 * zl3073x_dpll_register - register DPLL device and all its pins 1979 * @zldpll: pointer to zl3073x_dpll structure 1980 * 1981 * Registers given DPLL device and all its pins into DPLL sub-system. 1982 * 1983 * Return: 0 on success, <0 on error 1984 */ 1985 int 1986 zl3073x_dpll_register(struct zl3073x_dpll *zldpll) 1987 { 1988 int rc; 1989 1990 rc = zl3073x_dpll_device_register(zldpll); 1991 if (rc) 1992 return rc; 1993 1994 rc = zl3073x_dpll_pins_register(zldpll); 1995 if (rc) { 1996 zl3073x_dpll_device_unregister(zldpll); 1997 return rc; 1998 } 1999 2000 return 0; 2001 } 2002 2003 /** 2004 * zl3073x_dpll_unregister - unregister DPLL device and its pins 2005 * @zldpll: pointer to zl3073x_dpll structure 2006 * 2007 * Unregisters given DPLL device and all its pins from DPLL sub-system 2008 * previously registered by @zl3073x_dpll_register. 2009 */ 2010 void 2011 zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll) 2012 { 2013 /* Unregister all pins and dpll */ 2014 zl3073x_dpll_pins_unregister(zldpll); 2015 zl3073x_dpll_device_unregister(zldpll); 2016 } 2017