1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bits.h> 4 #include <linux/bitfield.h> 5 #include <linux/bug.h> 6 #include <linux/container_of.h> 7 #include <linux/dev_printk.h> 8 #include <linux/dpll.h> 9 #include <linux/err.h> 10 #include <linux/kthread.h> 11 #include <linux/math64.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/netlink.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/sprintf.h> 18 19 #include "core.h" 20 #include "dpll.h" 21 #include "prop.h" 22 #include "regs.h" 23 24 #define ZL3073X_DPLL_REF_NONE ZL3073X_NUM_REFS 25 #define ZL3073X_DPLL_REF_IS_VALID(_ref) ((_ref) != ZL3073X_DPLL_REF_NONE) 26 27 /** 28 * struct zl3073x_dpll_pin - DPLL pin 29 * @list: this DPLL pin list entry 30 * @dpll: DPLL the pin is registered to 31 * @dpll_pin: pointer to registered dpll_pin 32 * @label: package label 33 * @dir: pin direction 34 * @id: pin id 35 * @prio: pin priority <0, 14> 36 * @selectable: pin is selectable in automatic mode 37 * @esync_control: embedded sync is controllable 38 * @phase_gran: phase adjustment granularity 39 * @pin_state: last saved pin state 40 * @phase_offset: last saved pin phase offset 41 * @freq_offset: last saved fractional frequency offset 42 */ 43 struct zl3073x_dpll_pin { 44 struct list_head list; 45 struct zl3073x_dpll *dpll; 46 struct dpll_pin *dpll_pin; 47 char label[8]; 48 enum dpll_pin_direction dir; 49 u8 id; 50 u8 prio; 51 bool selectable; 52 bool esync_control; 53 s32 phase_gran; 54 enum dpll_pin_state pin_state; 55 s64 phase_offset; 56 s64 freq_offset; 57 }; 58 59 /* 60 * Supported esync ranges for input and for output per output pair type 61 */ 62 static const struct dpll_pin_frequency esync_freq_ranges[] = { 63 DPLL_PIN_FREQUENCY_RANGE(0, 1), 64 }; 65 66 /** 67 * zl3073x_dpll_is_input_pin - check if the pin is input one 68 * @pin: pin to check 69 * 70 * Return: true if pin is input, false if pin is output. 71 */ 72 static bool 73 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin) 74 { 75 return pin->dir == DPLL_PIN_DIRECTION_INPUT; 76 } 77 78 /** 79 * zl3073x_dpll_is_p_pin - check if the pin is P-pin 80 * @pin: pin to check 81 * 82 * Return: true if the pin is P-pin, false if it is N-pin 83 */ 84 static bool 85 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin) 86 { 87 return zl3073x_is_p_pin(pin->id); 88 } 89 90 static int 91 zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv, 92 const struct dpll_device *dpll, void *dpll_priv, 93 enum dpll_pin_direction *direction, 94 struct netlink_ext_ack *extack) 95 { 96 struct zl3073x_dpll_pin *pin = pin_priv; 97 98 *direction = pin->dir; 99 100 return 0; 101 } 102 103 static struct zl3073x_dpll_pin * 104 zl3073x_dpll_pin_get_by_ref(struct zl3073x_dpll *zldpll, u8 ref_id) 105 { 106 struct zl3073x_dpll_pin *pin; 107 108 list_for_each_entry(pin, &zldpll->pins, list) { 109 if (zl3073x_dpll_is_input_pin(pin) && 110 zl3073x_input_pin_ref_get(pin->id) == ref_id) 111 return pin; 112 } 113 114 return NULL; 115 } 116 117 static int 118 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, 119 void *pin_priv, 120 const struct dpll_device *dpll, 121 void *dpll_priv, 122 struct dpll_pin_esync *esync, 123 struct netlink_ext_ack *extack) 124 { 125 struct zl3073x_dpll *zldpll = dpll_priv; 126 struct zl3073x_dev *zldev = zldpll->dev; 127 struct zl3073x_dpll_pin *pin = pin_priv; 128 const struct zl3073x_ref *ref; 129 u8 ref_id; 130 131 ref_id = zl3073x_input_pin_ref_get(pin->id); 132 ref = zl3073x_ref_state_get(zldev, ref_id); 133 134 switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) { 135 case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: 136 esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0; 137 esync->pulse = 25; 138 break; 139 default: 140 esync->freq = 0; 141 esync->pulse = 0; 142 break; 143 } 144 145 /* If the pin supports esync control expose its range but only 146 * if the current reference frequency is > 1 Hz. 147 */ 148 if (pin->esync_control && zl3073x_ref_freq_get(ref) > 1) { 149 esync->range = esync_freq_ranges; 150 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 151 } else { 152 esync->range = NULL; 153 esync->range_num = 0; 154 } 155 156 return 0; 157 } 158 159 static int 160 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin, 161 void *pin_priv, 162 const struct dpll_device *dpll, 163 void *dpll_priv, u64 freq, 164 struct netlink_ext_ack *extack) 165 { 166 struct zl3073x_dpll *zldpll = dpll_priv; 167 struct zl3073x_dev *zldev = zldpll->dev; 168 struct zl3073x_dpll_pin *pin = pin_priv; 169 struct zl3073x_ref ref; 170 u8 ref_id, sync_mode; 171 172 ref_id = zl3073x_input_pin_ref_get(pin->id); 173 ref = *zl3073x_ref_state_get(zldev, ref_id); 174 175 /* Use freq == 0 to disable esync */ 176 if (!freq) 177 sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF; 178 else 179 sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75; 180 181 ref.sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE; 182 ref.sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode); 183 184 if (freq) { 185 /* 1 Hz is only supported frequency now */ 186 ref.esync_n_div = ZL_REF_ESYNC_DIV_1HZ; 187 } 188 189 /* Update reference configuration */ 190 return zl3073x_ref_state_set(zldev, ref_id, &ref); 191 } 192 193 static int 194 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv, 195 const struct dpll_device *dpll, void *dpll_priv, 196 s64 *ffo, struct netlink_ext_ack *extack) 197 { 198 struct zl3073x_dpll_pin *pin = pin_priv; 199 200 *ffo = pin->freq_offset; 201 202 return 0; 203 } 204 205 static int 206 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin, 207 void *pin_priv, 208 const struct dpll_device *dpll, 209 void *dpll_priv, u64 *frequency, 210 struct netlink_ext_ack *extack) 211 { 212 struct zl3073x_dpll *zldpll = dpll_priv; 213 struct zl3073x_dpll_pin *pin = pin_priv; 214 u8 ref_id; 215 216 ref_id = zl3073x_input_pin_ref_get(pin->id); 217 *frequency = zl3073x_dev_ref_freq_get(zldpll->dev, ref_id); 218 219 return 0; 220 } 221 222 static int 223 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin, 224 void *pin_priv, 225 const struct dpll_device *dpll, 226 void *dpll_priv, u64 frequency, 227 struct netlink_ext_ack *extack) 228 { 229 struct zl3073x_dpll *zldpll = dpll_priv; 230 struct zl3073x_dev *zldev = zldpll->dev; 231 struct zl3073x_dpll_pin *pin = pin_priv; 232 struct zl3073x_ref ref; 233 u8 ref_id; 234 235 /* Get reference state */ 236 ref_id = zl3073x_input_pin_ref_get(pin->id); 237 ref = *zl3073x_ref_state_get(zldev, ref_id); 238 239 /* Update frequency */ 240 zl3073x_ref_freq_set(&ref, frequency); 241 242 /* Commit reference state */ 243 return zl3073x_ref_state_set(zldev, ref_id, &ref); 244 } 245 246 /** 247 * zl3073x_dpll_selected_ref_get - get currently selected reference 248 * @zldpll: pointer to zl3073x_dpll 249 * @ref: place to store selected reference 250 * 251 * Check for currently selected reference the DPLL should be locked to 252 * and stores its index to given @ref. 253 * 254 * Return: 0 on success, <0 on error 255 */ 256 static int 257 zl3073x_dpll_selected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 258 { 259 struct zl3073x_dev *zldev = zldpll->dev; 260 u8 state, value; 261 int rc; 262 263 switch (zldpll->refsel_mode) { 264 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 265 /* For automatic mode read refsel_status register */ 266 rc = zl3073x_read_u8(zldev, 267 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id), 268 &value); 269 if (rc) 270 return rc; 271 272 /* Extract reference state */ 273 state = FIELD_GET(ZL_DPLL_REFSEL_STATUS_STATE, value); 274 275 /* Return the reference only if the DPLL is locked to it */ 276 if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK) 277 *ref = FIELD_GET(ZL_DPLL_REFSEL_STATUS_REFSEL, value); 278 else 279 *ref = ZL3073X_DPLL_REF_NONE; 280 break; 281 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 282 /* For manual mode return stored value */ 283 *ref = zldpll->forced_ref; 284 break; 285 default: 286 /* For other modes like NCO, freerun... there is no input ref */ 287 *ref = ZL3073X_DPLL_REF_NONE; 288 break; 289 } 290 291 return 0; 292 } 293 294 /** 295 * zl3073x_dpll_selected_ref_set - select reference in manual mode 296 * @zldpll: pointer to zl3073x_dpll 297 * @ref: input reference to be selected 298 * 299 * Selects the given reference for the DPLL channel it should be 300 * locked to. 301 * 302 * Return: 0 on success, <0 on error 303 */ 304 static int 305 zl3073x_dpll_selected_ref_set(struct zl3073x_dpll *zldpll, u8 ref) 306 { 307 struct zl3073x_dev *zldev = zldpll->dev; 308 u8 mode, mode_refsel; 309 int rc; 310 311 mode = zldpll->refsel_mode; 312 313 switch (mode) { 314 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 315 /* Manual mode with ref selected */ 316 if (ref == ZL3073X_DPLL_REF_NONE) { 317 switch (zldpll->lock_status) { 318 case DPLL_LOCK_STATUS_LOCKED_HO_ACQ: 319 case DPLL_LOCK_STATUS_HOLDOVER: 320 /* Switch to forced holdover */ 321 mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 322 break; 323 default: 324 /* Switch to freerun */ 325 mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 326 break; 327 } 328 /* Keep selected reference */ 329 ref = zldpll->forced_ref; 330 } else if (ref == zldpll->forced_ref) { 331 /* No register update - same mode and same ref */ 332 return 0; 333 } 334 break; 335 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 336 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 337 /* Manual mode without no ref */ 338 if (ref == ZL3073X_DPLL_REF_NONE) 339 /* No register update - keep current mode */ 340 return 0; 341 342 /* Switch to reflock mode and update ref selection */ 343 mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 344 break; 345 default: 346 /* For other modes like automatic or NCO ref cannot be selected 347 * manually 348 */ 349 return -EOPNOTSUPP; 350 } 351 352 /* Build mode_refsel value */ 353 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode) | 354 FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 355 356 /* Update dpll_mode_refsel register */ 357 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 358 mode_refsel); 359 if (rc) 360 return rc; 361 362 /* Store new mode and forced reference */ 363 zldpll->refsel_mode = mode; 364 zldpll->forced_ref = ref; 365 366 return rc; 367 } 368 369 /** 370 * zl3073x_dpll_connected_ref_get - get currently connected reference 371 * @zldpll: pointer to zl3073x_dpll 372 * @ref: place to store selected reference 373 * 374 * Looks for currently connected the DPLL is locked to and stores its index 375 * to given @ref. 376 * 377 * Return: 0 on success, <0 on error 378 */ 379 static int 380 zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 381 { 382 struct zl3073x_dev *zldev = zldpll->dev; 383 int rc; 384 385 /* Get currently selected input reference */ 386 rc = zl3073x_dpll_selected_ref_get(zldpll, ref); 387 if (rc) 388 return rc; 389 390 /* If the monitor indicates an error nothing is connected */ 391 if (ZL3073X_DPLL_REF_IS_VALID(*ref) && 392 !zl3073x_dev_ref_is_status_ok(zldev, *ref)) 393 *ref = ZL3073X_DPLL_REF_NONE; 394 395 return 0; 396 } 397 398 static int 399 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin, 400 void *pin_priv, 401 const struct dpll_device *dpll, 402 void *dpll_priv, s64 *phase_offset, 403 struct netlink_ext_ack *extack) 404 { 405 struct zl3073x_dpll *zldpll = dpll_priv; 406 struct zl3073x_dev *zldev = zldpll->dev; 407 struct zl3073x_dpll_pin *pin = pin_priv; 408 const struct zl3073x_ref *ref; 409 u8 conn_id, ref_id; 410 s64 ref_phase; 411 int rc; 412 413 /* Get currently connected reference */ 414 rc = zl3073x_dpll_connected_ref_get(zldpll, &conn_id); 415 if (rc) 416 return rc; 417 418 /* Report phase offset only for currently connected pin if the phase 419 * monitor feature is disabled and only if the input pin signal is 420 * present. 421 */ 422 ref_id = zl3073x_input_pin_ref_get(pin->id); 423 ref = zl3073x_ref_state_get(zldev, ref_id); 424 if ((!zldpll->phase_monitor && ref_id != conn_id) || 425 !zl3073x_ref_is_status_ok(ref)) { 426 *phase_offset = 0; 427 return 0; 428 } 429 430 ref_phase = pin->phase_offset; 431 432 /* The DPLL being locked to a higher freq than the current ref 433 * the phase offset is modded to the period of the signal 434 * the dpll is locked to. 435 */ 436 if (ZL3073X_DPLL_REF_IS_VALID(conn_id) && conn_id != ref_id) { 437 u32 conn_freq, ref_freq; 438 439 /* Get frequency of connected and given ref */ 440 conn_freq = zl3073x_dev_ref_freq_get(zldev, conn_id); 441 ref_freq = zl3073x_ref_freq_get(ref); 442 443 if (conn_freq > ref_freq) { 444 s64 conn_period, div_factor; 445 446 conn_period = div_s64(PSEC_PER_SEC, conn_freq); 447 div_factor = div64_s64(ref_phase, conn_period); 448 ref_phase -= conn_period * div_factor; 449 } 450 } 451 452 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER; 453 454 return rc; 455 } 456 457 static int 458 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 459 void *pin_priv, 460 const struct dpll_device *dpll, 461 void *dpll_priv, 462 s32 *phase_adjust, 463 struct netlink_ext_ack *extack) 464 { 465 struct zl3073x_dpll *zldpll = dpll_priv; 466 struct zl3073x_dev *zldev = zldpll->dev; 467 struct zl3073x_dpll_pin *pin = pin_priv; 468 const struct zl3073x_ref *ref; 469 s64 phase_comp; 470 u8 ref_id; 471 472 /* Read reference configuration */ 473 ref_id = zl3073x_input_pin_ref_get(pin->id); 474 ref = zl3073x_ref_state_get(zldev, ref_id); 475 476 /* Perform sign extension for 48bit signed value */ 477 phase_comp = sign_extend64(ref->phase_comp, 47); 478 479 /* Reverse two's complement negation applied during set and convert 480 * to 32bit signed int 481 */ 482 *phase_adjust = (s32)-phase_comp; 483 484 return 0; 485 } 486 487 static int 488 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 489 void *pin_priv, 490 const struct dpll_device *dpll, 491 void *dpll_priv, 492 s32 phase_adjust, 493 struct netlink_ext_ack *extack) 494 { 495 struct zl3073x_dpll *zldpll = dpll_priv; 496 struct zl3073x_dev *zldev = zldpll->dev; 497 struct zl3073x_dpll_pin *pin = pin_priv; 498 struct zl3073x_ref ref; 499 u8 ref_id; 500 501 /* Read reference configuration */ 502 ref_id = zl3073x_input_pin_ref_get(pin->id); 503 ref = *zl3073x_ref_state_get(zldev, ref_id); 504 505 /* The value in the register is stored as two's complement negation 506 * of requested value. 507 */ 508 ref.phase_comp = -phase_adjust; 509 510 /* Update reference configuration */ 511 return zl3073x_ref_state_set(zldev, ref_id, &ref); 512 } 513 514 /** 515 * zl3073x_dpll_ref_prio_get - get priority for given input pin 516 * @pin: pointer to pin 517 * @prio: place to store priority 518 * 519 * Reads current priority for the given input pin and stores the value 520 * to @prio. 521 * 522 * Return: 0 on success, <0 on error 523 */ 524 static int 525 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio) 526 { 527 struct zl3073x_dpll *zldpll = pin->dpll; 528 struct zl3073x_dev *zldev = zldpll->dev; 529 u8 ref, ref_prio; 530 int rc; 531 532 guard(mutex)(&zldev->multiop_lock); 533 534 /* Read DPLL configuration */ 535 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 536 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 537 if (rc) 538 return rc; 539 540 /* Read reference priority - one value for P&N pins (4 bits/pin) */ 541 ref = zl3073x_input_pin_ref_get(pin->id); 542 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), 543 &ref_prio); 544 if (rc) 545 return rc; 546 547 /* Select nibble according pin type */ 548 if (zl3073x_dpll_is_p_pin(pin)) 549 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_P, ref_prio); 550 else 551 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_N, ref_prio); 552 553 return rc; 554 } 555 556 /** 557 * zl3073x_dpll_ref_prio_set - set priority for given input pin 558 * @pin: pointer to pin 559 * @prio: place to store priority 560 * 561 * Sets priority for the given input pin. 562 * 563 * Return: 0 on success, <0 on error 564 */ 565 static int 566 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio) 567 { 568 struct zl3073x_dpll *zldpll = pin->dpll; 569 struct zl3073x_dev *zldev = zldpll->dev; 570 u8 ref, ref_prio; 571 int rc; 572 573 guard(mutex)(&zldev->multiop_lock); 574 575 /* Read DPLL configuration into mailbox */ 576 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 577 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 578 if (rc) 579 return rc; 580 581 /* Read reference priority - one value shared between P&N pins */ 582 ref = zl3073x_input_pin_ref_get(pin->id); 583 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio); 584 if (rc) 585 return rc; 586 587 /* Update nibble according pin type */ 588 if (zl3073x_dpll_is_p_pin(pin)) { 589 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_P; 590 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio); 591 } else { 592 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_N; 593 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio); 594 } 595 596 /* Update reference priority */ 597 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio); 598 if (rc) 599 return rc; 600 601 /* Commit configuration */ 602 return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR, 603 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 604 } 605 606 /** 607 * zl3073x_dpll_ref_state_get - get status for given input pin 608 * @pin: pointer to pin 609 * @state: place to store status 610 * 611 * Checks current status for the given input pin and stores the value 612 * to @state. 613 * 614 * Return: 0 on success, <0 on error 615 */ 616 static int 617 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin, 618 enum dpll_pin_state *state) 619 { 620 struct zl3073x_dpll *zldpll = pin->dpll; 621 struct zl3073x_dev *zldev = zldpll->dev; 622 u8 ref, ref_conn; 623 int rc; 624 625 ref = zl3073x_input_pin_ref_get(pin->id); 626 627 /* Get currently connected reference */ 628 rc = zl3073x_dpll_connected_ref_get(zldpll, &ref_conn); 629 if (rc) 630 return rc; 631 632 if (ref == ref_conn) { 633 *state = DPLL_PIN_STATE_CONNECTED; 634 return 0; 635 } 636 637 /* If the DPLL is running in automatic mode and the reference is 638 * selectable and its monitor does not report any error then report 639 * pin as selectable. 640 */ 641 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO && 642 zl3073x_dev_ref_is_status_ok(zldev, ref) && pin->selectable) { 643 *state = DPLL_PIN_STATE_SELECTABLE; 644 return 0; 645 } 646 647 /* Otherwise report the pin as disconnected */ 648 *state = DPLL_PIN_STATE_DISCONNECTED; 649 650 return 0; 651 } 652 653 static int 654 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 655 void *pin_priv, 656 const struct dpll_device *dpll, 657 void *dpll_priv, 658 enum dpll_pin_state *state, 659 struct netlink_ext_ack *extack) 660 { 661 struct zl3073x_dpll_pin *pin = pin_priv; 662 663 return zl3073x_dpll_ref_state_get(pin, state); 664 } 665 666 static int 667 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin, 668 void *pin_priv, 669 const struct dpll_device *dpll, 670 void *dpll_priv, 671 enum dpll_pin_state state, 672 struct netlink_ext_ack *extack) 673 { 674 struct zl3073x_dpll *zldpll = dpll_priv; 675 struct zl3073x_dpll_pin *pin = pin_priv; 676 u8 new_ref; 677 int rc; 678 679 switch (zldpll->refsel_mode) { 680 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 681 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 682 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 683 if (state == DPLL_PIN_STATE_CONNECTED) { 684 /* Choose the pin as new selected reference */ 685 new_ref = zl3073x_input_pin_ref_get(pin->id); 686 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 687 /* No reference */ 688 new_ref = ZL3073X_DPLL_REF_NONE; 689 } else { 690 NL_SET_ERR_MSG_MOD(extack, 691 "Invalid pin state for manual mode"); 692 return -EINVAL; 693 } 694 695 rc = zl3073x_dpll_selected_ref_set(zldpll, new_ref); 696 break; 697 698 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 699 if (state == DPLL_PIN_STATE_SELECTABLE) { 700 if (pin->selectable) 701 return 0; /* Pin is already selectable */ 702 703 /* Restore pin priority in HW */ 704 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 705 if (rc) 706 return rc; 707 708 /* Mark pin as selectable */ 709 pin->selectable = true; 710 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 711 if (!pin->selectable) 712 return 0; /* Pin is already disconnected */ 713 714 /* Set pin priority to none in HW */ 715 rc = zl3073x_dpll_ref_prio_set(pin, 716 ZL_DPLL_REF_PRIO_NONE); 717 if (rc) 718 return rc; 719 720 /* Mark pin as non-selectable */ 721 pin->selectable = false; 722 } else { 723 NL_SET_ERR_MSG(extack, 724 "Invalid pin state for automatic mode"); 725 return -EINVAL; 726 } 727 break; 728 729 default: 730 /* In other modes we cannot change input reference */ 731 NL_SET_ERR_MSG(extack, 732 "Pin state cannot be changed in current mode"); 733 rc = -EOPNOTSUPP; 734 break; 735 } 736 737 return rc; 738 } 739 740 static int 741 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv, 742 const struct dpll_device *dpll, void *dpll_priv, 743 u32 *prio, struct netlink_ext_ack *extack) 744 { 745 struct zl3073x_dpll_pin *pin = pin_priv; 746 747 *prio = pin->prio; 748 749 return 0; 750 } 751 752 static int 753 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv, 754 const struct dpll_device *dpll, void *dpll_priv, 755 u32 prio, struct netlink_ext_ack *extack) 756 { 757 struct zl3073x_dpll_pin *pin = pin_priv; 758 int rc; 759 760 if (prio > ZL_DPLL_REF_PRIO_MAX) 761 return -EINVAL; 762 763 /* If the pin is selectable then update HW registers */ 764 if (pin->selectable) { 765 rc = zl3073x_dpll_ref_prio_set(pin, prio); 766 if (rc) 767 return rc; 768 } 769 770 /* Save priority */ 771 pin->prio = prio; 772 773 return 0; 774 } 775 776 static int 777 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, 778 void *pin_priv, 779 const struct dpll_device *dpll, 780 void *dpll_priv, 781 struct dpll_pin_esync *esync, 782 struct netlink_ext_ack *extack) 783 { 784 struct zl3073x_dpll *zldpll = dpll_priv; 785 struct zl3073x_dev *zldev = zldpll->dev; 786 struct zl3073x_dpll_pin *pin = pin_priv; 787 const struct zl3073x_synth *synth; 788 const struct zl3073x_out *out; 789 u8 clock_type, out_id; 790 u32 synth_freq; 791 792 out_id = zl3073x_output_pin_out_get(pin->id); 793 out = zl3073x_out_state_get(zldev, out_id); 794 795 /* If N-division is enabled, esync is not supported. The register used 796 * for N-division is also used for the esync divider so both cannot 797 * be used. 798 */ 799 switch (zl3073x_out_signal_format_get(out)) { 800 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 801 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 802 return -EOPNOTSUPP; 803 default: 804 break; 805 } 806 807 /* Get attached synth frequency */ 808 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out)); 809 synth_freq = zl3073x_synth_freq_get(synth); 810 811 clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode); 812 if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { 813 /* No need to read esync data if it is not enabled */ 814 esync->freq = 0; 815 esync->pulse = 0; 816 817 goto finish; 818 } 819 820 /* Compute esync frequency */ 821 esync->freq = synth_freq / out->div / out->esync_n_period; 822 823 /* By comparing the esync_pulse_width to the half of the pulse width 824 * the esync pulse percentage can be determined. 825 * Note that half pulse width is in units of half synth cycles, which 826 * is why it reduces down to be output_div. 827 */ 828 esync->pulse = (50 * out->esync_n_width) / out->div; 829 830 finish: 831 /* Set supported esync ranges if the pin supports esync control and 832 * if the output frequency is > 1 Hz. 833 */ 834 if (pin->esync_control && (synth_freq / out->div) > 1) { 835 esync->range = esync_freq_ranges; 836 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 837 } else { 838 esync->range = NULL; 839 esync->range_num = 0; 840 } 841 842 return 0; 843 } 844 845 static int 846 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin, 847 void *pin_priv, 848 const struct dpll_device *dpll, 849 void *dpll_priv, u64 freq, 850 struct netlink_ext_ack *extack) 851 { 852 struct zl3073x_dpll *zldpll = dpll_priv; 853 struct zl3073x_dev *zldev = zldpll->dev; 854 struct zl3073x_dpll_pin *pin = pin_priv; 855 const struct zl3073x_synth *synth; 856 struct zl3073x_out out; 857 u8 clock_type, out_id; 858 u32 synth_freq; 859 860 out_id = zl3073x_output_pin_out_get(pin->id); 861 out = *zl3073x_out_state_get(zldev, out_id); 862 863 /* If N-division is enabled, esync is not supported. The register used 864 * for N-division is also used for the esync divider so both cannot 865 * be used. 866 */ 867 switch (zl3073x_out_signal_format_get(&out)) { 868 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 869 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 870 return -EOPNOTSUPP; 871 default: 872 break; 873 } 874 875 /* Select clock type */ 876 if (freq) 877 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC; 878 else 879 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL; 880 881 /* Update clock type in output mode */ 882 out.mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE; 883 out.mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type); 884 885 /* If esync is being disabled just write mailbox and finish */ 886 if (!freq) 887 goto write_mailbox; 888 889 /* Get attached synth frequency */ 890 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 891 synth_freq = zl3073x_synth_freq_get(synth); 892 893 /* Compute and update esync period */ 894 out.esync_n_period = synth_freq / (u32)freq / out.div; 895 896 /* Half of the period in units of 1/2 synth cycle can be represented by 897 * the output_div. To get the supported esync pulse width of 25% of the 898 * period the output_div can just be divided by 2. Note that this 899 * assumes that output_div is even, otherwise some resolution will be 900 * lost. 901 */ 902 out.esync_n_width = out.div / 2; 903 904 write_mailbox: 905 /* Commit output configuration */ 906 return zl3073x_out_state_set(zldev, out_id, &out); 907 } 908 909 static int 910 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin, 911 void *pin_priv, 912 const struct dpll_device *dpll, 913 void *dpll_priv, u64 *frequency, 914 struct netlink_ext_ack *extack) 915 { 916 struct zl3073x_dpll *zldpll = dpll_priv; 917 struct zl3073x_dev *zldev = zldpll->dev; 918 struct zl3073x_dpll_pin *pin = pin_priv; 919 const struct zl3073x_synth *synth; 920 const struct zl3073x_out *out; 921 u32 synth_freq; 922 u8 out_id; 923 924 out_id = zl3073x_output_pin_out_get(pin->id); 925 out = zl3073x_out_state_get(zldev, out_id); 926 927 /* Get attached synth frequency */ 928 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out)); 929 synth_freq = zl3073x_synth_freq_get(synth); 930 931 switch (zl3073x_out_signal_format_get(out)) { 932 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 933 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 934 /* In case of divided format we have to distiguish between 935 * given output pin type. 936 * 937 * For P-pin the resulting frequency is computed as simple 938 * division of synth frequency and output divisor. 939 * 940 * For N-pin we have to divide additionally by divisor stored 941 * in esync_n_period output mailbox register that is used as 942 * N-pin divisor for these modes. 943 */ 944 *frequency = synth_freq / out->div; 945 946 if (!zl3073x_dpll_is_p_pin(pin)) 947 *frequency = (u32)*frequency / out->esync_n_period; 948 949 break; 950 default: 951 /* In other modes the resulting frequency is computed as 952 * division of synth frequency and output divisor. 953 */ 954 *frequency = synth_freq / out->div; 955 break; 956 } 957 958 return 0; 959 } 960 961 static int 962 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, 963 void *pin_priv, 964 const struct dpll_device *dpll, 965 void *dpll_priv, u64 frequency, 966 struct netlink_ext_ack *extack) 967 { 968 struct zl3073x_dpll *zldpll = dpll_priv; 969 struct zl3073x_dev *zldev = zldpll->dev; 970 struct zl3073x_dpll_pin *pin = pin_priv; 971 const struct zl3073x_synth *synth; 972 u8 out_id, signal_format; 973 u32 new_div, synth_freq; 974 struct zl3073x_out out; 975 976 out_id = zl3073x_output_pin_out_get(pin->id); 977 out = *zl3073x_out_state_get(zldev, out_id); 978 979 /* Get attached synth frequency and compute new divisor */ 980 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 981 synth_freq = zl3073x_synth_freq_get(synth); 982 new_div = synth_freq / (u32)frequency; 983 984 /* Get used signal format for the given output */ 985 signal_format = zl3073x_out_signal_format_get(&out); 986 987 /* Check signal format */ 988 if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV && 989 signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) { 990 /* For non N-divided signal formats the frequency is computed 991 * as division of synth frequency and output divisor. 992 */ 993 out.div = new_div; 994 995 /* For 50/50 duty cycle the divisor is equal to width */ 996 out.width = new_div; 997 998 /* Commit output configuration */ 999 return zl3073x_out_state_set(zldev, out_id, &out); 1000 } 1001 1002 if (zl3073x_dpll_is_p_pin(pin)) { 1003 /* We are going to change output frequency for P-pin but 1004 * if the requested frequency is less than current N-pin 1005 * frequency then indicate a failure as we are not able 1006 * to compute N-pin divisor to keep its frequency unchanged. 1007 * 1008 * Update divisor for N-pin to keep N-pin frequency. 1009 */ 1010 out.esync_n_period = (out.esync_n_period * out.div) / new_div; 1011 if (!out.esync_n_period) 1012 return -EINVAL; 1013 1014 /* Update the output divisor */ 1015 out.div = new_div; 1016 1017 /* For 50/50 duty cycle the divisor is equal to width */ 1018 out.width = out.div; 1019 } else { 1020 /* We are going to change frequency of N-pin but if 1021 * the requested freq is greater or equal than freq of P-pin 1022 * in the output pair we cannot compute divisor for the N-pin. 1023 * In this case indicate a failure. 1024 * 1025 * Update divisor for N-pin 1026 */ 1027 out.esync_n_period = div64_u64(synth_freq, frequency * out.div); 1028 if (!out.esync_n_period) 1029 return -EINVAL; 1030 } 1031 1032 /* For 50/50 duty cycle the divisor is equal to width */ 1033 out.esync_n_width = out.esync_n_period; 1034 1035 /* Commit output configuration */ 1036 return zl3073x_out_state_set(zldev, out_id, &out); 1037 } 1038 1039 static int 1040 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 1041 void *pin_priv, 1042 const struct dpll_device *dpll, 1043 void *dpll_priv, 1044 s32 *phase_adjust, 1045 struct netlink_ext_ack *extack) 1046 { 1047 struct zl3073x_dpll *zldpll = dpll_priv; 1048 struct zl3073x_dev *zldev = zldpll->dev; 1049 struct zl3073x_dpll_pin *pin = pin_priv; 1050 const struct zl3073x_out *out; 1051 u8 out_id; 1052 1053 out_id = zl3073x_output_pin_out_get(pin->id); 1054 out = zl3073x_out_state_get(zldev, out_id); 1055 1056 /* Convert value to ps and reverse two's complement negation applied 1057 * during 'set' 1058 */ 1059 *phase_adjust = -out->phase_comp * pin->phase_gran; 1060 1061 return 0; 1062 } 1063 1064 static int 1065 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 1066 void *pin_priv, 1067 const struct dpll_device *dpll, 1068 void *dpll_priv, 1069 s32 phase_adjust, 1070 struct netlink_ext_ack *extack) 1071 { 1072 struct zl3073x_dpll *zldpll = dpll_priv; 1073 struct zl3073x_dev *zldev = zldpll->dev; 1074 struct zl3073x_dpll_pin *pin = pin_priv; 1075 struct zl3073x_out out; 1076 u8 out_id; 1077 1078 out_id = zl3073x_output_pin_out_get(pin->id); 1079 out = *zl3073x_out_state_get(zldev, out_id); 1080 1081 /* The value in the register is stored as two's complement negation 1082 * of requested value and expressed in half synth clock cycles. 1083 */ 1084 out.phase_comp = -phase_adjust / pin->phase_gran; 1085 1086 /* Update output configuration from mailbox */ 1087 return zl3073x_out_state_set(zldev, out_id, &out); 1088 } 1089 1090 static int 1091 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 1092 void *pin_priv, 1093 const struct dpll_device *dpll, 1094 void *dpll_priv, 1095 enum dpll_pin_state *state, 1096 struct netlink_ext_ack *extack) 1097 { 1098 /* If the output pin is registered then it is always connected */ 1099 *state = DPLL_PIN_STATE_CONNECTED; 1100 1101 return 0; 1102 } 1103 1104 static int 1105 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, 1106 enum dpll_lock_status *status, 1107 enum dpll_lock_status_error *status_error, 1108 struct netlink_ext_ack *extack) 1109 { 1110 struct zl3073x_dpll *zldpll = dpll_priv; 1111 struct zl3073x_dev *zldev = zldpll->dev; 1112 u8 mon_status, state; 1113 int rc; 1114 1115 switch (zldpll->refsel_mode) { 1116 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1117 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1118 /* In FREERUN and NCO modes the DPLL is always unlocked */ 1119 *status = DPLL_LOCK_STATUS_UNLOCKED; 1120 1121 return 0; 1122 default: 1123 break; 1124 } 1125 1126 /* Read DPLL monitor status */ 1127 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id), 1128 &mon_status); 1129 if (rc) 1130 return rc; 1131 state = FIELD_GET(ZL_DPLL_MON_STATUS_STATE, mon_status); 1132 1133 switch (state) { 1134 case ZL_DPLL_MON_STATUS_STATE_LOCK: 1135 if (FIELD_GET(ZL_DPLL_MON_STATUS_HO_READY, mon_status)) 1136 *status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 1137 else 1138 *status = DPLL_LOCK_STATUS_LOCKED; 1139 break; 1140 case ZL_DPLL_MON_STATUS_STATE_HOLDOVER: 1141 case ZL_DPLL_MON_STATUS_STATE_ACQUIRING: 1142 *status = DPLL_LOCK_STATUS_HOLDOVER; 1143 break; 1144 default: 1145 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n", 1146 mon_status); 1147 *status = DPLL_LOCK_STATUS_UNLOCKED; 1148 break; 1149 } 1150 1151 return 0; 1152 } 1153 1154 static int 1155 zl3073x_dpll_supported_modes_get(const struct dpll_device *dpll, 1156 void *dpll_priv, unsigned long *modes, 1157 struct netlink_ext_ack *extack) 1158 { 1159 struct zl3073x_dpll *zldpll = dpll_priv; 1160 1161 /* We support switching between automatic and manual mode, except in 1162 * a case where the DPLL channel is configured to run in NCO mode. 1163 * In this case, report only the manual mode to which the NCO is mapped 1164 * as the only supported one. 1165 */ 1166 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_NCO) 1167 __set_bit(DPLL_MODE_AUTOMATIC, modes); 1168 1169 __set_bit(DPLL_MODE_MANUAL, modes); 1170 1171 return 0; 1172 } 1173 1174 static int 1175 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, 1176 enum dpll_mode *mode, struct netlink_ext_ack *extack) 1177 { 1178 struct zl3073x_dpll *zldpll = dpll_priv; 1179 1180 switch (zldpll->refsel_mode) { 1181 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1182 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 1183 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1184 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 1185 /* Use MANUAL for device FREERUN, HOLDOVER, NCO and 1186 * REFLOCK modes 1187 */ 1188 *mode = DPLL_MODE_MANUAL; 1189 break; 1190 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 1191 /* Use AUTO for device AUTO mode */ 1192 *mode = DPLL_MODE_AUTOMATIC; 1193 break; 1194 default: 1195 return -EINVAL; 1196 } 1197 1198 return 0; 1199 } 1200 1201 static int 1202 zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device *dpll, 1203 void *dpll_priv, u32 *factor, 1204 struct netlink_ext_ack *extack) 1205 { 1206 struct zl3073x_dpll *zldpll = dpll_priv; 1207 1208 *factor = zl3073x_dev_phase_avg_factor_get(zldpll->dev); 1209 1210 return 0; 1211 } 1212 1213 static void 1214 zl3073x_dpll_change_work(struct work_struct *work) 1215 { 1216 struct zl3073x_dpll *zldpll; 1217 1218 zldpll = container_of(work, struct zl3073x_dpll, change_work); 1219 dpll_device_change_ntf(zldpll->dpll_dev); 1220 } 1221 1222 static int 1223 zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device *dpll, 1224 void *dpll_priv, u32 factor, 1225 struct netlink_ext_ack *extack) 1226 { 1227 struct zl3073x_dpll *item, *zldpll = dpll_priv; 1228 int rc; 1229 1230 if (factor > 15) { 1231 NL_SET_ERR_MSG_FMT(extack, 1232 "Phase offset average factor has to be from range <0,15>"); 1233 return -EINVAL; 1234 } 1235 1236 rc = zl3073x_dev_phase_avg_factor_set(zldpll->dev, factor); 1237 if (rc) { 1238 NL_SET_ERR_MSG_FMT(extack, 1239 "Failed to set phase offset averaging factor"); 1240 return rc; 1241 } 1242 1243 /* The averaging factor is common for all DPLL channels so after change 1244 * we have to send a notification for other DPLL devices. 1245 */ 1246 list_for_each_entry(item, &zldpll->dev->dplls, list) { 1247 if (item != zldpll) 1248 schedule_work(&item->change_work); 1249 } 1250 1251 return 0; 1252 } 1253 1254 static int 1255 zl3073x_dpll_mode_set(const struct dpll_device *dpll, void *dpll_priv, 1256 enum dpll_mode mode, struct netlink_ext_ack *extack) 1257 { 1258 struct zl3073x_dpll *zldpll = dpll_priv; 1259 u8 hw_mode, mode_refsel, ref; 1260 int rc; 1261 1262 rc = zl3073x_dpll_selected_ref_get(zldpll, &ref); 1263 if (rc) { 1264 NL_SET_ERR_MSG_MOD(extack, "failed to get selected reference"); 1265 return rc; 1266 } 1267 1268 if (mode == DPLL_MODE_MANUAL) { 1269 /* We are switching from automatic to manual mode: 1270 * - if we have a valid reference selected during auto mode then 1271 * we will switch to forced reference lock mode and use this 1272 * reference for selection 1273 * - if NO valid reference is selected, we will switch to forced 1274 * holdover mode or freerun mode, depending on the current 1275 * lock status 1276 */ 1277 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1278 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 1279 else if (zldpll->lock_status == DPLL_LOCK_STATUS_UNLOCKED) 1280 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 1281 else 1282 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 1283 } else { 1284 /* We are switching from manual to automatic mode: 1285 * - if there is a valid reference selected then ensure that 1286 * it is selectable after switch to automatic mode 1287 * - switch to automatic mode 1288 */ 1289 struct zl3073x_dpll_pin *pin; 1290 1291 pin = zl3073x_dpll_pin_get_by_ref(zldpll, ref); 1292 if (pin && !pin->selectable) { 1293 /* Restore pin priority in HW */ 1294 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 1295 if (rc) { 1296 NL_SET_ERR_MSG_MOD(extack, 1297 "failed to restore pin priority"); 1298 return rc; 1299 } 1300 1301 pin->selectable = true; 1302 } 1303 1304 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_AUTO; 1305 } 1306 1307 /* Build mode_refsel value */ 1308 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, hw_mode); 1309 1310 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1311 mode_refsel |= FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 1312 1313 /* Update dpll_mode_refsel register */ 1314 rc = zl3073x_write_u8(zldpll->dev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1315 mode_refsel); 1316 if (rc) { 1317 NL_SET_ERR_MSG_MOD(extack, 1318 "failed to set reference selection mode"); 1319 return rc; 1320 } 1321 1322 zldpll->refsel_mode = hw_mode; 1323 1324 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1325 zldpll->forced_ref = ref; 1326 1327 return 0; 1328 } 1329 1330 static int 1331 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll, 1332 void *dpll_priv, 1333 enum dpll_feature_state *state, 1334 struct netlink_ext_ack *extack) 1335 { 1336 struct zl3073x_dpll *zldpll = dpll_priv; 1337 1338 if (zldpll->phase_monitor) 1339 *state = DPLL_FEATURE_STATE_ENABLE; 1340 else 1341 *state = DPLL_FEATURE_STATE_DISABLE; 1342 1343 return 0; 1344 } 1345 1346 static int 1347 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll, 1348 void *dpll_priv, 1349 enum dpll_feature_state state, 1350 struct netlink_ext_ack *extack) 1351 { 1352 struct zl3073x_dpll *zldpll = dpll_priv; 1353 1354 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE); 1355 1356 return 0; 1357 } 1358 1359 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = { 1360 .direction_get = zl3073x_dpll_pin_direction_get, 1361 .esync_get = zl3073x_dpll_input_pin_esync_get, 1362 .esync_set = zl3073x_dpll_input_pin_esync_set, 1363 .ffo_get = zl3073x_dpll_input_pin_ffo_get, 1364 .frequency_get = zl3073x_dpll_input_pin_frequency_get, 1365 .frequency_set = zl3073x_dpll_input_pin_frequency_set, 1366 .phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get, 1367 .phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get, 1368 .phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set, 1369 .prio_get = zl3073x_dpll_input_pin_prio_get, 1370 .prio_set = zl3073x_dpll_input_pin_prio_set, 1371 .state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get, 1372 .state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set, 1373 }; 1374 1375 static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = { 1376 .direction_get = zl3073x_dpll_pin_direction_get, 1377 .esync_get = zl3073x_dpll_output_pin_esync_get, 1378 .esync_set = zl3073x_dpll_output_pin_esync_set, 1379 .frequency_get = zl3073x_dpll_output_pin_frequency_get, 1380 .frequency_set = zl3073x_dpll_output_pin_frequency_set, 1381 .phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get, 1382 .phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set, 1383 .state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get, 1384 }; 1385 1386 static const struct dpll_device_ops zl3073x_dpll_device_ops = { 1387 .lock_status_get = zl3073x_dpll_lock_status_get, 1388 .mode_get = zl3073x_dpll_mode_get, 1389 .mode_set = zl3073x_dpll_mode_set, 1390 .phase_offset_avg_factor_get = zl3073x_dpll_phase_offset_avg_factor_get, 1391 .phase_offset_avg_factor_set = zl3073x_dpll_phase_offset_avg_factor_set, 1392 .phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get, 1393 .phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set, 1394 .supported_modes_get = zl3073x_dpll_supported_modes_get, 1395 }; 1396 1397 /** 1398 * zl3073x_dpll_pin_alloc - allocate DPLL pin 1399 * @zldpll: pointer to zl3073x_dpll 1400 * @dir: pin direction 1401 * @id: pin id 1402 * 1403 * Allocates and initializes zl3073x_dpll_pin structure for given 1404 * pin id and direction. 1405 * 1406 * Return: pointer to allocated structure on success, error pointer on error 1407 */ 1408 static struct zl3073x_dpll_pin * 1409 zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir, 1410 u8 id) 1411 { 1412 struct zl3073x_dpll_pin *pin; 1413 1414 pin = kzalloc(sizeof(*pin), GFP_KERNEL); 1415 if (!pin) 1416 return ERR_PTR(-ENOMEM); 1417 1418 pin->dpll = zldpll; 1419 pin->dir = dir; 1420 pin->id = id; 1421 1422 return pin; 1423 } 1424 1425 /** 1426 * zl3073x_dpll_pin_free - deallocate DPLL pin 1427 * @pin: pin to free 1428 * 1429 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc. 1430 */ 1431 static void 1432 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin) 1433 { 1434 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); 1435 1436 kfree(pin); 1437 } 1438 1439 /** 1440 * zl3073x_dpll_pin_register - register DPLL pin 1441 * @pin: pointer to DPLL pin 1442 * @index: absolute pin index for registration 1443 * 1444 * Registers given DPLL pin into DPLL sub-system. 1445 * 1446 * Return: 0 on success, <0 on error 1447 */ 1448 static int 1449 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index) 1450 { 1451 struct zl3073x_dpll *zldpll = pin->dpll; 1452 struct zl3073x_pin_props *props; 1453 const struct dpll_pin_ops *ops; 1454 int rc; 1455 1456 /* Get pin properties */ 1457 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); 1458 if (IS_ERR(props)) 1459 return PTR_ERR(props); 1460 1461 /* Save package label, esync capability and phase adjust granularity */ 1462 strscpy(pin->label, props->package_label); 1463 pin->esync_control = props->esync_control; 1464 pin->phase_gran = props->dpll_props.phase_gran; 1465 1466 if (zl3073x_dpll_is_input_pin(pin)) { 1467 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); 1468 if (rc) 1469 goto err_prio_get; 1470 1471 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) { 1472 /* Clamp prio to max value & mark pin non-selectable */ 1473 pin->prio = ZL_DPLL_REF_PRIO_MAX; 1474 pin->selectable = false; 1475 } else { 1476 /* Mark pin as selectable */ 1477 pin->selectable = true; 1478 } 1479 } 1480 1481 /* Create or get existing DPLL pin */ 1482 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, 1483 &props->dpll_props); 1484 if (IS_ERR(pin->dpll_pin)) { 1485 rc = PTR_ERR(pin->dpll_pin); 1486 goto err_pin_get; 1487 } 1488 1489 if (zl3073x_dpll_is_input_pin(pin)) 1490 ops = &zl3073x_dpll_input_pin_ops; 1491 else 1492 ops = &zl3073x_dpll_output_pin_ops; 1493 1494 /* Register the pin */ 1495 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1496 if (rc) 1497 goto err_register; 1498 1499 /* Free pin properties */ 1500 zl3073x_pin_props_put(props); 1501 1502 return 0; 1503 1504 err_register: 1505 dpll_pin_put(pin->dpll_pin); 1506 err_prio_get: 1507 pin->dpll_pin = NULL; 1508 err_pin_get: 1509 zl3073x_pin_props_put(props); 1510 1511 return rc; 1512 } 1513 1514 /** 1515 * zl3073x_dpll_pin_unregister - unregister DPLL pin 1516 * @pin: pointer to DPLL pin 1517 * 1518 * Unregisters pin previously registered by @zl3073x_dpll_pin_register. 1519 */ 1520 static void 1521 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin) 1522 { 1523 struct zl3073x_dpll *zldpll = pin->dpll; 1524 const struct dpll_pin_ops *ops; 1525 1526 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); 1527 1528 if (zl3073x_dpll_is_input_pin(pin)) 1529 ops = &zl3073x_dpll_input_pin_ops; 1530 else 1531 ops = &zl3073x_dpll_output_pin_ops; 1532 1533 /* Unregister the pin */ 1534 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1535 1536 dpll_pin_put(pin->dpll_pin); 1537 pin->dpll_pin = NULL; 1538 } 1539 1540 /** 1541 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins 1542 * @zldpll: pointer to zl3073x_dpll structure 1543 * 1544 * Enumerates all DPLL pins registered to given DPLL device and 1545 * unregisters them. 1546 */ 1547 static void 1548 zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll) 1549 { 1550 struct zl3073x_dpll_pin *pin, *next; 1551 1552 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { 1553 zl3073x_dpll_pin_unregister(pin); 1554 list_del(&pin->list); 1555 zl3073x_dpll_pin_free(pin); 1556 } 1557 } 1558 1559 /** 1560 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable 1561 * @zldpll: pointer to zl3073x_dpll structure 1562 * @dir: pin direction 1563 * @index: pin index 1564 * 1565 * Checks if the given pin can be registered to given DPLL. For both 1566 * directions the pin can be registered if it is enabled. In case of 1567 * differential signal type only P-pin is reported as registrable. 1568 * And additionally for the output pin, the pin can be registered only 1569 * if it is connected to synthesizer that is driven by given DPLL. 1570 * 1571 * Return: true if the pin is registrable, false if not 1572 */ 1573 static bool 1574 zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll, 1575 enum dpll_pin_direction dir, u8 index) 1576 { 1577 struct zl3073x_dev *zldev = zldpll->dev; 1578 bool is_diff, is_enabled; 1579 const char *name; 1580 1581 if (dir == DPLL_PIN_DIRECTION_INPUT) { 1582 u8 ref_id = zl3073x_input_pin_ref_get(index); 1583 const struct zl3073x_ref *ref; 1584 1585 /* Skip the pin if the DPLL is running in NCO mode */ 1586 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO) 1587 return false; 1588 1589 name = "REF"; 1590 ref = zl3073x_ref_state_get(zldev, ref_id); 1591 is_diff = zl3073x_ref_is_diff(ref); 1592 is_enabled = zl3073x_ref_is_enabled(ref); 1593 } else { 1594 /* Output P&N pair shares single HW output */ 1595 u8 out = zl3073x_output_pin_out_get(index); 1596 1597 /* Skip the pin if it is connected to different DPLL channel */ 1598 if (zl3073x_dev_out_dpll_get(zldev, out) != zldpll->id) { 1599 dev_dbg(zldev->dev, 1600 "OUT%u is driven by different DPLL\n", out); 1601 1602 return false; 1603 } 1604 1605 name = "OUT"; 1606 is_diff = zl3073x_dev_out_is_diff(zldev, out); 1607 is_enabled = zl3073x_dev_output_pin_is_enabled(zldev, index); 1608 } 1609 1610 /* Skip N-pin if the corresponding input/output is differential */ 1611 if (is_diff && zl3073x_is_n_pin(index)) { 1612 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", 1613 name, index / 2); 1614 1615 return false; 1616 } 1617 1618 /* Skip the pin if it is disabled */ 1619 if (!is_enabled) { 1620 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, 1621 zl3073x_is_p_pin(index) ? 'P' : 'N'); 1622 1623 return false; 1624 } 1625 1626 return true; 1627 } 1628 1629 /** 1630 * zl3073x_dpll_pins_register - register all registerable DPLL pins 1631 * @zldpll: pointer to zl3073x_dpll structure 1632 * 1633 * Enumerates all possible input/output pins and registers all of them 1634 * that are registrable. 1635 * 1636 * Return: 0 on success, <0 on error 1637 */ 1638 static int 1639 zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll) 1640 { 1641 struct zl3073x_dpll_pin *pin; 1642 enum dpll_pin_direction dir; 1643 u8 id, index; 1644 int rc; 1645 1646 /* Process input pins */ 1647 for (index = 0; index < ZL3073X_NUM_PINS; index++) { 1648 /* First input pins and then output pins */ 1649 if (index < ZL3073X_NUM_INPUT_PINS) { 1650 id = index; 1651 dir = DPLL_PIN_DIRECTION_INPUT; 1652 } else { 1653 id = index - ZL3073X_NUM_INPUT_PINS; 1654 dir = DPLL_PIN_DIRECTION_OUTPUT; 1655 } 1656 1657 /* Check if the pin registrable to this DPLL */ 1658 if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id)) 1659 continue; 1660 1661 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id); 1662 if (IS_ERR(pin)) { 1663 rc = PTR_ERR(pin); 1664 goto error; 1665 } 1666 1667 rc = zl3073x_dpll_pin_register(pin, index); 1668 if (rc) 1669 goto error; 1670 1671 list_add(&pin->list, &zldpll->pins); 1672 } 1673 1674 return 0; 1675 1676 error: 1677 zl3073x_dpll_pins_unregister(zldpll); 1678 1679 return rc; 1680 } 1681 1682 /** 1683 * zl3073x_dpll_device_register - register DPLL device 1684 * @zldpll: pointer to zl3073x_dpll structure 1685 * 1686 * Registers given DPLL device into DPLL sub-system. 1687 * 1688 * Return: 0 on success, <0 on error 1689 */ 1690 static int 1691 zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll) 1692 { 1693 struct zl3073x_dev *zldev = zldpll->dev; 1694 u8 dpll_mode_refsel; 1695 int rc; 1696 1697 /* Read DPLL mode and forcibly selected reference */ 1698 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1699 &dpll_mode_refsel); 1700 if (rc) 1701 return rc; 1702 1703 /* Extract mode and selected input reference */ 1704 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE, 1705 dpll_mode_refsel); 1706 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF, 1707 dpll_mode_refsel); 1708 1709 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, 1710 THIS_MODULE); 1711 if (IS_ERR(zldpll->dpll_dev)) { 1712 rc = PTR_ERR(zldpll->dpll_dev); 1713 zldpll->dpll_dev = NULL; 1714 1715 return rc; 1716 } 1717 1718 rc = dpll_device_register(zldpll->dpll_dev, 1719 zl3073x_prop_dpll_type_get(zldev, zldpll->id), 1720 &zl3073x_dpll_device_ops, zldpll); 1721 if (rc) { 1722 dpll_device_put(zldpll->dpll_dev); 1723 zldpll->dpll_dev = NULL; 1724 } 1725 1726 return rc; 1727 } 1728 1729 /** 1730 * zl3073x_dpll_device_unregister - unregister DPLL device 1731 * @zldpll: pointer to zl3073x_dpll structure 1732 * 1733 * Unregisters given DPLL device from DPLL sub-system previously registered 1734 * by @zl3073x_dpll_device_register. 1735 */ 1736 static void 1737 zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll) 1738 { 1739 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n"); 1740 1741 cancel_work_sync(&zldpll->change_work); 1742 1743 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, 1744 zldpll); 1745 dpll_device_put(zldpll->dpll_dev); 1746 zldpll->dpll_dev = NULL; 1747 } 1748 1749 /** 1750 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change 1751 * @pin: pin to check 1752 * 1753 * Check for the change of DPLL to connected pin phase offset change. 1754 * 1755 * Return: true on phase offset change, false otherwise 1756 */ 1757 static bool 1758 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin) 1759 { 1760 struct zl3073x_dpll *zldpll = pin->dpll; 1761 struct zl3073x_dev *zldev = zldpll->dev; 1762 unsigned int reg; 1763 s64 phase_offset; 1764 u8 ref_id; 1765 int rc; 1766 1767 /* No phase offset if the ref monitor reports signal errors */ 1768 ref_id = zl3073x_input_pin_ref_get(pin->id); 1769 if (!zl3073x_dev_ref_is_status_ok(zldev, ref_id)) 1770 return false; 1771 1772 /* Select register to read phase offset value depending on pin and 1773 * phase monitor state: 1774 * 1) For connected pin use dpll_phase_err_data register 1775 * 2) For other pins use appropriate ref_phase register if the phase 1776 * monitor feature is enabled. 1777 */ 1778 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) 1779 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); 1780 else if (zldpll->phase_monitor) 1781 reg = ZL_REG_REF_PHASE(ref_id); 1782 else 1783 return false; 1784 1785 /* Read measured phase offset value */ 1786 rc = zl3073x_read_u48(zldev, reg, &phase_offset); 1787 if (rc) { 1788 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n", 1789 ERR_PTR(rc)); 1790 1791 return false; 1792 } 1793 1794 /* Convert to ps */ 1795 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100); 1796 1797 /* Compare with previous value */ 1798 if (phase_offset != pin->phase_offset) { 1799 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n", 1800 pin->label, pin->phase_offset, phase_offset); 1801 pin->phase_offset = phase_offset; 1802 1803 return true; 1804 } 1805 1806 return false; 1807 } 1808 1809 /** 1810 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change 1811 * @pin: pin to check 1812 * 1813 * Check for the given pin's fractional frequency change. 1814 * 1815 * Return: true on fractional frequency offset change, false otherwise 1816 */ 1817 static bool 1818 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin) 1819 { 1820 struct zl3073x_dpll *zldpll = pin->dpll; 1821 struct zl3073x_dev *zldev = zldpll->dev; 1822 const struct zl3073x_ref *ref; 1823 u8 ref_id; 1824 1825 /* Get reference monitor status */ 1826 ref_id = zl3073x_input_pin_ref_get(pin->id); 1827 ref = zl3073x_ref_state_get(zldev, ref_id); 1828 1829 /* Do not report ffo changes if the reference monitor report errors */ 1830 if (!zl3073x_ref_is_status_ok(ref)) 1831 return false; 1832 1833 /* Compare with previous value */ 1834 if (pin->freq_offset != ref->ffo) { 1835 dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n", 1836 pin->label, pin->freq_offset, ref->ffo); 1837 pin->freq_offset = ref->ffo; 1838 1839 return true; 1840 } 1841 1842 return false; 1843 } 1844 1845 /** 1846 * zl3073x_dpll_changes_check - check for changes and send notifications 1847 * @zldpll: pointer to zl3073x_dpll structure 1848 * 1849 * Checks for changes on given DPLL device and its registered DPLL pins 1850 * and sends notifications about them. 1851 * 1852 * This function is periodically called from @zl3073x_dev_periodic_work. 1853 */ 1854 void 1855 zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll) 1856 { 1857 struct zl3073x_dev *zldev = zldpll->dev; 1858 enum dpll_lock_status lock_status; 1859 struct device *dev = zldev->dev; 1860 struct zl3073x_dpll_pin *pin; 1861 int rc; 1862 1863 zldpll->check_count++; 1864 1865 /* Get current lock status for the DPLL */ 1866 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, 1867 &lock_status, NULL, NULL); 1868 if (rc) { 1869 dev_err(dev, "Failed to get DPLL%u lock status: %pe\n", 1870 zldpll->id, ERR_PTR(rc)); 1871 return; 1872 } 1873 1874 /* If lock status was changed then notify DPLL core */ 1875 if (zldpll->lock_status != lock_status) { 1876 zldpll->lock_status = lock_status; 1877 dpll_device_change_ntf(zldpll->dpll_dev); 1878 } 1879 1880 /* Input pin monitoring does make sense only in automatic 1881 * or forced reference modes. 1882 */ 1883 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO && 1884 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK) 1885 return; 1886 1887 /* Update phase offset latch registers for this DPLL if the phase 1888 * offset monitor feature is enabled. 1889 */ 1890 if (zldpll->phase_monitor) { 1891 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id); 1892 if (rc) { 1893 dev_err(zldev->dev, 1894 "Failed to update phase offsets: %pe\n", 1895 ERR_PTR(rc)); 1896 return; 1897 } 1898 } 1899 1900 list_for_each_entry(pin, &zldpll->pins, list) { 1901 enum dpll_pin_state state; 1902 bool pin_changed = false; 1903 1904 /* Output pins change checks are not necessary because output 1905 * states are constant. 1906 */ 1907 if (!zl3073x_dpll_is_input_pin(pin)) 1908 continue; 1909 1910 rc = zl3073x_dpll_ref_state_get(pin, &state); 1911 if (rc) { 1912 dev_err(dev, 1913 "Failed to get %s on DPLL%u state: %pe\n", 1914 pin->label, zldpll->id, ERR_PTR(rc)); 1915 return; 1916 } 1917 1918 if (state != pin->pin_state) { 1919 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, 1920 pin->pin_state, state); 1921 pin->pin_state = state; 1922 pin_changed = true; 1923 } 1924 1925 /* Check for phase offset and ffo change once per second */ 1926 if (zldpll->check_count % 2 == 0) { 1927 if (zl3073x_dpll_pin_phase_offset_check(pin)) 1928 pin_changed = true; 1929 1930 if (zl3073x_dpll_pin_ffo_check(pin)) 1931 pin_changed = true; 1932 } 1933 1934 if (pin_changed) 1935 dpll_pin_change_ntf(pin->dpll_pin); 1936 } 1937 } 1938 1939 /** 1940 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments 1941 * @zldev: pointer to zl3073x device 1942 * 1943 * Performs initial fine phase adjustments needed per datasheet. 1944 * 1945 * Return: 0 on success, <0 on error 1946 */ 1947 int 1948 zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev) 1949 { 1950 int rc; 1951 1952 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); 1953 if (rc) 1954 return rc; 1955 1956 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); 1957 if (rc) 1958 return rc; 1959 1960 rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff); 1961 if (rc) 1962 return rc; 1963 1964 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); 1965 if (rc) 1966 return rc; 1967 1968 return rc; 1969 } 1970 1971 /** 1972 * zl3073x_dpll_alloc - allocate DPLL device 1973 * @zldev: pointer to zl3073x device 1974 * @ch: DPLL channel number 1975 * 1976 * Allocates DPLL device structure for given DPLL channel. 1977 * 1978 * Return: pointer to DPLL device on success, error pointer on error 1979 */ 1980 struct zl3073x_dpll * 1981 zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch) 1982 { 1983 struct zl3073x_dpll *zldpll; 1984 1985 zldpll = kzalloc(sizeof(*zldpll), GFP_KERNEL); 1986 if (!zldpll) 1987 return ERR_PTR(-ENOMEM); 1988 1989 zldpll->dev = zldev; 1990 zldpll->id = ch; 1991 INIT_LIST_HEAD(&zldpll->pins); 1992 INIT_WORK(&zldpll->change_work, zl3073x_dpll_change_work); 1993 1994 return zldpll; 1995 } 1996 1997 /** 1998 * zl3073x_dpll_free - free DPLL device 1999 * @zldpll: pointer to zl3073x_dpll structure 2000 * 2001 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc. 2002 */ 2003 void 2004 zl3073x_dpll_free(struct zl3073x_dpll *zldpll) 2005 { 2006 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); 2007 2008 kfree(zldpll); 2009 } 2010 2011 /** 2012 * zl3073x_dpll_register - register DPLL device and all its pins 2013 * @zldpll: pointer to zl3073x_dpll structure 2014 * 2015 * Registers given DPLL device and all its pins into DPLL sub-system. 2016 * 2017 * Return: 0 on success, <0 on error 2018 */ 2019 int 2020 zl3073x_dpll_register(struct zl3073x_dpll *zldpll) 2021 { 2022 int rc; 2023 2024 rc = zl3073x_dpll_device_register(zldpll); 2025 if (rc) 2026 return rc; 2027 2028 rc = zl3073x_dpll_pins_register(zldpll); 2029 if (rc) { 2030 zl3073x_dpll_device_unregister(zldpll); 2031 return rc; 2032 } 2033 2034 return 0; 2035 } 2036 2037 /** 2038 * zl3073x_dpll_unregister - unregister DPLL device and its pins 2039 * @zldpll: pointer to zl3073x_dpll structure 2040 * 2041 * Unregisters given DPLL device and all its pins from DPLL sub-system 2042 * previously registered by @zl3073x_dpll_register. 2043 */ 2044 void 2045 zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll) 2046 { 2047 /* Unregister all pins and dpll */ 2048 zl3073x_dpll_pins_unregister(zldpll); 2049 zl3073x_dpll_device_unregister(zldpll); 2050 } 2051