1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bits.h> 4 #include <linux/bitfield.h> 5 #include <linux/bug.h> 6 #include <linux/container_of.h> 7 #include <linux/dev_printk.h> 8 #include <linux/dpll.h> 9 #include <linux/err.h> 10 #include <linux/kthread.h> 11 #include <linux/math64.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/netlink.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/sprintf.h> 18 19 #include "core.h" 20 #include "dpll.h" 21 #include "prop.h" 22 #include "regs.h" 23 24 #define ZL3073X_DPLL_REF_NONE ZL3073X_NUM_REFS 25 #define ZL3073X_DPLL_REF_IS_VALID(_ref) ((_ref) != ZL3073X_DPLL_REF_NONE) 26 27 /** 28 * struct zl3073x_dpll_pin - DPLL pin 29 * @list: this DPLL pin list entry 30 * @dpll: DPLL the pin is registered to 31 * @dpll_pin: pointer to registered dpll_pin 32 * @label: package label 33 * @dir: pin direction 34 * @id: pin id 35 * @prio: pin priority <0, 14> 36 * @selectable: pin is selectable in automatic mode 37 * @pin_state: last saved pin state 38 */ 39 struct zl3073x_dpll_pin { 40 struct list_head list; 41 struct zl3073x_dpll *dpll; 42 struct dpll_pin *dpll_pin; 43 char label[8]; 44 enum dpll_pin_direction dir; 45 u8 id; 46 u8 prio; 47 bool selectable; 48 enum dpll_pin_state pin_state; 49 }; 50 51 /** 52 * zl3073x_dpll_is_input_pin - check if the pin is input one 53 * @pin: pin to check 54 * 55 * Return: true if pin is input, false if pin is output. 56 */ 57 static bool 58 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin) 59 { 60 return pin->dir == DPLL_PIN_DIRECTION_INPUT; 61 } 62 63 /** 64 * zl3073x_dpll_is_p_pin - check if the pin is P-pin 65 * @pin: pin to check 66 * 67 * Return: true if the pin is P-pin, false if it is N-pin 68 */ 69 static bool 70 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin) 71 { 72 return zl3073x_is_p_pin(pin->id); 73 } 74 75 static int 76 zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv, 77 const struct dpll_device *dpll, void *dpll_priv, 78 enum dpll_pin_direction *direction, 79 struct netlink_ext_ack *extack) 80 { 81 struct zl3073x_dpll_pin *pin = pin_priv; 82 83 *direction = pin->dir; 84 85 return 0; 86 } 87 88 /** 89 * zl3073x_dpll_input_ref_frequency_get - get input reference frequency 90 * @zldpll: pointer to zl3073x_dpll 91 * @ref_id: reference id 92 * @frequency: pointer to variable to store frequency 93 * 94 * Reads frequency of given input reference. 95 * 96 * Return: 0 on success, <0 on error 97 */ 98 static int 99 zl3073x_dpll_input_ref_frequency_get(struct zl3073x_dpll *zldpll, u8 ref_id, 100 u32 *frequency) 101 { 102 struct zl3073x_dev *zldev = zldpll->dev; 103 u16 base, mult, num, denom; 104 int rc; 105 106 guard(mutex)(&zldev->multiop_lock); 107 108 /* Read reference configuration */ 109 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 110 ZL_REG_REF_MB_MASK, BIT(ref_id)); 111 if (rc) 112 return rc; 113 114 /* Read registers to compute resulting frequency */ 115 rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_BASE, &base); 116 if (rc) 117 return rc; 118 rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_MULT, &mult); 119 if (rc) 120 return rc; 121 rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_M, &num); 122 if (rc) 123 return rc; 124 rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_N, &denom); 125 if (rc) 126 return rc; 127 128 /* Sanity check that HW has not returned zero denominator */ 129 if (!denom) { 130 dev_err(zldev->dev, 131 "Zero divisor for ref %u frequency got from device\n", 132 ref_id); 133 return -EINVAL; 134 } 135 136 /* Compute the frequency */ 137 *frequency = mul_u64_u32_div(base * mult, num, denom); 138 139 return rc; 140 } 141 142 static int 143 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin, 144 void *pin_priv, 145 const struct dpll_device *dpll, 146 void *dpll_priv, u64 *frequency, 147 struct netlink_ext_ack *extack) 148 { 149 struct zl3073x_dpll *zldpll = dpll_priv; 150 struct zl3073x_dpll_pin *pin = pin_priv; 151 u32 ref_freq; 152 u8 ref; 153 int rc; 154 155 /* Read and return ref frequency */ 156 ref = zl3073x_input_pin_ref_get(pin->id); 157 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, ref, &ref_freq); 158 if (!rc) 159 *frequency = ref_freq; 160 161 return rc; 162 } 163 164 static int 165 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin, 166 void *pin_priv, 167 const struct dpll_device *dpll, 168 void *dpll_priv, u64 frequency, 169 struct netlink_ext_ack *extack) 170 { 171 struct zl3073x_dpll *zldpll = dpll_priv; 172 struct zl3073x_dev *zldev = zldpll->dev; 173 struct zl3073x_dpll_pin *pin = pin_priv; 174 u16 base, mult; 175 u8 ref; 176 int rc; 177 178 /* Get base frequency and multiplier for the requested frequency */ 179 rc = zl3073x_ref_freq_factorize(frequency, &base, &mult); 180 if (rc) 181 return rc; 182 183 guard(mutex)(&zldev->multiop_lock); 184 185 /* Load reference configuration */ 186 ref = zl3073x_input_pin_ref_get(pin->id); 187 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 188 ZL_REG_REF_MB_MASK, BIT(ref)); 189 190 /* Update base frequency, multiplier, numerator & denominator */ 191 rc = zl3073x_write_u16(zldev, ZL_REG_REF_FREQ_BASE, base); 192 if (rc) 193 return rc; 194 rc = zl3073x_write_u16(zldev, ZL_REG_REF_FREQ_MULT, mult); 195 if (rc) 196 return rc; 197 rc = zl3073x_write_u16(zldev, ZL_REG_REF_RATIO_M, 1); 198 if (rc) 199 return rc; 200 rc = zl3073x_write_u16(zldev, ZL_REG_REF_RATIO_N, 1); 201 if (rc) 202 return rc; 203 204 /* Commit reference configuration */ 205 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR, 206 ZL_REG_REF_MB_MASK, BIT(ref)); 207 } 208 209 /** 210 * zl3073x_dpll_selected_ref_get - get currently selected reference 211 * @zldpll: pointer to zl3073x_dpll 212 * @ref: place to store selected reference 213 * 214 * Check for currently selected reference the DPLL should be locked to 215 * and stores its index to given @ref. 216 * 217 * Return: 0 on success, <0 on error 218 */ 219 static int 220 zl3073x_dpll_selected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 221 { 222 struct zl3073x_dev *zldev = zldpll->dev; 223 u8 state, value; 224 int rc; 225 226 switch (zldpll->refsel_mode) { 227 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 228 /* For automatic mode read refsel_status register */ 229 rc = zl3073x_read_u8(zldev, 230 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id), 231 &value); 232 if (rc) 233 return rc; 234 235 /* Extract reference state */ 236 state = FIELD_GET(ZL_DPLL_REFSEL_STATUS_STATE, value); 237 238 /* Return the reference only if the DPLL is locked to it */ 239 if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK) 240 *ref = FIELD_GET(ZL_DPLL_REFSEL_STATUS_REFSEL, value); 241 else 242 *ref = ZL3073X_DPLL_REF_NONE; 243 break; 244 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 245 /* For manual mode return stored value */ 246 *ref = zldpll->forced_ref; 247 break; 248 default: 249 /* For other modes like NCO, freerun... there is no input ref */ 250 *ref = ZL3073X_DPLL_REF_NONE; 251 break; 252 } 253 254 return 0; 255 } 256 257 /** 258 * zl3073x_dpll_selected_ref_set - select reference in manual mode 259 * @zldpll: pointer to zl3073x_dpll 260 * @ref: input reference to be selected 261 * 262 * Selects the given reference for the DPLL channel it should be 263 * locked to. 264 * 265 * Return: 0 on success, <0 on error 266 */ 267 static int 268 zl3073x_dpll_selected_ref_set(struct zl3073x_dpll *zldpll, u8 ref) 269 { 270 struct zl3073x_dev *zldev = zldpll->dev; 271 u8 mode, mode_refsel; 272 int rc; 273 274 mode = zldpll->refsel_mode; 275 276 switch (mode) { 277 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 278 /* Manual mode with ref selected */ 279 if (ref == ZL3073X_DPLL_REF_NONE) { 280 switch (zldpll->lock_status) { 281 case DPLL_LOCK_STATUS_LOCKED_HO_ACQ: 282 case DPLL_LOCK_STATUS_HOLDOVER: 283 /* Switch to forced holdover */ 284 mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 285 break; 286 default: 287 /* Switch to freerun */ 288 mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 289 break; 290 } 291 /* Keep selected reference */ 292 ref = zldpll->forced_ref; 293 } else if (ref == zldpll->forced_ref) { 294 /* No register update - same mode and same ref */ 295 return 0; 296 } 297 break; 298 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 299 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 300 /* Manual mode without no ref */ 301 if (ref == ZL3073X_DPLL_REF_NONE) 302 /* No register update - keep current mode */ 303 return 0; 304 305 /* Switch to reflock mode and update ref selection */ 306 mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 307 break; 308 default: 309 /* For other modes like automatic or NCO ref cannot be selected 310 * manually 311 */ 312 return -EOPNOTSUPP; 313 } 314 315 /* Build mode_refsel value */ 316 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode) | 317 FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 318 319 /* Update dpll_mode_refsel register */ 320 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 321 mode_refsel); 322 if (rc) 323 return rc; 324 325 /* Store new mode and forced reference */ 326 zldpll->refsel_mode = mode; 327 zldpll->forced_ref = ref; 328 329 return rc; 330 } 331 332 /** 333 * zl3073x_dpll_connected_ref_get - get currently connected reference 334 * @zldpll: pointer to zl3073x_dpll 335 * @ref: place to store selected reference 336 * 337 * Looks for currently connected the DPLL is locked to and stores its index 338 * to given @ref. 339 * 340 * Return: 0 on success, <0 on error 341 */ 342 static int 343 zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 344 { 345 struct zl3073x_dev *zldev = zldpll->dev; 346 int rc; 347 348 /* Get currently selected input reference */ 349 rc = zl3073x_dpll_selected_ref_get(zldpll, ref); 350 if (rc) 351 return rc; 352 353 if (ZL3073X_DPLL_REF_IS_VALID(*ref)) { 354 u8 ref_status; 355 356 /* Read the reference monitor status */ 357 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(*ref), 358 &ref_status); 359 if (rc) 360 return rc; 361 362 /* If the monitor indicates an error nothing is connected */ 363 if (ref_status != ZL_REF_MON_STATUS_OK) 364 *ref = ZL3073X_DPLL_REF_NONE; 365 } 366 367 return 0; 368 } 369 370 /** 371 * zl3073x_dpll_ref_prio_get - get priority for given input pin 372 * @pin: pointer to pin 373 * @prio: place to store priority 374 * 375 * Reads current priority for the given input pin and stores the value 376 * to @prio. 377 * 378 * Return: 0 on success, <0 on error 379 */ 380 static int 381 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio) 382 { 383 struct zl3073x_dpll *zldpll = pin->dpll; 384 struct zl3073x_dev *zldev = zldpll->dev; 385 u8 ref, ref_prio; 386 int rc; 387 388 guard(mutex)(&zldev->multiop_lock); 389 390 /* Read DPLL configuration */ 391 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 392 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 393 if (rc) 394 return rc; 395 396 /* Read reference priority - one value for P&N pins (4 bits/pin) */ 397 ref = zl3073x_input_pin_ref_get(pin->id); 398 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), 399 &ref_prio); 400 if (rc) 401 return rc; 402 403 /* Select nibble according pin type */ 404 if (zl3073x_dpll_is_p_pin(pin)) 405 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_P, ref_prio); 406 else 407 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_N, ref_prio); 408 409 return rc; 410 } 411 412 /** 413 * zl3073x_dpll_ref_prio_set - set priority for given input pin 414 * @pin: pointer to pin 415 * @prio: place to store priority 416 * 417 * Sets priority for the given input pin. 418 * 419 * Return: 0 on success, <0 on error 420 */ 421 static int 422 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio) 423 { 424 struct zl3073x_dpll *zldpll = pin->dpll; 425 struct zl3073x_dev *zldev = zldpll->dev; 426 u8 ref, ref_prio; 427 int rc; 428 429 guard(mutex)(&zldev->multiop_lock); 430 431 /* Read DPLL configuration into mailbox */ 432 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 433 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 434 if (rc) 435 return rc; 436 437 /* Read reference priority - one value shared between P&N pins */ 438 ref = zl3073x_input_pin_ref_get(pin->id); 439 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio); 440 if (rc) 441 return rc; 442 443 /* Update nibble according pin type */ 444 if (zl3073x_dpll_is_p_pin(pin)) { 445 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_P; 446 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio); 447 } else { 448 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_N; 449 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio); 450 } 451 452 /* Update reference priority */ 453 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio); 454 if (rc) 455 return rc; 456 457 /* Commit configuration */ 458 return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR, 459 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 460 } 461 462 /** 463 * zl3073x_dpll_ref_state_get - get status for given input pin 464 * @pin: pointer to pin 465 * @state: place to store status 466 * 467 * Checks current status for the given input pin and stores the value 468 * to @state. 469 * 470 * Return: 0 on success, <0 on error 471 */ 472 static int 473 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin, 474 enum dpll_pin_state *state) 475 { 476 struct zl3073x_dpll *zldpll = pin->dpll; 477 struct zl3073x_dev *zldev = zldpll->dev; 478 u8 ref, ref_conn, status; 479 int rc; 480 481 ref = zl3073x_input_pin_ref_get(pin->id); 482 483 /* Get currently connected reference */ 484 rc = zl3073x_dpll_connected_ref_get(zldpll, &ref_conn); 485 if (rc) 486 return rc; 487 488 if (ref == ref_conn) { 489 *state = DPLL_PIN_STATE_CONNECTED; 490 return 0; 491 } 492 493 /* If the DPLL is running in automatic mode and the reference is 494 * selectable and its monitor does not report any error then report 495 * pin as selectable. 496 */ 497 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO && 498 pin->selectable) { 499 /* Read reference monitor status */ 500 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), 501 &status); 502 if (rc) 503 return rc; 504 505 /* If the monitor indicates errors report the reference 506 * as disconnected 507 */ 508 if (status == ZL_REF_MON_STATUS_OK) { 509 *state = DPLL_PIN_STATE_SELECTABLE; 510 return 0; 511 } 512 } 513 514 /* Otherwise report the pin as disconnected */ 515 *state = DPLL_PIN_STATE_DISCONNECTED; 516 517 return 0; 518 } 519 520 static int 521 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 522 void *pin_priv, 523 const struct dpll_device *dpll, 524 void *dpll_priv, 525 enum dpll_pin_state *state, 526 struct netlink_ext_ack *extack) 527 { 528 struct zl3073x_dpll_pin *pin = pin_priv; 529 530 return zl3073x_dpll_ref_state_get(pin, state); 531 } 532 533 static int 534 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin, 535 void *pin_priv, 536 const struct dpll_device *dpll, 537 void *dpll_priv, 538 enum dpll_pin_state state, 539 struct netlink_ext_ack *extack) 540 { 541 struct zl3073x_dpll *zldpll = dpll_priv; 542 struct zl3073x_dpll_pin *pin = pin_priv; 543 u8 new_ref; 544 int rc; 545 546 switch (zldpll->refsel_mode) { 547 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 548 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 549 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 550 if (state == DPLL_PIN_STATE_CONNECTED) { 551 /* Choose the pin as new selected reference */ 552 new_ref = zl3073x_input_pin_ref_get(pin->id); 553 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 554 /* No reference */ 555 new_ref = ZL3073X_DPLL_REF_NONE; 556 } else { 557 NL_SET_ERR_MSG_MOD(extack, 558 "Invalid pin state for manual mode"); 559 return -EINVAL; 560 } 561 562 rc = zl3073x_dpll_selected_ref_set(zldpll, new_ref); 563 break; 564 565 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 566 if (state == DPLL_PIN_STATE_SELECTABLE) { 567 if (pin->selectable) 568 return 0; /* Pin is already selectable */ 569 570 /* Restore pin priority in HW */ 571 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 572 if (rc) 573 return rc; 574 575 /* Mark pin as selectable */ 576 pin->selectable = true; 577 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 578 if (!pin->selectable) 579 return 0; /* Pin is already disconnected */ 580 581 /* Set pin priority to none in HW */ 582 rc = zl3073x_dpll_ref_prio_set(pin, 583 ZL_DPLL_REF_PRIO_NONE); 584 if (rc) 585 return rc; 586 587 /* Mark pin as non-selectable */ 588 pin->selectable = false; 589 } else { 590 NL_SET_ERR_MSG(extack, 591 "Invalid pin state for automatic mode"); 592 return -EINVAL; 593 } 594 break; 595 596 default: 597 /* In other modes we cannot change input reference */ 598 NL_SET_ERR_MSG(extack, 599 "Pin state cannot be changed in current mode"); 600 rc = -EOPNOTSUPP; 601 break; 602 } 603 604 return rc; 605 } 606 607 static int 608 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv, 609 const struct dpll_device *dpll, void *dpll_priv, 610 u32 *prio, struct netlink_ext_ack *extack) 611 { 612 struct zl3073x_dpll_pin *pin = pin_priv; 613 614 *prio = pin->prio; 615 616 return 0; 617 } 618 619 static int 620 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv, 621 const struct dpll_device *dpll, void *dpll_priv, 622 u32 prio, struct netlink_ext_ack *extack) 623 { 624 struct zl3073x_dpll_pin *pin = pin_priv; 625 int rc; 626 627 if (prio > ZL_DPLL_REF_PRIO_MAX) 628 return -EINVAL; 629 630 /* If the pin is selectable then update HW registers */ 631 if (pin->selectable) { 632 rc = zl3073x_dpll_ref_prio_set(pin, prio); 633 if (rc) 634 return rc; 635 } 636 637 /* Save priority */ 638 pin->prio = prio; 639 640 return 0; 641 } 642 643 static int 644 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin, 645 void *pin_priv, 646 const struct dpll_device *dpll, 647 void *dpll_priv, u64 *frequency, 648 struct netlink_ext_ack *extack) 649 { 650 struct zl3073x_dpll *zldpll = dpll_priv; 651 struct zl3073x_dev *zldev = zldpll->dev; 652 struct zl3073x_dpll_pin *pin = pin_priv; 653 struct device *dev = zldev->dev; 654 u8 out, signal_format, synth; 655 u32 output_div, synth_freq; 656 int rc; 657 658 out = zl3073x_output_pin_out_get(pin->id); 659 synth = zl3073x_out_synth_get(zldev, out); 660 synth_freq = zl3073x_synth_freq_get(zldev, synth); 661 662 guard(mutex)(&zldev->multiop_lock); 663 664 /* Read output configuration into mailbox */ 665 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 666 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 667 if (rc) 668 return rc; 669 670 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div); 671 if (rc) 672 return rc; 673 674 /* Check output divisor for zero */ 675 if (!output_div) { 676 dev_err(dev, "Zero divisor for output %u got from device\n", 677 out); 678 return -EINVAL; 679 } 680 681 /* Read used signal format for the given output */ 682 signal_format = zl3073x_out_signal_format_get(zldev, out); 683 684 switch (signal_format) { 685 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 686 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 687 /* In case of divided format we have to distiguish between 688 * given output pin type. 689 */ 690 if (zl3073x_dpll_is_p_pin(pin)) { 691 /* For P-pin the resulting frequency is computed as 692 * simple division of synth frequency and output 693 * divisor. 694 */ 695 *frequency = synth_freq / output_div; 696 } else { 697 /* For N-pin we have to divide additionally by 698 * divisor stored in esync_period output mailbox 699 * register that is used as N-pin divisor for these 700 * modes. 701 */ 702 u32 ndiv; 703 704 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, 705 &ndiv); 706 if (rc) 707 return rc; 708 709 /* Check N-pin divisor for zero */ 710 if (!ndiv) { 711 dev_err(dev, 712 "Zero N-pin divisor for output %u got from device\n", 713 out); 714 return -EINVAL; 715 } 716 717 /* Compute final divisor for N-pin */ 718 *frequency = synth_freq / output_div / ndiv; 719 } 720 break; 721 default: 722 /* In other modes the resulting frequency is computed as 723 * division of synth frequency and output divisor. 724 */ 725 *frequency = synth_freq / output_div; 726 break; 727 } 728 729 return rc; 730 } 731 732 static int 733 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, 734 void *pin_priv, 735 const struct dpll_device *dpll, 736 void *dpll_priv, u64 frequency, 737 struct netlink_ext_ack *extack) 738 { 739 struct zl3073x_dpll *zldpll = dpll_priv; 740 struct zl3073x_dev *zldev = zldpll->dev; 741 struct zl3073x_dpll_pin *pin = pin_priv; 742 struct device *dev = zldev->dev; 743 u32 output_n_freq, output_p_freq; 744 u8 out, signal_format, synth; 745 u32 cur_div, new_div, ndiv; 746 u32 synth_freq; 747 int rc; 748 749 out = zl3073x_output_pin_out_get(pin->id); 750 synth = zl3073x_out_synth_get(zldev, out); 751 synth_freq = zl3073x_synth_freq_get(zldev, synth); 752 new_div = synth_freq / (u32)frequency; 753 754 /* Get used signal format for the given output */ 755 signal_format = zl3073x_out_signal_format_get(zldev, out); 756 757 guard(mutex)(&zldev->multiop_lock); 758 759 /* Load output configuration */ 760 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 761 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 762 if (rc) 763 return rc; 764 765 /* Check signal format */ 766 if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV && 767 signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) { 768 /* For non N-divided signal formats the frequency is computed 769 * as division of synth frequency and output divisor. 770 */ 771 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_DIV, new_div); 772 if (rc) 773 return rc; 774 775 /* For 50/50 duty cycle the divisor is equal to width */ 776 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_WIDTH, new_div); 777 if (rc) 778 return rc; 779 780 /* Commit output configuration */ 781 return zl3073x_mb_op(zldev, 782 ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 783 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 784 } 785 786 /* For N-divided signal format get current divisor */ 787 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &cur_div); 788 if (rc) 789 return rc; 790 791 /* Check output divisor for zero */ 792 if (!cur_div) { 793 dev_err(dev, "Zero divisor for output %u got from device\n", 794 out); 795 return -EINVAL; 796 } 797 798 /* Get N-pin divisor (shares the same register with esync */ 799 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, &ndiv); 800 if (rc) 801 return rc; 802 803 /* Check N-pin divisor for zero */ 804 if (!ndiv) { 805 dev_err(dev, 806 "Zero N-pin divisor for output %u got from device\n", 807 out); 808 return -EINVAL; 809 } 810 811 /* Compute current output frequency for P-pin */ 812 output_p_freq = synth_freq / cur_div; 813 814 /* Compute current N-pin frequency */ 815 output_n_freq = output_p_freq / ndiv; 816 817 if (zl3073x_dpll_is_p_pin(pin)) { 818 /* We are going to change output frequency for P-pin but 819 * if the requested frequency is less than current N-pin 820 * frequency then indicate a failure as we are not able 821 * to compute N-pin divisor to keep its frequency unchanged. 822 */ 823 if (frequency <= output_n_freq) 824 return -EINVAL; 825 826 /* Update the output divisor */ 827 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_DIV, new_div); 828 if (rc) 829 return rc; 830 831 /* For 50/50 duty cycle the divisor is equal to width */ 832 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_WIDTH, new_div); 833 if (rc) 834 return rc; 835 836 /* Compute new divisor for N-pin */ 837 ndiv = (u32)frequency / output_n_freq; 838 } else { 839 /* We are going to change frequency of N-pin but if 840 * the requested freq is greater or equal than freq of P-pin 841 * in the output pair we cannot compute divisor for the N-pin. 842 * In this case indicate a failure. 843 */ 844 if (output_p_freq <= frequency) 845 return -EINVAL; 846 847 /* Compute new divisor for N-pin */ 848 ndiv = output_p_freq / (u32)frequency; 849 } 850 851 /* Update divisor for the N-pin */ 852 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, ndiv); 853 if (rc) 854 return rc; 855 856 /* For 50/50 duty cycle the divisor is equal to width */ 857 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, ndiv); 858 if (rc) 859 return rc; 860 861 /* Commit output configuration */ 862 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 863 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 864 } 865 866 static int 867 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 868 void *pin_priv, 869 const struct dpll_device *dpll, 870 void *dpll_priv, 871 enum dpll_pin_state *state, 872 struct netlink_ext_ack *extack) 873 { 874 /* If the output pin is registered then it is always connected */ 875 *state = DPLL_PIN_STATE_CONNECTED; 876 877 return 0; 878 } 879 880 static int 881 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, 882 enum dpll_lock_status *status, 883 enum dpll_lock_status_error *status_error, 884 struct netlink_ext_ack *extack) 885 { 886 struct zl3073x_dpll *zldpll = dpll_priv; 887 struct zl3073x_dev *zldev = zldpll->dev; 888 u8 mon_status, state; 889 int rc; 890 891 switch (zldpll->refsel_mode) { 892 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 893 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 894 /* In FREERUN and NCO modes the DPLL is always unlocked */ 895 *status = DPLL_LOCK_STATUS_UNLOCKED; 896 897 return 0; 898 default: 899 break; 900 } 901 902 /* Read DPLL monitor status */ 903 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id), 904 &mon_status); 905 if (rc) 906 return rc; 907 state = FIELD_GET(ZL_DPLL_MON_STATUS_STATE, mon_status); 908 909 switch (state) { 910 case ZL_DPLL_MON_STATUS_STATE_LOCK: 911 if (FIELD_GET(ZL_DPLL_MON_STATUS_HO_READY, mon_status)) 912 *status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 913 else 914 *status = DPLL_LOCK_STATUS_LOCKED; 915 break; 916 case ZL_DPLL_MON_STATUS_STATE_HOLDOVER: 917 case ZL_DPLL_MON_STATUS_STATE_ACQUIRING: 918 *status = DPLL_LOCK_STATUS_HOLDOVER; 919 break; 920 default: 921 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n", 922 mon_status); 923 *status = DPLL_LOCK_STATUS_UNLOCKED; 924 break; 925 } 926 927 return 0; 928 } 929 930 static int 931 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, 932 enum dpll_mode *mode, struct netlink_ext_ack *extack) 933 { 934 struct zl3073x_dpll *zldpll = dpll_priv; 935 936 switch (zldpll->refsel_mode) { 937 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 938 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 939 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 940 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 941 /* Use MANUAL for device FREERUN, HOLDOVER, NCO and 942 * REFLOCK modes 943 */ 944 *mode = DPLL_MODE_MANUAL; 945 break; 946 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 947 /* Use AUTO for device AUTO mode */ 948 *mode = DPLL_MODE_AUTOMATIC; 949 break; 950 default: 951 return -EINVAL; 952 } 953 954 return 0; 955 } 956 957 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = { 958 .direction_get = zl3073x_dpll_pin_direction_get, 959 .frequency_get = zl3073x_dpll_input_pin_frequency_get, 960 .frequency_set = zl3073x_dpll_input_pin_frequency_set, 961 .prio_get = zl3073x_dpll_input_pin_prio_get, 962 .prio_set = zl3073x_dpll_input_pin_prio_set, 963 .state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get, 964 .state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set, 965 }; 966 967 static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = { 968 .direction_get = zl3073x_dpll_pin_direction_get, 969 .frequency_get = zl3073x_dpll_output_pin_frequency_get, 970 .frequency_set = zl3073x_dpll_output_pin_frequency_set, 971 .state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get, 972 }; 973 974 static const struct dpll_device_ops zl3073x_dpll_device_ops = { 975 .lock_status_get = zl3073x_dpll_lock_status_get, 976 .mode_get = zl3073x_dpll_mode_get, 977 }; 978 979 /** 980 * zl3073x_dpll_pin_alloc - allocate DPLL pin 981 * @zldpll: pointer to zl3073x_dpll 982 * @dir: pin direction 983 * @id: pin id 984 * 985 * Allocates and initializes zl3073x_dpll_pin structure for given 986 * pin id and direction. 987 * 988 * Return: pointer to allocated structure on success, error pointer on error 989 */ 990 static struct zl3073x_dpll_pin * 991 zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir, 992 u8 id) 993 { 994 struct zl3073x_dpll_pin *pin; 995 996 pin = kzalloc(sizeof(*pin), GFP_KERNEL); 997 if (!pin) 998 return ERR_PTR(-ENOMEM); 999 1000 pin->dpll = zldpll; 1001 pin->dir = dir; 1002 pin->id = id; 1003 1004 return pin; 1005 } 1006 1007 /** 1008 * zl3073x_dpll_pin_free - deallocate DPLL pin 1009 * @pin: pin to free 1010 * 1011 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc. 1012 */ 1013 static void 1014 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin) 1015 { 1016 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); 1017 1018 kfree(pin); 1019 } 1020 1021 /** 1022 * zl3073x_dpll_pin_register - register DPLL pin 1023 * @pin: pointer to DPLL pin 1024 * @index: absolute pin index for registration 1025 * 1026 * Registers given DPLL pin into DPLL sub-system. 1027 * 1028 * Return: 0 on success, <0 on error 1029 */ 1030 static int 1031 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index) 1032 { 1033 struct zl3073x_dpll *zldpll = pin->dpll; 1034 struct zl3073x_pin_props *props; 1035 const struct dpll_pin_ops *ops; 1036 int rc; 1037 1038 /* Get pin properties */ 1039 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); 1040 if (IS_ERR(props)) 1041 return PTR_ERR(props); 1042 1043 /* Save package label */ 1044 strscpy(pin->label, props->package_label); 1045 1046 if (zl3073x_dpll_is_input_pin(pin)) { 1047 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); 1048 if (rc) 1049 goto err_prio_get; 1050 1051 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) { 1052 /* Clamp prio to max value & mark pin non-selectable */ 1053 pin->prio = ZL_DPLL_REF_PRIO_MAX; 1054 pin->selectable = false; 1055 } else { 1056 /* Mark pin as selectable */ 1057 pin->selectable = true; 1058 } 1059 } 1060 1061 /* Create or get existing DPLL pin */ 1062 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, 1063 &props->dpll_props); 1064 if (IS_ERR(pin->dpll_pin)) { 1065 rc = PTR_ERR(pin->dpll_pin); 1066 goto err_pin_get; 1067 } 1068 1069 if (zl3073x_dpll_is_input_pin(pin)) 1070 ops = &zl3073x_dpll_input_pin_ops; 1071 else 1072 ops = &zl3073x_dpll_output_pin_ops; 1073 1074 /* Register the pin */ 1075 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1076 if (rc) 1077 goto err_register; 1078 1079 /* Free pin properties */ 1080 zl3073x_pin_props_put(props); 1081 1082 return 0; 1083 1084 err_register: 1085 dpll_pin_put(pin->dpll_pin); 1086 err_prio_get: 1087 pin->dpll_pin = NULL; 1088 err_pin_get: 1089 zl3073x_pin_props_put(props); 1090 1091 return rc; 1092 } 1093 1094 /** 1095 * zl3073x_dpll_pin_unregister - unregister DPLL pin 1096 * @pin: pointer to DPLL pin 1097 * 1098 * Unregisters pin previously registered by @zl3073x_dpll_pin_register. 1099 */ 1100 static void 1101 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin) 1102 { 1103 struct zl3073x_dpll *zldpll = pin->dpll; 1104 const struct dpll_pin_ops *ops; 1105 1106 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); 1107 1108 if (zl3073x_dpll_is_input_pin(pin)) 1109 ops = &zl3073x_dpll_input_pin_ops; 1110 else 1111 ops = &zl3073x_dpll_output_pin_ops; 1112 1113 /* Unregister the pin */ 1114 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1115 1116 dpll_pin_put(pin->dpll_pin); 1117 pin->dpll_pin = NULL; 1118 } 1119 1120 /** 1121 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins 1122 * @zldpll: pointer to zl3073x_dpll structure 1123 * 1124 * Enumerates all DPLL pins registered to given DPLL device and 1125 * unregisters them. 1126 */ 1127 static void 1128 zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll) 1129 { 1130 struct zl3073x_dpll_pin *pin, *next; 1131 1132 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { 1133 zl3073x_dpll_pin_unregister(pin); 1134 list_del(&pin->list); 1135 zl3073x_dpll_pin_free(pin); 1136 } 1137 } 1138 1139 /** 1140 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable 1141 * @zldpll: pointer to zl3073x_dpll structure 1142 * @dir: pin direction 1143 * @index: pin index 1144 * 1145 * Checks if the given pin can be registered to given DPLL. For both 1146 * directions the pin can be registered if it is enabled. In case of 1147 * differential signal type only P-pin is reported as registrable. 1148 * And additionally for the output pin, the pin can be registered only 1149 * if it is connected to synthesizer that is driven by given DPLL. 1150 * 1151 * Return: true if the pin is registrable, false if not 1152 */ 1153 static bool 1154 zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll, 1155 enum dpll_pin_direction dir, u8 index) 1156 { 1157 struct zl3073x_dev *zldev = zldpll->dev; 1158 bool is_diff, is_enabled; 1159 const char *name; 1160 1161 if (dir == DPLL_PIN_DIRECTION_INPUT) { 1162 u8 ref = zl3073x_input_pin_ref_get(index); 1163 1164 name = "REF"; 1165 1166 /* Skip the pin if the DPLL is running in NCO mode */ 1167 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO) 1168 return false; 1169 1170 is_diff = zl3073x_ref_is_diff(zldev, ref); 1171 is_enabled = zl3073x_ref_is_enabled(zldev, ref); 1172 } else { 1173 /* Output P&N pair shares single HW output */ 1174 u8 out = zl3073x_output_pin_out_get(index); 1175 1176 name = "OUT"; 1177 1178 /* Skip the pin if it is connected to different DPLL channel */ 1179 if (zl3073x_out_dpll_get(zldev, out) != zldpll->id) { 1180 dev_dbg(zldev->dev, 1181 "%s%u is driven by different DPLL\n", name, 1182 out); 1183 1184 return false; 1185 } 1186 1187 is_diff = zl3073x_out_is_diff(zldev, out); 1188 is_enabled = zl3073x_out_is_enabled(zldev, out); 1189 } 1190 1191 /* Skip N-pin if the corresponding input/output is differential */ 1192 if (is_diff && zl3073x_is_n_pin(index)) { 1193 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", 1194 name, index / 2); 1195 1196 return false; 1197 } 1198 1199 /* Skip the pin if it is disabled */ 1200 if (!is_enabled) { 1201 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, 1202 zl3073x_is_p_pin(index) ? 'P' : 'N'); 1203 1204 return false; 1205 } 1206 1207 return true; 1208 } 1209 1210 /** 1211 * zl3073x_dpll_pins_register - register all registerable DPLL pins 1212 * @zldpll: pointer to zl3073x_dpll structure 1213 * 1214 * Enumerates all possible input/output pins and registers all of them 1215 * that are registrable. 1216 * 1217 * Return: 0 on success, <0 on error 1218 */ 1219 static int 1220 zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll) 1221 { 1222 struct zl3073x_dpll_pin *pin; 1223 enum dpll_pin_direction dir; 1224 u8 id, index; 1225 int rc; 1226 1227 /* Process input pins */ 1228 for (index = 0; index < ZL3073X_NUM_PINS; index++) { 1229 /* First input pins and then output pins */ 1230 if (index < ZL3073X_NUM_INPUT_PINS) { 1231 id = index; 1232 dir = DPLL_PIN_DIRECTION_INPUT; 1233 } else { 1234 id = index - ZL3073X_NUM_INPUT_PINS; 1235 dir = DPLL_PIN_DIRECTION_OUTPUT; 1236 } 1237 1238 /* Check if the pin registrable to this DPLL */ 1239 if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id)) 1240 continue; 1241 1242 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id); 1243 if (IS_ERR(pin)) { 1244 rc = PTR_ERR(pin); 1245 goto error; 1246 } 1247 1248 rc = zl3073x_dpll_pin_register(pin, index); 1249 if (rc) 1250 goto error; 1251 1252 list_add(&pin->list, &zldpll->pins); 1253 } 1254 1255 return 0; 1256 1257 error: 1258 zl3073x_dpll_pins_unregister(zldpll); 1259 1260 return rc; 1261 } 1262 1263 /** 1264 * zl3073x_dpll_device_register - register DPLL device 1265 * @zldpll: pointer to zl3073x_dpll structure 1266 * 1267 * Registers given DPLL device into DPLL sub-system. 1268 * 1269 * Return: 0 on success, <0 on error 1270 */ 1271 static int 1272 zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll) 1273 { 1274 struct zl3073x_dev *zldev = zldpll->dev; 1275 u8 dpll_mode_refsel; 1276 int rc; 1277 1278 /* Read DPLL mode and forcibly selected reference */ 1279 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1280 &dpll_mode_refsel); 1281 if (rc) 1282 return rc; 1283 1284 /* Extract mode and selected input reference */ 1285 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE, 1286 dpll_mode_refsel); 1287 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF, 1288 dpll_mode_refsel); 1289 1290 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, 1291 THIS_MODULE); 1292 if (IS_ERR(zldpll->dpll_dev)) { 1293 rc = PTR_ERR(zldpll->dpll_dev); 1294 zldpll->dpll_dev = NULL; 1295 1296 return rc; 1297 } 1298 1299 rc = dpll_device_register(zldpll->dpll_dev, 1300 zl3073x_prop_dpll_type_get(zldev, zldpll->id), 1301 &zl3073x_dpll_device_ops, zldpll); 1302 if (rc) { 1303 dpll_device_put(zldpll->dpll_dev); 1304 zldpll->dpll_dev = NULL; 1305 } 1306 1307 return rc; 1308 } 1309 1310 /** 1311 * zl3073x_dpll_device_unregister - unregister DPLL device 1312 * @zldpll: pointer to zl3073x_dpll structure 1313 * 1314 * Unregisters given DPLL device from DPLL sub-system previously registered 1315 * by @zl3073x_dpll_device_register. 1316 */ 1317 static void 1318 zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll) 1319 { 1320 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n"); 1321 1322 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, 1323 zldpll); 1324 dpll_device_put(zldpll->dpll_dev); 1325 zldpll->dpll_dev = NULL; 1326 } 1327 1328 /** 1329 * zl3073x_dpll_changes_check - check for changes and send notifications 1330 * @zldpll: pointer to zl3073x_dpll structure 1331 * 1332 * Checks for changes on given DPLL device and its registered DPLL pins 1333 * and sends notifications about them. 1334 * 1335 * This function is periodically called from @zl3073x_dev_periodic_work. 1336 */ 1337 void 1338 zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll) 1339 { 1340 struct zl3073x_dev *zldev = zldpll->dev; 1341 enum dpll_lock_status lock_status; 1342 struct device *dev = zldev->dev; 1343 struct zl3073x_dpll_pin *pin; 1344 int rc; 1345 1346 /* Get current lock status for the DPLL */ 1347 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, 1348 &lock_status, NULL, NULL); 1349 if (rc) { 1350 dev_err(dev, "Failed to get DPLL%u lock status: %pe\n", 1351 zldpll->id, ERR_PTR(rc)); 1352 return; 1353 } 1354 1355 /* If lock status was changed then notify DPLL core */ 1356 if (zldpll->lock_status != lock_status) { 1357 zldpll->lock_status = lock_status; 1358 dpll_device_change_ntf(zldpll->dpll_dev); 1359 } 1360 1361 /* Input pin monitoring does make sense only in automatic 1362 * or forced reference modes. 1363 */ 1364 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO && 1365 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK) 1366 return; 1367 1368 list_for_each_entry(pin, &zldpll->pins, list) { 1369 enum dpll_pin_state state; 1370 1371 /* Output pins change checks are not necessary because output 1372 * states are constant. 1373 */ 1374 if (!zl3073x_dpll_is_input_pin(pin)) 1375 continue; 1376 1377 rc = zl3073x_dpll_ref_state_get(pin, &state); 1378 if (rc) { 1379 dev_err(dev, 1380 "Failed to get %s on DPLL%u state: %pe\n", 1381 pin->label, zldpll->id, ERR_PTR(rc)); 1382 return; 1383 } 1384 1385 if (state != pin->pin_state) { 1386 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, 1387 pin->pin_state, state); 1388 pin->pin_state = state; 1389 dpll_pin_change_ntf(pin->dpll_pin); 1390 } 1391 } 1392 } 1393 1394 /** 1395 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments 1396 * @zldev: pointer to zl3073x device 1397 * 1398 * Performs initial fine phase adjustments needed per datasheet. 1399 * 1400 * Return: 0 on success, <0 on error 1401 */ 1402 int 1403 zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev) 1404 { 1405 int rc; 1406 1407 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); 1408 if (rc) 1409 return rc; 1410 1411 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); 1412 if (rc) 1413 return rc; 1414 1415 rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff); 1416 if (rc) 1417 return rc; 1418 1419 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); 1420 if (rc) 1421 return rc; 1422 1423 return rc; 1424 } 1425 1426 /** 1427 * zl3073x_dpll_alloc - allocate DPLL device 1428 * @zldev: pointer to zl3073x device 1429 * @ch: DPLL channel number 1430 * 1431 * Allocates DPLL device structure for given DPLL channel. 1432 * 1433 * Return: pointer to DPLL device on success, error pointer on error 1434 */ 1435 struct zl3073x_dpll * 1436 zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch) 1437 { 1438 struct zl3073x_dpll *zldpll; 1439 1440 zldpll = kzalloc(sizeof(*zldpll), GFP_KERNEL); 1441 if (!zldpll) 1442 return ERR_PTR(-ENOMEM); 1443 1444 zldpll->dev = zldev; 1445 zldpll->id = ch; 1446 INIT_LIST_HEAD(&zldpll->pins); 1447 1448 return zldpll; 1449 } 1450 1451 /** 1452 * zl3073x_dpll_free - free DPLL device 1453 * @zldpll: pointer to zl3073x_dpll structure 1454 * 1455 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc. 1456 */ 1457 void 1458 zl3073x_dpll_free(struct zl3073x_dpll *zldpll) 1459 { 1460 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); 1461 1462 kfree(zldpll); 1463 } 1464 1465 /** 1466 * zl3073x_dpll_register - register DPLL device and all its pins 1467 * @zldpll: pointer to zl3073x_dpll structure 1468 * 1469 * Registers given DPLL device and all its pins into DPLL sub-system. 1470 * 1471 * Return: 0 on success, <0 on error 1472 */ 1473 int 1474 zl3073x_dpll_register(struct zl3073x_dpll *zldpll) 1475 { 1476 int rc; 1477 1478 rc = zl3073x_dpll_device_register(zldpll); 1479 if (rc) 1480 return rc; 1481 1482 rc = zl3073x_dpll_pins_register(zldpll); 1483 if (rc) { 1484 zl3073x_dpll_device_unregister(zldpll); 1485 return rc; 1486 } 1487 1488 return 0; 1489 } 1490 1491 /** 1492 * zl3073x_dpll_unregister - unregister DPLL device and its pins 1493 * @zldpll: pointer to zl3073x_dpll structure 1494 * 1495 * Unregisters given DPLL device and all its pins from DPLL sub-system 1496 * previously registered by @zl3073x_dpll_register. 1497 */ 1498 void 1499 zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll) 1500 { 1501 /* Unregister all pins and dpll */ 1502 zl3073x_dpll_pins_unregister(zldpll); 1503 zl3073x_dpll_device_unregister(zldpll); 1504 } 1505