1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bits.h> 4 #include <linux/bitfield.h> 5 #include <linux/bug.h> 6 #include <linux/container_of.h> 7 #include <linux/dev_printk.h> 8 #include <linux/dpll.h> 9 #include <linux/err.h> 10 #include <linux/kthread.h> 11 #include <linux/math64.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/netlink.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/sprintf.h> 18 19 #include "core.h" 20 #include "dpll.h" 21 #include "prop.h" 22 #include "regs.h" 23 24 #define ZL3073X_DPLL_REF_NONE ZL3073X_NUM_REFS 25 #define ZL3073X_DPLL_REF_IS_VALID(_ref) ((_ref) != ZL3073X_DPLL_REF_NONE) 26 27 /** 28 * struct zl3073x_dpll_pin - DPLL pin 29 * @list: this DPLL pin list entry 30 * @dpll: DPLL the pin is registered to 31 * @dpll_pin: pointer to registered dpll_pin 32 * @label: package label 33 * @dir: pin direction 34 * @id: pin id 35 * @prio: pin priority <0, 14> 36 * @selectable: pin is selectable in automatic mode 37 * @esync_control: embedded sync is controllable 38 * @pin_state: last saved pin state 39 * @phase_offset: last saved pin phase offset 40 * @freq_offset: last saved fractional frequency offset 41 */ 42 struct zl3073x_dpll_pin { 43 struct list_head list; 44 struct zl3073x_dpll *dpll; 45 struct dpll_pin *dpll_pin; 46 char label[8]; 47 enum dpll_pin_direction dir; 48 u8 id; 49 u8 prio; 50 bool selectable; 51 bool esync_control; 52 enum dpll_pin_state pin_state; 53 s64 phase_offset; 54 s64 freq_offset; 55 }; 56 57 /* 58 * Supported esync ranges for input and for output per output pair type 59 */ 60 static const struct dpll_pin_frequency esync_freq_ranges[] = { 61 DPLL_PIN_FREQUENCY_RANGE(0, 1), 62 }; 63 64 /** 65 * zl3073x_dpll_is_input_pin - check if the pin is input one 66 * @pin: pin to check 67 * 68 * Return: true if pin is input, false if pin is output. 69 */ 70 static bool 71 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin) 72 { 73 return pin->dir == DPLL_PIN_DIRECTION_INPUT; 74 } 75 76 /** 77 * zl3073x_dpll_is_p_pin - check if the pin is P-pin 78 * @pin: pin to check 79 * 80 * Return: true if the pin is P-pin, false if it is N-pin 81 */ 82 static bool 83 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin) 84 { 85 return zl3073x_is_p_pin(pin->id); 86 } 87 88 static int 89 zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv, 90 const struct dpll_device *dpll, void *dpll_priv, 91 enum dpll_pin_direction *direction, 92 struct netlink_ext_ack *extack) 93 { 94 struct zl3073x_dpll_pin *pin = pin_priv; 95 96 *direction = pin->dir; 97 98 return 0; 99 } 100 101 /** 102 * zl3073x_dpll_input_ref_frequency_get - get input reference frequency 103 * @zldpll: pointer to zl3073x_dpll 104 * @ref_id: reference id 105 * @frequency: pointer to variable to store frequency 106 * 107 * Reads frequency of given input reference. 108 * 109 * Return: 0 on success, <0 on error 110 */ 111 static int 112 zl3073x_dpll_input_ref_frequency_get(struct zl3073x_dpll *zldpll, u8 ref_id, 113 u32 *frequency) 114 { 115 struct zl3073x_dev *zldev = zldpll->dev; 116 u16 base, mult, num, denom; 117 int rc; 118 119 guard(mutex)(&zldev->multiop_lock); 120 121 /* Read reference configuration */ 122 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 123 ZL_REG_REF_MB_MASK, BIT(ref_id)); 124 if (rc) 125 return rc; 126 127 /* Read registers to compute resulting frequency */ 128 rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_BASE, &base); 129 if (rc) 130 return rc; 131 rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_MULT, &mult); 132 if (rc) 133 return rc; 134 rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_M, &num); 135 if (rc) 136 return rc; 137 rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_N, &denom); 138 if (rc) 139 return rc; 140 141 /* Sanity check that HW has not returned zero denominator */ 142 if (!denom) { 143 dev_err(zldev->dev, 144 "Zero divisor for ref %u frequency got from device\n", 145 ref_id); 146 return -EINVAL; 147 } 148 149 /* Compute the frequency */ 150 *frequency = mul_u64_u32_div(base * mult, num, denom); 151 152 return rc; 153 } 154 155 static int 156 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, 157 void *pin_priv, 158 const struct dpll_device *dpll, 159 void *dpll_priv, 160 struct dpll_pin_esync *esync, 161 struct netlink_ext_ack *extack) 162 { 163 struct zl3073x_dpll *zldpll = dpll_priv; 164 struct zl3073x_dev *zldev = zldpll->dev; 165 struct zl3073x_dpll_pin *pin = pin_priv; 166 u8 ref, ref_sync_ctrl, sync_mode; 167 u32 esync_div, ref_freq; 168 int rc; 169 170 /* Get reference frequency */ 171 ref = zl3073x_input_pin_ref_get(pin->id); 172 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, pin->id, &ref_freq); 173 if (rc) 174 return rc; 175 176 guard(mutex)(&zldev->multiop_lock); 177 178 /* Read reference configuration into mailbox */ 179 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 180 ZL_REG_REF_MB_MASK, BIT(ref)); 181 if (rc) 182 return rc; 183 184 /* Get ref sync mode */ 185 rc = zl3073x_read_u8(zldev, ZL_REG_REF_SYNC_CTRL, &ref_sync_ctrl); 186 if (rc) 187 return rc; 188 189 /* Get esync divisor */ 190 rc = zl3073x_read_u32(zldev, ZL_REG_REF_ESYNC_DIV, &esync_div); 191 if (rc) 192 return rc; 193 194 sync_mode = FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref_sync_ctrl); 195 196 switch (sync_mode) { 197 case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: 198 esync->freq = (esync_div == ZL_REF_ESYNC_DIV_1HZ) ? 1 : 0; 199 esync->pulse = 25; 200 break; 201 default: 202 esync->freq = 0; 203 esync->pulse = 0; 204 break; 205 } 206 207 /* If the pin supports esync control expose its range but only 208 * if the current reference frequency is > 1 Hz. 209 */ 210 if (pin->esync_control && ref_freq > 1) { 211 esync->range = esync_freq_ranges; 212 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 213 } else { 214 esync->range = NULL; 215 esync->range_num = 0; 216 } 217 218 return rc; 219 } 220 221 static int 222 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin, 223 void *pin_priv, 224 const struct dpll_device *dpll, 225 void *dpll_priv, u64 freq, 226 struct netlink_ext_ack *extack) 227 { 228 struct zl3073x_dpll *zldpll = dpll_priv; 229 struct zl3073x_dev *zldev = zldpll->dev; 230 struct zl3073x_dpll_pin *pin = pin_priv; 231 u8 ref, ref_sync_ctrl, sync_mode; 232 int rc; 233 234 guard(mutex)(&zldev->multiop_lock); 235 236 /* Read reference configuration into mailbox */ 237 ref = zl3073x_input_pin_ref_get(pin->id); 238 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 239 ZL_REG_REF_MB_MASK, BIT(ref)); 240 if (rc) 241 return rc; 242 243 /* Get ref sync mode */ 244 rc = zl3073x_read_u8(zldev, ZL_REG_REF_SYNC_CTRL, &ref_sync_ctrl); 245 if (rc) 246 return rc; 247 248 /* Use freq == 0 to disable esync */ 249 if (!freq) 250 sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF; 251 else 252 sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75; 253 254 ref_sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE; 255 ref_sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode); 256 257 /* Update ref sync control register */ 258 rc = zl3073x_write_u8(zldev, ZL_REG_REF_SYNC_CTRL, ref_sync_ctrl); 259 if (rc) 260 return rc; 261 262 if (freq) { 263 /* 1 Hz is only supported frequnecy currently */ 264 rc = zl3073x_write_u32(zldev, ZL_REG_REF_ESYNC_DIV, 265 ZL_REF_ESYNC_DIV_1HZ); 266 if (rc) 267 return rc; 268 } 269 270 /* Commit reference configuration */ 271 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR, 272 ZL_REG_REF_MB_MASK, BIT(ref)); 273 } 274 275 static int 276 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv, 277 const struct dpll_device *dpll, void *dpll_priv, 278 s64 *ffo, struct netlink_ext_ack *extack) 279 { 280 struct zl3073x_dpll_pin *pin = pin_priv; 281 282 *ffo = pin->freq_offset; 283 284 return 0; 285 } 286 287 static int 288 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin, 289 void *pin_priv, 290 const struct dpll_device *dpll, 291 void *dpll_priv, u64 *frequency, 292 struct netlink_ext_ack *extack) 293 { 294 struct zl3073x_dpll *zldpll = dpll_priv; 295 struct zl3073x_dpll_pin *pin = pin_priv; 296 u32 ref_freq; 297 u8 ref; 298 int rc; 299 300 /* Read and return ref frequency */ 301 ref = zl3073x_input_pin_ref_get(pin->id); 302 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, ref, &ref_freq); 303 if (!rc) 304 *frequency = ref_freq; 305 306 return rc; 307 } 308 309 static int 310 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin, 311 void *pin_priv, 312 const struct dpll_device *dpll, 313 void *dpll_priv, u64 frequency, 314 struct netlink_ext_ack *extack) 315 { 316 struct zl3073x_dpll *zldpll = dpll_priv; 317 struct zl3073x_dev *zldev = zldpll->dev; 318 struct zl3073x_dpll_pin *pin = pin_priv; 319 u16 base, mult; 320 u8 ref; 321 int rc; 322 323 /* Get base frequency and multiplier for the requested frequency */ 324 rc = zl3073x_ref_freq_factorize(frequency, &base, &mult); 325 if (rc) 326 return rc; 327 328 guard(mutex)(&zldev->multiop_lock); 329 330 /* Load reference configuration */ 331 ref = zl3073x_input_pin_ref_get(pin->id); 332 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 333 ZL_REG_REF_MB_MASK, BIT(ref)); 334 335 /* Update base frequency, multiplier, numerator & denominator */ 336 rc = zl3073x_write_u16(zldev, ZL_REG_REF_FREQ_BASE, base); 337 if (rc) 338 return rc; 339 rc = zl3073x_write_u16(zldev, ZL_REG_REF_FREQ_MULT, mult); 340 if (rc) 341 return rc; 342 rc = zl3073x_write_u16(zldev, ZL_REG_REF_RATIO_M, 1); 343 if (rc) 344 return rc; 345 rc = zl3073x_write_u16(zldev, ZL_REG_REF_RATIO_N, 1); 346 if (rc) 347 return rc; 348 349 /* Commit reference configuration */ 350 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR, 351 ZL_REG_REF_MB_MASK, BIT(ref)); 352 } 353 354 /** 355 * zl3073x_dpll_selected_ref_get - get currently selected reference 356 * @zldpll: pointer to zl3073x_dpll 357 * @ref: place to store selected reference 358 * 359 * Check for currently selected reference the DPLL should be locked to 360 * and stores its index to given @ref. 361 * 362 * Return: 0 on success, <0 on error 363 */ 364 static int 365 zl3073x_dpll_selected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 366 { 367 struct zl3073x_dev *zldev = zldpll->dev; 368 u8 state, value; 369 int rc; 370 371 switch (zldpll->refsel_mode) { 372 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 373 /* For automatic mode read refsel_status register */ 374 rc = zl3073x_read_u8(zldev, 375 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id), 376 &value); 377 if (rc) 378 return rc; 379 380 /* Extract reference state */ 381 state = FIELD_GET(ZL_DPLL_REFSEL_STATUS_STATE, value); 382 383 /* Return the reference only if the DPLL is locked to it */ 384 if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK) 385 *ref = FIELD_GET(ZL_DPLL_REFSEL_STATUS_REFSEL, value); 386 else 387 *ref = ZL3073X_DPLL_REF_NONE; 388 break; 389 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 390 /* For manual mode return stored value */ 391 *ref = zldpll->forced_ref; 392 break; 393 default: 394 /* For other modes like NCO, freerun... there is no input ref */ 395 *ref = ZL3073X_DPLL_REF_NONE; 396 break; 397 } 398 399 return 0; 400 } 401 402 /** 403 * zl3073x_dpll_selected_ref_set - select reference in manual mode 404 * @zldpll: pointer to zl3073x_dpll 405 * @ref: input reference to be selected 406 * 407 * Selects the given reference for the DPLL channel it should be 408 * locked to. 409 * 410 * Return: 0 on success, <0 on error 411 */ 412 static int 413 zl3073x_dpll_selected_ref_set(struct zl3073x_dpll *zldpll, u8 ref) 414 { 415 struct zl3073x_dev *zldev = zldpll->dev; 416 u8 mode, mode_refsel; 417 int rc; 418 419 mode = zldpll->refsel_mode; 420 421 switch (mode) { 422 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 423 /* Manual mode with ref selected */ 424 if (ref == ZL3073X_DPLL_REF_NONE) { 425 switch (zldpll->lock_status) { 426 case DPLL_LOCK_STATUS_LOCKED_HO_ACQ: 427 case DPLL_LOCK_STATUS_HOLDOVER: 428 /* Switch to forced holdover */ 429 mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 430 break; 431 default: 432 /* Switch to freerun */ 433 mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 434 break; 435 } 436 /* Keep selected reference */ 437 ref = zldpll->forced_ref; 438 } else if (ref == zldpll->forced_ref) { 439 /* No register update - same mode and same ref */ 440 return 0; 441 } 442 break; 443 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 444 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 445 /* Manual mode without no ref */ 446 if (ref == ZL3073X_DPLL_REF_NONE) 447 /* No register update - keep current mode */ 448 return 0; 449 450 /* Switch to reflock mode and update ref selection */ 451 mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 452 break; 453 default: 454 /* For other modes like automatic or NCO ref cannot be selected 455 * manually 456 */ 457 return -EOPNOTSUPP; 458 } 459 460 /* Build mode_refsel value */ 461 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode) | 462 FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 463 464 /* Update dpll_mode_refsel register */ 465 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 466 mode_refsel); 467 if (rc) 468 return rc; 469 470 /* Store new mode and forced reference */ 471 zldpll->refsel_mode = mode; 472 zldpll->forced_ref = ref; 473 474 return rc; 475 } 476 477 /** 478 * zl3073x_dpll_connected_ref_get - get currently connected reference 479 * @zldpll: pointer to zl3073x_dpll 480 * @ref: place to store selected reference 481 * 482 * Looks for currently connected the DPLL is locked to and stores its index 483 * to given @ref. 484 * 485 * Return: 0 on success, <0 on error 486 */ 487 static int 488 zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 489 { 490 struct zl3073x_dev *zldev = zldpll->dev; 491 int rc; 492 493 /* Get currently selected input reference */ 494 rc = zl3073x_dpll_selected_ref_get(zldpll, ref); 495 if (rc) 496 return rc; 497 498 if (ZL3073X_DPLL_REF_IS_VALID(*ref)) { 499 u8 ref_status; 500 501 /* Read the reference monitor status */ 502 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(*ref), 503 &ref_status); 504 if (rc) 505 return rc; 506 507 /* If the monitor indicates an error nothing is connected */ 508 if (ref_status != ZL_REF_MON_STATUS_OK) 509 *ref = ZL3073X_DPLL_REF_NONE; 510 } 511 512 return 0; 513 } 514 515 static int 516 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin, 517 void *pin_priv, 518 const struct dpll_device *dpll, 519 void *dpll_priv, s64 *phase_offset, 520 struct netlink_ext_ack *extack) 521 { 522 struct zl3073x_dpll *zldpll = dpll_priv; 523 struct zl3073x_dev *zldev = zldpll->dev; 524 struct zl3073x_dpll_pin *pin = pin_priv; 525 u8 conn_ref, ref, ref_status; 526 s64 ref_phase; 527 int rc; 528 529 /* Get currently connected reference */ 530 rc = zl3073x_dpll_connected_ref_get(zldpll, &conn_ref); 531 if (rc) 532 return rc; 533 534 /* Report phase offset only for currently connected pin if the phase 535 * monitor feature is disabled. 536 */ 537 ref = zl3073x_input_pin_ref_get(pin->id); 538 if (!zldpll->phase_monitor && ref != conn_ref) { 539 *phase_offset = 0; 540 541 return 0; 542 } 543 544 /* Get this pin monitor status */ 545 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), &ref_status); 546 if (rc) 547 return rc; 548 549 /* Report phase offset only if the input pin signal is present */ 550 if (ref_status != ZL_REF_MON_STATUS_OK) { 551 *phase_offset = 0; 552 553 return 0; 554 } 555 556 ref_phase = pin->phase_offset; 557 558 /* The DPLL being locked to a higher freq than the current ref 559 * the phase offset is modded to the period of the signal 560 * the dpll is locked to. 561 */ 562 if (ZL3073X_DPLL_REF_IS_VALID(conn_ref) && conn_ref != ref) { 563 u32 conn_freq, ref_freq; 564 565 /* Get frequency of connected ref */ 566 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, conn_ref, 567 &conn_freq); 568 if (rc) 569 return rc; 570 571 /* Get frequency of given ref */ 572 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, ref, 573 &ref_freq); 574 if (rc) 575 return rc; 576 577 if (conn_freq > ref_freq) { 578 s64 conn_period, div_factor; 579 580 conn_period = div_s64(PSEC_PER_SEC, conn_freq); 581 div_factor = div64_s64(ref_phase, conn_period); 582 ref_phase -= conn_period * div_factor; 583 } 584 } 585 586 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER; 587 588 return rc; 589 } 590 591 static int 592 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 593 void *pin_priv, 594 const struct dpll_device *dpll, 595 void *dpll_priv, 596 s32 *phase_adjust, 597 struct netlink_ext_ack *extack) 598 { 599 struct zl3073x_dpll *zldpll = dpll_priv; 600 struct zl3073x_dev *zldev = zldpll->dev; 601 struct zl3073x_dpll_pin *pin = pin_priv; 602 s64 phase_comp; 603 u8 ref; 604 int rc; 605 606 guard(mutex)(&zldev->multiop_lock); 607 608 /* Read reference configuration */ 609 ref = zl3073x_input_pin_ref_get(pin->id); 610 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 611 ZL_REG_REF_MB_MASK, BIT(ref)); 612 if (rc) 613 return rc; 614 615 /* Read current phase offset compensation */ 616 rc = zl3073x_read_u48(zldev, ZL_REG_REF_PHASE_OFFSET_COMP, &phase_comp); 617 if (rc) 618 return rc; 619 620 /* Perform sign extension for 48bit signed value */ 621 phase_comp = sign_extend64(phase_comp, 47); 622 623 /* Reverse two's complement negation applied during set and convert 624 * to 32bit signed int 625 */ 626 *phase_adjust = (s32)-phase_comp; 627 628 return rc; 629 } 630 631 static int 632 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 633 void *pin_priv, 634 const struct dpll_device *dpll, 635 void *dpll_priv, 636 s32 phase_adjust, 637 struct netlink_ext_ack *extack) 638 { 639 struct zl3073x_dpll *zldpll = dpll_priv; 640 struct zl3073x_dev *zldev = zldpll->dev; 641 struct zl3073x_dpll_pin *pin = pin_priv; 642 s64 phase_comp; 643 u8 ref; 644 int rc; 645 646 /* The value in the register is stored as two's complement negation 647 * of requested value. 648 */ 649 phase_comp = -phase_adjust; 650 651 guard(mutex)(&zldev->multiop_lock); 652 653 /* Read reference configuration */ 654 ref = zl3073x_input_pin_ref_get(pin->id); 655 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 656 ZL_REG_REF_MB_MASK, BIT(ref)); 657 if (rc) 658 return rc; 659 660 /* Write the requested value into the compensation register */ 661 rc = zl3073x_write_u48(zldev, ZL_REG_REF_PHASE_OFFSET_COMP, phase_comp); 662 if (rc) 663 return rc; 664 665 /* Commit reference configuration */ 666 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR, 667 ZL_REG_REF_MB_MASK, BIT(ref)); 668 } 669 670 /** 671 * zl3073x_dpll_ref_prio_get - get priority for given input pin 672 * @pin: pointer to pin 673 * @prio: place to store priority 674 * 675 * Reads current priority for the given input pin and stores the value 676 * to @prio. 677 * 678 * Return: 0 on success, <0 on error 679 */ 680 static int 681 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio) 682 { 683 struct zl3073x_dpll *zldpll = pin->dpll; 684 struct zl3073x_dev *zldev = zldpll->dev; 685 u8 ref, ref_prio; 686 int rc; 687 688 guard(mutex)(&zldev->multiop_lock); 689 690 /* Read DPLL configuration */ 691 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 692 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 693 if (rc) 694 return rc; 695 696 /* Read reference priority - one value for P&N pins (4 bits/pin) */ 697 ref = zl3073x_input_pin_ref_get(pin->id); 698 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), 699 &ref_prio); 700 if (rc) 701 return rc; 702 703 /* Select nibble according pin type */ 704 if (zl3073x_dpll_is_p_pin(pin)) 705 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_P, ref_prio); 706 else 707 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_N, ref_prio); 708 709 return rc; 710 } 711 712 /** 713 * zl3073x_dpll_ref_prio_set - set priority for given input pin 714 * @pin: pointer to pin 715 * @prio: place to store priority 716 * 717 * Sets priority for the given input pin. 718 * 719 * Return: 0 on success, <0 on error 720 */ 721 static int 722 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio) 723 { 724 struct zl3073x_dpll *zldpll = pin->dpll; 725 struct zl3073x_dev *zldev = zldpll->dev; 726 u8 ref, ref_prio; 727 int rc; 728 729 guard(mutex)(&zldev->multiop_lock); 730 731 /* Read DPLL configuration into mailbox */ 732 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 733 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 734 if (rc) 735 return rc; 736 737 /* Read reference priority - one value shared between P&N pins */ 738 ref = zl3073x_input_pin_ref_get(pin->id); 739 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio); 740 if (rc) 741 return rc; 742 743 /* Update nibble according pin type */ 744 if (zl3073x_dpll_is_p_pin(pin)) { 745 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_P; 746 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio); 747 } else { 748 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_N; 749 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio); 750 } 751 752 /* Update reference priority */ 753 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio); 754 if (rc) 755 return rc; 756 757 /* Commit configuration */ 758 return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR, 759 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 760 } 761 762 /** 763 * zl3073x_dpll_ref_state_get - get status for given input pin 764 * @pin: pointer to pin 765 * @state: place to store status 766 * 767 * Checks current status for the given input pin and stores the value 768 * to @state. 769 * 770 * Return: 0 on success, <0 on error 771 */ 772 static int 773 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin, 774 enum dpll_pin_state *state) 775 { 776 struct zl3073x_dpll *zldpll = pin->dpll; 777 struct zl3073x_dev *zldev = zldpll->dev; 778 u8 ref, ref_conn, status; 779 int rc; 780 781 ref = zl3073x_input_pin_ref_get(pin->id); 782 783 /* Get currently connected reference */ 784 rc = zl3073x_dpll_connected_ref_get(zldpll, &ref_conn); 785 if (rc) 786 return rc; 787 788 if (ref == ref_conn) { 789 *state = DPLL_PIN_STATE_CONNECTED; 790 return 0; 791 } 792 793 /* If the DPLL is running in automatic mode and the reference is 794 * selectable and its monitor does not report any error then report 795 * pin as selectable. 796 */ 797 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO && 798 pin->selectable) { 799 /* Read reference monitor status */ 800 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), 801 &status); 802 if (rc) 803 return rc; 804 805 /* If the monitor indicates errors report the reference 806 * as disconnected 807 */ 808 if (status == ZL_REF_MON_STATUS_OK) { 809 *state = DPLL_PIN_STATE_SELECTABLE; 810 return 0; 811 } 812 } 813 814 /* Otherwise report the pin as disconnected */ 815 *state = DPLL_PIN_STATE_DISCONNECTED; 816 817 return 0; 818 } 819 820 static int 821 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 822 void *pin_priv, 823 const struct dpll_device *dpll, 824 void *dpll_priv, 825 enum dpll_pin_state *state, 826 struct netlink_ext_ack *extack) 827 { 828 struct zl3073x_dpll_pin *pin = pin_priv; 829 830 return zl3073x_dpll_ref_state_get(pin, state); 831 } 832 833 static int 834 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin, 835 void *pin_priv, 836 const struct dpll_device *dpll, 837 void *dpll_priv, 838 enum dpll_pin_state state, 839 struct netlink_ext_ack *extack) 840 { 841 struct zl3073x_dpll *zldpll = dpll_priv; 842 struct zl3073x_dpll_pin *pin = pin_priv; 843 u8 new_ref; 844 int rc; 845 846 switch (zldpll->refsel_mode) { 847 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 848 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 849 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 850 if (state == DPLL_PIN_STATE_CONNECTED) { 851 /* Choose the pin as new selected reference */ 852 new_ref = zl3073x_input_pin_ref_get(pin->id); 853 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 854 /* No reference */ 855 new_ref = ZL3073X_DPLL_REF_NONE; 856 } else { 857 NL_SET_ERR_MSG_MOD(extack, 858 "Invalid pin state for manual mode"); 859 return -EINVAL; 860 } 861 862 rc = zl3073x_dpll_selected_ref_set(zldpll, new_ref); 863 break; 864 865 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 866 if (state == DPLL_PIN_STATE_SELECTABLE) { 867 if (pin->selectable) 868 return 0; /* Pin is already selectable */ 869 870 /* Restore pin priority in HW */ 871 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 872 if (rc) 873 return rc; 874 875 /* Mark pin as selectable */ 876 pin->selectable = true; 877 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 878 if (!pin->selectable) 879 return 0; /* Pin is already disconnected */ 880 881 /* Set pin priority to none in HW */ 882 rc = zl3073x_dpll_ref_prio_set(pin, 883 ZL_DPLL_REF_PRIO_NONE); 884 if (rc) 885 return rc; 886 887 /* Mark pin as non-selectable */ 888 pin->selectable = false; 889 } else { 890 NL_SET_ERR_MSG(extack, 891 "Invalid pin state for automatic mode"); 892 return -EINVAL; 893 } 894 break; 895 896 default: 897 /* In other modes we cannot change input reference */ 898 NL_SET_ERR_MSG(extack, 899 "Pin state cannot be changed in current mode"); 900 rc = -EOPNOTSUPP; 901 break; 902 } 903 904 return rc; 905 } 906 907 static int 908 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv, 909 const struct dpll_device *dpll, void *dpll_priv, 910 u32 *prio, struct netlink_ext_ack *extack) 911 { 912 struct zl3073x_dpll_pin *pin = pin_priv; 913 914 *prio = pin->prio; 915 916 return 0; 917 } 918 919 static int 920 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv, 921 const struct dpll_device *dpll, void *dpll_priv, 922 u32 prio, struct netlink_ext_ack *extack) 923 { 924 struct zl3073x_dpll_pin *pin = pin_priv; 925 int rc; 926 927 if (prio > ZL_DPLL_REF_PRIO_MAX) 928 return -EINVAL; 929 930 /* If the pin is selectable then update HW registers */ 931 if (pin->selectable) { 932 rc = zl3073x_dpll_ref_prio_set(pin, prio); 933 if (rc) 934 return rc; 935 } 936 937 /* Save priority */ 938 pin->prio = prio; 939 940 return 0; 941 } 942 943 static int 944 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, 945 void *pin_priv, 946 const struct dpll_device *dpll, 947 void *dpll_priv, 948 struct dpll_pin_esync *esync, 949 struct netlink_ext_ack *extack) 950 { 951 struct zl3073x_dpll *zldpll = dpll_priv; 952 struct zl3073x_dev *zldev = zldpll->dev; 953 struct zl3073x_dpll_pin *pin = pin_priv; 954 struct device *dev = zldev->dev; 955 u32 esync_period, esync_width; 956 u8 clock_type, synth; 957 u8 out, output_mode; 958 u32 output_div; 959 u32 synth_freq; 960 int rc; 961 962 out = zl3073x_output_pin_out_get(pin->id); 963 964 /* If N-division is enabled, esync is not supported. The register used 965 * for N-division is also used for the esync divider so both cannot 966 * be used. 967 */ 968 switch (zl3073x_out_signal_format_get(zldev, out)) { 969 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 970 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 971 return -EOPNOTSUPP; 972 default: 973 break; 974 } 975 976 guard(mutex)(&zldev->multiop_lock); 977 978 /* Read output configuration into mailbox */ 979 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 980 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 981 if (rc) 982 return rc; 983 984 /* Read output mode */ 985 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode); 986 if (rc) 987 return rc; 988 989 /* Read output divisor */ 990 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div); 991 if (rc) 992 return rc; 993 994 /* Check output divisor for zero */ 995 if (!output_div) { 996 dev_err(dev, "Zero divisor for OUTPUT%u got from device\n", 997 out); 998 return -EINVAL; 999 } 1000 1001 /* Get synth attached to output pin */ 1002 synth = zl3073x_out_synth_get(zldev, out); 1003 1004 /* Get synth frequency */ 1005 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1006 1007 clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, output_mode); 1008 if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { 1009 /* No need to read esync data if it is not enabled */ 1010 esync->freq = 0; 1011 esync->pulse = 0; 1012 1013 goto finish; 1014 } 1015 1016 /* Read esync period */ 1017 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, &esync_period); 1018 if (rc) 1019 return rc; 1020 1021 /* Check esync divisor for zero */ 1022 if (!esync_period) { 1023 dev_err(dev, "Zero esync divisor for OUTPUT%u got from device\n", 1024 out); 1025 return -EINVAL; 1026 } 1027 1028 /* Get esync pulse width in units of half synth cycles */ 1029 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, &esync_width); 1030 if (rc) 1031 return rc; 1032 1033 /* Compute esync frequency */ 1034 esync->freq = synth_freq / output_div / esync_period; 1035 1036 /* By comparing the esync_pulse_width to the half of the pulse width 1037 * the esync pulse percentage can be determined. 1038 * Note that half pulse width is in units of half synth cycles, which 1039 * is why it reduces down to be output_div. 1040 */ 1041 esync->pulse = (50 * esync_width) / output_div; 1042 1043 finish: 1044 /* Set supported esync ranges if the pin supports esync control and 1045 * if the output frequency is > 1 Hz. 1046 */ 1047 if (pin->esync_control && (synth_freq / output_div) > 1) { 1048 esync->range = esync_freq_ranges; 1049 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 1050 } else { 1051 esync->range = NULL; 1052 esync->range_num = 0; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static int 1059 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin, 1060 void *pin_priv, 1061 const struct dpll_device *dpll, 1062 void *dpll_priv, u64 freq, 1063 struct netlink_ext_ack *extack) 1064 { 1065 u32 esync_period, esync_width, output_div; 1066 struct zl3073x_dpll *zldpll = dpll_priv; 1067 struct zl3073x_dev *zldev = zldpll->dev; 1068 struct zl3073x_dpll_pin *pin = pin_priv; 1069 u8 clock_type, out, output_mode, synth; 1070 u32 synth_freq; 1071 int rc; 1072 1073 out = zl3073x_output_pin_out_get(pin->id); 1074 1075 /* If N-division is enabled, esync is not supported. The register used 1076 * for N-division is also used for the esync divider so both cannot 1077 * be used. 1078 */ 1079 switch (zl3073x_out_signal_format_get(zldev, out)) { 1080 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 1081 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 1082 return -EOPNOTSUPP; 1083 default: 1084 break; 1085 } 1086 1087 guard(mutex)(&zldev->multiop_lock); 1088 1089 /* Read output configuration into mailbox */ 1090 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1091 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1092 if (rc) 1093 return rc; 1094 1095 /* Read output mode */ 1096 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode); 1097 if (rc) 1098 return rc; 1099 1100 /* Select clock type */ 1101 if (freq) 1102 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC; 1103 else 1104 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL; 1105 1106 /* Update clock type in output mode */ 1107 output_mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE; 1108 output_mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type); 1109 rc = zl3073x_write_u8(zldev, ZL_REG_OUTPUT_MODE, output_mode); 1110 if (rc) 1111 return rc; 1112 1113 /* If esync is being disabled just write mailbox and finish */ 1114 if (!freq) 1115 goto write_mailbox; 1116 1117 /* Get synth attached to output pin */ 1118 synth = zl3073x_out_synth_get(zldev, out); 1119 1120 /* Get synth frequency */ 1121 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1122 1123 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div); 1124 if (rc) 1125 return rc; 1126 1127 /* Check output divisor for zero */ 1128 if (!output_div) { 1129 dev_err(zldev->dev, 1130 "Zero divisor for OUTPUT%u got from device\n", out); 1131 return -EINVAL; 1132 } 1133 1134 /* Compute and update esync period */ 1135 esync_period = synth_freq / (u32)freq / output_div; 1136 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, esync_period); 1137 if (rc) 1138 return rc; 1139 1140 /* Half of the period in units of 1/2 synth cycle can be represented by 1141 * the output_div. To get the supported esync pulse width of 25% of the 1142 * period the output_div can just be divided by 2. Note that this 1143 * assumes that output_div is even, otherwise some resolution will be 1144 * lost. 1145 */ 1146 esync_width = output_div / 2; 1147 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, esync_width); 1148 if (rc) 1149 return rc; 1150 1151 write_mailbox: 1152 /* Commit output configuration */ 1153 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 1154 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1155 } 1156 1157 static int 1158 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin, 1159 void *pin_priv, 1160 const struct dpll_device *dpll, 1161 void *dpll_priv, u64 *frequency, 1162 struct netlink_ext_ack *extack) 1163 { 1164 struct zl3073x_dpll *zldpll = dpll_priv; 1165 struct zl3073x_dev *zldev = zldpll->dev; 1166 struct zl3073x_dpll_pin *pin = pin_priv; 1167 struct device *dev = zldev->dev; 1168 u8 out, signal_format, synth; 1169 u32 output_div, synth_freq; 1170 int rc; 1171 1172 out = zl3073x_output_pin_out_get(pin->id); 1173 synth = zl3073x_out_synth_get(zldev, out); 1174 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1175 1176 guard(mutex)(&zldev->multiop_lock); 1177 1178 /* Read output configuration into mailbox */ 1179 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1180 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1181 if (rc) 1182 return rc; 1183 1184 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div); 1185 if (rc) 1186 return rc; 1187 1188 /* Check output divisor for zero */ 1189 if (!output_div) { 1190 dev_err(dev, "Zero divisor for output %u got from device\n", 1191 out); 1192 return -EINVAL; 1193 } 1194 1195 /* Read used signal format for the given output */ 1196 signal_format = zl3073x_out_signal_format_get(zldev, out); 1197 1198 switch (signal_format) { 1199 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 1200 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 1201 /* In case of divided format we have to distiguish between 1202 * given output pin type. 1203 */ 1204 if (zl3073x_dpll_is_p_pin(pin)) { 1205 /* For P-pin the resulting frequency is computed as 1206 * simple division of synth frequency and output 1207 * divisor. 1208 */ 1209 *frequency = synth_freq / output_div; 1210 } else { 1211 /* For N-pin we have to divide additionally by 1212 * divisor stored in esync_period output mailbox 1213 * register that is used as N-pin divisor for these 1214 * modes. 1215 */ 1216 u32 ndiv; 1217 1218 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, 1219 &ndiv); 1220 if (rc) 1221 return rc; 1222 1223 /* Check N-pin divisor for zero */ 1224 if (!ndiv) { 1225 dev_err(dev, 1226 "Zero N-pin divisor for output %u got from device\n", 1227 out); 1228 return -EINVAL; 1229 } 1230 1231 /* Compute final divisor for N-pin */ 1232 *frequency = synth_freq / output_div / ndiv; 1233 } 1234 break; 1235 default: 1236 /* In other modes the resulting frequency is computed as 1237 * division of synth frequency and output divisor. 1238 */ 1239 *frequency = synth_freq / output_div; 1240 break; 1241 } 1242 1243 return rc; 1244 } 1245 1246 static int 1247 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, 1248 void *pin_priv, 1249 const struct dpll_device *dpll, 1250 void *dpll_priv, u64 frequency, 1251 struct netlink_ext_ack *extack) 1252 { 1253 struct zl3073x_dpll *zldpll = dpll_priv; 1254 struct zl3073x_dev *zldev = zldpll->dev; 1255 struct zl3073x_dpll_pin *pin = pin_priv; 1256 struct device *dev = zldev->dev; 1257 u32 output_n_freq, output_p_freq; 1258 u8 out, signal_format, synth; 1259 u32 cur_div, new_div, ndiv; 1260 u32 synth_freq; 1261 int rc; 1262 1263 out = zl3073x_output_pin_out_get(pin->id); 1264 synth = zl3073x_out_synth_get(zldev, out); 1265 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1266 new_div = synth_freq / (u32)frequency; 1267 1268 /* Get used signal format for the given output */ 1269 signal_format = zl3073x_out_signal_format_get(zldev, out); 1270 1271 guard(mutex)(&zldev->multiop_lock); 1272 1273 /* Load output configuration */ 1274 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1275 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1276 if (rc) 1277 return rc; 1278 1279 /* Check signal format */ 1280 if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV && 1281 signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) { 1282 /* For non N-divided signal formats the frequency is computed 1283 * as division of synth frequency and output divisor. 1284 */ 1285 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_DIV, new_div); 1286 if (rc) 1287 return rc; 1288 1289 /* For 50/50 duty cycle the divisor is equal to width */ 1290 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_WIDTH, new_div); 1291 if (rc) 1292 return rc; 1293 1294 /* Commit output configuration */ 1295 return zl3073x_mb_op(zldev, 1296 ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 1297 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1298 } 1299 1300 /* For N-divided signal format get current divisor */ 1301 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &cur_div); 1302 if (rc) 1303 return rc; 1304 1305 /* Check output divisor for zero */ 1306 if (!cur_div) { 1307 dev_err(dev, "Zero divisor for output %u got from device\n", 1308 out); 1309 return -EINVAL; 1310 } 1311 1312 /* Get N-pin divisor (shares the same register with esync */ 1313 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, &ndiv); 1314 if (rc) 1315 return rc; 1316 1317 /* Check N-pin divisor for zero */ 1318 if (!ndiv) { 1319 dev_err(dev, 1320 "Zero N-pin divisor for output %u got from device\n", 1321 out); 1322 return -EINVAL; 1323 } 1324 1325 /* Compute current output frequency for P-pin */ 1326 output_p_freq = synth_freq / cur_div; 1327 1328 /* Compute current N-pin frequency */ 1329 output_n_freq = output_p_freq / ndiv; 1330 1331 if (zl3073x_dpll_is_p_pin(pin)) { 1332 /* We are going to change output frequency for P-pin but 1333 * if the requested frequency is less than current N-pin 1334 * frequency then indicate a failure as we are not able 1335 * to compute N-pin divisor to keep its frequency unchanged. 1336 */ 1337 if (frequency <= output_n_freq) 1338 return -EINVAL; 1339 1340 /* Update the output divisor */ 1341 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_DIV, new_div); 1342 if (rc) 1343 return rc; 1344 1345 /* For 50/50 duty cycle the divisor is equal to width */ 1346 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_WIDTH, new_div); 1347 if (rc) 1348 return rc; 1349 1350 /* Compute new divisor for N-pin */ 1351 ndiv = (u32)frequency / output_n_freq; 1352 } else { 1353 /* We are going to change frequency of N-pin but if 1354 * the requested freq is greater or equal than freq of P-pin 1355 * in the output pair we cannot compute divisor for the N-pin. 1356 * In this case indicate a failure. 1357 */ 1358 if (output_p_freq <= frequency) 1359 return -EINVAL; 1360 1361 /* Compute new divisor for N-pin */ 1362 ndiv = output_p_freq / (u32)frequency; 1363 } 1364 1365 /* Update divisor for the N-pin */ 1366 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, ndiv); 1367 if (rc) 1368 return rc; 1369 1370 /* For 50/50 duty cycle the divisor is equal to width */ 1371 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, ndiv); 1372 if (rc) 1373 return rc; 1374 1375 /* Commit output configuration */ 1376 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 1377 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1378 } 1379 1380 static int 1381 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 1382 void *pin_priv, 1383 const struct dpll_device *dpll, 1384 void *dpll_priv, 1385 s32 *phase_adjust, 1386 struct netlink_ext_ack *extack) 1387 { 1388 struct zl3073x_dpll *zldpll = dpll_priv; 1389 struct zl3073x_dev *zldev = zldpll->dev; 1390 struct zl3073x_dpll_pin *pin = pin_priv; 1391 u32 synth_freq; 1392 s32 phase_comp; 1393 u8 out, synth; 1394 int rc; 1395 1396 out = zl3073x_output_pin_out_get(pin->id); 1397 synth = zl3073x_out_synth_get(zldev, out); 1398 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1399 1400 /* Check synth freq for zero */ 1401 if (!synth_freq) { 1402 dev_err(zldev->dev, "Got zero synth frequency for output %u\n", 1403 out); 1404 return -EINVAL; 1405 } 1406 1407 guard(mutex)(&zldev->multiop_lock); 1408 1409 /* Read output configuration */ 1410 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1411 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1412 if (rc) 1413 return rc; 1414 1415 /* Read current output phase compensation */ 1416 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, &phase_comp); 1417 if (rc) 1418 return rc; 1419 1420 /* Value in register is expressed in half synth clock cycles */ 1421 phase_comp *= (int)div_u64(PSEC_PER_SEC, 2 * synth_freq); 1422 1423 /* Reverse two's complement negation applied during 'set' */ 1424 *phase_adjust = -phase_comp; 1425 1426 return rc; 1427 } 1428 1429 static int 1430 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 1431 void *pin_priv, 1432 const struct dpll_device *dpll, 1433 void *dpll_priv, 1434 s32 phase_adjust, 1435 struct netlink_ext_ack *extack) 1436 { 1437 struct zl3073x_dpll *zldpll = dpll_priv; 1438 struct zl3073x_dev *zldev = zldpll->dev; 1439 struct zl3073x_dpll_pin *pin = pin_priv; 1440 int half_synth_cycle; 1441 u32 synth_freq; 1442 u8 out, synth; 1443 int rc; 1444 1445 /* Get attached synth */ 1446 out = zl3073x_output_pin_out_get(pin->id); 1447 synth = zl3073x_out_synth_get(zldev, out); 1448 1449 /* Get synth's frequency */ 1450 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1451 1452 /* Value in register is expressed in half synth clock cycles so 1453 * the given phase adjustment a multiple of half synth clock. 1454 */ 1455 half_synth_cycle = (int)div_u64(PSEC_PER_SEC, 2 * synth_freq); 1456 1457 if ((phase_adjust % half_synth_cycle) != 0) { 1458 NL_SET_ERR_MSG_FMT(extack, 1459 "Phase adjustment value has to be multiple of %d", 1460 half_synth_cycle); 1461 return -EINVAL; 1462 } 1463 phase_adjust /= half_synth_cycle; 1464 1465 /* The value in the register is stored as two's complement negation 1466 * of requested value. 1467 */ 1468 phase_adjust = -phase_adjust; 1469 1470 guard(mutex)(&zldev->multiop_lock); 1471 1472 /* Read output configuration */ 1473 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1474 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1475 if (rc) 1476 return rc; 1477 1478 /* Write the requested value into the compensation register */ 1479 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, phase_adjust); 1480 if (rc) 1481 return rc; 1482 1483 /* Update output configuration from mailbox */ 1484 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 1485 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1486 } 1487 1488 static int 1489 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 1490 void *pin_priv, 1491 const struct dpll_device *dpll, 1492 void *dpll_priv, 1493 enum dpll_pin_state *state, 1494 struct netlink_ext_ack *extack) 1495 { 1496 /* If the output pin is registered then it is always connected */ 1497 *state = DPLL_PIN_STATE_CONNECTED; 1498 1499 return 0; 1500 } 1501 1502 static int 1503 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, 1504 enum dpll_lock_status *status, 1505 enum dpll_lock_status_error *status_error, 1506 struct netlink_ext_ack *extack) 1507 { 1508 struct zl3073x_dpll *zldpll = dpll_priv; 1509 struct zl3073x_dev *zldev = zldpll->dev; 1510 u8 mon_status, state; 1511 int rc; 1512 1513 switch (zldpll->refsel_mode) { 1514 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1515 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1516 /* In FREERUN and NCO modes the DPLL is always unlocked */ 1517 *status = DPLL_LOCK_STATUS_UNLOCKED; 1518 1519 return 0; 1520 default: 1521 break; 1522 } 1523 1524 /* Read DPLL monitor status */ 1525 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id), 1526 &mon_status); 1527 if (rc) 1528 return rc; 1529 state = FIELD_GET(ZL_DPLL_MON_STATUS_STATE, mon_status); 1530 1531 switch (state) { 1532 case ZL_DPLL_MON_STATUS_STATE_LOCK: 1533 if (FIELD_GET(ZL_DPLL_MON_STATUS_HO_READY, mon_status)) 1534 *status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 1535 else 1536 *status = DPLL_LOCK_STATUS_LOCKED; 1537 break; 1538 case ZL_DPLL_MON_STATUS_STATE_HOLDOVER: 1539 case ZL_DPLL_MON_STATUS_STATE_ACQUIRING: 1540 *status = DPLL_LOCK_STATUS_HOLDOVER; 1541 break; 1542 default: 1543 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n", 1544 mon_status); 1545 *status = DPLL_LOCK_STATUS_UNLOCKED; 1546 break; 1547 } 1548 1549 return 0; 1550 } 1551 1552 static int 1553 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, 1554 enum dpll_mode *mode, struct netlink_ext_ack *extack) 1555 { 1556 struct zl3073x_dpll *zldpll = dpll_priv; 1557 1558 switch (zldpll->refsel_mode) { 1559 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1560 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 1561 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1562 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 1563 /* Use MANUAL for device FREERUN, HOLDOVER, NCO and 1564 * REFLOCK modes 1565 */ 1566 *mode = DPLL_MODE_MANUAL; 1567 break; 1568 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 1569 /* Use AUTO for device AUTO mode */ 1570 *mode = DPLL_MODE_AUTOMATIC; 1571 break; 1572 default: 1573 return -EINVAL; 1574 } 1575 1576 return 0; 1577 } 1578 1579 static int 1580 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll, 1581 void *dpll_priv, 1582 enum dpll_feature_state *state, 1583 struct netlink_ext_ack *extack) 1584 { 1585 struct zl3073x_dpll *zldpll = dpll_priv; 1586 1587 if (zldpll->phase_monitor) 1588 *state = DPLL_FEATURE_STATE_ENABLE; 1589 else 1590 *state = DPLL_FEATURE_STATE_DISABLE; 1591 1592 return 0; 1593 } 1594 1595 static int 1596 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll, 1597 void *dpll_priv, 1598 enum dpll_feature_state state, 1599 struct netlink_ext_ack *extack) 1600 { 1601 struct zl3073x_dpll *zldpll = dpll_priv; 1602 1603 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE); 1604 1605 return 0; 1606 } 1607 1608 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = { 1609 .direction_get = zl3073x_dpll_pin_direction_get, 1610 .esync_get = zl3073x_dpll_input_pin_esync_get, 1611 .esync_set = zl3073x_dpll_input_pin_esync_set, 1612 .ffo_get = zl3073x_dpll_input_pin_ffo_get, 1613 .frequency_get = zl3073x_dpll_input_pin_frequency_get, 1614 .frequency_set = zl3073x_dpll_input_pin_frequency_set, 1615 .phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get, 1616 .phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get, 1617 .phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set, 1618 .prio_get = zl3073x_dpll_input_pin_prio_get, 1619 .prio_set = zl3073x_dpll_input_pin_prio_set, 1620 .state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get, 1621 .state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set, 1622 }; 1623 1624 static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = { 1625 .direction_get = zl3073x_dpll_pin_direction_get, 1626 .esync_get = zl3073x_dpll_output_pin_esync_get, 1627 .esync_set = zl3073x_dpll_output_pin_esync_set, 1628 .frequency_get = zl3073x_dpll_output_pin_frequency_get, 1629 .frequency_set = zl3073x_dpll_output_pin_frequency_set, 1630 .phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get, 1631 .phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set, 1632 .state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get, 1633 }; 1634 1635 static const struct dpll_device_ops zl3073x_dpll_device_ops = { 1636 .lock_status_get = zl3073x_dpll_lock_status_get, 1637 .mode_get = zl3073x_dpll_mode_get, 1638 .phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get, 1639 .phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set, 1640 }; 1641 1642 /** 1643 * zl3073x_dpll_pin_alloc - allocate DPLL pin 1644 * @zldpll: pointer to zl3073x_dpll 1645 * @dir: pin direction 1646 * @id: pin id 1647 * 1648 * Allocates and initializes zl3073x_dpll_pin structure for given 1649 * pin id and direction. 1650 * 1651 * Return: pointer to allocated structure on success, error pointer on error 1652 */ 1653 static struct zl3073x_dpll_pin * 1654 zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir, 1655 u8 id) 1656 { 1657 struct zl3073x_dpll_pin *pin; 1658 1659 pin = kzalloc(sizeof(*pin), GFP_KERNEL); 1660 if (!pin) 1661 return ERR_PTR(-ENOMEM); 1662 1663 pin->dpll = zldpll; 1664 pin->dir = dir; 1665 pin->id = id; 1666 1667 return pin; 1668 } 1669 1670 /** 1671 * zl3073x_dpll_pin_free - deallocate DPLL pin 1672 * @pin: pin to free 1673 * 1674 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc. 1675 */ 1676 static void 1677 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin) 1678 { 1679 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); 1680 1681 kfree(pin); 1682 } 1683 1684 /** 1685 * zl3073x_dpll_pin_register - register DPLL pin 1686 * @pin: pointer to DPLL pin 1687 * @index: absolute pin index for registration 1688 * 1689 * Registers given DPLL pin into DPLL sub-system. 1690 * 1691 * Return: 0 on success, <0 on error 1692 */ 1693 static int 1694 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index) 1695 { 1696 struct zl3073x_dpll *zldpll = pin->dpll; 1697 struct zl3073x_pin_props *props; 1698 const struct dpll_pin_ops *ops; 1699 int rc; 1700 1701 /* Get pin properties */ 1702 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); 1703 if (IS_ERR(props)) 1704 return PTR_ERR(props); 1705 1706 /* Save package label & esync capability */ 1707 strscpy(pin->label, props->package_label); 1708 pin->esync_control = props->esync_control; 1709 1710 if (zl3073x_dpll_is_input_pin(pin)) { 1711 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); 1712 if (rc) 1713 goto err_prio_get; 1714 1715 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) { 1716 /* Clamp prio to max value & mark pin non-selectable */ 1717 pin->prio = ZL_DPLL_REF_PRIO_MAX; 1718 pin->selectable = false; 1719 } else { 1720 /* Mark pin as selectable */ 1721 pin->selectable = true; 1722 } 1723 } 1724 1725 /* Create or get existing DPLL pin */ 1726 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, 1727 &props->dpll_props); 1728 if (IS_ERR(pin->dpll_pin)) { 1729 rc = PTR_ERR(pin->dpll_pin); 1730 goto err_pin_get; 1731 } 1732 1733 if (zl3073x_dpll_is_input_pin(pin)) 1734 ops = &zl3073x_dpll_input_pin_ops; 1735 else 1736 ops = &zl3073x_dpll_output_pin_ops; 1737 1738 /* Register the pin */ 1739 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1740 if (rc) 1741 goto err_register; 1742 1743 /* Free pin properties */ 1744 zl3073x_pin_props_put(props); 1745 1746 return 0; 1747 1748 err_register: 1749 dpll_pin_put(pin->dpll_pin); 1750 err_prio_get: 1751 pin->dpll_pin = NULL; 1752 err_pin_get: 1753 zl3073x_pin_props_put(props); 1754 1755 return rc; 1756 } 1757 1758 /** 1759 * zl3073x_dpll_pin_unregister - unregister DPLL pin 1760 * @pin: pointer to DPLL pin 1761 * 1762 * Unregisters pin previously registered by @zl3073x_dpll_pin_register. 1763 */ 1764 static void 1765 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin) 1766 { 1767 struct zl3073x_dpll *zldpll = pin->dpll; 1768 const struct dpll_pin_ops *ops; 1769 1770 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); 1771 1772 if (zl3073x_dpll_is_input_pin(pin)) 1773 ops = &zl3073x_dpll_input_pin_ops; 1774 else 1775 ops = &zl3073x_dpll_output_pin_ops; 1776 1777 /* Unregister the pin */ 1778 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1779 1780 dpll_pin_put(pin->dpll_pin); 1781 pin->dpll_pin = NULL; 1782 } 1783 1784 /** 1785 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins 1786 * @zldpll: pointer to zl3073x_dpll structure 1787 * 1788 * Enumerates all DPLL pins registered to given DPLL device and 1789 * unregisters them. 1790 */ 1791 static void 1792 zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll) 1793 { 1794 struct zl3073x_dpll_pin *pin, *next; 1795 1796 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { 1797 zl3073x_dpll_pin_unregister(pin); 1798 list_del(&pin->list); 1799 zl3073x_dpll_pin_free(pin); 1800 } 1801 } 1802 1803 /** 1804 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable 1805 * @zldpll: pointer to zl3073x_dpll structure 1806 * @dir: pin direction 1807 * @index: pin index 1808 * 1809 * Checks if the given pin can be registered to given DPLL. For both 1810 * directions the pin can be registered if it is enabled. In case of 1811 * differential signal type only P-pin is reported as registrable. 1812 * And additionally for the output pin, the pin can be registered only 1813 * if it is connected to synthesizer that is driven by given DPLL. 1814 * 1815 * Return: true if the pin is registrable, false if not 1816 */ 1817 static bool 1818 zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll, 1819 enum dpll_pin_direction dir, u8 index) 1820 { 1821 struct zl3073x_dev *zldev = zldpll->dev; 1822 bool is_diff, is_enabled; 1823 const char *name; 1824 1825 if (dir == DPLL_PIN_DIRECTION_INPUT) { 1826 u8 ref = zl3073x_input_pin_ref_get(index); 1827 1828 name = "REF"; 1829 1830 /* Skip the pin if the DPLL is running in NCO mode */ 1831 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO) 1832 return false; 1833 1834 is_diff = zl3073x_ref_is_diff(zldev, ref); 1835 is_enabled = zl3073x_ref_is_enabled(zldev, ref); 1836 } else { 1837 /* Output P&N pair shares single HW output */ 1838 u8 out = zl3073x_output_pin_out_get(index); 1839 1840 name = "OUT"; 1841 1842 /* Skip the pin if it is connected to different DPLL channel */ 1843 if (zl3073x_out_dpll_get(zldev, out) != zldpll->id) { 1844 dev_dbg(zldev->dev, 1845 "%s%u is driven by different DPLL\n", name, 1846 out); 1847 1848 return false; 1849 } 1850 1851 is_diff = zl3073x_out_is_diff(zldev, out); 1852 is_enabled = zl3073x_out_is_enabled(zldev, out); 1853 } 1854 1855 /* Skip N-pin if the corresponding input/output is differential */ 1856 if (is_diff && zl3073x_is_n_pin(index)) { 1857 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", 1858 name, index / 2); 1859 1860 return false; 1861 } 1862 1863 /* Skip the pin if it is disabled */ 1864 if (!is_enabled) { 1865 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, 1866 zl3073x_is_p_pin(index) ? 'P' : 'N'); 1867 1868 return false; 1869 } 1870 1871 return true; 1872 } 1873 1874 /** 1875 * zl3073x_dpll_pins_register - register all registerable DPLL pins 1876 * @zldpll: pointer to zl3073x_dpll structure 1877 * 1878 * Enumerates all possible input/output pins and registers all of them 1879 * that are registrable. 1880 * 1881 * Return: 0 on success, <0 on error 1882 */ 1883 static int 1884 zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll) 1885 { 1886 struct zl3073x_dpll_pin *pin; 1887 enum dpll_pin_direction dir; 1888 u8 id, index; 1889 int rc; 1890 1891 /* Process input pins */ 1892 for (index = 0; index < ZL3073X_NUM_PINS; index++) { 1893 /* First input pins and then output pins */ 1894 if (index < ZL3073X_NUM_INPUT_PINS) { 1895 id = index; 1896 dir = DPLL_PIN_DIRECTION_INPUT; 1897 } else { 1898 id = index - ZL3073X_NUM_INPUT_PINS; 1899 dir = DPLL_PIN_DIRECTION_OUTPUT; 1900 } 1901 1902 /* Check if the pin registrable to this DPLL */ 1903 if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id)) 1904 continue; 1905 1906 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id); 1907 if (IS_ERR(pin)) { 1908 rc = PTR_ERR(pin); 1909 goto error; 1910 } 1911 1912 rc = zl3073x_dpll_pin_register(pin, index); 1913 if (rc) 1914 goto error; 1915 1916 list_add(&pin->list, &zldpll->pins); 1917 } 1918 1919 return 0; 1920 1921 error: 1922 zl3073x_dpll_pins_unregister(zldpll); 1923 1924 return rc; 1925 } 1926 1927 /** 1928 * zl3073x_dpll_device_register - register DPLL device 1929 * @zldpll: pointer to zl3073x_dpll structure 1930 * 1931 * Registers given DPLL device into DPLL sub-system. 1932 * 1933 * Return: 0 on success, <0 on error 1934 */ 1935 static int 1936 zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll) 1937 { 1938 struct zl3073x_dev *zldev = zldpll->dev; 1939 u8 dpll_mode_refsel; 1940 int rc; 1941 1942 /* Read DPLL mode and forcibly selected reference */ 1943 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1944 &dpll_mode_refsel); 1945 if (rc) 1946 return rc; 1947 1948 /* Extract mode and selected input reference */ 1949 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE, 1950 dpll_mode_refsel); 1951 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF, 1952 dpll_mode_refsel); 1953 1954 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, 1955 THIS_MODULE); 1956 if (IS_ERR(zldpll->dpll_dev)) { 1957 rc = PTR_ERR(zldpll->dpll_dev); 1958 zldpll->dpll_dev = NULL; 1959 1960 return rc; 1961 } 1962 1963 rc = dpll_device_register(zldpll->dpll_dev, 1964 zl3073x_prop_dpll_type_get(zldev, zldpll->id), 1965 &zl3073x_dpll_device_ops, zldpll); 1966 if (rc) { 1967 dpll_device_put(zldpll->dpll_dev); 1968 zldpll->dpll_dev = NULL; 1969 } 1970 1971 return rc; 1972 } 1973 1974 /** 1975 * zl3073x_dpll_device_unregister - unregister DPLL device 1976 * @zldpll: pointer to zl3073x_dpll structure 1977 * 1978 * Unregisters given DPLL device from DPLL sub-system previously registered 1979 * by @zl3073x_dpll_device_register. 1980 */ 1981 static void 1982 zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll) 1983 { 1984 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n"); 1985 1986 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, 1987 zldpll); 1988 dpll_device_put(zldpll->dpll_dev); 1989 zldpll->dpll_dev = NULL; 1990 } 1991 1992 /** 1993 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change 1994 * @pin: pin to check 1995 * 1996 * Check for the change of DPLL to connected pin phase offset change. 1997 * 1998 * Return: true on phase offset change, false otherwise 1999 */ 2000 static bool 2001 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin) 2002 { 2003 struct zl3073x_dpll *zldpll = pin->dpll; 2004 struct zl3073x_dev *zldev = zldpll->dev; 2005 unsigned int reg; 2006 s64 phase_offset; 2007 u8 ref; 2008 int rc; 2009 2010 ref = zl3073x_input_pin_ref_get(pin->id); 2011 2012 /* Select register to read phase offset value depending on pin and 2013 * phase monitor state: 2014 * 1) For connected pin use dpll_phase_err_data register 2015 * 2) For other pins use appropriate ref_phase register if the phase 2016 * monitor feature is enabled and reference monitor does not 2017 * report signal errors for given input pin 2018 */ 2019 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) { 2020 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); 2021 } else if (zldpll->phase_monitor) { 2022 u8 status; 2023 2024 /* Get reference monitor status */ 2025 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), 2026 &status); 2027 if (rc) { 2028 dev_err(zldev->dev, 2029 "Failed to read %s refmon status: %pe\n", 2030 pin->label, ERR_PTR(rc)); 2031 2032 return false; 2033 } 2034 2035 if (status != ZL_REF_MON_STATUS_OK) 2036 return false; 2037 2038 reg = ZL_REG_REF_PHASE(ref); 2039 } else { 2040 /* The pin is not connected or phase monitor disabled */ 2041 return false; 2042 } 2043 2044 /* Read measured phase offset value */ 2045 rc = zl3073x_read_u48(zldev, reg, &phase_offset); 2046 if (rc) { 2047 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n", 2048 ERR_PTR(rc)); 2049 2050 return false; 2051 } 2052 2053 /* Convert to ps */ 2054 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100); 2055 2056 /* Compare with previous value */ 2057 if (phase_offset != pin->phase_offset) { 2058 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n", 2059 pin->label, pin->phase_offset, phase_offset); 2060 pin->phase_offset = phase_offset; 2061 2062 return true; 2063 } 2064 2065 return false; 2066 } 2067 2068 /** 2069 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change 2070 * @pin: pin to check 2071 * 2072 * Check for the given pin's fractional frequency change. 2073 * 2074 * Return: true on fractional frequency offset change, false otherwise 2075 */ 2076 static bool 2077 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin) 2078 { 2079 struct zl3073x_dpll *zldpll = pin->dpll; 2080 struct zl3073x_dev *zldev = zldpll->dev; 2081 u8 ref, status; 2082 s64 ffo; 2083 int rc; 2084 2085 /* Get reference monitor status */ 2086 ref = zl3073x_input_pin_ref_get(pin->id); 2087 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), &status); 2088 if (rc) { 2089 dev_err(zldev->dev, "Failed to read %s refmon status: %pe\n", 2090 pin->label, ERR_PTR(rc)); 2091 2092 return false; 2093 } 2094 2095 /* Do not report ffo changes if the reference monitor report errors */ 2096 if (status != ZL_REF_MON_STATUS_OK) 2097 return false; 2098 2099 /* Get the latest measured ref's ffo */ 2100 ffo = zl3073x_ref_ffo_get(zldev, ref); 2101 2102 /* Compare with previous value */ 2103 if (pin->freq_offset != ffo) { 2104 dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n", 2105 pin->label, pin->freq_offset, ffo); 2106 pin->freq_offset = ffo; 2107 2108 return true; 2109 } 2110 2111 return false; 2112 } 2113 2114 /** 2115 * zl3073x_dpll_changes_check - check for changes and send notifications 2116 * @zldpll: pointer to zl3073x_dpll structure 2117 * 2118 * Checks for changes on given DPLL device and its registered DPLL pins 2119 * and sends notifications about them. 2120 * 2121 * This function is periodically called from @zl3073x_dev_periodic_work. 2122 */ 2123 void 2124 zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll) 2125 { 2126 struct zl3073x_dev *zldev = zldpll->dev; 2127 enum dpll_lock_status lock_status; 2128 struct device *dev = zldev->dev; 2129 struct zl3073x_dpll_pin *pin; 2130 int rc; 2131 2132 zldpll->check_count++; 2133 2134 /* Get current lock status for the DPLL */ 2135 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, 2136 &lock_status, NULL, NULL); 2137 if (rc) { 2138 dev_err(dev, "Failed to get DPLL%u lock status: %pe\n", 2139 zldpll->id, ERR_PTR(rc)); 2140 return; 2141 } 2142 2143 /* If lock status was changed then notify DPLL core */ 2144 if (zldpll->lock_status != lock_status) { 2145 zldpll->lock_status = lock_status; 2146 dpll_device_change_ntf(zldpll->dpll_dev); 2147 } 2148 2149 /* Input pin monitoring does make sense only in automatic 2150 * or forced reference modes. 2151 */ 2152 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO && 2153 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK) 2154 return; 2155 2156 /* Update phase offset latch registers for this DPLL if the phase 2157 * offset monitor feature is enabled. 2158 */ 2159 if (zldpll->phase_monitor) { 2160 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id); 2161 if (rc) { 2162 dev_err(zldev->dev, 2163 "Failed to update phase offsets: %pe\n", 2164 ERR_PTR(rc)); 2165 return; 2166 } 2167 } 2168 2169 list_for_each_entry(pin, &zldpll->pins, list) { 2170 enum dpll_pin_state state; 2171 bool pin_changed = false; 2172 2173 /* Output pins change checks are not necessary because output 2174 * states are constant. 2175 */ 2176 if (!zl3073x_dpll_is_input_pin(pin)) 2177 continue; 2178 2179 rc = zl3073x_dpll_ref_state_get(pin, &state); 2180 if (rc) { 2181 dev_err(dev, 2182 "Failed to get %s on DPLL%u state: %pe\n", 2183 pin->label, zldpll->id, ERR_PTR(rc)); 2184 return; 2185 } 2186 2187 if (state != pin->pin_state) { 2188 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, 2189 pin->pin_state, state); 2190 pin->pin_state = state; 2191 pin_changed = true; 2192 } 2193 2194 /* Check for phase offset and ffo change once per second */ 2195 if (zldpll->check_count % 2 == 0) { 2196 if (zl3073x_dpll_pin_phase_offset_check(pin)) 2197 pin_changed = true; 2198 2199 if (zl3073x_dpll_pin_ffo_check(pin)) 2200 pin_changed = true; 2201 } 2202 2203 if (pin_changed) 2204 dpll_pin_change_ntf(pin->dpll_pin); 2205 } 2206 } 2207 2208 /** 2209 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments 2210 * @zldev: pointer to zl3073x device 2211 * 2212 * Performs initial fine phase adjustments needed per datasheet. 2213 * 2214 * Return: 0 on success, <0 on error 2215 */ 2216 int 2217 zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev) 2218 { 2219 int rc; 2220 2221 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); 2222 if (rc) 2223 return rc; 2224 2225 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); 2226 if (rc) 2227 return rc; 2228 2229 rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff); 2230 if (rc) 2231 return rc; 2232 2233 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); 2234 if (rc) 2235 return rc; 2236 2237 return rc; 2238 } 2239 2240 /** 2241 * zl3073x_dpll_alloc - allocate DPLL device 2242 * @zldev: pointer to zl3073x device 2243 * @ch: DPLL channel number 2244 * 2245 * Allocates DPLL device structure for given DPLL channel. 2246 * 2247 * Return: pointer to DPLL device on success, error pointer on error 2248 */ 2249 struct zl3073x_dpll * 2250 zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch) 2251 { 2252 struct zl3073x_dpll *zldpll; 2253 2254 zldpll = kzalloc(sizeof(*zldpll), GFP_KERNEL); 2255 if (!zldpll) 2256 return ERR_PTR(-ENOMEM); 2257 2258 zldpll->dev = zldev; 2259 zldpll->id = ch; 2260 INIT_LIST_HEAD(&zldpll->pins); 2261 2262 return zldpll; 2263 } 2264 2265 /** 2266 * zl3073x_dpll_free - free DPLL device 2267 * @zldpll: pointer to zl3073x_dpll structure 2268 * 2269 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc. 2270 */ 2271 void 2272 zl3073x_dpll_free(struct zl3073x_dpll *zldpll) 2273 { 2274 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); 2275 2276 kfree(zldpll); 2277 } 2278 2279 /** 2280 * zl3073x_dpll_register - register DPLL device and all its pins 2281 * @zldpll: pointer to zl3073x_dpll structure 2282 * 2283 * Registers given DPLL device and all its pins into DPLL sub-system. 2284 * 2285 * Return: 0 on success, <0 on error 2286 */ 2287 int 2288 zl3073x_dpll_register(struct zl3073x_dpll *zldpll) 2289 { 2290 int rc; 2291 2292 rc = zl3073x_dpll_device_register(zldpll); 2293 if (rc) 2294 return rc; 2295 2296 rc = zl3073x_dpll_pins_register(zldpll); 2297 if (rc) { 2298 zl3073x_dpll_device_unregister(zldpll); 2299 return rc; 2300 } 2301 2302 return 0; 2303 } 2304 2305 /** 2306 * zl3073x_dpll_unregister - unregister DPLL device and its pins 2307 * @zldpll: pointer to zl3073x_dpll structure 2308 * 2309 * Unregisters given DPLL device and all its pins from DPLL sub-system 2310 * previously registered by @zl3073x_dpll_register. 2311 */ 2312 void 2313 zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll) 2314 { 2315 /* Unregister all pins and dpll */ 2316 zl3073x_dpll_pins_unregister(zldpll); 2317 zl3073x_dpll_device_unregister(zldpll); 2318 } 2319