1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bits.h> 4 #include <linux/bitfield.h> 5 #include <linux/bug.h> 6 #include <linux/container_of.h> 7 #include <linux/dev_printk.h> 8 #include <linux/dpll.h> 9 #include <linux/err.h> 10 #include <linux/kthread.h> 11 #include <linux/math64.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/netlink.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/sprintf.h> 18 19 #include "core.h" 20 #include "dpll.h" 21 #include "prop.h" 22 #include "regs.h" 23 24 #define ZL3073X_DPLL_REF_NONE ZL3073X_NUM_REFS 25 #define ZL3073X_DPLL_REF_IS_VALID(_ref) ((_ref) != ZL3073X_DPLL_REF_NONE) 26 27 /** 28 * struct zl3073x_dpll_pin - DPLL pin 29 * @list: this DPLL pin list entry 30 * @dpll: DPLL the pin is registered to 31 * @dpll_pin: pointer to registered dpll_pin 32 * @tracker: tracking object for the acquired reference 33 * @label: package label 34 * @dir: pin direction 35 * @id: pin id 36 * @prio: pin priority <0, 14> 37 * @selectable: pin is selectable in automatic mode 38 * @esync_control: embedded sync is controllable 39 * @phase_gran: phase adjustment granularity 40 * @pin_state: last saved pin state 41 * @phase_offset: last saved pin phase offset 42 * @freq_offset: last saved fractional frequency offset 43 */ 44 struct zl3073x_dpll_pin { 45 struct list_head list; 46 struct zl3073x_dpll *dpll; 47 struct dpll_pin *dpll_pin; 48 dpll_tracker tracker; 49 char label[8]; 50 enum dpll_pin_direction dir; 51 u8 id; 52 u8 prio; 53 bool selectable; 54 bool esync_control; 55 s32 phase_gran; 56 enum dpll_pin_state pin_state; 57 s64 phase_offset; 58 s64 freq_offset; 59 }; 60 61 /* 62 * Supported esync ranges for input and for output per output pair type 63 */ 64 static const struct dpll_pin_frequency esync_freq_ranges[] = { 65 DPLL_PIN_FREQUENCY_RANGE(0, 1), 66 }; 67 68 /** 69 * zl3073x_dpll_is_input_pin - check if the pin is input one 70 * @pin: pin to check 71 * 72 * Return: true if pin is input, false if pin is output. 73 */ 74 static bool 75 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin) 76 { 77 return pin->dir == DPLL_PIN_DIRECTION_INPUT; 78 } 79 80 /** 81 * zl3073x_dpll_is_p_pin - check if the pin is P-pin 82 * @pin: pin to check 83 * 84 * Return: true if the pin is P-pin, false if it is N-pin 85 */ 86 static bool 87 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin) 88 { 89 return zl3073x_is_p_pin(pin->id); 90 } 91 92 static int 93 zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv, 94 const struct dpll_device *dpll, void *dpll_priv, 95 enum dpll_pin_direction *direction, 96 struct netlink_ext_ack *extack) 97 { 98 struct zl3073x_dpll_pin *pin = pin_priv; 99 100 *direction = pin->dir; 101 102 return 0; 103 } 104 105 static struct zl3073x_dpll_pin * 106 zl3073x_dpll_pin_get_by_ref(struct zl3073x_dpll *zldpll, u8 ref_id) 107 { 108 struct zl3073x_dpll_pin *pin; 109 110 list_for_each_entry(pin, &zldpll->pins, list) { 111 if (zl3073x_dpll_is_input_pin(pin) && 112 zl3073x_input_pin_ref_get(pin->id) == ref_id) 113 return pin; 114 } 115 116 return NULL; 117 } 118 119 static int 120 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, 121 void *pin_priv, 122 const struct dpll_device *dpll, 123 void *dpll_priv, 124 struct dpll_pin_esync *esync, 125 struct netlink_ext_ack *extack) 126 { 127 struct zl3073x_dpll *zldpll = dpll_priv; 128 struct zl3073x_dev *zldev = zldpll->dev; 129 struct zl3073x_dpll_pin *pin = pin_priv; 130 const struct zl3073x_ref *ref; 131 u8 ref_id; 132 133 ref_id = zl3073x_input_pin_ref_get(pin->id); 134 ref = zl3073x_ref_state_get(zldev, ref_id); 135 136 switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) { 137 case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: 138 esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0; 139 esync->pulse = 25; 140 break; 141 default: 142 esync->freq = 0; 143 esync->pulse = 0; 144 break; 145 } 146 147 /* If the pin supports esync control expose its range but only 148 * if the current reference frequency is > 1 Hz. 149 */ 150 if (pin->esync_control && zl3073x_ref_freq_get(ref) > 1) { 151 esync->range = esync_freq_ranges; 152 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 153 } else { 154 esync->range = NULL; 155 esync->range_num = 0; 156 } 157 158 return 0; 159 } 160 161 static int 162 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin, 163 void *pin_priv, 164 const struct dpll_device *dpll, 165 void *dpll_priv, u64 freq, 166 struct netlink_ext_ack *extack) 167 { 168 struct zl3073x_dpll *zldpll = dpll_priv; 169 struct zl3073x_dev *zldev = zldpll->dev; 170 struct zl3073x_dpll_pin *pin = pin_priv; 171 struct zl3073x_ref ref; 172 u8 ref_id, sync_mode; 173 174 ref_id = zl3073x_input_pin_ref_get(pin->id); 175 ref = *zl3073x_ref_state_get(zldev, ref_id); 176 177 /* Use freq == 0 to disable esync */ 178 if (!freq) 179 sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF; 180 else 181 sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75; 182 183 ref.sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE; 184 ref.sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode); 185 186 if (freq) { 187 /* 1 Hz is only supported frequency now */ 188 ref.esync_n_div = ZL_REF_ESYNC_DIV_1HZ; 189 } 190 191 /* Update reference configuration */ 192 return zl3073x_ref_state_set(zldev, ref_id, &ref); 193 } 194 195 static int 196 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv, 197 const struct dpll_device *dpll, void *dpll_priv, 198 s64 *ffo, struct netlink_ext_ack *extack) 199 { 200 struct zl3073x_dpll_pin *pin = pin_priv; 201 202 *ffo = pin->freq_offset; 203 204 return 0; 205 } 206 207 static int 208 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin, 209 void *pin_priv, 210 const struct dpll_device *dpll, 211 void *dpll_priv, u64 *frequency, 212 struct netlink_ext_ack *extack) 213 { 214 struct zl3073x_dpll *zldpll = dpll_priv; 215 struct zl3073x_dpll_pin *pin = pin_priv; 216 u8 ref_id; 217 218 ref_id = zl3073x_input_pin_ref_get(pin->id); 219 *frequency = zl3073x_dev_ref_freq_get(zldpll->dev, ref_id); 220 221 return 0; 222 } 223 224 static int 225 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin, 226 void *pin_priv, 227 const struct dpll_device *dpll, 228 void *dpll_priv, u64 frequency, 229 struct netlink_ext_ack *extack) 230 { 231 struct zl3073x_dpll *zldpll = dpll_priv; 232 struct zl3073x_dev *zldev = zldpll->dev; 233 struct zl3073x_dpll_pin *pin = pin_priv; 234 struct zl3073x_ref ref; 235 u8 ref_id; 236 237 /* Get reference state */ 238 ref_id = zl3073x_input_pin_ref_get(pin->id); 239 ref = *zl3073x_ref_state_get(zldev, ref_id); 240 241 /* Update frequency */ 242 zl3073x_ref_freq_set(&ref, frequency); 243 244 /* Commit reference state */ 245 return zl3073x_ref_state_set(zldev, ref_id, &ref); 246 } 247 248 /** 249 * zl3073x_dpll_selected_ref_get - get currently selected reference 250 * @zldpll: pointer to zl3073x_dpll 251 * @ref: place to store selected reference 252 * 253 * Check for currently selected reference the DPLL should be locked to 254 * and stores its index to given @ref. 255 * 256 * Return: 0 on success, <0 on error 257 */ 258 static int 259 zl3073x_dpll_selected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 260 { 261 struct zl3073x_dev *zldev = zldpll->dev; 262 u8 state, value; 263 int rc; 264 265 switch (zldpll->refsel_mode) { 266 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 267 /* For automatic mode read refsel_status register */ 268 rc = zl3073x_read_u8(zldev, 269 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id), 270 &value); 271 if (rc) 272 return rc; 273 274 /* Extract reference state */ 275 state = FIELD_GET(ZL_DPLL_REFSEL_STATUS_STATE, value); 276 277 /* Return the reference only if the DPLL is locked to it */ 278 if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK) 279 *ref = FIELD_GET(ZL_DPLL_REFSEL_STATUS_REFSEL, value); 280 else 281 *ref = ZL3073X_DPLL_REF_NONE; 282 break; 283 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 284 /* For manual mode return stored value */ 285 *ref = zldpll->forced_ref; 286 break; 287 default: 288 /* For other modes like NCO, freerun... there is no input ref */ 289 *ref = ZL3073X_DPLL_REF_NONE; 290 break; 291 } 292 293 return 0; 294 } 295 296 /** 297 * zl3073x_dpll_selected_ref_set - select reference in manual mode 298 * @zldpll: pointer to zl3073x_dpll 299 * @ref: input reference to be selected 300 * 301 * Selects the given reference for the DPLL channel it should be 302 * locked to. 303 * 304 * Return: 0 on success, <0 on error 305 */ 306 static int 307 zl3073x_dpll_selected_ref_set(struct zl3073x_dpll *zldpll, u8 ref) 308 { 309 struct zl3073x_dev *zldev = zldpll->dev; 310 u8 mode, mode_refsel; 311 int rc; 312 313 mode = zldpll->refsel_mode; 314 315 switch (mode) { 316 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 317 /* Manual mode with ref selected */ 318 if (ref == ZL3073X_DPLL_REF_NONE) { 319 switch (zldpll->lock_status) { 320 case DPLL_LOCK_STATUS_LOCKED_HO_ACQ: 321 case DPLL_LOCK_STATUS_HOLDOVER: 322 /* Switch to forced holdover */ 323 mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 324 break; 325 default: 326 /* Switch to freerun */ 327 mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 328 break; 329 } 330 /* Keep selected reference */ 331 ref = zldpll->forced_ref; 332 } else if (ref == zldpll->forced_ref) { 333 /* No register update - same mode and same ref */ 334 return 0; 335 } 336 break; 337 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 338 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 339 /* Manual mode without no ref */ 340 if (ref == ZL3073X_DPLL_REF_NONE) 341 /* No register update - keep current mode */ 342 return 0; 343 344 /* Switch to reflock mode and update ref selection */ 345 mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 346 break; 347 default: 348 /* For other modes like automatic or NCO ref cannot be selected 349 * manually 350 */ 351 return -EOPNOTSUPP; 352 } 353 354 /* Build mode_refsel value */ 355 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode) | 356 FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 357 358 /* Update dpll_mode_refsel register */ 359 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 360 mode_refsel); 361 if (rc) 362 return rc; 363 364 /* Store new mode and forced reference */ 365 zldpll->refsel_mode = mode; 366 zldpll->forced_ref = ref; 367 368 return rc; 369 } 370 371 /** 372 * zl3073x_dpll_connected_ref_get - get currently connected reference 373 * @zldpll: pointer to zl3073x_dpll 374 * @ref: place to store selected reference 375 * 376 * Looks for currently connected the DPLL is locked to and stores its index 377 * to given @ref. 378 * 379 * Return: 0 on success, <0 on error 380 */ 381 static int 382 zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 383 { 384 struct zl3073x_dev *zldev = zldpll->dev; 385 int rc; 386 387 /* Get currently selected input reference */ 388 rc = zl3073x_dpll_selected_ref_get(zldpll, ref); 389 if (rc) 390 return rc; 391 392 /* If the monitor indicates an error nothing is connected */ 393 if (ZL3073X_DPLL_REF_IS_VALID(*ref) && 394 !zl3073x_dev_ref_is_status_ok(zldev, *ref)) 395 *ref = ZL3073X_DPLL_REF_NONE; 396 397 return 0; 398 } 399 400 static int 401 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin, 402 void *pin_priv, 403 const struct dpll_device *dpll, 404 void *dpll_priv, s64 *phase_offset, 405 struct netlink_ext_ack *extack) 406 { 407 struct zl3073x_dpll *zldpll = dpll_priv; 408 struct zl3073x_dev *zldev = zldpll->dev; 409 struct zl3073x_dpll_pin *pin = pin_priv; 410 const struct zl3073x_ref *ref; 411 u8 conn_id, ref_id; 412 s64 ref_phase; 413 int rc; 414 415 /* Get currently connected reference */ 416 rc = zl3073x_dpll_connected_ref_get(zldpll, &conn_id); 417 if (rc) 418 return rc; 419 420 /* Report phase offset only for currently connected pin if the phase 421 * monitor feature is disabled and only if the input pin signal is 422 * present. 423 */ 424 ref_id = zl3073x_input_pin_ref_get(pin->id); 425 ref = zl3073x_ref_state_get(zldev, ref_id); 426 if ((!zldpll->phase_monitor && ref_id != conn_id) || 427 !zl3073x_ref_is_status_ok(ref)) { 428 *phase_offset = 0; 429 return 0; 430 } 431 432 ref_phase = pin->phase_offset; 433 434 /* The DPLL being locked to a higher freq than the current ref 435 * the phase offset is modded to the period of the signal 436 * the dpll is locked to. 437 */ 438 if (ZL3073X_DPLL_REF_IS_VALID(conn_id) && conn_id != ref_id) { 439 u32 conn_freq, ref_freq; 440 441 /* Get frequency of connected and given ref */ 442 conn_freq = zl3073x_dev_ref_freq_get(zldev, conn_id); 443 ref_freq = zl3073x_ref_freq_get(ref); 444 445 if (conn_freq > ref_freq) { 446 s64 conn_period, div_factor; 447 448 conn_period = div_s64(PSEC_PER_SEC, conn_freq); 449 div_factor = div64_s64(ref_phase, conn_period); 450 ref_phase -= conn_period * div_factor; 451 } 452 } 453 454 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER; 455 456 return rc; 457 } 458 459 static int 460 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 461 void *pin_priv, 462 const struct dpll_device *dpll, 463 void *dpll_priv, 464 s32 *phase_adjust, 465 struct netlink_ext_ack *extack) 466 { 467 struct zl3073x_dpll *zldpll = dpll_priv; 468 struct zl3073x_dev *zldev = zldpll->dev; 469 struct zl3073x_dpll_pin *pin = pin_priv; 470 const struct zl3073x_ref *ref; 471 s64 phase_comp; 472 u8 ref_id; 473 474 /* Read reference configuration */ 475 ref_id = zl3073x_input_pin_ref_get(pin->id); 476 ref = zl3073x_ref_state_get(zldev, ref_id); 477 478 /* Perform sign extension based on register width */ 479 if (zl3073x_dev_is_ref_phase_comp_32bit(zldev)) 480 phase_comp = sign_extend64(ref->phase_comp, 31); 481 else 482 phase_comp = sign_extend64(ref->phase_comp, 47); 483 484 /* Reverse two's complement negation applied during set and convert 485 * to 32bit signed int 486 */ 487 *phase_adjust = (s32)-phase_comp; 488 489 return 0; 490 } 491 492 static int 493 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 494 void *pin_priv, 495 const struct dpll_device *dpll, 496 void *dpll_priv, 497 s32 phase_adjust, 498 struct netlink_ext_ack *extack) 499 { 500 struct zl3073x_dpll *zldpll = dpll_priv; 501 struct zl3073x_dev *zldev = zldpll->dev; 502 struct zl3073x_dpll_pin *pin = pin_priv; 503 struct zl3073x_ref ref; 504 u8 ref_id; 505 506 /* Read reference configuration */ 507 ref_id = zl3073x_input_pin_ref_get(pin->id); 508 ref = *zl3073x_ref_state_get(zldev, ref_id); 509 510 /* The value in the register is stored as two's complement negation 511 * of requested value. 512 */ 513 ref.phase_comp = -phase_adjust; 514 515 /* Update reference configuration */ 516 return zl3073x_ref_state_set(zldev, ref_id, &ref); 517 } 518 519 /** 520 * zl3073x_dpll_ref_prio_get - get priority for given input pin 521 * @pin: pointer to pin 522 * @prio: place to store priority 523 * 524 * Reads current priority for the given input pin and stores the value 525 * to @prio. 526 * 527 * Return: 0 on success, <0 on error 528 */ 529 static int 530 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio) 531 { 532 struct zl3073x_dpll *zldpll = pin->dpll; 533 struct zl3073x_dev *zldev = zldpll->dev; 534 u8 ref, ref_prio; 535 int rc; 536 537 guard(mutex)(&zldev->multiop_lock); 538 539 /* Read DPLL configuration */ 540 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 541 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 542 if (rc) 543 return rc; 544 545 /* Read reference priority - one value for P&N pins (4 bits/pin) */ 546 ref = zl3073x_input_pin_ref_get(pin->id); 547 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), 548 &ref_prio); 549 if (rc) 550 return rc; 551 552 /* Select nibble according pin type */ 553 if (zl3073x_dpll_is_p_pin(pin)) 554 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_P, ref_prio); 555 else 556 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_N, ref_prio); 557 558 return rc; 559 } 560 561 /** 562 * zl3073x_dpll_ref_prio_set - set priority for given input pin 563 * @pin: pointer to pin 564 * @prio: place to store priority 565 * 566 * Sets priority for the given input pin. 567 * 568 * Return: 0 on success, <0 on error 569 */ 570 static int 571 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio) 572 { 573 struct zl3073x_dpll *zldpll = pin->dpll; 574 struct zl3073x_dev *zldev = zldpll->dev; 575 u8 ref, ref_prio; 576 int rc; 577 578 guard(mutex)(&zldev->multiop_lock); 579 580 /* Read DPLL configuration into mailbox */ 581 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 582 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 583 if (rc) 584 return rc; 585 586 /* Read reference priority - one value shared between P&N pins */ 587 ref = zl3073x_input_pin_ref_get(pin->id); 588 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio); 589 if (rc) 590 return rc; 591 592 /* Update nibble according pin type */ 593 if (zl3073x_dpll_is_p_pin(pin)) { 594 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_P; 595 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio); 596 } else { 597 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_N; 598 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio); 599 } 600 601 /* Update reference priority */ 602 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio); 603 if (rc) 604 return rc; 605 606 /* Commit configuration */ 607 return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR, 608 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 609 } 610 611 /** 612 * zl3073x_dpll_ref_state_get - get status for given input pin 613 * @pin: pointer to pin 614 * @state: place to store status 615 * 616 * Checks current status for the given input pin and stores the value 617 * to @state. 618 * 619 * Return: 0 on success, <0 on error 620 */ 621 static int 622 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin, 623 enum dpll_pin_state *state) 624 { 625 struct zl3073x_dpll *zldpll = pin->dpll; 626 struct zl3073x_dev *zldev = zldpll->dev; 627 u8 ref, ref_conn; 628 int rc; 629 630 ref = zl3073x_input_pin_ref_get(pin->id); 631 632 /* Get currently connected reference */ 633 rc = zl3073x_dpll_connected_ref_get(zldpll, &ref_conn); 634 if (rc) 635 return rc; 636 637 if (ref == ref_conn) { 638 *state = DPLL_PIN_STATE_CONNECTED; 639 return 0; 640 } 641 642 /* If the DPLL is running in automatic mode and the reference is 643 * selectable and its monitor does not report any error then report 644 * pin as selectable. 645 */ 646 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO && 647 zl3073x_dev_ref_is_status_ok(zldev, ref) && pin->selectable) { 648 *state = DPLL_PIN_STATE_SELECTABLE; 649 return 0; 650 } 651 652 /* Otherwise report the pin as disconnected */ 653 *state = DPLL_PIN_STATE_DISCONNECTED; 654 655 return 0; 656 } 657 658 static int 659 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 660 void *pin_priv, 661 const struct dpll_device *dpll, 662 void *dpll_priv, 663 enum dpll_pin_state *state, 664 struct netlink_ext_ack *extack) 665 { 666 struct zl3073x_dpll_pin *pin = pin_priv; 667 668 return zl3073x_dpll_ref_state_get(pin, state); 669 } 670 671 static int 672 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin, 673 void *pin_priv, 674 const struct dpll_device *dpll, 675 void *dpll_priv, 676 enum dpll_pin_state state, 677 struct netlink_ext_ack *extack) 678 { 679 struct zl3073x_dpll *zldpll = dpll_priv; 680 struct zl3073x_dpll_pin *pin = pin_priv; 681 u8 new_ref; 682 int rc; 683 684 switch (zldpll->refsel_mode) { 685 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 686 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 687 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 688 if (state == DPLL_PIN_STATE_CONNECTED) { 689 /* Choose the pin as new selected reference */ 690 new_ref = zl3073x_input_pin_ref_get(pin->id); 691 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 692 /* No reference */ 693 new_ref = ZL3073X_DPLL_REF_NONE; 694 } else { 695 NL_SET_ERR_MSG_MOD(extack, 696 "Invalid pin state for manual mode"); 697 return -EINVAL; 698 } 699 700 rc = zl3073x_dpll_selected_ref_set(zldpll, new_ref); 701 break; 702 703 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 704 if (state == DPLL_PIN_STATE_SELECTABLE) { 705 if (pin->selectable) 706 return 0; /* Pin is already selectable */ 707 708 /* Restore pin priority in HW */ 709 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 710 if (rc) 711 return rc; 712 713 /* Mark pin as selectable */ 714 pin->selectable = true; 715 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 716 if (!pin->selectable) 717 return 0; /* Pin is already disconnected */ 718 719 /* Set pin priority to none in HW */ 720 rc = zl3073x_dpll_ref_prio_set(pin, 721 ZL_DPLL_REF_PRIO_NONE); 722 if (rc) 723 return rc; 724 725 /* Mark pin as non-selectable */ 726 pin->selectable = false; 727 } else { 728 NL_SET_ERR_MSG(extack, 729 "Invalid pin state for automatic mode"); 730 return -EINVAL; 731 } 732 break; 733 734 default: 735 /* In other modes we cannot change input reference */ 736 NL_SET_ERR_MSG(extack, 737 "Pin state cannot be changed in current mode"); 738 rc = -EOPNOTSUPP; 739 break; 740 } 741 742 return rc; 743 } 744 745 static int 746 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv, 747 const struct dpll_device *dpll, void *dpll_priv, 748 u32 *prio, struct netlink_ext_ack *extack) 749 { 750 struct zl3073x_dpll_pin *pin = pin_priv; 751 752 *prio = pin->prio; 753 754 return 0; 755 } 756 757 static int 758 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv, 759 const struct dpll_device *dpll, void *dpll_priv, 760 u32 prio, struct netlink_ext_ack *extack) 761 { 762 struct zl3073x_dpll_pin *pin = pin_priv; 763 int rc; 764 765 if (prio > ZL_DPLL_REF_PRIO_MAX) 766 return -EINVAL; 767 768 /* If the pin is selectable then update HW registers */ 769 if (pin->selectable) { 770 rc = zl3073x_dpll_ref_prio_set(pin, prio); 771 if (rc) 772 return rc; 773 } 774 775 /* Save priority */ 776 pin->prio = prio; 777 778 return 0; 779 } 780 781 static int 782 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, 783 void *pin_priv, 784 const struct dpll_device *dpll, 785 void *dpll_priv, 786 struct dpll_pin_esync *esync, 787 struct netlink_ext_ack *extack) 788 { 789 struct zl3073x_dpll *zldpll = dpll_priv; 790 struct zl3073x_dev *zldev = zldpll->dev; 791 struct zl3073x_dpll_pin *pin = pin_priv; 792 const struct zl3073x_synth *synth; 793 const struct zl3073x_out *out; 794 u8 clock_type, out_id; 795 u32 synth_freq; 796 797 out_id = zl3073x_output_pin_out_get(pin->id); 798 out = zl3073x_out_state_get(zldev, out_id); 799 800 /* If N-division is enabled, esync is not supported. The register used 801 * for N-division is also used for the esync divider so both cannot 802 * be used. 803 */ 804 switch (zl3073x_out_signal_format_get(out)) { 805 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 806 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 807 return -EOPNOTSUPP; 808 default: 809 break; 810 } 811 812 /* Get attached synth frequency */ 813 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out)); 814 synth_freq = zl3073x_synth_freq_get(synth); 815 816 clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode); 817 if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { 818 /* No need to read esync data if it is not enabled */ 819 esync->freq = 0; 820 esync->pulse = 0; 821 822 goto finish; 823 } 824 825 /* Compute esync frequency */ 826 esync->freq = synth_freq / out->div / out->esync_n_period; 827 828 /* By comparing the esync_pulse_width to the half of the pulse width 829 * the esync pulse percentage can be determined. 830 * Note that half pulse width is in units of half synth cycles, which 831 * is why it reduces down to be output_div. 832 */ 833 esync->pulse = (50 * out->esync_n_width) / out->div; 834 835 finish: 836 /* Set supported esync ranges if the pin supports esync control and 837 * if the output frequency is > 1 Hz. 838 */ 839 if (pin->esync_control && (synth_freq / out->div) > 1) { 840 esync->range = esync_freq_ranges; 841 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 842 } else { 843 esync->range = NULL; 844 esync->range_num = 0; 845 } 846 847 return 0; 848 } 849 850 static int 851 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin, 852 void *pin_priv, 853 const struct dpll_device *dpll, 854 void *dpll_priv, u64 freq, 855 struct netlink_ext_ack *extack) 856 { 857 struct zl3073x_dpll *zldpll = dpll_priv; 858 struct zl3073x_dev *zldev = zldpll->dev; 859 struct zl3073x_dpll_pin *pin = pin_priv; 860 const struct zl3073x_synth *synth; 861 struct zl3073x_out out; 862 u8 clock_type, out_id; 863 u32 synth_freq; 864 865 out_id = zl3073x_output_pin_out_get(pin->id); 866 out = *zl3073x_out_state_get(zldev, out_id); 867 868 /* If N-division is enabled, esync is not supported. The register used 869 * for N-division is also used for the esync divider so both cannot 870 * be used. 871 */ 872 switch (zl3073x_out_signal_format_get(&out)) { 873 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 874 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 875 return -EOPNOTSUPP; 876 default: 877 break; 878 } 879 880 /* Select clock type */ 881 if (freq) 882 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC; 883 else 884 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL; 885 886 /* Update clock type in output mode */ 887 out.mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE; 888 out.mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type); 889 890 /* If esync is being disabled just write mailbox and finish */ 891 if (!freq) 892 goto write_mailbox; 893 894 /* Get attached synth frequency */ 895 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 896 synth_freq = zl3073x_synth_freq_get(synth); 897 898 /* Compute and update esync period */ 899 out.esync_n_period = synth_freq / (u32)freq / out.div; 900 901 /* Half of the period in units of 1/2 synth cycle can be represented by 902 * the output_div. To get the supported esync pulse width of 25% of the 903 * period the output_div can just be divided by 2. Note that this 904 * assumes that output_div is even, otherwise some resolution will be 905 * lost. 906 */ 907 out.esync_n_width = out.div / 2; 908 909 write_mailbox: 910 /* Commit output configuration */ 911 return zl3073x_out_state_set(zldev, out_id, &out); 912 } 913 914 static int 915 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin, 916 void *pin_priv, 917 const struct dpll_device *dpll, 918 void *dpll_priv, u64 *frequency, 919 struct netlink_ext_ack *extack) 920 { 921 struct zl3073x_dpll *zldpll = dpll_priv; 922 struct zl3073x_dpll_pin *pin = pin_priv; 923 924 *frequency = zl3073x_dev_output_pin_freq_get(zldpll->dev, pin->id); 925 926 return 0; 927 } 928 929 static int 930 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, 931 void *pin_priv, 932 const struct dpll_device *dpll, 933 void *dpll_priv, u64 frequency, 934 struct netlink_ext_ack *extack) 935 { 936 struct zl3073x_dpll *zldpll = dpll_priv; 937 struct zl3073x_dev *zldev = zldpll->dev; 938 struct zl3073x_dpll_pin *pin = pin_priv; 939 const struct zl3073x_synth *synth; 940 u8 out_id, signal_format; 941 u32 new_div, synth_freq; 942 struct zl3073x_out out; 943 944 out_id = zl3073x_output_pin_out_get(pin->id); 945 out = *zl3073x_out_state_get(zldev, out_id); 946 947 /* Get attached synth frequency and compute new divisor */ 948 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 949 synth_freq = zl3073x_synth_freq_get(synth); 950 new_div = synth_freq / (u32)frequency; 951 952 /* Get used signal format for the given output */ 953 signal_format = zl3073x_out_signal_format_get(&out); 954 955 /* Check signal format */ 956 if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV && 957 signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) { 958 /* For non N-divided signal formats the frequency is computed 959 * as division of synth frequency and output divisor. 960 */ 961 out.div = new_div; 962 963 /* For 50/50 duty cycle the divisor is equal to width */ 964 out.width = new_div; 965 966 /* Commit output configuration */ 967 return zl3073x_out_state_set(zldev, out_id, &out); 968 } 969 970 if (zl3073x_dpll_is_p_pin(pin)) { 971 /* We are going to change output frequency for P-pin but 972 * if the requested frequency is less than current N-pin 973 * frequency then indicate a failure as we are not able 974 * to compute N-pin divisor to keep its frequency unchanged. 975 * 976 * Update divisor for N-pin to keep N-pin frequency. 977 */ 978 out.esync_n_period = (out.esync_n_period * out.div) / new_div; 979 if (!out.esync_n_period) 980 return -EINVAL; 981 982 /* Update the output divisor */ 983 out.div = new_div; 984 985 /* For 50/50 duty cycle the divisor is equal to width */ 986 out.width = out.div; 987 } else { 988 /* We are going to change frequency of N-pin but if 989 * the requested freq is greater or equal than freq of P-pin 990 * in the output pair we cannot compute divisor for the N-pin. 991 * In this case indicate a failure. 992 * 993 * Update divisor for N-pin 994 */ 995 out.esync_n_period = div64_u64(synth_freq, frequency * out.div); 996 if (!out.esync_n_period) 997 return -EINVAL; 998 } 999 1000 /* For 50/50 duty cycle the divisor is equal to width */ 1001 out.esync_n_width = out.esync_n_period; 1002 1003 /* Commit output configuration */ 1004 return zl3073x_out_state_set(zldev, out_id, &out); 1005 } 1006 1007 static int 1008 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 1009 void *pin_priv, 1010 const struct dpll_device *dpll, 1011 void *dpll_priv, 1012 s32 *phase_adjust, 1013 struct netlink_ext_ack *extack) 1014 { 1015 struct zl3073x_dpll *zldpll = dpll_priv; 1016 struct zl3073x_dev *zldev = zldpll->dev; 1017 struct zl3073x_dpll_pin *pin = pin_priv; 1018 const struct zl3073x_out *out; 1019 u8 out_id; 1020 1021 out_id = zl3073x_output_pin_out_get(pin->id); 1022 out = zl3073x_out_state_get(zldev, out_id); 1023 1024 /* The value in the register is expressed in half synth clock cycles. */ 1025 *phase_adjust = out->phase_comp * pin->phase_gran; 1026 1027 return 0; 1028 } 1029 1030 static int 1031 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 1032 void *pin_priv, 1033 const struct dpll_device *dpll, 1034 void *dpll_priv, 1035 s32 phase_adjust, 1036 struct netlink_ext_ack *extack) 1037 { 1038 struct zl3073x_dpll *zldpll = dpll_priv; 1039 struct zl3073x_dev *zldev = zldpll->dev; 1040 struct zl3073x_dpll_pin *pin = pin_priv; 1041 struct zl3073x_out out; 1042 u8 out_id; 1043 1044 out_id = zl3073x_output_pin_out_get(pin->id); 1045 out = *zl3073x_out_state_get(zldev, out_id); 1046 1047 /* The value in the register is expressed in half synth clock cycles. */ 1048 out.phase_comp = phase_adjust / pin->phase_gran; 1049 1050 /* Update output configuration from mailbox */ 1051 return zl3073x_out_state_set(zldev, out_id, &out); 1052 } 1053 1054 static int 1055 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 1056 void *pin_priv, 1057 const struct dpll_device *dpll, 1058 void *dpll_priv, 1059 enum dpll_pin_state *state, 1060 struct netlink_ext_ack *extack) 1061 { 1062 /* If the output pin is registered then it is always connected */ 1063 *state = DPLL_PIN_STATE_CONNECTED; 1064 1065 return 0; 1066 } 1067 1068 static int 1069 zl3073x_dpll_temp_get(const struct dpll_device *dpll, void *dpll_priv, 1070 s32 *temp, struct netlink_ext_ack *extack) 1071 { 1072 struct zl3073x_dpll *zldpll = dpll_priv; 1073 struct zl3073x_dev *zldev = zldpll->dev; 1074 u16 val; 1075 int rc; 1076 1077 rc = zl3073x_read_u16(zldev, ZL_REG_DIE_TEMP_STATUS, &val); 1078 if (rc) 1079 return rc; 1080 1081 /* Register value is in units of 0.1 C, convert to millidegrees */ 1082 *temp = (s16)val * 100; 1083 1084 return 0; 1085 } 1086 1087 static int 1088 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, 1089 enum dpll_lock_status *status, 1090 enum dpll_lock_status_error *status_error, 1091 struct netlink_ext_ack *extack) 1092 { 1093 struct zl3073x_dpll *zldpll = dpll_priv; 1094 struct zl3073x_dev *zldev = zldpll->dev; 1095 u8 mon_status, state; 1096 int rc; 1097 1098 switch (zldpll->refsel_mode) { 1099 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1100 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1101 /* In FREERUN and NCO modes the DPLL is always unlocked */ 1102 *status = DPLL_LOCK_STATUS_UNLOCKED; 1103 1104 return 0; 1105 default: 1106 break; 1107 } 1108 1109 /* Read DPLL monitor status */ 1110 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id), 1111 &mon_status); 1112 if (rc) 1113 return rc; 1114 state = FIELD_GET(ZL_DPLL_MON_STATUS_STATE, mon_status); 1115 1116 switch (state) { 1117 case ZL_DPLL_MON_STATUS_STATE_LOCK: 1118 if (FIELD_GET(ZL_DPLL_MON_STATUS_HO_READY, mon_status)) 1119 *status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 1120 else 1121 *status = DPLL_LOCK_STATUS_LOCKED; 1122 break; 1123 case ZL_DPLL_MON_STATUS_STATE_HOLDOVER: 1124 case ZL_DPLL_MON_STATUS_STATE_ACQUIRING: 1125 *status = DPLL_LOCK_STATUS_HOLDOVER; 1126 break; 1127 default: 1128 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n", 1129 mon_status); 1130 *status = DPLL_LOCK_STATUS_UNLOCKED; 1131 break; 1132 } 1133 1134 return 0; 1135 } 1136 1137 static int 1138 zl3073x_dpll_supported_modes_get(const struct dpll_device *dpll, 1139 void *dpll_priv, unsigned long *modes, 1140 struct netlink_ext_ack *extack) 1141 { 1142 struct zl3073x_dpll *zldpll = dpll_priv; 1143 1144 /* We support switching between automatic and manual mode, except in 1145 * a case where the DPLL channel is configured to run in NCO mode. 1146 * In this case, report only the manual mode to which the NCO is mapped 1147 * as the only supported one. 1148 */ 1149 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_NCO) 1150 __set_bit(DPLL_MODE_AUTOMATIC, modes); 1151 1152 __set_bit(DPLL_MODE_MANUAL, modes); 1153 1154 return 0; 1155 } 1156 1157 static int 1158 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, 1159 enum dpll_mode *mode, struct netlink_ext_ack *extack) 1160 { 1161 struct zl3073x_dpll *zldpll = dpll_priv; 1162 1163 switch (zldpll->refsel_mode) { 1164 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1165 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 1166 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1167 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 1168 /* Use MANUAL for device FREERUN, HOLDOVER, NCO and 1169 * REFLOCK modes 1170 */ 1171 *mode = DPLL_MODE_MANUAL; 1172 break; 1173 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 1174 /* Use AUTO for device AUTO mode */ 1175 *mode = DPLL_MODE_AUTOMATIC; 1176 break; 1177 default: 1178 return -EINVAL; 1179 } 1180 1181 return 0; 1182 } 1183 1184 static int 1185 zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device *dpll, 1186 void *dpll_priv, u32 *factor, 1187 struct netlink_ext_ack *extack) 1188 { 1189 struct zl3073x_dpll *zldpll = dpll_priv; 1190 1191 *factor = zl3073x_dev_phase_avg_factor_get(zldpll->dev); 1192 1193 return 0; 1194 } 1195 1196 static void 1197 zl3073x_dpll_change_work(struct work_struct *work) 1198 { 1199 struct zl3073x_dpll *zldpll; 1200 1201 zldpll = container_of(work, struct zl3073x_dpll, change_work); 1202 dpll_device_change_ntf(zldpll->dpll_dev); 1203 } 1204 1205 static int 1206 zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device *dpll, 1207 void *dpll_priv, u32 factor, 1208 struct netlink_ext_ack *extack) 1209 { 1210 struct zl3073x_dpll *item, *zldpll = dpll_priv; 1211 int rc; 1212 1213 if (factor > 15) { 1214 NL_SET_ERR_MSG_FMT(extack, 1215 "Phase offset average factor has to be from range <0,15>"); 1216 return -EINVAL; 1217 } 1218 1219 rc = zl3073x_dev_phase_avg_factor_set(zldpll->dev, factor); 1220 if (rc) { 1221 NL_SET_ERR_MSG_FMT(extack, 1222 "Failed to set phase offset averaging factor"); 1223 return rc; 1224 } 1225 1226 /* The averaging factor is common for all DPLL channels so after change 1227 * we have to send a notification for other DPLL devices. 1228 */ 1229 list_for_each_entry(item, &zldpll->dev->dplls, list) { 1230 if (item != zldpll) 1231 schedule_work(&item->change_work); 1232 } 1233 1234 return 0; 1235 } 1236 1237 static int 1238 zl3073x_dpll_mode_set(const struct dpll_device *dpll, void *dpll_priv, 1239 enum dpll_mode mode, struct netlink_ext_ack *extack) 1240 { 1241 struct zl3073x_dpll *zldpll = dpll_priv; 1242 u8 hw_mode, mode_refsel, ref; 1243 int rc; 1244 1245 rc = zl3073x_dpll_selected_ref_get(zldpll, &ref); 1246 if (rc) { 1247 NL_SET_ERR_MSG_MOD(extack, "failed to get selected reference"); 1248 return rc; 1249 } 1250 1251 if (mode == DPLL_MODE_MANUAL) { 1252 /* We are switching from automatic to manual mode: 1253 * - if we have a valid reference selected during auto mode then 1254 * we will switch to forced reference lock mode and use this 1255 * reference for selection 1256 * - if NO valid reference is selected, we will switch to forced 1257 * holdover mode or freerun mode, depending on the current 1258 * lock status 1259 */ 1260 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1261 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 1262 else if (zldpll->lock_status == DPLL_LOCK_STATUS_UNLOCKED) 1263 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 1264 else 1265 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 1266 } else { 1267 /* We are switching from manual to automatic mode: 1268 * - if there is a valid reference selected then ensure that 1269 * it is selectable after switch to automatic mode 1270 * - switch to automatic mode 1271 */ 1272 struct zl3073x_dpll_pin *pin; 1273 1274 pin = zl3073x_dpll_pin_get_by_ref(zldpll, ref); 1275 if (pin && !pin->selectable) { 1276 /* Restore pin priority in HW */ 1277 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 1278 if (rc) { 1279 NL_SET_ERR_MSG_MOD(extack, 1280 "failed to restore pin priority"); 1281 return rc; 1282 } 1283 1284 pin->selectable = true; 1285 } 1286 1287 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_AUTO; 1288 } 1289 1290 /* Build mode_refsel value */ 1291 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, hw_mode); 1292 1293 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1294 mode_refsel |= FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 1295 1296 /* Update dpll_mode_refsel register */ 1297 rc = zl3073x_write_u8(zldpll->dev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1298 mode_refsel); 1299 if (rc) { 1300 NL_SET_ERR_MSG_MOD(extack, 1301 "failed to set reference selection mode"); 1302 return rc; 1303 } 1304 1305 zldpll->refsel_mode = hw_mode; 1306 1307 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1308 zldpll->forced_ref = ref; 1309 1310 return 0; 1311 } 1312 1313 static int 1314 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll, 1315 void *dpll_priv, 1316 enum dpll_feature_state *state, 1317 struct netlink_ext_ack *extack) 1318 { 1319 struct zl3073x_dpll *zldpll = dpll_priv; 1320 1321 if (zldpll->phase_monitor) 1322 *state = DPLL_FEATURE_STATE_ENABLE; 1323 else 1324 *state = DPLL_FEATURE_STATE_DISABLE; 1325 1326 return 0; 1327 } 1328 1329 static int 1330 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll, 1331 void *dpll_priv, 1332 enum dpll_feature_state state, 1333 struct netlink_ext_ack *extack) 1334 { 1335 struct zl3073x_dpll *zldpll = dpll_priv; 1336 1337 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE); 1338 1339 return 0; 1340 } 1341 1342 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = { 1343 .direction_get = zl3073x_dpll_pin_direction_get, 1344 .esync_get = zl3073x_dpll_input_pin_esync_get, 1345 .esync_set = zl3073x_dpll_input_pin_esync_set, 1346 .ffo_get = zl3073x_dpll_input_pin_ffo_get, 1347 .frequency_get = zl3073x_dpll_input_pin_frequency_get, 1348 .frequency_set = zl3073x_dpll_input_pin_frequency_set, 1349 .phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get, 1350 .phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get, 1351 .phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set, 1352 .prio_get = zl3073x_dpll_input_pin_prio_get, 1353 .prio_set = zl3073x_dpll_input_pin_prio_set, 1354 .state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get, 1355 .state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set, 1356 }; 1357 1358 static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = { 1359 .direction_get = zl3073x_dpll_pin_direction_get, 1360 .esync_get = zl3073x_dpll_output_pin_esync_get, 1361 .esync_set = zl3073x_dpll_output_pin_esync_set, 1362 .frequency_get = zl3073x_dpll_output_pin_frequency_get, 1363 .frequency_set = zl3073x_dpll_output_pin_frequency_set, 1364 .phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get, 1365 .phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set, 1366 .state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get, 1367 }; 1368 1369 static const struct dpll_device_ops zl3073x_dpll_device_ops = { 1370 .lock_status_get = zl3073x_dpll_lock_status_get, 1371 .mode_get = zl3073x_dpll_mode_get, 1372 .mode_set = zl3073x_dpll_mode_set, 1373 .phase_offset_avg_factor_get = zl3073x_dpll_phase_offset_avg_factor_get, 1374 .phase_offset_avg_factor_set = zl3073x_dpll_phase_offset_avg_factor_set, 1375 .phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get, 1376 .phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set, 1377 .supported_modes_get = zl3073x_dpll_supported_modes_get, 1378 }; 1379 1380 /** 1381 * zl3073x_dpll_pin_alloc - allocate DPLL pin 1382 * @zldpll: pointer to zl3073x_dpll 1383 * @dir: pin direction 1384 * @id: pin id 1385 * 1386 * Allocates and initializes zl3073x_dpll_pin structure for given 1387 * pin id and direction. 1388 * 1389 * Return: pointer to allocated structure on success, error pointer on error 1390 */ 1391 static struct zl3073x_dpll_pin * 1392 zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir, 1393 u8 id) 1394 { 1395 struct zl3073x_dpll_pin *pin; 1396 1397 pin = kzalloc_obj(*pin); 1398 if (!pin) 1399 return ERR_PTR(-ENOMEM); 1400 1401 pin->dpll = zldpll; 1402 pin->dir = dir; 1403 pin->id = id; 1404 1405 return pin; 1406 } 1407 1408 /** 1409 * zl3073x_dpll_pin_free - deallocate DPLL pin 1410 * @pin: pin to free 1411 * 1412 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc. 1413 */ 1414 static void 1415 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin) 1416 { 1417 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); 1418 1419 kfree(pin); 1420 } 1421 1422 /** 1423 * zl3073x_dpll_pin_register - register DPLL pin 1424 * @pin: pointer to DPLL pin 1425 * @index: absolute pin index for registration 1426 * 1427 * Registers given DPLL pin into DPLL sub-system. 1428 * 1429 * Return: 0 on success, <0 on error 1430 */ 1431 static int 1432 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index) 1433 { 1434 struct zl3073x_dpll *zldpll = pin->dpll; 1435 struct zl3073x_pin_props *props; 1436 const struct dpll_pin_ops *ops; 1437 int rc; 1438 1439 /* Get pin properties */ 1440 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); 1441 if (IS_ERR(props)) 1442 return PTR_ERR(props); 1443 1444 /* Save package label, esync capability and phase adjust granularity */ 1445 strscpy(pin->label, props->package_label); 1446 pin->esync_control = props->esync_control; 1447 pin->phase_gran = props->dpll_props.phase_gran; 1448 1449 if (zl3073x_dpll_is_input_pin(pin)) { 1450 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); 1451 if (rc) 1452 goto err_prio_get; 1453 1454 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) { 1455 /* Clamp prio to max value & mark pin non-selectable */ 1456 pin->prio = ZL_DPLL_REF_PRIO_MAX; 1457 pin->selectable = false; 1458 } else { 1459 /* Mark pin as selectable */ 1460 pin->selectable = true; 1461 } 1462 } 1463 1464 /* Create or get existing DPLL pin */ 1465 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, 1466 &props->dpll_props, &pin->tracker); 1467 if (IS_ERR(pin->dpll_pin)) { 1468 rc = PTR_ERR(pin->dpll_pin); 1469 goto err_pin_get; 1470 } 1471 dpll_pin_fwnode_set(pin->dpll_pin, props->fwnode); 1472 1473 if (zl3073x_dpll_is_input_pin(pin)) 1474 ops = &zl3073x_dpll_input_pin_ops; 1475 else 1476 ops = &zl3073x_dpll_output_pin_ops; 1477 1478 /* Register the pin */ 1479 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1480 if (rc) 1481 goto err_register; 1482 1483 /* Free pin properties */ 1484 zl3073x_pin_props_put(props); 1485 1486 return 0; 1487 1488 err_register: 1489 dpll_pin_put(pin->dpll_pin, &pin->tracker); 1490 err_prio_get: 1491 pin->dpll_pin = NULL; 1492 err_pin_get: 1493 zl3073x_pin_props_put(props); 1494 1495 return rc; 1496 } 1497 1498 /** 1499 * zl3073x_dpll_pin_unregister - unregister DPLL pin 1500 * @pin: pointer to DPLL pin 1501 * 1502 * Unregisters pin previously registered by @zl3073x_dpll_pin_register. 1503 */ 1504 static void 1505 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin) 1506 { 1507 struct zl3073x_dpll *zldpll = pin->dpll; 1508 const struct dpll_pin_ops *ops; 1509 1510 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); 1511 1512 if (zl3073x_dpll_is_input_pin(pin)) 1513 ops = &zl3073x_dpll_input_pin_ops; 1514 else 1515 ops = &zl3073x_dpll_output_pin_ops; 1516 1517 /* Unregister the pin */ 1518 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1519 1520 dpll_pin_put(pin->dpll_pin, &pin->tracker); 1521 pin->dpll_pin = NULL; 1522 } 1523 1524 /** 1525 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins 1526 * @zldpll: pointer to zl3073x_dpll structure 1527 * 1528 * Enumerates all DPLL pins registered to given DPLL device and 1529 * unregisters them. 1530 */ 1531 static void 1532 zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll) 1533 { 1534 struct zl3073x_dpll_pin *pin, *next; 1535 1536 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { 1537 zl3073x_dpll_pin_unregister(pin); 1538 list_del(&pin->list); 1539 zl3073x_dpll_pin_free(pin); 1540 } 1541 } 1542 1543 /** 1544 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable 1545 * @zldpll: pointer to zl3073x_dpll structure 1546 * @dir: pin direction 1547 * @index: pin index 1548 * 1549 * Checks if the given pin can be registered to given DPLL. For both 1550 * directions the pin can be registered if it is enabled. In case of 1551 * differential signal type only P-pin is reported as registrable. 1552 * And additionally for the output pin, the pin can be registered only 1553 * if it is connected to synthesizer that is driven by given DPLL. 1554 * 1555 * Return: true if the pin is registrable, false if not 1556 */ 1557 static bool 1558 zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll, 1559 enum dpll_pin_direction dir, u8 index) 1560 { 1561 struct zl3073x_dev *zldev = zldpll->dev; 1562 bool is_diff, is_enabled; 1563 const char *name; 1564 1565 if (dir == DPLL_PIN_DIRECTION_INPUT) { 1566 u8 ref_id = zl3073x_input_pin_ref_get(index); 1567 const struct zl3073x_ref *ref; 1568 1569 /* Skip the pin if the DPLL is running in NCO mode */ 1570 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO) 1571 return false; 1572 1573 name = "REF"; 1574 ref = zl3073x_ref_state_get(zldev, ref_id); 1575 is_diff = zl3073x_ref_is_diff(ref); 1576 is_enabled = zl3073x_ref_is_enabled(ref); 1577 } else { 1578 /* Output P&N pair shares single HW output */ 1579 u8 out = zl3073x_output_pin_out_get(index); 1580 1581 /* Skip the pin if it is connected to different DPLL channel */ 1582 if (zl3073x_dev_out_dpll_get(zldev, out) != zldpll->id) { 1583 dev_dbg(zldev->dev, 1584 "OUT%u is driven by different DPLL\n", out); 1585 1586 return false; 1587 } 1588 1589 name = "OUT"; 1590 is_diff = zl3073x_dev_out_is_diff(zldev, out); 1591 is_enabled = zl3073x_dev_output_pin_is_enabled(zldev, index); 1592 } 1593 1594 /* Skip N-pin if the corresponding input/output is differential */ 1595 if (is_diff && zl3073x_is_n_pin(index)) { 1596 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", 1597 name, index / 2); 1598 1599 return false; 1600 } 1601 1602 /* Skip the pin if it is disabled */ 1603 if (!is_enabled) { 1604 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, 1605 zl3073x_is_p_pin(index) ? 'P' : 'N'); 1606 1607 return false; 1608 } 1609 1610 return true; 1611 } 1612 1613 /** 1614 * zl3073x_dpll_pins_register - register all registerable DPLL pins 1615 * @zldpll: pointer to zl3073x_dpll structure 1616 * 1617 * Enumerates all possible input/output pins and registers all of them 1618 * that are registrable. 1619 * 1620 * Return: 0 on success, <0 on error 1621 */ 1622 static int 1623 zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll) 1624 { 1625 struct zl3073x_dpll_pin *pin; 1626 enum dpll_pin_direction dir; 1627 u8 id, index; 1628 int rc; 1629 1630 /* Process input pins */ 1631 for (index = 0; index < ZL3073X_NUM_PINS; index++) { 1632 /* First input pins and then output pins */ 1633 if (index < ZL3073X_NUM_INPUT_PINS) { 1634 id = index; 1635 dir = DPLL_PIN_DIRECTION_INPUT; 1636 } else { 1637 id = index - ZL3073X_NUM_INPUT_PINS; 1638 dir = DPLL_PIN_DIRECTION_OUTPUT; 1639 } 1640 1641 /* Check if the pin registrable to this DPLL */ 1642 if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id)) 1643 continue; 1644 1645 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id); 1646 if (IS_ERR(pin)) { 1647 rc = PTR_ERR(pin); 1648 goto error; 1649 } 1650 1651 rc = zl3073x_dpll_pin_register(pin, index); 1652 if (rc) 1653 goto error; 1654 1655 list_add(&pin->list, &zldpll->pins); 1656 } 1657 1658 return 0; 1659 1660 error: 1661 zl3073x_dpll_pins_unregister(zldpll); 1662 1663 return rc; 1664 } 1665 1666 /** 1667 * zl3073x_dpll_device_register - register DPLL device 1668 * @zldpll: pointer to zl3073x_dpll structure 1669 * 1670 * Registers given DPLL device into DPLL sub-system. 1671 * 1672 * Return: 0 on success, <0 on error 1673 */ 1674 static int 1675 zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll) 1676 { 1677 struct zl3073x_dev *zldev = zldpll->dev; 1678 u8 dpll_mode_refsel; 1679 int rc; 1680 1681 /* Read DPLL mode and forcibly selected reference */ 1682 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1683 &dpll_mode_refsel); 1684 if (rc) 1685 return rc; 1686 1687 /* Extract mode and selected input reference */ 1688 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE, 1689 dpll_mode_refsel); 1690 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF, 1691 dpll_mode_refsel); 1692 1693 zldpll->ops = zl3073x_dpll_device_ops; 1694 if (zldev->info->flags & ZL3073X_FLAG_DIE_TEMP) 1695 zldpll->ops.temp_get = zl3073x_dpll_temp_get; 1696 1697 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, 1698 THIS_MODULE, &zldpll->tracker); 1699 if (IS_ERR(zldpll->dpll_dev)) { 1700 rc = PTR_ERR(zldpll->dpll_dev); 1701 zldpll->dpll_dev = NULL; 1702 1703 return rc; 1704 } 1705 1706 rc = dpll_device_register(zldpll->dpll_dev, 1707 zl3073x_prop_dpll_type_get(zldev, zldpll->id), 1708 &zldpll->ops, zldpll); 1709 if (rc) { 1710 dpll_device_put(zldpll->dpll_dev, &zldpll->tracker); 1711 zldpll->dpll_dev = NULL; 1712 } 1713 1714 return rc; 1715 } 1716 1717 /** 1718 * zl3073x_dpll_device_unregister - unregister DPLL device 1719 * @zldpll: pointer to zl3073x_dpll structure 1720 * 1721 * Unregisters given DPLL device from DPLL sub-system previously registered 1722 * by @zl3073x_dpll_device_register. 1723 */ 1724 static void 1725 zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll) 1726 { 1727 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n"); 1728 1729 cancel_work_sync(&zldpll->change_work); 1730 1731 dpll_device_unregister(zldpll->dpll_dev, &zldpll->ops, zldpll); 1732 dpll_device_put(zldpll->dpll_dev, &zldpll->tracker); 1733 zldpll->dpll_dev = NULL; 1734 } 1735 1736 /** 1737 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change 1738 * @pin: pin to check 1739 * 1740 * Check for the change of DPLL to connected pin phase offset change. 1741 * 1742 * Return: true on phase offset change, false otherwise 1743 */ 1744 static bool 1745 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin) 1746 { 1747 struct zl3073x_dpll *zldpll = pin->dpll; 1748 struct zl3073x_dev *zldev = zldpll->dev; 1749 unsigned int reg; 1750 s64 phase_offset; 1751 u8 ref_id; 1752 int rc; 1753 1754 /* No phase offset if the ref monitor reports signal errors */ 1755 ref_id = zl3073x_input_pin_ref_get(pin->id); 1756 if (!zl3073x_dev_ref_is_status_ok(zldev, ref_id)) 1757 return false; 1758 1759 /* Select register to read phase offset value depending on pin and 1760 * phase monitor state: 1761 * 1) For connected pin use dpll_phase_err_data register 1762 * 2) For other pins use appropriate ref_phase register if the phase 1763 * monitor feature is enabled. 1764 */ 1765 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) 1766 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); 1767 else if (zldpll->phase_monitor) 1768 reg = ZL_REG_REF_PHASE(ref_id); 1769 else 1770 return false; 1771 1772 /* Read measured phase offset value */ 1773 rc = zl3073x_read_u48(zldev, reg, &phase_offset); 1774 if (rc) { 1775 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n", 1776 ERR_PTR(rc)); 1777 1778 return false; 1779 } 1780 1781 /* Convert to ps */ 1782 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100); 1783 1784 /* Compare with previous value */ 1785 if (phase_offset != pin->phase_offset) { 1786 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n", 1787 pin->label, pin->phase_offset, phase_offset); 1788 pin->phase_offset = phase_offset; 1789 1790 return true; 1791 } 1792 1793 return false; 1794 } 1795 1796 /** 1797 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change 1798 * @pin: pin to check 1799 * 1800 * Check for the given pin's fractional frequency change. 1801 * 1802 * Return: true on fractional frequency offset change, false otherwise 1803 */ 1804 static bool 1805 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin) 1806 { 1807 struct zl3073x_dpll *zldpll = pin->dpll; 1808 struct zl3073x_dev *zldev = zldpll->dev; 1809 const struct zl3073x_ref *ref; 1810 u8 ref_id; 1811 1812 /* Get reference monitor status */ 1813 ref_id = zl3073x_input_pin_ref_get(pin->id); 1814 ref = zl3073x_ref_state_get(zldev, ref_id); 1815 1816 /* Do not report ffo changes if the reference monitor report errors */ 1817 if (!zl3073x_ref_is_status_ok(ref)) 1818 return false; 1819 1820 /* Compare with previous value */ 1821 if (pin->freq_offset != ref->ffo) { 1822 dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n", 1823 pin->label, pin->freq_offset, ref->ffo); 1824 pin->freq_offset = ref->ffo; 1825 1826 return true; 1827 } 1828 1829 return false; 1830 } 1831 1832 /** 1833 * zl3073x_dpll_changes_check - check for changes and send notifications 1834 * @zldpll: pointer to zl3073x_dpll structure 1835 * 1836 * Checks for changes on given DPLL device and its registered DPLL pins 1837 * and sends notifications about them. 1838 * 1839 * This function is periodically called from @zl3073x_dev_periodic_work. 1840 */ 1841 void 1842 zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll) 1843 { 1844 struct zl3073x_dev *zldev = zldpll->dev; 1845 enum dpll_lock_status lock_status; 1846 struct device *dev = zldev->dev; 1847 struct zl3073x_dpll_pin *pin; 1848 int rc; 1849 1850 zldpll->check_count++; 1851 1852 /* Get current lock status for the DPLL */ 1853 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, 1854 &lock_status, NULL, NULL); 1855 if (rc) { 1856 dev_err(dev, "Failed to get DPLL%u lock status: %pe\n", 1857 zldpll->id, ERR_PTR(rc)); 1858 return; 1859 } 1860 1861 /* If lock status was changed then notify DPLL core */ 1862 if (zldpll->lock_status != lock_status) { 1863 zldpll->lock_status = lock_status; 1864 dpll_device_change_ntf(zldpll->dpll_dev); 1865 } 1866 1867 /* Input pin monitoring does make sense only in automatic 1868 * or forced reference modes. 1869 */ 1870 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO && 1871 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK) 1872 return; 1873 1874 /* Update phase offset latch registers for this DPLL if the phase 1875 * offset monitor feature is enabled. 1876 */ 1877 if (zldpll->phase_monitor) { 1878 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id); 1879 if (rc) { 1880 dev_err(zldev->dev, 1881 "Failed to update phase offsets: %pe\n", 1882 ERR_PTR(rc)); 1883 return; 1884 } 1885 } 1886 1887 list_for_each_entry(pin, &zldpll->pins, list) { 1888 enum dpll_pin_state state; 1889 bool pin_changed = false; 1890 1891 /* Output pins change checks are not necessary because output 1892 * states are constant. 1893 */ 1894 if (!zl3073x_dpll_is_input_pin(pin)) 1895 continue; 1896 1897 rc = zl3073x_dpll_ref_state_get(pin, &state); 1898 if (rc) { 1899 dev_err(dev, 1900 "Failed to get %s on DPLL%u state: %pe\n", 1901 pin->label, zldpll->id, ERR_PTR(rc)); 1902 return; 1903 } 1904 1905 if (state != pin->pin_state) { 1906 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, 1907 pin->pin_state, state); 1908 pin->pin_state = state; 1909 pin_changed = true; 1910 } 1911 1912 /* Check for phase offset and ffo change once per second */ 1913 if (zldpll->check_count % 2 == 0) { 1914 if (zl3073x_dpll_pin_phase_offset_check(pin)) 1915 pin_changed = true; 1916 1917 if (zl3073x_dpll_pin_ffo_check(pin)) 1918 pin_changed = true; 1919 } 1920 1921 if (pin_changed) 1922 dpll_pin_change_ntf(pin->dpll_pin); 1923 } 1924 } 1925 1926 /** 1927 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments 1928 * @zldev: pointer to zl3073x device 1929 * 1930 * Performs initial fine phase adjustments needed per datasheet. 1931 * 1932 * Return: 0 on success, <0 on error 1933 */ 1934 int 1935 zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev) 1936 { 1937 int rc; 1938 1939 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); 1940 if (rc) 1941 return rc; 1942 1943 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); 1944 if (rc) 1945 return rc; 1946 1947 rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff); 1948 if (rc) 1949 return rc; 1950 1951 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); 1952 if (rc) 1953 return rc; 1954 1955 return rc; 1956 } 1957 1958 /** 1959 * zl3073x_dpll_alloc - allocate DPLL device 1960 * @zldev: pointer to zl3073x device 1961 * @ch: DPLL channel number 1962 * 1963 * Allocates DPLL device structure for given DPLL channel. 1964 * 1965 * Return: pointer to DPLL device on success, error pointer on error 1966 */ 1967 struct zl3073x_dpll * 1968 zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch) 1969 { 1970 struct zl3073x_dpll *zldpll; 1971 1972 zldpll = kzalloc_obj(*zldpll); 1973 if (!zldpll) 1974 return ERR_PTR(-ENOMEM); 1975 1976 zldpll->dev = zldev; 1977 zldpll->id = ch; 1978 INIT_LIST_HEAD(&zldpll->pins); 1979 INIT_WORK(&zldpll->change_work, zl3073x_dpll_change_work); 1980 1981 return zldpll; 1982 } 1983 1984 /** 1985 * zl3073x_dpll_free - free DPLL device 1986 * @zldpll: pointer to zl3073x_dpll structure 1987 * 1988 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc. 1989 */ 1990 void 1991 zl3073x_dpll_free(struct zl3073x_dpll *zldpll) 1992 { 1993 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); 1994 1995 kfree(zldpll); 1996 } 1997 1998 /** 1999 * zl3073x_dpll_register - register DPLL device and all its pins 2000 * @zldpll: pointer to zl3073x_dpll structure 2001 * 2002 * Registers given DPLL device and all its pins into DPLL sub-system. 2003 * 2004 * Return: 0 on success, <0 on error 2005 */ 2006 int 2007 zl3073x_dpll_register(struct zl3073x_dpll *zldpll) 2008 { 2009 int rc; 2010 2011 rc = zl3073x_dpll_device_register(zldpll); 2012 if (rc) 2013 return rc; 2014 2015 rc = zl3073x_dpll_pins_register(zldpll); 2016 if (rc) { 2017 zl3073x_dpll_device_unregister(zldpll); 2018 return rc; 2019 } 2020 2021 return 0; 2022 } 2023 2024 /** 2025 * zl3073x_dpll_unregister - unregister DPLL device and its pins 2026 * @zldpll: pointer to zl3073x_dpll structure 2027 * 2028 * Unregisters given DPLL device and all its pins from DPLL sub-system 2029 * previously registered by @zl3073x_dpll_register. 2030 */ 2031 void 2032 zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll) 2033 { 2034 /* Unregister all pins and dpll */ 2035 zl3073x_dpll_pins_unregister(zldpll); 2036 zl3073x_dpll_device_unregister(zldpll); 2037 } 2038