1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bits.h> 4 #include <linux/bitfield.h> 5 #include <linux/bug.h> 6 #include <linux/container_of.h> 7 #include <linux/dev_printk.h> 8 #include <linux/dpll.h> 9 #include <linux/err.h> 10 #include <linux/kthread.h> 11 #include <linux/math64.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/netlink.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/sprintf.h> 18 19 #include "core.h" 20 #include "dpll.h" 21 #include "prop.h" 22 #include "regs.h" 23 24 #define ZL3073X_DPLL_REF_NONE ZL3073X_NUM_REFS 25 #define ZL3073X_DPLL_REF_IS_VALID(_ref) ((_ref) != ZL3073X_DPLL_REF_NONE) 26 27 /** 28 * struct zl3073x_dpll_pin - DPLL pin 29 * @list: this DPLL pin list entry 30 * @dpll: DPLL the pin is registered to 31 * @dpll_pin: pointer to registered dpll_pin 32 * @tracker: tracking object for the acquired reference 33 * @label: package label 34 * @dir: pin direction 35 * @id: pin id 36 * @prio: pin priority <0, 14> 37 * @selectable: pin is selectable in automatic mode 38 * @esync_control: embedded sync is controllable 39 * @phase_gran: phase adjustment granularity 40 * @pin_state: last saved pin state 41 * @phase_offset: last saved pin phase offset 42 * @freq_offset: last saved fractional frequency offset 43 */ 44 struct zl3073x_dpll_pin { 45 struct list_head list; 46 struct zl3073x_dpll *dpll; 47 struct dpll_pin *dpll_pin; 48 dpll_tracker tracker; 49 char label[8]; 50 enum dpll_pin_direction dir; 51 u8 id; 52 u8 prio; 53 bool selectable; 54 bool esync_control; 55 s32 phase_gran; 56 enum dpll_pin_state pin_state; 57 s64 phase_offset; 58 s64 freq_offset; 59 }; 60 61 /* 62 * Supported esync ranges for input and for output per output pair type 63 */ 64 static const struct dpll_pin_frequency esync_freq_ranges[] = { 65 DPLL_PIN_FREQUENCY_RANGE(0, 1), 66 }; 67 68 /** 69 * zl3073x_dpll_is_input_pin - check if the pin is input one 70 * @pin: pin to check 71 * 72 * Return: true if pin is input, false if pin is output. 73 */ 74 static bool 75 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin) 76 { 77 return pin->dir == DPLL_PIN_DIRECTION_INPUT; 78 } 79 80 /** 81 * zl3073x_dpll_is_p_pin - check if the pin is P-pin 82 * @pin: pin to check 83 * 84 * Return: true if the pin is P-pin, false if it is N-pin 85 */ 86 static bool 87 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin) 88 { 89 return zl3073x_is_p_pin(pin->id); 90 } 91 92 static int 93 zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv, 94 const struct dpll_device *dpll, void *dpll_priv, 95 enum dpll_pin_direction *direction, 96 struct netlink_ext_ack *extack) 97 { 98 struct zl3073x_dpll_pin *pin = pin_priv; 99 100 *direction = pin->dir; 101 102 return 0; 103 } 104 105 static struct zl3073x_dpll_pin * 106 zl3073x_dpll_pin_get_by_ref(struct zl3073x_dpll *zldpll, u8 ref_id) 107 { 108 struct zl3073x_dpll_pin *pin; 109 110 list_for_each_entry(pin, &zldpll->pins, list) { 111 if (zl3073x_dpll_is_input_pin(pin) && 112 zl3073x_input_pin_ref_get(pin->id) == ref_id) 113 return pin; 114 } 115 116 return NULL; 117 } 118 119 static int 120 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, 121 void *pin_priv, 122 const struct dpll_device *dpll, 123 void *dpll_priv, 124 struct dpll_pin_esync *esync, 125 struct netlink_ext_ack *extack) 126 { 127 struct zl3073x_dpll *zldpll = dpll_priv; 128 struct zl3073x_dev *zldev = zldpll->dev; 129 struct zl3073x_dpll_pin *pin = pin_priv; 130 const struct zl3073x_ref *ref; 131 u8 ref_id; 132 133 ref_id = zl3073x_input_pin_ref_get(pin->id); 134 ref = zl3073x_ref_state_get(zldev, ref_id); 135 136 switch (FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref->sync_ctrl)) { 137 case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: 138 esync->freq = ref->esync_n_div == ZL_REF_ESYNC_DIV_1HZ ? 1 : 0; 139 esync->pulse = 25; 140 break; 141 default: 142 esync->freq = 0; 143 esync->pulse = 0; 144 break; 145 } 146 147 /* If the pin supports esync control expose its range but only 148 * if the current reference frequency is > 1 Hz. 149 */ 150 if (pin->esync_control && zl3073x_ref_freq_get(ref) > 1) { 151 esync->range = esync_freq_ranges; 152 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 153 } else { 154 esync->range = NULL; 155 esync->range_num = 0; 156 } 157 158 return 0; 159 } 160 161 static int 162 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin, 163 void *pin_priv, 164 const struct dpll_device *dpll, 165 void *dpll_priv, u64 freq, 166 struct netlink_ext_ack *extack) 167 { 168 struct zl3073x_dpll *zldpll = dpll_priv; 169 struct zl3073x_dev *zldev = zldpll->dev; 170 struct zl3073x_dpll_pin *pin = pin_priv; 171 struct zl3073x_ref ref; 172 u8 ref_id, sync_mode; 173 174 ref_id = zl3073x_input_pin_ref_get(pin->id); 175 ref = *zl3073x_ref_state_get(zldev, ref_id); 176 177 /* Use freq == 0 to disable esync */ 178 if (!freq) 179 sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF; 180 else 181 sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75; 182 183 ref.sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE; 184 ref.sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode); 185 186 if (freq) { 187 /* 1 Hz is only supported frequency now */ 188 ref.esync_n_div = ZL_REF_ESYNC_DIV_1HZ; 189 } 190 191 /* Update reference configuration */ 192 return zl3073x_ref_state_set(zldev, ref_id, &ref); 193 } 194 195 static int 196 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv, 197 const struct dpll_device *dpll, void *dpll_priv, 198 s64 *ffo, struct netlink_ext_ack *extack) 199 { 200 struct zl3073x_dpll_pin *pin = pin_priv; 201 202 *ffo = pin->freq_offset; 203 204 return 0; 205 } 206 207 static int 208 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin, 209 void *pin_priv, 210 const struct dpll_device *dpll, 211 void *dpll_priv, u64 *frequency, 212 struct netlink_ext_ack *extack) 213 { 214 struct zl3073x_dpll *zldpll = dpll_priv; 215 struct zl3073x_dpll_pin *pin = pin_priv; 216 u8 ref_id; 217 218 ref_id = zl3073x_input_pin_ref_get(pin->id); 219 *frequency = zl3073x_dev_ref_freq_get(zldpll->dev, ref_id); 220 221 return 0; 222 } 223 224 static int 225 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin, 226 void *pin_priv, 227 const struct dpll_device *dpll, 228 void *dpll_priv, u64 frequency, 229 struct netlink_ext_ack *extack) 230 { 231 struct zl3073x_dpll *zldpll = dpll_priv; 232 struct zl3073x_dev *zldev = zldpll->dev; 233 struct zl3073x_dpll_pin *pin = pin_priv; 234 struct zl3073x_ref ref; 235 u8 ref_id; 236 237 /* Get reference state */ 238 ref_id = zl3073x_input_pin_ref_get(pin->id); 239 ref = *zl3073x_ref_state_get(zldev, ref_id); 240 241 /* Update frequency */ 242 zl3073x_ref_freq_set(&ref, frequency); 243 244 /* Commit reference state */ 245 return zl3073x_ref_state_set(zldev, ref_id, &ref); 246 } 247 248 /** 249 * zl3073x_dpll_selected_ref_get - get currently selected reference 250 * @zldpll: pointer to zl3073x_dpll 251 * @ref: place to store selected reference 252 * 253 * Check for currently selected reference the DPLL should be locked to 254 * and stores its index to given @ref. 255 * 256 * Return: 0 on success, <0 on error 257 */ 258 static int 259 zl3073x_dpll_selected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 260 { 261 struct zl3073x_dev *zldev = zldpll->dev; 262 u8 state, value; 263 int rc; 264 265 switch (zldpll->refsel_mode) { 266 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 267 /* For automatic mode read refsel_status register */ 268 rc = zl3073x_read_u8(zldev, 269 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id), 270 &value); 271 if (rc) 272 return rc; 273 274 /* Extract reference state */ 275 state = FIELD_GET(ZL_DPLL_REFSEL_STATUS_STATE, value); 276 277 /* Return the reference only if the DPLL is locked to it */ 278 if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK) 279 *ref = FIELD_GET(ZL_DPLL_REFSEL_STATUS_REFSEL, value); 280 else 281 *ref = ZL3073X_DPLL_REF_NONE; 282 break; 283 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 284 /* For manual mode return stored value */ 285 *ref = zldpll->forced_ref; 286 break; 287 default: 288 /* For other modes like NCO, freerun... there is no input ref */ 289 *ref = ZL3073X_DPLL_REF_NONE; 290 break; 291 } 292 293 return 0; 294 } 295 296 /** 297 * zl3073x_dpll_selected_ref_set - select reference in manual mode 298 * @zldpll: pointer to zl3073x_dpll 299 * @ref: input reference to be selected 300 * 301 * Selects the given reference for the DPLL channel it should be 302 * locked to. 303 * 304 * Return: 0 on success, <0 on error 305 */ 306 static int 307 zl3073x_dpll_selected_ref_set(struct zl3073x_dpll *zldpll, u8 ref) 308 { 309 struct zl3073x_dev *zldev = zldpll->dev; 310 u8 mode, mode_refsel; 311 int rc; 312 313 mode = zldpll->refsel_mode; 314 315 switch (mode) { 316 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 317 /* Manual mode with ref selected */ 318 if (ref == ZL3073X_DPLL_REF_NONE) { 319 switch (zldpll->lock_status) { 320 case DPLL_LOCK_STATUS_LOCKED_HO_ACQ: 321 case DPLL_LOCK_STATUS_HOLDOVER: 322 /* Switch to forced holdover */ 323 mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 324 break; 325 default: 326 /* Switch to freerun */ 327 mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 328 break; 329 } 330 /* Keep selected reference */ 331 ref = zldpll->forced_ref; 332 } else if (ref == zldpll->forced_ref) { 333 /* No register update - same mode and same ref */ 334 return 0; 335 } 336 break; 337 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 338 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 339 /* Manual mode without no ref */ 340 if (ref == ZL3073X_DPLL_REF_NONE) 341 /* No register update - keep current mode */ 342 return 0; 343 344 /* Switch to reflock mode and update ref selection */ 345 mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 346 break; 347 default: 348 /* For other modes like automatic or NCO ref cannot be selected 349 * manually 350 */ 351 return -EOPNOTSUPP; 352 } 353 354 /* Build mode_refsel value */ 355 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode) | 356 FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 357 358 /* Update dpll_mode_refsel register */ 359 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 360 mode_refsel); 361 if (rc) 362 return rc; 363 364 /* Store new mode and forced reference */ 365 zldpll->refsel_mode = mode; 366 zldpll->forced_ref = ref; 367 368 return rc; 369 } 370 371 /** 372 * zl3073x_dpll_connected_ref_get - get currently connected reference 373 * @zldpll: pointer to zl3073x_dpll 374 * @ref: place to store selected reference 375 * 376 * Looks for currently connected the DPLL is locked to and stores its index 377 * to given @ref. 378 * 379 * Return: 0 on success, <0 on error 380 */ 381 static int 382 zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 383 { 384 struct zl3073x_dev *zldev = zldpll->dev; 385 int rc; 386 387 /* Get currently selected input reference */ 388 rc = zl3073x_dpll_selected_ref_get(zldpll, ref); 389 if (rc) 390 return rc; 391 392 /* If the monitor indicates an error nothing is connected */ 393 if (ZL3073X_DPLL_REF_IS_VALID(*ref) && 394 !zl3073x_dev_ref_is_status_ok(zldev, *ref)) 395 *ref = ZL3073X_DPLL_REF_NONE; 396 397 return 0; 398 } 399 400 static int 401 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin, 402 void *pin_priv, 403 const struct dpll_device *dpll, 404 void *dpll_priv, s64 *phase_offset, 405 struct netlink_ext_ack *extack) 406 { 407 struct zl3073x_dpll *zldpll = dpll_priv; 408 struct zl3073x_dev *zldev = zldpll->dev; 409 struct zl3073x_dpll_pin *pin = pin_priv; 410 const struct zl3073x_ref *ref; 411 u8 conn_id, ref_id; 412 s64 ref_phase; 413 int rc; 414 415 /* Get currently connected reference */ 416 rc = zl3073x_dpll_connected_ref_get(zldpll, &conn_id); 417 if (rc) 418 return rc; 419 420 /* Report phase offset only for currently connected pin if the phase 421 * monitor feature is disabled and only if the input pin signal is 422 * present. 423 */ 424 ref_id = zl3073x_input_pin_ref_get(pin->id); 425 ref = zl3073x_ref_state_get(zldev, ref_id); 426 if ((!zldpll->phase_monitor && ref_id != conn_id) || 427 !zl3073x_ref_is_status_ok(ref)) { 428 *phase_offset = 0; 429 return 0; 430 } 431 432 ref_phase = pin->phase_offset; 433 434 /* The DPLL being locked to a higher freq than the current ref 435 * the phase offset is modded to the period of the signal 436 * the dpll is locked to. 437 */ 438 if (ZL3073X_DPLL_REF_IS_VALID(conn_id) && conn_id != ref_id) { 439 u32 conn_freq, ref_freq; 440 441 /* Get frequency of connected and given ref */ 442 conn_freq = zl3073x_dev_ref_freq_get(zldev, conn_id); 443 ref_freq = zl3073x_ref_freq_get(ref); 444 445 if (conn_freq > ref_freq) { 446 s64 conn_period, div_factor; 447 448 conn_period = div_s64(PSEC_PER_SEC, conn_freq); 449 div_factor = div64_s64(ref_phase, conn_period); 450 ref_phase -= conn_period * div_factor; 451 } 452 } 453 454 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER; 455 456 return rc; 457 } 458 459 static int 460 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 461 void *pin_priv, 462 const struct dpll_device *dpll, 463 void *dpll_priv, 464 s32 *phase_adjust, 465 struct netlink_ext_ack *extack) 466 { 467 struct zl3073x_dpll *zldpll = dpll_priv; 468 struct zl3073x_dev *zldev = zldpll->dev; 469 struct zl3073x_dpll_pin *pin = pin_priv; 470 const struct zl3073x_ref *ref; 471 s64 phase_comp; 472 u8 ref_id; 473 474 /* Read reference configuration */ 475 ref_id = zl3073x_input_pin_ref_get(pin->id); 476 ref = zl3073x_ref_state_get(zldev, ref_id); 477 478 /* Perform sign extension based on register width */ 479 if (zl3073x_dev_is_ref_phase_comp_32bit(zldev)) 480 phase_comp = sign_extend64(ref->phase_comp, 31); 481 else 482 phase_comp = sign_extend64(ref->phase_comp, 47); 483 484 /* Reverse two's complement negation applied during set and convert 485 * to 32bit signed int 486 */ 487 *phase_adjust = (s32)-phase_comp; 488 489 return 0; 490 } 491 492 static int 493 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 494 void *pin_priv, 495 const struct dpll_device *dpll, 496 void *dpll_priv, 497 s32 phase_adjust, 498 struct netlink_ext_ack *extack) 499 { 500 struct zl3073x_dpll *zldpll = dpll_priv; 501 struct zl3073x_dev *zldev = zldpll->dev; 502 struct zl3073x_dpll_pin *pin = pin_priv; 503 struct zl3073x_ref ref; 504 u8 ref_id; 505 506 /* Read reference configuration */ 507 ref_id = zl3073x_input_pin_ref_get(pin->id); 508 ref = *zl3073x_ref_state_get(zldev, ref_id); 509 510 /* The value in the register is stored as two's complement negation 511 * of requested value. 512 */ 513 ref.phase_comp = -phase_adjust; 514 515 /* Update reference configuration */ 516 return zl3073x_ref_state_set(zldev, ref_id, &ref); 517 } 518 519 /** 520 * zl3073x_dpll_ref_prio_get - get priority for given input pin 521 * @pin: pointer to pin 522 * @prio: place to store priority 523 * 524 * Reads current priority for the given input pin and stores the value 525 * to @prio. 526 * 527 * Return: 0 on success, <0 on error 528 */ 529 static int 530 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio) 531 { 532 struct zl3073x_dpll *zldpll = pin->dpll; 533 struct zl3073x_dev *zldev = zldpll->dev; 534 u8 ref, ref_prio; 535 int rc; 536 537 guard(mutex)(&zldev->multiop_lock); 538 539 /* Read DPLL configuration */ 540 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 541 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 542 if (rc) 543 return rc; 544 545 /* Read reference priority - one value for P&N pins (4 bits/pin) */ 546 ref = zl3073x_input_pin_ref_get(pin->id); 547 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), 548 &ref_prio); 549 if (rc) 550 return rc; 551 552 /* Select nibble according pin type */ 553 if (zl3073x_dpll_is_p_pin(pin)) 554 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_P, ref_prio); 555 else 556 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_N, ref_prio); 557 558 return rc; 559 } 560 561 /** 562 * zl3073x_dpll_ref_prio_set - set priority for given input pin 563 * @pin: pointer to pin 564 * @prio: place to store priority 565 * 566 * Sets priority for the given input pin. 567 * 568 * Return: 0 on success, <0 on error 569 */ 570 static int 571 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio) 572 { 573 struct zl3073x_dpll *zldpll = pin->dpll; 574 struct zl3073x_dev *zldev = zldpll->dev; 575 u8 ref, ref_prio; 576 int rc; 577 578 guard(mutex)(&zldev->multiop_lock); 579 580 /* Read DPLL configuration into mailbox */ 581 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 582 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 583 if (rc) 584 return rc; 585 586 /* Read reference priority - one value shared between P&N pins */ 587 ref = zl3073x_input_pin_ref_get(pin->id); 588 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio); 589 if (rc) 590 return rc; 591 592 /* Update nibble according pin type */ 593 if (zl3073x_dpll_is_p_pin(pin)) { 594 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_P; 595 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio); 596 } else { 597 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_N; 598 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio); 599 } 600 601 /* Update reference priority */ 602 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio); 603 if (rc) 604 return rc; 605 606 /* Commit configuration */ 607 return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR, 608 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 609 } 610 611 /** 612 * zl3073x_dpll_ref_state_get - get status for given input pin 613 * @pin: pointer to pin 614 * @state: place to store status 615 * 616 * Checks current status for the given input pin and stores the value 617 * to @state. 618 * 619 * Return: 0 on success, <0 on error 620 */ 621 static int 622 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin, 623 enum dpll_pin_state *state) 624 { 625 struct zl3073x_dpll *zldpll = pin->dpll; 626 struct zl3073x_dev *zldev = zldpll->dev; 627 u8 ref, ref_conn; 628 int rc; 629 630 ref = zl3073x_input_pin_ref_get(pin->id); 631 632 /* Get currently connected reference */ 633 rc = zl3073x_dpll_connected_ref_get(zldpll, &ref_conn); 634 if (rc) 635 return rc; 636 637 if (ref == ref_conn) { 638 *state = DPLL_PIN_STATE_CONNECTED; 639 return 0; 640 } 641 642 /* If the DPLL is running in automatic mode and the reference is 643 * selectable and its monitor does not report any error then report 644 * pin as selectable. 645 */ 646 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO && 647 zl3073x_dev_ref_is_status_ok(zldev, ref) && pin->selectable) { 648 *state = DPLL_PIN_STATE_SELECTABLE; 649 return 0; 650 } 651 652 /* Otherwise report the pin as disconnected */ 653 *state = DPLL_PIN_STATE_DISCONNECTED; 654 655 return 0; 656 } 657 658 static int 659 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 660 void *pin_priv, 661 const struct dpll_device *dpll, 662 void *dpll_priv, 663 enum dpll_pin_state *state, 664 struct netlink_ext_ack *extack) 665 { 666 struct zl3073x_dpll_pin *pin = pin_priv; 667 668 return zl3073x_dpll_ref_state_get(pin, state); 669 } 670 671 static int 672 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin, 673 void *pin_priv, 674 const struct dpll_device *dpll, 675 void *dpll_priv, 676 enum dpll_pin_state state, 677 struct netlink_ext_ack *extack) 678 { 679 struct zl3073x_dpll *zldpll = dpll_priv; 680 struct zl3073x_dpll_pin *pin = pin_priv; 681 u8 new_ref; 682 int rc; 683 684 switch (zldpll->refsel_mode) { 685 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 686 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 687 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 688 if (state == DPLL_PIN_STATE_CONNECTED) { 689 /* Choose the pin as new selected reference */ 690 new_ref = zl3073x_input_pin_ref_get(pin->id); 691 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 692 /* No reference */ 693 new_ref = ZL3073X_DPLL_REF_NONE; 694 } else { 695 NL_SET_ERR_MSG_MOD(extack, 696 "Invalid pin state for manual mode"); 697 return -EINVAL; 698 } 699 700 rc = zl3073x_dpll_selected_ref_set(zldpll, new_ref); 701 break; 702 703 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 704 if (state == DPLL_PIN_STATE_SELECTABLE) { 705 if (pin->selectable) 706 return 0; /* Pin is already selectable */ 707 708 /* Restore pin priority in HW */ 709 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 710 if (rc) 711 return rc; 712 713 /* Mark pin as selectable */ 714 pin->selectable = true; 715 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 716 if (!pin->selectable) 717 return 0; /* Pin is already disconnected */ 718 719 /* Set pin priority to none in HW */ 720 rc = zl3073x_dpll_ref_prio_set(pin, 721 ZL_DPLL_REF_PRIO_NONE); 722 if (rc) 723 return rc; 724 725 /* Mark pin as non-selectable */ 726 pin->selectable = false; 727 } else { 728 NL_SET_ERR_MSG(extack, 729 "Invalid pin state for automatic mode"); 730 return -EINVAL; 731 } 732 break; 733 734 default: 735 /* In other modes we cannot change input reference */ 736 NL_SET_ERR_MSG(extack, 737 "Pin state cannot be changed in current mode"); 738 rc = -EOPNOTSUPP; 739 break; 740 } 741 742 return rc; 743 } 744 745 static int 746 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv, 747 const struct dpll_device *dpll, void *dpll_priv, 748 u32 *prio, struct netlink_ext_ack *extack) 749 { 750 struct zl3073x_dpll_pin *pin = pin_priv; 751 752 *prio = pin->prio; 753 754 return 0; 755 } 756 757 static int 758 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv, 759 const struct dpll_device *dpll, void *dpll_priv, 760 u32 prio, struct netlink_ext_ack *extack) 761 { 762 struct zl3073x_dpll_pin *pin = pin_priv; 763 int rc; 764 765 if (prio > ZL_DPLL_REF_PRIO_MAX) 766 return -EINVAL; 767 768 /* If the pin is selectable then update HW registers */ 769 if (pin->selectable) { 770 rc = zl3073x_dpll_ref_prio_set(pin, prio); 771 if (rc) 772 return rc; 773 } 774 775 /* Save priority */ 776 pin->prio = prio; 777 778 return 0; 779 } 780 781 static int 782 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, 783 void *pin_priv, 784 const struct dpll_device *dpll, 785 void *dpll_priv, 786 struct dpll_pin_esync *esync, 787 struct netlink_ext_ack *extack) 788 { 789 struct zl3073x_dpll *zldpll = dpll_priv; 790 struct zl3073x_dev *zldev = zldpll->dev; 791 struct zl3073x_dpll_pin *pin = pin_priv; 792 const struct zl3073x_synth *synth; 793 const struct zl3073x_out *out; 794 u8 clock_type, out_id; 795 u32 synth_freq; 796 797 out_id = zl3073x_output_pin_out_get(pin->id); 798 out = zl3073x_out_state_get(zldev, out_id); 799 800 /* If N-division is enabled, esync is not supported. The register used 801 * for N-division is also used for the esync divider so both cannot 802 * be used. 803 */ 804 switch (zl3073x_out_signal_format_get(out)) { 805 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 806 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 807 return -EOPNOTSUPP; 808 default: 809 break; 810 } 811 812 /* Get attached synth frequency */ 813 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(out)); 814 synth_freq = zl3073x_synth_freq_get(synth); 815 816 clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, out->mode); 817 if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { 818 /* No need to read esync data if it is not enabled */ 819 esync->freq = 0; 820 esync->pulse = 0; 821 822 goto finish; 823 } 824 825 /* Compute esync frequency */ 826 esync->freq = synth_freq / out->div / out->esync_n_period; 827 828 /* By comparing the esync_pulse_width to the half of the pulse width 829 * the esync pulse percentage can be determined. 830 * Note that half pulse width is in units of half synth cycles, which 831 * is why it reduces down to be output_div. 832 */ 833 esync->pulse = (50 * out->esync_n_width) / out->div; 834 835 finish: 836 /* Set supported esync ranges if the pin supports esync control and 837 * if the output frequency is > 1 Hz. 838 */ 839 if (pin->esync_control && (synth_freq / out->div) > 1) { 840 esync->range = esync_freq_ranges; 841 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 842 } else { 843 esync->range = NULL; 844 esync->range_num = 0; 845 } 846 847 return 0; 848 } 849 850 static int 851 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin, 852 void *pin_priv, 853 const struct dpll_device *dpll, 854 void *dpll_priv, u64 freq, 855 struct netlink_ext_ack *extack) 856 { 857 struct zl3073x_dpll *zldpll = dpll_priv; 858 struct zl3073x_dev *zldev = zldpll->dev; 859 struct zl3073x_dpll_pin *pin = pin_priv; 860 const struct zl3073x_synth *synth; 861 struct zl3073x_out out; 862 u8 clock_type, out_id; 863 u32 synth_freq; 864 865 out_id = zl3073x_output_pin_out_get(pin->id); 866 out = *zl3073x_out_state_get(zldev, out_id); 867 868 /* If N-division is enabled, esync is not supported. The register used 869 * for N-division is also used for the esync divider so both cannot 870 * be used. 871 */ 872 switch (zl3073x_out_signal_format_get(&out)) { 873 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 874 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 875 return -EOPNOTSUPP; 876 default: 877 break; 878 } 879 880 /* Select clock type */ 881 if (freq) 882 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC; 883 else 884 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL; 885 886 /* Update clock type in output mode */ 887 out.mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE; 888 out.mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type); 889 890 /* If esync is being disabled just write mailbox and finish */ 891 if (!freq) 892 goto write_mailbox; 893 894 /* Get attached synth frequency */ 895 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 896 synth_freq = zl3073x_synth_freq_get(synth); 897 898 /* Compute and update esync period */ 899 out.esync_n_period = synth_freq / (u32)freq / out.div; 900 901 /* Half of the period in units of 1/2 synth cycle can be represented by 902 * the output_div. To get the supported esync pulse width of 25% of the 903 * period the output_div can just be divided by 2. Note that this 904 * assumes that output_div is even, otherwise some resolution will be 905 * lost. 906 */ 907 out.esync_n_width = out.div / 2; 908 909 write_mailbox: 910 /* Commit output configuration */ 911 return zl3073x_out_state_set(zldev, out_id, &out); 912 } 913 914 static int 915 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin, 916 void *pin_priv, 917 const struct dpll_device *dpll, 918 void *dpll_priv, u64 *frequency, 919 struct netlink_ext_ack *extack) 920 { 921 struct zl3073x_dpll *zldpll = dpll_priv; 922 struct zl3073x_dpll_pin *pin = pin_priv; 923 924 *frequency = zl3073x_dev_output_pin_freq_get(zldpll->dev, pin->id); 925 926 return 0; 927 } 928 929 static int 930 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, 931 void *pin_priv, 932 const struct dpll_device *dpll, 933 void *dpll_priv, u64 frequency, 934 struct netlink_ext_ack *extack) 935 { 936 struct zl3073x_dpll *zldpll = dpll_priv; 937 struct zl3073x_dev *zldev = zldpll->dev; 938 struct zl3073x_dpll_pin *pin = pin_priv; 939 const struct zl3073x_synth *synth; 940 u8 out_id, signal_format; 941 u32 new_div, synth_freq; 942 struct zl3073x_out out; 943 944 out_id = zl3073x_output_pin_out_get(pin->id); 945 out = *zl3073x_out_state_get(zldev, out_id); 946 947 /* Get attached synth frequency and compute new divisor */ 948 synth = zl3073x_synth_state_get(zldev, zl3073x_out_synth_get(&out)); 949 synth_freq = zl3073x_synth_freq_get(synth); 950 new_div = synth_freq / (u32)frequency; 951 952 /* Get used signal format for the given output */ 953 signal_format = zl3073x_out_signal_format_get(&out); 954 955 /* Check signal format */ 956 if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV && 957 signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) { 958 /* For non N-divided signal formats the frequency is computed 959 * as division of synth frequency and output divisor. 960 */ 961 out.div = new_div; 962 963 /* For 50/50 duty cycle the divisor is equal to width */ 964 out.width = new_div; 965 966 /* Commit output configuration */ 967 return zl3073x_out_state_set(zldev, out_id, &out); 968 } 969 970 if (zl3073x_dpll_is_p_pin(pin)) { 971 /* We are going to change output frequency for P-pin but 972 * if the requested frequency is less than current N-pin 973 * frequency then indicate a failure as we are not able 974 * to compute N-pin divisor to keep its frequency unchanged. 975 * 976 * Update divisor for N-pin to keep N-pin frequency. 977 */ 978 out.esync_n_period = (out.esync_n_period * out.div) / new_div; 979 if (!out.esync_n_period) 980 return -EINVAL; 981 982 /* Update the output divisor */ 983 out.div = new_div; 984 985 /* For 50/50 duty cycle the divisor is equal to width */ 986 out.width = out.div; 987 } else { 988 /* We are going to change frequency of N-pin but if 989 * the requested freq is greater or equal than freq of P-pin 990 * in the output pair we cannot compute divisor for the N-pin. 991 * In this case indicate a failure. 992 * 993 * Update divisor for N-pin 994 */ 995 out.esync_n_period = div64_u64(synth_freq, frequency * out.div); 996 if (!out.esync_n_period) 997 return -EINVAL; 998 } 999 1000 /* For 50/50 duty cycle the divisor is equal to width */ 1001 out.esync_n_width = out.esync_n_period; 1002 1003 /* Commit output configuration */ 1004 return zl3073x_out_state_set(zldev, out_id, &out); 1005 } 1006 1007 static int 1008 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 1009 void *pin_priv, 1010 const struct dpll_device *dpll, 1011 void *dpll_priv, 1012 s32 *phase_adjust, 1013 struct netlink_ext_ack *extack) 1014 { 1015 struct zl3073x_dpll *zldpll = dpll_priv; 1016 struct zl3073x_dev *zldev = zldpll->dev; 1017 struct zl3073x_dpll_pin *pin = pin_priv; 1018 const struct zl3073x_out *out; 1019 u8 out_id; 1020 1021 out_id = zl3073x_output_pin_out_get(pin->id); 1022 out = zl3073x_out_state_get(zldev, out_id); 1023 1024 /* The value in the register is expressed in half synth clock cycles. */ 1025 *phase_adjust = out->phase_comp * pin->phase_gran; 1026 1027 return 0; 1028 } 1029 1030 static int 1031 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 1032 void *pin_priv, 1033 const struct dpll_device *dpll, 1034 void *dpll_priv, 1035 s32 phase_adjust, 1036 struct netlink_ext_ack *extack) 1037 { 1038 struct zl3073x_dpll *zldpll = dpll_priv; 1039 struct zl3073x_dev *zldev = zldpll->dev; 1040 struct zl3073x_dpll_pin *pin = pin_priv; 1041 struct zl3073x_out out; 1042 u8 out_id; 1043 1044 out_id = zl3073x_output_pin_out_get(pin->id); 1045 out = *zl3073x_out_state_get(zldev, out_id); 1046 1047 /* The value in the register is expressed in half synth clock cycles. */ 1048 out.phase_comp = phase_adjust / pin->phase_gran; 1049 1050 /* Update output configuration from mailbox */ 1051 return zl3073x_out_state_set(zldev, out_id, &out); 1052 } 1053 1054 static int 1055 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 1056 void *pin_priv, 1057 const struct dpll_device *dpll, 1058 void *dpll_priv, 1059 enum dpll_pin_state *state, 1060 struct netlink_ext_ack *extack) 1061 { 1062 /* If the output pin is registered then it is always connected */ 1063 *state = DPLL_PIN_STATE_CONNECTED; 1064 1065 return 0; 1066 } 1067 1068 static int 1069 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, 1070 enum dpll_lock_status *status, 1071 enum dpll_lock_status_error *status_error, 1072 struct netlink_ext_ack *extack) 1073 { 1074 struct zl3073x_dpll *zldpll = dpll_priv; 1075 struct zl3073x_dev *zldev = zldpll->dev; 1076 u8 mon_status, state; 1077 int rc; 1078 1079 switch (zldpll->refsel_mode) { 1080 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1081 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1082 /* In FREERUN and NCO modes the DPLL is always unlocked */ 1083 *status = DPLL_LOCK_STATUS_UNLOCKED; 1084 1085 return 0; 1086 default: 1087 break; 1088 } 1089 1090 /* Read DPLL monitor status */ 1091 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id), 1092 &mon_status); 1093 if (rc) 1094 return rc; 1095 state = FIELD_GET(ZL_DPLL_MON_STATUS_STATE, mon_status); 1096 1097 switch (state) { 1098 case ZL_DPLL_MON_STATUS_STATE_LOCK: 1099 if (FIELD_GET(ZL_DPLL_MON_STATUS_HO_READY, mon_status)) 1100 *status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 1101 else 1102 *status = DPLL_LOCK_STATUS_LOCKED; 1103 break; 1104 case ZL_DPLL_MON_STATUS_STATE_HOLDOVER: 1105 case ZL_DPLL_MON_STATUS_STATE_ACQUIRING: 1106 *status = DPLL_LOCK_STATUS_HOLDOVER; 1107 break; 1108 default: 1109 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n", 1110 mon_status); 1111 *status = DPLL_LOCK_STATUS_UNLOCKED; 1112 break; 1113 } 1114 1115 return 0; 1116 } 1117 1118 static int 1119 zl3073x_dpll_supported_modes_get(const struct dpll_device *dpll, 1120 void *dpll_priv, unsigned long *modes, 1121 struct netlink_ext_ack *extack) 1122 { 1123 struct zl3073x_dpll *zldpll = dpll_priv; 1124 1125 /* We support switching between automatic and manual mode, except in 1126 * a case where the DPLL channel is configured to run in NCO mode. 1127 * In this case, report only the manual mode to which the NCO is mapped 1128 * as the only supported one. 1129 */ 1130 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_NCO) 1131 __set_bit(DPLL_MODE_AUTOMATIC, modes); 1132 1133 __set_bit(DPLL_MODE_MANUAL, modes); 1134 1135 return 0; 1136 } 1137 1138 static int 1139 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, 1140 enum dpll_mode *mode, struct netlink_ext_ack *extack) 1141 { 1142 struct zl3073x_dpll *zldpll = dpll_priv; 1143 1144 switch (zldpll->refsel_mode) { 1145 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1146 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 1147 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1148 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 1149 /* Use MANUAL for device FREERUN, HOLDOVER, NCO and 1150 * REFLOCK modes 1151 */ 1152 *mode = DPLL_MODE_MANUAL; 1153 break; 1154 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 1155 /* Use AUTO for device AUTO mode */ 1156 *mode = DPLL_MODE_AUTOMATIC; 1157 break; 1158 default: 1159 return -EINVAL; 1160 } 1161 1162 return 0; 1163 } 1164 1165 static int 1166 zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device *dpll, 1167 void *dpll_priv, u32 *factor, 1168 struct netlink_ext_ack *extack) 1169 { 1170 struct zl3073x_dpll *zldpll = dpll_priv; 1171 1172 *factor = zl3073x_dev_phase_avg_factor_get(zldpll->dev); 1173 1174 return 0; 1175 } 1176 1177 static void 1178 zl3073x_dpll_change_work(struct work_struct *work) 1179 { 1180 struct zl3073x_dpll *zldpll; 1181 1182 zldpll = container_of(work, struct zl3073x_dpll, change_work); 1183 dpll_device_change_ntf(zldpll->dpll_dev); 1184 } 1185 1186 static int 1187 zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device *dpll, 1188 void *dpll_priv, u32 factor, 1189 struct netlink_ext_ack *extack) 1190 { 1191 struct zl3073x_dpll *item, *zldpll = dpll_priv; 1192 int rc; 1193 1194 if (factor > 15) { 1195 NL_SET_ERR_MSG_FMT(extack, 1196 "Phase offset average factor has to be from range <0,15>"); 1197 return -EINVAL; 1198 } 1199 1200 rc = zl3073x_dev_phase_avg_factor_set(zldpll->dev, factor); 1201 if (rc) { 1202 NL_SET_ERR_MSG_FMT(extack, 1203 "Failed to set phase offset averaging factor"); 1204 return rc; 1205 } 1206 1207 /* The averaging factor is common for all DPLL channels so after change 1208 * we have to send a notification for other DPLL devices. 1209 */ 1210 list_for_each_entry(item, &zldpll->dev->dplls, list) { 1211 if (item != zldpll) 1212 schedule_work(&item->change_work); 1213 } 1214 1215 return 0; 1216 } 1217 1218 static int 1219 zl3073x_dpll_mode_set(const struct dpll_device *dpll, void *dpll_priv, 1220 enum dpll_mode mode, struct netlink_ext_ack *extack) 1221 { 1222 struct zl3073x_dpll *zldpll = dpll_priv; 1223 u8 hw_mode, mode_refsel, ref; 1224 int rc; 1225 1226 rc = zl3073x_dpll_selected_ref_get(zldpll, &ref); 1227 if (rc) { 1228 NL_SET_ERR_MSG_MOD(extack, "failed to get selected reference"); 1229 return rc; 1230 } 1231 1232 if (mode == DPLL_MODE_MANUAL) { 1233 /* We are switching from automatic to manual mode: 1234 * - if we have a valid reference selected during auto mode then 1235 * we will switch to forced reference lock mode and use this 1236 * reference for selection 1237 * - if NO valid reference is selected, we will switch to forced 1238 * holdover mode or freerun mode, depending on the current 1239 * lock status 1240 */ 1241 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1242 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 1243 else if (zldpll->lock_status == DPLL_LOCK_STATUS_UNLOCKED) 1244 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 1245 else 1246 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 1247 } else { 1248 /* We are switching from manual to automatic mode: 1249 * - if there is a valid reference selected then ensure that 1250 * it is selectable after switch to automatic mode 1251 * - switch to automatic mode 1252 */ 1253 struct zl3073x_dpll_pin *pin; 1254 1255 pin = zl3073x_dpll_pin_get_by_ref(zldpll, ref); 1256 if (pin && !pin->selectable) { 1257 /* Restore pin priority in HW */ 1258 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 1259 if (rc) { 1260 NL_SET_ERR_MSG_MOD(extack, 1261 "failed to restore pin priority"); 1262 return rc; 1263 } 1264 1265 pin->selectable = true; 1266 } 1267 1268 hw_mode = ZL_DPLL_MODE_REFSEL_MODE_AUTO; 1269 } 1270 1271 /* Build mode_refsel value */ 1272 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, hw_mode); 1273 1274 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1275 mode_refsel |= FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 1276 1277 /* Update dpll_mode_refsel register */ 1278 rc = zl3073x_write_u8(zldpll->dev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1279 mode_refsel); 1280 if (rc) { 1281 NL_SET_ERR_MSG_MOD(extack, 1282 "failed to set reference selection mode"); 1283 return rc; 1284 } 1285 1286 zldpll->refsel_mode = hw_mode; 1287 1288 if (ZL3073X_DPLL_REF_IS_VALID(ref)) 1289 zldpll->forced_ref = ref; 1290 1291 return 0; 1292 } 1293 1294 static int 1295 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll, 1296 void *dpll_priv, 1297 enum dpll_feature_state *state, 1298 struct netlink_ext_ack *extack) 1299 { 1300 struct zl3073x_dpll *zldpll = dpll_priv; 1301 1302 if (zldpll->phase_monitor) 1303 *state = DPLL_FEATURE_STATE_ENABLE; 1304 else 1305 *state = DPLL_FEATURE_STATE_DISABLE; 1306 1307 return 0; 1308 } 1309 1310 static int 1311 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll, 1312 void *dpll_priv, 1313 enum dpll_feature_state state, 1314 struct netlink_ext_ack *extack) 1315 { 1316 struct zl3073x_dpll *zldpll = dpll_priv; 1317 1318 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE); 1319 1320 return 0; 1321 } 1322 1323 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = { 1324 .direction_get = zl3073x_dpll_pin_direction_get, 1325 .esync_get = zl3073x_dpll_input_pin_esync_get, 1326 .esync_set = zl3073x_dpll_input_pin_esync_set, 1327 .ffo_get = zl3073x_dpll_input_pin_ffo_get, 1328 .frequency_get = zl3073x_dpll_input_pin_frequency_get, 1329 .frequency_set = zl3073x_dpll_input_pin_frequency_set, 1330 .phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get, 1331 .phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get, 1332 .phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set, 1333 .prio_get = zl3073x_dpll_input_pin_prio_get, 1334 .prio_set = zl3073x_dpll_input_pin_prio_set, 1335 .state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get, 1336 .state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set, 1337 }; 1338 1339 static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = { 1340 .direction_get = zl3073x_dpll_pin_direction_get, 1341 .esync_get = zl3073x_dpll_output_pin_esync_get, 1342 .esync_set = zl3073x_dpll_output_pin_esync_set, 1343 .frequency_get = zl3073x_dpll_output_pin_frequency_get, 1344 .frequency_set = zl3073x_dpll_output_pin_frequency_set, 1345 .phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get, 1346 .phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set, 1347 .state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get, 1348 }; 1349 1350 static const struct dpll_device_ops zl3073x_dpll_device_ops = { 1351 .lock_status_get = zl3073x_dpll_lock_status_get, 1352 .mode_get = zl3073x_dpll_mode_get, 1353 .mode_set = zl3073x_dpll_mode_set, 1354 .phase_offset_avg_factor_get = zl3073x_dpll_phase_offset_avg_factor_get, 1355 .phase_offset_avg_factor_set = zl3073x_dpll_phase_offset_avg_factor_set, 1356 .phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get, 1357 .phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set, 1358 .supported_modes_get = zl3073x_dpll_supported_modes_get, 1359 }; 1360 1361 /** 1362 * zl3073x_dpll_pin_alloc - allocate DPLL pin 1363 * @zldpll: pointer to zl3073x_dpll 1364 * @dir: pin direction 1365 * @id: pin id 1366 * 1367 * Allocates and initializes zl3073x_dpll_pin structure for given 1368 * pin id and direction. 1369 * 1370 * Return: pointer to allocated structure on success, error pointer on error 1371 */ 1372 static struct zl3073x_dpll_pin * 1373 zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir, 1374 u8 id) 1375 { 1376 struct zl3073x_dpll_pin *pin; 1377 1378 pin = kzalloc_obj(*pin); 1379 if (!pin) 1380 return ERR_PTR(-ENOMEM); 1381 1382 pin->dpll = zldpll; 1383 pin->dir = dir; 1384 pin->id = id; 1385 1386 return pin; 1387 } 1388 1389 /** 1390 * zl3073x_dpll_pin_free - deallocate DPLL pin 1391 * @pin: pin to free 1392 * 1393 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc. 1394 */ 1395 static void 1396 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin) 1397 { 1398 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); 1399 1400 kfree(pin); 1401 } 1402 1403 /** 1404 * zl3073x_dpll_pin_register - register DPLL pin 1405 * @pin: pointer to DPLL pin 1406 * @index: absolute pin index for registration 1407 * 1408 * Registers given DPLL pin into DPLL sub-system. 1409 * 1410 * Return: 0 on success, <0 on error 1411 */ 1412 static int 1413 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index) 1414 { 1415 struct zl3073x_dpll *zldpll = pin->dpll; 1416 struct zl3073x_pin_props *props; 1417 const struct dpll_pin_ops *ops; 1418 int rc; 1419 1420 /* Get pin properties */ 1421 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); 1422 if (IS_ERR(props)) 1423 return PTR_ERR(props); 1424 1425 /* Save package label, esync capability and phase adjust granularity */ 1426 strscpy(pin->label, props->package_label); 1427 pin->esync_control = props->esync_control; 1428 pin->phase_gran = props->dpll_props.phase_gran; 1429 1430 if (zl3073x_dpll_is_input_pin(pin)) { 1431 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); 1432 if (rc) 1433 goto err_prio_get; 1434 1435 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) { 1436 /* Clamp prio to max value & mark pin non-selectable */ 1437 pin->prio = ZL_DPLL_REF_PRIO_MAX; 1438 pin->selectable = false; 1439 } else { 1440 /* Mark pin as selectable */ 1441 pin->selectable = true; 1442 } 1443 } 1444 1445 /* Create or get existing DPLL pin */ 1446 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, 1447 &props->dpll_props, &pin->tracker); 1448 if (IS_ERR(pin->dpll_pin)) { 1449 rc = PTR_ERR(pin->dpll_pin); 1450 goto err_pin_get; 1451 } 1452 dpll_pin_fwnode_set(pin->dpll_pin, props->fwnode); 1453 1454 if (zl3073x_dpll_is_input_pin(pin)) 1455 ops = &zl3073x_dpll_input_pin_ops; 1456 else 1457 ops = &zl3073x_dpll_output_pin_ops; 1458 1459 /* Register the pin */ 1460 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1461 if (rc) 1462 goto err_register; 1463 1464 /* Free pin properties */ 1465 zl3073x_pin_props_put(props); 1466 1467 return 0; 1468 1469 err_register: 1470 dpll_pin_put(pin->dpll_pin, &pin->tracker); 1471 err_prio_get: 1472 pin->dpll_pin = NULL; 1473 err_pin_get: 1474 zl3073x_pin_props_put(props); 1475 1476 return rc; 1477 } 1478 1479 /** 1480 * zl3073x_dpll_pin_unregister - unregister DPLL pin 1481 * @pin: pointer to DPLL pin 1482 * 1483 * Unregisters pin previously registered by @zl3073x_dpll_pin_register. 1484 */ 1485 static void 1486 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin) 1487 { 1488 struct zl3073x_dpll *zldpll = pin->dpll; 1489 const struct dpll_pin_ops *ops; 1490 1491 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); 1492 1493 if (zl3073x_dpll_is_input_pin(pin)) 1494 ops = &zl3073x_dpll_input_pin_ops; 1495 else 1496 ops = &zl3073x_dpll_output_pin_ops; 1497 1498 /* Unregister the pin */ 1499 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1500 1501 dpll_pin_put(pin->dpll_pin, &pin->tracker); 1502 pin->dpll_pin = NULL; 1503 } 1504 1505 /** 1506 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins 1507 * @zldpll: pointer to zl3073x_dpll structure 1508 * 1509 * Enumerates all DPLL pins registered to given DPLL device and 1510 * unregisters them. 1511 */ 1512 static void 1513 zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll) 1514 { 1515 struct zl3073x_dpll_pin *pin, *next; 1516 1517 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { 1518 zl3073x_dpll_pin_unregister(pin); 1519 list_del(&pin->list); 1520 zl3073x_dpll_pin_free(pin); 1521 } 1522 } 1523 1524 /** 1525 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable 1526 * @zldpll: pointer to zl3073x_dpll structure 1527 * @dir: pin direction 1528 * @index: pin index 1529 * 1530 * Checks if the given pin can be registered to given DPLL. For both 1531 * directions the pin can be registered if it is enabled. In case of 1532 * differential signal type only P-pin is reported as registrable. 1533 * And additionally for the output pin, the pin can be registered only 1534 * if it is connected to synthesizer that is driven by given DPLL. 1535 * 1536 * Return: true if the pin is registrable, false if not 1537 */ 1538 static bool 1539 zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll, 1540 enum dpll_pin_direction dir, u8 index) 1541 { 1542 struct zl3073x_dev *zldev = zldpll->dev; 1543 bool is_diff, is_enabled; 1544 const char *name; 1545 1546 if (dir == DPLL_PIN_DIRECTION_INPUT) { 1547 u8 ref_id = zl3073x_input_pin_ref_get(index); 1548 const struct zl3073x_ref *ref; 1549 1550 /* Skip the pin if the DPLL is running in NCO mode */ 1551 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO) 1552 return false; 1553 1554 name = "REF"; 1555 ref = zl3073x_ref_state_get(zldev, ref_id); 1556 is_diff = zl3073x_ref_is_diff(ref); 1557 is_enabled = zl3073x_ref_is_enabled(ref); 1558 } else { 1559 /* Output P&N pair shares single HW output */ 1560 u8 out = zl3073x_output_pin_out_get(index); 1561 1562 /* Skip the pin if it is connected to different DPLL channel */ 1563 if (zl3073x_dev_out_dpll_get(zldev, out) != zldpll->id) { 1564 dev_dbg(zldev->dev, 1565 "OUT%u is driven by different DPLL\n", out); 1566 1567 return false; 1568 } 1569 1570 name = "OUT"; 1571 is_diff = zl3073x_dev_out_is_diff(zldev, out); 1572 is_enabled = zl3073x_dev_output_pin_is_enabled(zldev, index); 1573 } 1574 1575 /* Skip N-pin if the corresponding input/output is differential */ 1576 if (is_diff && zl3073x_is_n_pin(index)) { 1577 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", 1578 name, index / 2); 1579 1580 return false; 1581 } 1582 1583 /* Skip the pin if it is disabled */ 1584 if (!is_enabled) { 1585 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, 1586 zl3073x_is_p_pin(index) ? 'P' : 'N'); 1587 1588 return false; 1589 } 1590 1591 return true; 1592 } 1593 1594 /** 1595 * zl3073x_dpll_pins_register - register all registerable DPLL pins 1596 * @zldpll: pointer to zl3073x_dpll structure 1597 * 1598 * Enumerates all possible input/output pins and registers all of them 1599 * that are registrable. 1600 * 1601 * Return: 0 on success, <0 on error 1602 */ 1603 static int 1604 zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll) 1605 { 1606 struct zl3073x_dpll_pin *pin; 1607 enum dpll_pin_direction dir; 1608 u8 id, index; 1609 int rc; 1610 1611 /* Process input pins */ 1612 for (index = 0; index < ZL3073X_NUM_PINS; index++) { 1613 /* First input pins and then output pins */ 1614 if (index < ZL3073X_NUM_INPUT_PINS) { 1615 id = index; 1616 dir = DPLL_PIN_DIRECTION_INPUT; 1617 } else { 1618 id = index - ZL3073X_NUM_INPUT_PINS; 1619 dir = DPLL_PIN_DIRECTION_OUTPUT; 1620 } 1621 1622 /* Check if the pin registrable to this DPLL */ 1623 if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id)) 1624 continue; 1625 1626 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id); 1627 if (IS_ERR(pin)) { 1628 rc = PTR_ERR(pin); 1629 goto error; 1630 } 1631 1632 rc = zl3073x_dpll_pin_register(pin, index); 1633 if (rc) 1634 goto error; 1635 1636 list_add(&pin->list, &zldpll->pins); 1637 } 1638 1639 return 0; 1640 1641 error: 1642 zl3073x_dpll_pins_unregister(zldpll); 1643 1644 return rc; 1645 } 1646 1647 /** 1648 * zl3073x_dpll_device_register - register DPLL device 1649 * @zldpll: pointer to zl3073x_dpll structure 1650 * 1651 * Registers given DPLL device into DPLL sub-system. 1652 * 1653 * Return: 0 on success, <0 on error 1654 */ 1655 static int 1656 zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll) 1657 { 1658 struct zl3073x_dev *zldev = zldpll->dev; 1659 u8 dpll_mode_refsel; 1660 int rc; 1661 1662 /* Read DPLL mode and forcibly selected reference */ 1663 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1664 &dpll_mode_refsel); 1665 if (rc) 1666 return rc; 1667 1668 /* Extract mode and selected input reference */ 1669 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE, 1670 dpll_mode_refsel); 1671 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF, 1672 dpll_mode_refsel); 1673 1674 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, 1675 THIS_MODULE, &zldpll->tracker); 1676 if (IS_ERR(zldpll->dpll_dev)) { 1677 rc = PTR_ERR(zldpll->dpll_dev); 1678 zldpll->dpll_dev = NULL; 1679 1680 return rc; 1681 } 1682 1683 rc = dpll_device_register(zldpll->dpll_dev, 1684 zl3073x_prop_dpll_type_get(zldev, zldpll->id), 1685 &zl3073x_dpll_device_ops, zldpll); 1686 if (rc) { 1687 dpll_device_put(zldpll->dpll_dev, &zldpll->tracker); 1688 zldpll->dpll_dev = NULL; 1689 } 1690 1691 return rc; 1692 } 1693 1694 /** 1695 * zl3073x_dpll_device_unregister - unregister DPLL device 1696 * @zldpll: pointer to zl3073x_dpll structure 1697 * 1698 * Unregisters given DPLL device from DPLL sub-system previously registered 1699 * by @zl3073x_dpll_device_register. 1700 */ 1701 static void 1702 zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll) 1703 { 1704 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n"); 1705 1706 cancel_work_sync(&zldpll->change_work); 1707 1708 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, 1709 zldpll); 1710 dpll_device_put(zldpll->dpll_dev, &zldpll->tracker); 1711 zldpll->dpll_dev = NULL; 1712 } 1713 1714 /** 1715 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change 1716 * @pin: pin to check 1717 * 1718 * Check for the change of DPLL to connected pin phase offset change. 1719 * 1720 * Return: true on phase offset change, false otherwise 1721 */ 1722 static bool 1723 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin) 1724 { 1725 struct zl3073x_dpll *zldpll = pin->dpll; 1726 struct zl3073x_dev *zldev = zldpll->dev; 1727 unsigned int reg; 1728 s64 phase_offset; 1729 u8 ref_id; 1730 int rc; 1731 1732 /* No phase offset if the ref monitor reports signal errors */ 1733 ref_id = zl3073x_input_pin_ref_get(pin->id); 1734 if (!zl3073x_dev_ref_is_status_ok(zldev, ref_id)) 1735 return false; 1736 1737 /* Select register to read phase offset value depending on pin and 1738 * phase monitor state: 1739 * 1) For connected pin use dpll_phase_err_data register 1740 * 2) For other pins use appropriate ref_phase register if the phase 1741 * monitor feature is enabled. 1742 */ 1743 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) 1744 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); 1745 else if (zldpll->phase_monitor) 1746 reg = ZL_REG_REF_PHASE(ref_id); 1747 else 1748 return false; 1749 1750 /* Read measured phase offset value */ 1751 rc = zl3073x_read_u48(zldev, reg, &phase_offset); 1752 if (rc) { 1753 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n", 1754 ERR_PTR(rc)); 1755 1756 return false; 1757 } 1758 1759 /* Convert to ps */ 1760 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100); 1761 1762 /* Compare with previous value */ 1763 if (phase_offset != pin->phase_offset) { 1764 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n", 1765 pin->label, pin->phase_offset, phase_offset); 1766 pin->phase_offset = phase_offset; 1767 1768 return true; 1769 } 1770 1771 return false; 1772 } 1773 1774 /** 1775 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change 1776 * @pin: pin to check 1777 * 1778 * Check for the given pin's fractional frequency change. 1779 * 1780 * Return: true on fractional frequency offset change, false otherwise 1781 */ 1782 static bool 1783 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin) 1784 { 1785 struct zl3073x_dpll *zldpll = pin->dpll; 1786 struct zl3073x_dev *zldev = zldpll->dev; 1787 const struct zl3073x_ref *ref; 1788 u8 ref_id; 1789 1790 /* Get reference monitor status */ 1791 ref_id = zl3073x_input_pin_ref_get(pin->id); 1792 ref = zl3073x_ref_state_get(zldev, ref_id); 1793 1794 /* Do not report ffo changes if the reference monitor report errors */ 1795 if (!zl3073x_ref_is_status_ok(ref)) 1796 return false; 1797 1798 /* Compare with previous value */ 1799 if (pin->freq_offset != ref->ffo) { 1800 dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n", 1801 pin->label, pin->freq_offset, ref->ffo); 1802 pin->freq_offset = ref->ffo; 1803 1804 return true; 1805 } 1806 1807 return false; 1808 } 1809 1810 /** 1811 * zl3073x_dpll_changes_check - check for changes and send notifications 1812 * @zldpll: pointer to zl3073x_dpll structure 1813 * 1814 * Checks for changes on given DPLL device and its registered DPLL pins 1815 * and sends notifications about them. 1816 * 1817 * This function is periodically called from @zl3073x_dev_periodic_work. 1818 */ 1819 void 1820 zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll) 1821 { 1822 struct zl3073x_dev *zldev = zldpll->dev; 1823 enum dpll_lock_status lock_status; 1824 struct device *dev = zldev->dev; 1825 struct zl3073x_dpll_pin *pin; 1826 int rc; 1827 1828 zldpll->check_count++; 1829 1830 /* Get current lock status for the DPLL */ 1831 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, 1832 &lock_status, NULL, NULL); 1833 if (rc) { 1834 dev_err(dev, "Failed to get DPLL%u lock status: %pe\n", 1835 zldpll->id, ERR_PTR(rc)); 1836 return; 1837 } 1838 1839 /* If lock status was changed then notify DPLL core */ 1840 if (zldpll->lock_status != lock_status) { 1841 zldpll->lock_status = lock_status; 1842 dpll_device_change_ntf(zldpll->dpll_dev); 1843 } 1844 1845 /* Input pin monitoring does make sense only in automatic 1846 * or forced reference modes. 1847 */ 1848 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO && 1849 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK) 1850 return; 1851 1852 /* Update phase offset latch registers for this DPLL if the phase 1853 * offset monitor feature is enabled. 1854 */ 1855 if (zldpll->phase_monitor) { 1856 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id); 1857 if (rc) { 1858 dev_err(zldev->dev, 1859 "Failed to update phase offsets: %pe\n", 1860 ERR_PTR(rc)); 1861 return; 1862 } 1863 } 1864 1865 list_for_each_entry(pin, &zldpll->pins, list) { 1866 enum dpll_pin_state state; 1867 bool pin_changed = false; 1868 1869 /* Output pins change checks are not necessary because output 1870 * states are constant. 1871 */ 1872 if (!zl3073x_dpll_is_input_pin(pin)) 1873 continue; 1874 1875 rc = zl3073x_dpll_ref_state_get(pin, &state); 1876 if (rc) { 1877 dev_err(dev, 1878 "Failed to get %s on DPLL%u state: %pe\n", 1879 pin->label, zldpll->id, ERR_PTR(rc)); 1880 return; 1881 } 1882 1883 if (state != pin->pin_state) { 1884 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, 1885 pin->pin_state, state); 1886 pin->pin_state = state; 1887 pin_changed = true; 1888 } 1889 1890 /* Check for phase offset and ffo change once per second */ 1891 if (zldpll->check_count % 2 == 0) { 1892 if (zl3073x_dpll_pin_phase_offset_check(pin)) 1893 pin_changed = true; 1894 1895 if (zl3073x_dpll_pin_ffo_check(pin)) 1896 pin_changed = true; 1897 } 1898 1899 if (pin_changed) 1900 dpll_pin_change_ntf(pin->dpll_pin); 1901 } 1902 } 1903 1904 /** 1905 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments 1906 * @zldev: pointer to zl3073x device 1907 * 1908 * Performs initial fine phase adjustments needed per datasheet. 1909 * 1910 * Return: 0 on success, <0 on error 1911 */ 1912 int 1913 zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev) 1914 { 1915 int rc; 1916 1917 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); 1918 if (rc) 1919 return rc; 1920 1921 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); 1922 if (rc) 1923 return rc; 1924 1925 rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff); 1926 if (rc) 1927 return rc; 1928 1929 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); 1930 if (rc) 1931 return rc; 1932 1933 return rc; 1934 } 1935 1936 /** 1937 * zl3073x_dpll_alloc - allocate DPLL device 1938 * @zldev: pointer to zl3073x device 1939 * @ch: DPLL channel number 1940 * 1941 * Allocates DPLL device structure for given DPLL channel. 1942 * 1943 * Return: pointer to DPLL device on success, error pointer on error 1944 */ 1945 struct zl3073x_dpll * 1946 zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch) 1947 { 1948 struct zl3073x_dpll *zldpll; 1949 1950 zldpll = kzalloc_obj(*zldpll); 1951 if (!zldpll) 1952 return ERR_PTR(-ENOMEM); 1953 1954 zldpll->dev = zldev; 1955 zldpll->id = ch; 1956 INIT_LIST_HEAD(&zldpll->pins); 1957 INIT_WORK(&zldpll->change_work, zl3073x_dpll_change_work); 1958 1959 return zldpll; 1960 } 1961 1962 /** 1963 * zl3073x_dpll_free - free DPLL device 1964 * @zldpll: pointer to zl3073x_dpll structure 1965 * 1966 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc. 1967 */ 1968 void 1969 zl3073x_dpll_free(struct zl3073x_dpll *zldpll) 1970 { 1971 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); 1972 1973 kfree(zldpll); 1974 } 1975 1976 /** 1977 * zl3073x_dpll_register - register DPLL device and all its pins 1978 * @zldpll: pointer to zl3073x_dpll structure 1979 * 1980 * Registers given DPLL device and all its pins into DPLL sub-system. 1981 * 1982 * Return: 0 on success, <0 on error 1983 */ 1984 int 1985 zl3073x_dpll_register(struct zl3073x_dpll *zldpll) 1986 { 1987 int rc; 1988 1989 rc = zl3073x_dpll_device_register(zldpll); 1990 if (rc) 1991 return rc; 1992 1993 rc = zl3073x_dpll_pins_register(zldpll); 1994 if (rc) { 1995 zl3073x_dpll_device_unregister(zldpll); 1996 return rc; 1997 } 1998 1999 return 0; 2000 } 2001 2002 /** 2003 * zl3073x_dpll_unregister - unregister DPLL device and its pins 2004 * @zldpll: pointer to zl3073x_dpll structure 2005 * 2006 * Unregisters given DPLL device and all its pins from DPLL sub-system 2007 * previously registered by @zl3073x_dpll_register. 2008 */ 2009 void 2010 zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll) 2011 { 2012 /* Unregister all pins and dpll */ 2013 zl3073x_dpll_pins_unregister(zldpll); 2014 zl3073x_dpll_device_unregister(zldpll); 2015 } 2016