1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/bits.h> 4 #include <linux/bitfield.h> 5 #include <linux/bug.h> 6 #include <linux/container_of.h> 7 #include <linux/dev_printk.h> 8 #include <linux/dpll.h> 9 #include <linux/err.h> 10 #include <linux/kthread.h> 11 #include <linux/math64.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/netlink.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/sprintf.h> 18 19 #include "core.h" 20 #include "dpll.h" 21 #include "prop.h" 22 #include "regs.h" 23 24 #define ZL3073X_DPLL_REF_NONE ZL3073X_NUM_REFS 25 #define ZL3073X_DPLL_REF_IS_VALID(_ref) ((_ref) != ZL3073X_DPLL_REF_NONE) 26 27 /** 28 * struct zl3073x_dpll_pin - DPLL pin 29 * @list: this DPLL pin list entry 30 * @dpll: DPLL the pin is registered to 31 * @dpll_pin: pointer to registered dpll_pin 32 * @label: package label 33 * @dir: pin direction 34 * @id: pin id 35 * @prio: pin priority <0, 14> 36 * @selectable: pin is selectable in automatic mode 37 * @esync_control: embedded sync is controllable 38 * @phase_gran: phase adjustment granularity 39 * @pin_state: last saved pin state 40 * @phase_offset: last saved pin phase offset 41 * @freq_offset: last saved fractional frequency offset 42 */ 43 struct zl3073x_dpll_pin { 44 struct list_head list; 45 struct zl3073x_dpll *dpll; 46 struct dpll_pin *dpll_pin; 47 char label[8]; 48 enum dpll_pin_direction dir; 49 u8 id; 50 u8 prio; 51 bool selectable; 52 bool esync_control; 53 s32 phase_gran; 54 enum dpll_pin_state pin_state; 55 s64 phase_offset; 56 s64 freq_offset; 57 }; 58 59 /* 60 * Supported esync ranges for input and for output per output pair type 61 */ 62 static const struct dpll_pin_frequency esync_freq_ranges[] = { 63 DPLL_PIN_FREQUENCY_RANGE(0, 1), 64 }; 65 66 /** 67 * zl3073x_dpll_is_input_pin - check if the pin is input one 68 * @pin: pin to check 69 * 70 * Return: true if pin is input, false if pin is output. 71 */ 72 static bool 73 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin) 74 { 75 return pin->dir == DPLL_PIN_DIRECTION_INPUT; 76 } 77 78 /** 79 * zl3073x_dpll_is_p_pin - check if the pin is P-pin 80 * @pin: pin to check 81 * 82 * Return: true if the pin is P-pin, false if it is N-pin 83 */ 84 static bool 85 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin) 86 { 87 return zl3073x_is_p_pin(pin->id); 88 } 89 90 static int 91 zl3073x_dpll_pin_direction_get(const struct dpll_pin *dpll_pin, void *pin_priv, 92 const struct dpll_device *dpll, void *dpll_priv, 93 enum dpll_pin_direction *direction, 94 struct netlink_ext_ack *extack) 95 { 96 struct zl3073x_dpll_pin *pin = pin_priv; 97 98 *direction = pin->dir; 99 100 return 0; 101 } 102 103 /** 104 * zl3073x_dpll_input_ref_frequency_get - get input reference frequency 105 * @zldpll: pointer to zl3073x_dpll 106 * @ref_id: reference id 107 * @frequency: pointer to variable to store frequency 108 * 109 * Reads frequency of given input reference. 110 * 111 * Return: 0 on success, <0 on error 112 */ 113 static int 114 zl3073x_dpll_input_ref_frequency_get(struct zl3073x_dpll *zldpll, u8 ref_id, 115 u32 *frequency) 116 { 117 struct zl3073x_dev *zldev = zldpll->dev; 118 u16 base, mult, num, denom; 119 int rc; 120 121 guard(mutex)(&zldev->multiop_lock); 122 123 /* Read reference configuration */ 124 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 125 ZL_REG_REF_MB_MASK, BIT(ref_id)); 126 if (rc) 127 return rc; 128 129 /* Read registers to compute resulting frequency */ 130 rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_BASE, &base); 131 if (rc) 132 return rc; 133 rc = zl3073x_read_u16(zldev, ZL_REG_REF_FREQ_MULT, &mult); 134 if (rc) 135 return rc; 136 rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_M, &num); 137 if (rc) 138 return rc; 139 rc = zl3073x_read_u16(zldev, ZL_REG_REF_RATIO_N, &denom); 140 if (rc) 141 return rc; 142 143 /* Sanity check that HW has not returned zero denominator */ 144 if (!denom) { 145 dev_err(zldev->dev, 146 "Zero divisor for ref %u frequency got from device\n", 147 ref_id); 148 return -EINVAL; 149 } 150 151 /* Compute the frequency */ 152 *frequency = mul_u64_u32_div(base * mult, num, denom); 153 154 return rc; 155 } 156 157 static int 158 zl3073x_dpll_input_pin_esync_get(const struct dpll_pin *dpll_pin, 159 void *pin_priv, 160 const struct dpll_device *dpll, 161 void *dpll_priv, 162 struct dpll_pin_esync *esync, 163 struct netlink_ext_ack *extack) 164 { 165 struct zl3073x_dpll *zldpll = dpll_priv; 166 struct zl3073x_dev *zldev = zldpll->dev; 167 struct zl3073x_dpll_pin *pin = pin_priv; 168 u8 ref, ref_sync_ctrl, sync_mode; 169 u32 esync_div, ref_freq; 170 int rc; 171 172 /* Get reference frequency */ 173 ref = zl3073x_input_pin_ref_get(pin->id); 174 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, pin->id, &ref_freq); 175 if (rc) 176 return rc; 177 178 guard(mutex)(&zldev->multiop_lock); 179 180 /* Read reference configuration into mailbox */ 181 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 182 ZL_REG_REF_MB_MASK, BIT(ref)); 183 if (rc) 184 return rc; 185 186 /* Get ref sync mode */ 187 rc = zl3073x_read_u8(zldev, ZL_REG_REF_SYNC_CTRL, &ref_sync_ctrl); 188 if (rc) 189 return rc; 190 191 /* Get esync divisor */ 192 rc = zl3073x_read_u32(zldev, ZL_REG_REF_ESYNC_DIV, &esync_div); 193 if (rc) 194 return rc; 195 196 sync_mode = FIELD_GET(ZL_REF_SYNC_CTRL_MODE, ref_sync_ctrl); 197 198 switch (sync_mode) { 199 case ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75: 200 esync->freq = (esync_div == ZL_REF_ESYNC_DIV_1HZ) ? 1 : 0; 201 esync->pulse = 25; 202 break; 203 default: 204 esync->freq = 0; 205 esync->pulse = 0; 206 break; 207 } 208 209 /* If the pin supports esync control expose its range but only 210 * if the current reference frequency is > 1 Hz. 211 */ 212 if (pin->esync_control && ref_freq > 1) { 213 esync->range = esync_freq_ranges; 214 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 215 } else { 216 esync->range = NULL; 217 esync->range_num = 0; 218 } 219 220 return rc; 221 } 222 223 static int 224 zl3073x_dpll_input_pin_esync_set(const struct dpll_pin *dpll_pin, 225 void *pin_priv, 226 const struct dpll_device *dpll, 227 void *dpll_priv, u64 freq, 228 struct netlink_ext_ack *extack) 229 { 230 struct zl3073x_dpll *zldpll = dpll_priv; 231 struct zl3073x_dev *zldev = zldpll->dev; 232 struct zl3073x_dpll_pin *pin = pin_priv; 233 u8 ref, ref_sync_ctrl, sync_mode; 234 int rc; 235 236 guard(mutex)(&zldev->multiop_lock); 237 238 /* Read reference configuration into mailbox */ 239 ref = zl3073x_input_pin_ref_get(pin->id); 240 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 241 ZL_REG_REF_MB_MASK, BIT(ref)); 242 if (rc) 243 return rc; 244 245 /* Get ref sync mode */ 246 rc = zl3073x_read_u8(zldev, ZL_REG_REF_SYNC_CTRL, &ref_sync_ctrl); 247 if (rc) 248 return rc; 249 250 /* Use freq == 0 to disable esync */ 251 if (!freq) 252 sync_mode = ZL_REF_SYNC_CTRL_MODE_REFSYNC_PAIR_OFF; 253 else 254 sync_mode = ZL_REF_SYNC_CTRL_MODE_50_50_ESYNC_25_75; 255 256 ref_sync_ctrl &= ~ZL_REF_SYNC_CTRL_MODE; 257 ref_sync_ctrl |= FIELD_PREP(ZL_REF_SYNC_CTRL_MODE, sync_mode); 258 259 /* Update ref sync control register */ 260 rc = zl3073x_write_u8(zldev, ZL_REG_REF_SYNC_CTRL, ref_sync_ctrl); 261 if (rc) 262 return rc; 263 264 if (freq) { 265 /* 1 Hz is only supported frequnecy currently */ 266 rc = zl3073x_write_u32(zldev, ZL_REG_REF_ESYNC_DIV, 267 ZL_REF_ESYNC_DIV_1HZ); 268 if (rc) 269 return rc; 270 } 271 272 /* Commit reference configuration */ 273 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR, 274 ZL_REG_REF_MB_MASK, BIT(ref)); 275 } 276 277 static int 278 zl3073x_dpll_input_pin_ffo_get(const struct dpll_pin *dpll_pin, void *pin_priv, 279 const struct dpll_device *dpll, void *dpll_priv, 280 s64 *ffo, struct netlink_ext_ack *extack) 281 { 282 struct zl3073x_dpll_pin *pin = pin_priv; 283 284 *ffo = pin->freq_offset; 285 286 return 0; 287 } 288 289 static int 290 zl3073x_dpll_input_pin_frequency_get(const struct dpll_pin *dpll_pin, 291 void *pin_priv, 292 const struct dpll_device *dpll, 293 void *dpll_priv, u64 *frequency, 294 struct netlink_ext_ack *extack) 295 { 296 struct zl3073x_dpll *zldpll = dpll_priv; 297 struct zl3073x_dpll_pin *pin = pin_priv; 298 u32 ref_freq; 299 u8 ref; 300 int rc; 301 302 /* Read and return ref frequency */ 303 ref = zl3073x_input_pin_ref_get(pin->id); 304 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, ref, &ref_freq); 305 if (!rc) 306 *frequency = ref_freq; 307 308 return rc; 309 } 310 311 static int 312 zl3073x_dpll_input_pin_frequency_set(const struct dpll_pin *dpll_pin, 313 void *pin_priv, 314 const struct dpll_device *dpll, 315 void *dpll_priv, u64 frequency, 316 struct netlink_ext_ack *extack) 317 { 318 struct zl3073x_dpll *zldpll = dpll_priv; 319 struct zl3073x_dev *zldev = zldpll->dev; 320 struct zl3073x_dpll_pin *pin = pin_priv; 321 u16 base, mult; 322 u8 ref; 323 int rc; 324 325 /* Get base frequency and multiplier for the requested frequency */ 326 rc = zl3073x_ref_freq_factorize(frequency, &base, &mult); 327 if (rc) 328 return rc; 329 330 guard(mutex)(&zldev->multiop_lock); 331 332 /* Load reference configuration */ 333 ref = zl3073x_input_pin_ref_get(pin->id); 334 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 335 ZL_REG_REF_MB_MASK, BIT(ref)); 336 337 /* Update base frequency, multiplier, numerator & denominator */ 338 rc = zl3073x_write_u16(zldev, ZL_REG_REF_FREQ_BASE, base); 339 if (rc) 340 return rc; 341 rc = zl3073x_write_u16(zldev, ZL_REG_REF_FREQ_MULT, mult); 342 if (rc) 343 return rc; 344 rc = zl3073x_write_u16(zldev, ZL_REG_REF_RATIO_M, 1); 345 if (rc) 346 return rc; 347 rc = zl3073x_write_u16(zldev, ZL_REG_REF_RATIO_N, 1); 348 if (rc) 349 return rc; 350 351 /* Commit reference configuration */ 352 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR, 353 ZL_REG_REF_MB_MASK, BIT(ref)); 354 } 355 356 /** 357 * zl3073x_dpll_selected_ref_get - get currently selected reference 358 * @zldpll: pointer to zl3073x_dpll 359 * @ref: place to store selected reference 360 * 361 * Check for currently selected reference the DPLL should be locked to 362 * and stores its index to given @ref. 363 * 364 * Return: 0 on success, <0 on error 365 */ 366 static int 367 zl3073x_dpll_selected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 368 { 369 struct zl3073x_dev *zldev = zldpll->dev; 370 u8 state, value; 371 int rc; 372 373 switch (zldpll->refsel_mode) { 374 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 375 /* For automatic mode read refsel_status register */ 376 rc = zl3073x_read_u8(zldev, 377 ZL_REG_DPLL_REFSEL_STATUS(zldpll->id), 378 &value); 379 if (rc) 380 return rc; 381 382 /* Extract reference state */ 383 state = FIELD_GET(ZL_DPLL_REFSEL_STATUS_STATE, value); 384 385 /* Return the reference only if the DPLL is locked to it */ 386 if (state == ZL_DPLL_REFSEL_STATUS_STATE_LOCK) 387 *ref = FIELD_GET(ZL_DPLL_REFSEL_STATUS_REFSEL, value); 388 else 389 *ref = ZL3073X_DPLL_REF_NONE; 390 break; 391 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 392 /* For manual mode return stored value */ 393 *ref = zldpll->forced_ref; 394 break; 395 default: 396 /* For other modes like NCO, freerun... there is no input ref */ 397 *ref = ZL3073X_DPLL_REF_NONE; 398 break; 399 } 400 401 return 0; 402 } 403 404 /** 405 * zl3073x_dpll_selected_ref_set - select reference in manual mode 406 * @zldpll: pointer to zl3073x_dpll 407 * @ref: input reference to be selected 408 * 409 * Selects the given reference for the DPLL channel it should be 410 * locked to. 411 * 412 * Return: 0 on success, <0 on error 413 */ 414 static int 415 zl3073x_dpll_selected_ref_set(struct zl3073x_dpll *zldpll, u8 ref) 416 { 417 struct zl3073x_dev *zldev = zldpll->dev; 418 u8 mode, mode_refsel; 419 int rc; 420 421 mode = zldpll->refsel_mode; 422 423 switch (mode) { 424 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 425 /* Manual mode with ref selected */ 426 if (ref == ZL3073X_DPLL_REF_NONE) { 427 switch (zldpll->lock_status) { 428 case DPLL_LOCK_STATUS_LOCKED_HO_ACQ: 429 case DPLL_LOCK_STATUS_HOLDOVER: 430 /* Switch to forced holdover */ 431 mode = ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER; 432 break; 433 default: 434 /* Switch to freerun */ 435 mode = ZL_DPLL_MODE_REFSEL_MODE_FREERUN; 436 break; 437 } 438 /* Keep selected reference */ 439 ref = zldpll->forced_ref; 440 } else if (ref == zldpll->forced_ref) { 441 /* No register update - same mode and same ref */ 442 return 0; 443 } 444 break; 445 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 446 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 447 /* Manual mode without no ref */ 448 if (ref == ZL3073X_DPLL_REF_NONE) 449 /* No register update - keep current mode */ 450 return 0; 451 452 /* Switch to reflock mode and update ref selection */ 453 mode = ZL_DPLL_MODE_REFSEL_MODE_REFLOCK; 454 break; 455 default: 456 /* For other modes like automatic or NCO ref cannot be selected 457 * manually 458 */ 459 return -EOPNOTSUPP; 460 } 461 462 /* Build mode_refsel value */ 463 mode_refsel = FIELD_PREP(ZL_DPLL_MODE_REFSEL_MODE, mode) | 464 FIELD_PREP(ZL_DPLL_MODE_REFSEL_REF, ref); 465 466 /* Update dpll_mode_refsel register */ 467 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 468 mode_refsel); 469 if (rc) 470 return rc; 471 472 /* Store new mode and forced reference */ 473 zldpll->refsel_mode = mode; 474 zldpll->forced_ref = ref; 475 476 return rc; 477 } 478 479 /** 480 * zl3073x_dpll_connected_ref_get - get currently connected reference 481 * @zldpll: pointer to zl3073x_dpll 482 * @ref: place to store selected reference 483 * 484 * Looks for currently connected the DPLL is locked to and stores its index 485 * to given @ref. 486 * 487 * Return: 0 on success, <0 on error 488 */ 489 static int 490 zl3073x_dpll_connected_ref_get(struct zl3073x_dpll *zldpll, u8 *ref) 491 { 492 struct zl3073x_dev *zldev = zldpll->dev; 493 int rc; 494 495 /* Get currently selected input reference */ 496 rc = zl3073x_dpll_selected_ref_get(zldpll, ref); 497 if (rc) 498 return rc; 499 500 if (ZL3073X_DPLL_REF_IS_VALID(*ref)) { 501 u8 ref_status; 502 503 /* Read the reference monitor status */ 504 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(*ref), 505 &ref_status); 506 if (rc) 507 return rc; 508 509 /* If the monitor indicates an error nothing is connected */ 510 if (ref_status != ZL_REF_MON_STATUS_OK) 511 *ref = ZL3073X_DPLL_REF_NONE; 512 } 513 514 return 0; 515 } 516 517 static int 518 zl3073x_dpll_input_pin_phase_offset_get(const struct dpll_pin *dpll_pin, 519 void *pin_priv, 520 const struct dpll_device *dpll, 521 void *dpll_priv, s64 *phase_offset, 522 struct netlink_ext_ack *extack) 523 { 524 struct zl3073x_dpll *zldpll = dpll_priv; 525 struct zl3073x_dev *zldev = zldpll->dev; 526 struct zl3073x_dpll_pin *pin = pin_priv; 527 u8 conn_ref, ref, ref_status; 528 s64 ref_phase; 529 int rc; 530 531 /* Get currently connected reference */ 532 rc = zl3073x_dpll_connected_ref_get(zldpll, &conn_ref); 533 if (rc) 534 return rc; 535 536 /* Report phase offset only for currently connected pin if the phase 537 * monitor feature is disabled. 538 */ 539 ref = zl3073x_input_pin_ref_get(pin->id); 540 if (!zldpll->phase_monitor && ref != conn_ref) { 541 *phase_offset = 0; 542 543 return 0; 544 } 545 546 /* Get this pin monitor status */ 547 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), &ref_status); 548 if (rc) 549 return rc; 550 551 /* Report phase offset only if the input pin signal is present */ 552 if (ref_status != ZL_REF_MON_STATUS_OK) { 553 *phase_offset = 0; 554 555 return 0; 556 } 557 558 ref_phase = pin->phase_offset; 559 560 /* The DPLL being locked to a higher freq than the current ref 561 * the phase offset is modded to the period of the signal 562 * the dpll is locked to. 563 */ 564 if (ZL3073X_DPLL_REF_IS_VALID(conn_ref) && conn_ref != ref) { 565 u32 conn_freq, ref_freq; 566 567 /* Get frequency of connected ref */ 568 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, conn_ref, 569 &conn_freq); 570 if (rc) 571 return rc; 572 573 /* Get frequency of given ref */ 574 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, ref, 575 &ref_freq); 576 if (rc) 577 return rc; 578 579 if (conn_freq > ref_freq) { 580 s64 conn_period, div_factor; 581 582 conn_period = div_s64(PSEC_PER_SEC, conn_freq); 583 div_factor = div64_s64(ref_phase, conn_period); 584 ref_phase -= conn_period * div_factor; 585 } 586 } 587 588 *phase_offset = ref_phase * DPLL_PHASE_OFFSET_DIVIDER; 589 590 return rc; 591 } 592 593 static int 594 zl3073x_dpll_input_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 595 void *pin_priv, 596 const struct dpll_device *dpll, 597 void *dpll_priv, 598 s32 *phase_adjust, 599 struct netlink_ext_ack *extack) 600 { 601 struct zl3073x_dpll *zldpll = dpll_priv; 602 struct zl3073x_dev *zldev = zldpll->dev; 603 struct zl3073x_dpll_pin *pin = pin_priv; 604 s64 phase_comp; 605 u8 ref; 606 int rc; 607 608 guard(mutex)(&zldev->multiop_lock); 609 610 /* Read reference configuration */ 611 ref = zl3073x_input_pin_ref_get(pin->id); 612 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 613 ZL_REG_REF_MB_MASK, BIT(ref)); 614 if (rc) 615 return rc; 616 617 /* Read current phase offset compensation */ 618 rc = zl3073x_read_u48(zldev, ZL_REG_REF_PHASE_OFFSET_COMP, &phase_comp); 619 if (rc) 620 return rc; 621 622 /* Perform sign extension for 48bit signed value */ 623 phase_comp = sign_extend64(phase_comp, 47); 624 625 /* Reverse two's complement negation applied during set and convert 626 * to 32bit signed int 627 */ 628 *phase_adjust = (s32)-phase_comp; 629 630 return rc; 631 } 632 633 static int 634 zl3073x_dpll_input_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 635 void *pin_priv, 636 const struct dpll_device *dpll, 637 void *dpll_priv, 638 s32 phase_adjust, 639 struct netlink_ext_ack *extack) 640 { 641 struct zl3073x_dpll *zldpll = dpll_priv; 642 struct zl3073x_dev *zldev = zldpll->dev; 643 struct zl3073x_dpll_pin *pin = pin_priv; 644 s64 phase_comp; 645 u8 ref; 646 int rc; 647 648 /* The value in the register is stored as two's complement negation 649 * of requested value. 650 */ 651 phase_comp = -phase_adjust; 652 653 guard(mutex)(&zldev->multiop_lock); 654 655 /* Read reference configuration */ 656 ref = zl3073x_input_pin_ref_get(pin->id); 657 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 658 ZL_REG_REF_MB_MASK, BIT(ref)); 659 if (rc) 660 return rc; 661 662 /* Write the requested value into the compensation register */ 663 rc = zl3073x_write_u48(zldev, ZL_REG_REF_PHASE_OFFSET_COMP, phase_comp); 664 if (rc) 665 return rc; 666 667 /* Commit reference configuration */ 668 return zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_WR, 669 ZL_REG_REF_MB_MASK, BIT(ref)); 670 } 671 672 /** 673 * zl3073x_dpll_ref_prio_get - get priority for given input pin 674 * @pin: pointer to pin 675 * @prio: place to store priority 676 * 677 * Reads current priority for the given input pin and stores the value 678 * to @prio. 679 * 680 * Return: 0 on success, <0 on error 681 */ 682 static int 683 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio) 684 { 685 struct zl3073x_dpll *zldpll = pin->dpll; 686 struct zl3073x_dev *zldev = zldpll->dev; 687 u8 ref, ref_prio; 688 int rc; 689 690 guard(mutex)(&zldev->multiop_lock); 691 692 /* Read DPLL configuration */ 693 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 694 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 695 if (rc) 696 return rc; 697 698 /* Read reference priority - one value for P&N pins (4 bits/pin) */ 699 ref = zl3073x_input_pin_ref_get(pin->id); 700 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), 701 &ref_prio); 702 if (rc) 703 return rc; 704 705 /* Select nibble according pin type */ 706 if (zl3073x_dpll_is_p_pin(pin)) 707 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_P, ref_prio); 708 else 709 *prio = FIELD_GET(ZL_DPLL_REF_PRIO_REF_N, ref_prio); 710 711 return rc; 712 } 713 714 /** 715 * zl3073x_dpll_ref_prio_set - set priority for given input pin 716 * @pin: pointer to pin 717 * @prio: place to store priority 718 * 719 * Sets priority for the given input pin. 720 * 721 * Return: 0 on success, <0 on error 722 */ 723 static int 724 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio) 725 { 726 struct zl3073x_dpll *zldpll = pin->dpll; 727 struct zl3073x_dev *zldev = zldpll->dev; 728 u8 ref, ref_prio; 729 int rc; 730 731 guard(mutex)(&zldev->multiop_lock); 732 733 /* Read DPLL configuration into mailbox */ 734 rc = zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_RD, 735 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 736 if (rc) 737 return rc; 738 739 /* Read reference priority - one value shared between P&N pins */ 740 ref = zl3073x_input_pin_ref_get(pin->id); 741 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), &ref_prio); 742 if (rc) 743 return rc; 744 745 /* Update nibble according pin type */ 746 if (zl3073x_dpll_is_p_pin(pin)) { 747 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_P; 748 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_P, prio); 749 } else { 750 ref_prio &= ~ZL_DPLL_REF_PRIO_REF_N; 751 ref_prio |= FIELD_PREP(ZL_DPLL_REF_PRIO_REF_N, prio); 752 } 753 754 /* Update reference priority */ 755 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_REF_PRIO(ref / 2), ref_prio); 756 if (rc) 757 return rc; 758 759 /* Commit configuration */ 760 return zl3073x_mb_op(zldev, ZL_REG_DPLL_MB_SEM, ZL_DPLL_MB_SEM_WR, 761 ZL_REG_DPLL_MB_MASK, BIT(zldpll->id)); 762 } 763 764 /** 765 * zl3073x_dpll_ref_state_get - get status for given input pin 766 * @pin: pointer to pin 767 * @state: place to store status 768 * 769 * Checks current status for the given input pin and stores the value 770 * to @state. 771 * 772 * Return: 0 on success, <0 on error 773 */ 774 static int 775 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin, 776 enum dpll_pin_state *state) 777 { 778 struct zl3073x_dpll *zldpll = pin->dpll; 779 struct zl3073x_dev *zldev = zldpll->dev; 780 u8 ref, ref_conn, status; 781 int rc; 782 783 ref = zl3073x_input_pin_ref_get(pin->id); 784 785 /* Get currently connected reference */ 786 rc = zl3073x_dpll_connected_ref_get(zldpll, &ref_conn); 787 if (rc) 788 return rc; 789 790 if (ref == ref_conn) { 791 *state = DPLL_PIN_STATE_CONNECTED; 792 return 0; 793 } 794 795 /* If the DPLL is running in automatic mode and the reference is 796 * selectable and its monitor does not report any error then report 797 * pin as selectable. 798 */ 799 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_AUTO && 800 pin->selectable) { 801 /* Read reference monitor status */ 802 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), 803 &status); 804 if (rc) 805 return rc; 806 807 /* If the monitor indicates errors report the reference 808 * as disconnected 809 */ 810 if (status == ZL_REF_MON_STATUS_OK) { 811 *state = DPLL_PIN_STATE_SELECTABLE; 812 return 0; 813 } 814 } 815 816 /* Otherwise report the pin as disconnected */ 817 *state = DPLL_PIN_STATE_DISCONNECTED; 818 819 return 0; 820 } 821 822 static int 823 zl3073x_dpll_input_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 824 void *pin_priv, 825 const struct dpll_device *dpll, 826 void *dpll_priv, 827 enum dpll_pin_state *state, 828 struct netlink_ext_ack *extack) 829 { 830 struct zl3073x_dpll_pin *pin = pin_priv; 831 832 return zl3073x_dpll_ref_state_get(pin, state); 833 } 834 835 static int 836 zl3073x_dpll_input_pin_state_on_dpll_set(const struct dpll_pin *dpll_pin, 837 void *pin_priv, 838 const struct dpll_device *dpll, 839 void *dpll_priv, 840 enum dpll_pin_state state, 841 struct netlink_ext_ack *extack) 842 { 843 struct zl3073x_dpll *zldpll = dpll_priv; 844 struct zl3073x_dpll_pin *pin = pin_priv; 845 u8 new_ref; 846 int rc; 847 848 switch (zldpll->refsel_mode) { 849 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 850 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 851 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 852 if (state == DPLL_PIN_STATE_CONNECTED) { 853 /* Choose the pin as new selected reference */ 854 new_ref = zl3073x_input_pin_ref_get(pin->id); 855 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 856 /* No reference */ 857 new_ref = ZL3073X_DPLL_REF_NONE; 858 } else { 859 NL_SET_ERR_MSG_MOD(extack, 860 "Invalid pin state for manual mode"); 861 return -EINVAL; 862 } 863 864 rc = zl3073x_dpll_selected_ref_set(zldpll, new_ref); 865 break; 866 867 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 868 if (state == DPLL_PIN_STATE_SELECTABLE) { 869 if (pin->selectable) 870 return 0; /* Pin is already selectable */ 871 872 /* Restore pin priority in HW */ 873 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio); 874 if (rc) 875 return rc; 876 877 /* Mark pin as selectable */ 878 pin->selectable = true; 879 } else if (state == DPLL_PIN_STATE_DISCONNECTED) { 880 if (!pin->selectable) 881 return 0; /* Pin is already disconnected */ 882 883 /* Set pin priority to none in HW */ 884 rc = zl3073x_dpll_ref_prio_set(pin, 885 ZL_DPLL_REF_PRIO_NONE); 886 if (rc) 887 return rc; 888 889 /* Mark pin as non-selectable */ 890 pin->selectable = false; 891 } else { 892 NL_SET_ERR_MSG(extack, 893 "Invalid pin state for automatic mode"); 894 return -EINVAL; 895 } 896 break; 897 898 default: 899 /* In other modes we cannot change input reference */ 900 NL_SET_ERR_MSG(extack, 901 "Pin state cannot be changed in current mode"); 902 rc = -EOPNOTSUPP; 903 break; 904 } 905 906 return rc; 907 } 908 909 static int 910 zl3073x_dpll_input_pin_prio_get(const struct dpll_pin *dpll_pin, void *pin_priv, 911 const struct dpll_device *dpll, void *dpll_priv, 912 u32 *prio, struct netlink_ext_ack *extack) 913 { 914 struct zl3073x_dpll_pin *pin = pin_priv; 915 916 *prio = pin->prio; 917 918 return 0; 919 } 920 921 static int 922 zl3073x_dpll_input_pin_prio_set(const struct dpll_pin *dpll_pin, void *pin_priv, 923 const struct dpll_device *dpll, void *dpll_priv, 924 u32 prio, struct netlink_ext_ack *extack) 925 { 926 struct zl3073x_dpll_pin *pin = pin_priv; 927 int rc; 928 929 if (prio > ZL_DPLL_REF_PRIO_MAX) 930 return -EINVAL; 931 932 /* If the pin is selectable then update HW registers */ 933 if (pin->selectable) { 934 rc = zl3073x_dpll_ref_prio_set(pin, prio); 935 if (rc) 936 return rc; 937 } 938 939 /* Save priority */ 940 pin->prio = prio; 941 942 return 0; 943 } 944 945 static int 946 zl3073x_dpll_output_pin_esync_get(const struct dpll_pin *dpll_pin, 947 void *pin_priv, 948 const struct dpll_device *dpll, 949 void *dpll_priv, 950 struct dpll_pin_esync *esync, 951 struct netlink_ext_ack *extack) 952 { 953 struct zl3073x_dpll *zldpll = dpll_priv; 954 struct zl3073x_dev *zldev = zldpll->dev; 955 struct zl3073x_dpll_pin *pin = pin_priv; 956 struct device *dev = zldev->dev; 957 u32 esync_period, esync_width; 958 u8 clock_type, synth; 959 u8 out, output_mode; 960 u32 output_div; 961 u32 synth_freq; 962 int rc; 963 964 out = zl3073x_output_pin_out_get(pin->id); 965 966 /* If N-division is enabled, esync is not supported. The register used 967 * for N-division is also used for the esync divider so both cannot 968 * be used. 969 */ 970 switch (zl3073x_out_signal_format_get(zldev, out)) { 971 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 972 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 973 return -EOPNOTSUPP; 974 default: 975 break; 976 } 977 978 guard(mutex)(&zldev->multiop_lock); 979 980 /* Read output configuration into mailbox */ 981 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 982 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 983 if (rc) 984 return rc; 985 986 /* Read output mode */ 987 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode); 988 if (rc) 989 return rc; 990 991 /* Read output divisor */ 992 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div); 993 if (rc) 994 return rc; 995 996 /* Check output divisor for zero */ 997 if (!output_div) { 998 dev_err(dev, "Zero divisor for OUTPUT%u got from device\n", 999 out); 1000 return -EINVAL; 1001 } 1002 1003 /* Get synth attached to output pin */ 1004 synth = zl3073x_out_synth_get(zldev, out); 1005 1006 /* Get synth frequency */ 1007 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1008 1009 clock_type = FIELD_GET(ZL_OUTPUT_MODE_CLOCK_TYPE, output_mode); 1010 if (clock_type != ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC) { 1011 /* No need to read esync data if it is not enabled */ 1012 esync->freq = 0; 1013 esync->pulse = 0; 1014 1015 goto finish; 1016 } 1017 1018 /* Read esync period */ 1019 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, &esync_period); 1020 if (rc) 1021 return rc; 1022 1023 /* Check esync divisor for zero */ 1024 if (!esync_period) { 1025 dev_err(dev, "Zero esync divisor for OUTPUT%u got from device\n", 1026 out); 1027 return -EINVAL; 1028 } 1029 1030 /* Get esync pulse width in units of half synth cycles */ 1031 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, &esync_width); 1032 if (rc) 1033 return rc; 1034 1035 /* Compute esync frequency */ 1036 esync->freq = synth_freq / output_div / esync_period; 1037 1038 /* By comparing the esync_pulse_width to the half of the pulse width 1039 * the esync pulse percentage can be determined. 1040 * Note that half pulse width is in units of half synth cycles, which 1041 * is why it reduces down to be output_div. 1042 */ 1043 esync->pulse = (50 * esync_width) / output_div; 1044 1045 finish: 1046 /* Set supported esync ranges if the pin supports esync control and 1047 * if the output frequency is > 1 Hz. 1048 */ 1049 if (pin->esync_control && (synth_freq / output_div) > 1) { 1050 esync->range = esync_freq_ranges; 1051 esync->range_num = ARRAY_SIZE(esync_freq_ranges); 1052 } else { 1053 esync->range = NULL; 1054 esync->range_num = 0; 1055 } 1056 1057 return 0; 1058 } 1059 1060 static int 1061 zl3073x_dpll_output_pin_esync_set(const struct dpll_pin *dpll_pin, 1062 void *pin_priv, 1063 const struct dpll_device *dpll, 1064 void *dpll_priv, u64 freq, 1065 struct netlink_ext_ack *extack) 1066 { 1067 u32 esync_period, esync_width, output_div; 1068 struct zl3073x_dpll *zldpll = dpll_priv; 1069 struct zl3073x_dev *zldev = zldpll->dev; 1070 struct zl3073x_dpll_pin *pin = pin_priv; 1071 u8 clock_type, out, output_mode, synth; 1072 u32 synth_freq; 1073 int rc; 1074 1075 out = zl3073x_output_pin_out_get(pin->id); 1076 1077 /* If N-division is enabled, esync is not supported. The register used 1078 * for N-division is also used for the esync divider so both cannot 1079 * be used. 1080 */ 1081 switch (zl3073x_out_signal_format_get(zldev, out)) { 1082 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 1083 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 1084 return -EOPNOTSUPP; 1085 default: 1086 break; 1087 } 1088 1089 guard(mutex)(&zldev->multiop_lock); 1090 1091 /* Read output configuration into mailbox */ 1092 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1093 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1094 if (rc) 1095 return rc; 1096 1097 /* Read output mode */ 1098 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode); 1099 if (rc) 1100 return rc; 1101 1102 /* Select clock type */ 1103 if (freq) 1104 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_ESYNC; 1105 else 1106 clock_type = ZL_OUTPUT_MODE_CLOCK_TYPE_NORMAL; 1107 1108 /* Update clock type in output mode */ 1109 output_mode &= ~ZL_OUTPUT_MODE_CLOCK_TYPE; 1110 output_mode |= FIELD_PREP(ZL_OUTPUT_MODE_CLOCK_TYPE, clock_type); 1111 rc = zl3073x_write_u8(zldev, ZL_REG_OUTPUT_MODE, output_mode); 1112 if (rc) 1113 return rc; 1114 1115 /* If esync is being disabled just write mailbox and finish */ 1116 if (!freq) 1117 goto write_mailbox; 1118 1119 /* Get synth attached to output pin */ 1120 synth = zl3073x_out_synth_get(zldev, out); 1121 1122 /* Get synth frequency */ 1123 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1124 1125 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div); 1126 if (rc) 1127 return rc; 1128 1129 /* Check output divisor for zero */ 1130 if (!output_div) { 1131 dev_err(zldev->dev, 1132 "Zero divisor for OUTPUT%u got from device\n", out); 1133 return -EINVAL; 1134 } 1135 1136 /* Compute and update esync period */ 1137 esync_period = synth_freq / (u32)freq / output_div; 1138 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, esync_period); 1139 if (rc) 1140 return rc; 1141 1142 /* Half of the period in units of 1/2 synth cycle can be represented by 1143 * the output_div. To get the supported esync pulse width of 25% of the 1144 * period the output_div can just be divided by 2. Note that this 1145 * assumes that output_div is even, otherwise some resolution will be 1146 * lost. 1147 */ 1148 esync_width = output_div / 2; 1149 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, esync_width); 1150 if (rc) 1151 return rc; 1152 1153 write_mailbox: 1154 /* Commit output configuration */ 1155 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 1156 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1157 } 1158 1159 static int 1160 zl3073x_dpll_output_pin_frequency_get(const struct dpll_pin *dpll_pin, 1161 void *pin_priv, 1162 const struct dpll_device *dpll, 1163 void *dpll_priv, u64 *frequency, 1164 struct netlink_ext_ack *extack) 1165 { 1166 struct zl3073x_dpll *zldpll = dpll_priv; 1167 struct zl3073x_dev *zldev = zldpll->dev; 1168 struct zl3073x_dpll_pin *pin = pin_priv; 1169 struct device *dev = zldev->dev; 1170 u8 out, signal_format, synth; 1171 u32 output_div, synth_freq; 1172 int rc; 1173 1174 out = zl3073x_output_pin_out_get(pin->id); 1175 synth = zl3073x_out_synth_get(zldev, out); 1176 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1177 1178 guard(mutex)(&zldev->multiop_lock); 1179 1180 /* Read output configuration into mailbox */ 1181 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1182 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1183 if (rc) 1184 return rc; 1185 1186 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &output_div); 1187 if (rc) 1188 return rc; 1189 1190 /* Check output divisor for zero */ 1191 if (!output_div) { 1192 dev_err(dev, "Zero divisor for output %u got from device\n", 1193 out); 1194 return -EINVAL; 1195 } 1196 1197 /* Read used signal format for the given output */ 1198 signal_format = zl3073x_out_signal_format_get(zldev, out); 1199 1200 switch (signal_format) { 1201 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV: 1202 case ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV: 1203 /* In case of divided format we have to distiguish between 1204 * given output pin type. 1205 */ 1206 if (zl3073x_dpll_is_p_pin(pin)) { 1207 /* For P-pin the resulting frequency is computed as 1208 * simple division of synth frequency and output 1209 * divisor. 1210 */ 1211 *frequency = synth_freq / output_div; 1212 } else { 1213 /* For N-pin we have to divide additionally by 1214 * divisor stored in esync_period output mailbox 1215 * register that is used as N-pin divisor for these 1216 * modes. 1217 */ 1218 u32 ndiv; 1219 1220 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, 1221 &ndiv); 1222 if (rc) 1223 return rc; 1224 1225 /* Check N-pin divisor for zero */ 1226 if (!ndiv) { 1227 dev_err(dev, 1228 "Zero N-pin divisor for output %u got from device\n", 1229 out); 1230 return -EINVAL; 1231 } 1232 1233 /* Compute final divisor for N-pin */ 1234 *frequency = synth_freq / output_div / ndiv; 1235 } 1236 break; 1237 default: 1238 /* In other modes the resulting frequency is computed as 1239 * division of synth frequency and output divisor. 1240 */ 1241 *frequency = synth_freq / output_div; 1242 break; 1243 } 1244 1245 return rc; 1246 } 1247 1248 static int 1249 zl3073x_dpll_output_pin_frequency_set(const struct dpll_pin *dpll_pin, 1250 void *pin_priv, 1251 const struct dpll_device *dpll, 1252 void *dpll_priv, u64 frequency, 1253 struct netlink_ext_ack *extack) 1254 { 1255 struct zl3073x_dpll *zldpll = dpll_priv; 1256 struct zl3073x_dev *zldev = zldpll->dev; 1257 struct zl3073x_dpll_pin *pin = pin_priv; 1258 struct device *dev = zldev->dev; 1259 u32 output_n_freq, output_p_freq; 1260 u8 out, signal_format, synth; 1261 u32 cur_div, new_div, ndiv; 1262 u32 synth_freq; 1263 int rc; 1264 1265 out = zl3073x_output_pin_out_get(pin->id); 1266 synth = zl3073x_out_synth_get(zldev, out); 1267 synth_freq = zl3073x_synth_freq_get(zldev, synth); 1268 new_div = synth_freq / (u32)frequency; 1269 1270 /* Get used signal format for the given output */ 1271 signal_format = zl3073x_out_signal_format_get(zldev, out); 1272 1273 guard(mutex)(&zldev->multiop_lock); 1274 1275 /* Load output configuration */ 1276 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1277 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1278 if (rc) 1279 return rc; 1280 1281 /* Check signal format */ 1282 if (signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV && 1283 signal_format != ZL_OUTPUT_MODE_SIGNAL_FORMAT_2_NDIV_INV) { 1284 /* For non N-divided signal formats the frequency is computed 1285 * as division of synth frequency and output divisor. 1286 */ 1287 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_DIV, new_div); 1288 if (rc) 1289 return rc; 1290 1291 /* For 50/50 duty cycle the divisor is equal to width */ 1292 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_WIDTH, new_div); 1293 if (rc) 1294 return rc; 1295 1296 /* Commit output configuration */ 1297 return zl3073x_mb_op(zldev, 1298 ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 1299 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1300 } 1301 1302 /* For N-divided signal format get current divisor */ 1303 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_DIV, &cur_div); 1304 if (rc) 1305 return rc; 1306 1307 /* Check output divisor for zero */ 1308 if (!cur_div) { 1309 dev_err(dev, "Zero divisor for output %u got from device\n", 1310 out); 1311 return -EINVAL; 1312 } 1313 1314 /* Get N-pin divisor (shares the same register with esync */ 1315 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, &ndiv); 1316 if (rc) 1317 return rc; 1318 1319 /* Check N-pin divisor for zero */ 1320 if (!ndiv) { 1321 dev_err(dev, 1322 "Zero N-pin divisor for output %u got from device\n", 1323 out); 1324 return -EINVAL; 1325 } 1326 1327 /* Compute current output frequency for P-pin */ 1328 output_p_freq = synth_freq / cur_div; 1329 1330 /* Compute current N-pin frequency */ 1331 output_n_freq = output_p_freq / ndiv; 1332 1333 if (zl3073x_dpll_is_p_pin(pin)) { 1334 /* We are going to change output frequency for P-pin but 1335 * if the requested frequency is less than current N-pin 1336 * frequency then indicate a failure as we are not able 1337 * to compute N-pin divisor to keep its frequency unchanged. 1338 */ 1339 if (frequency <= output_n_freq) 1340 return -EINVAL; 1341 1342 /* Update the output divisor */ 1343 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_DIV, new_div); 1344 if (rc) 1345 return rc; 1346 1347 /* For 50/50 duty cycle the divisor is equal to width */ 1348 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_WIDTH, new_div); 1349 if (rc) 1350 return rc; 1351 1352 /* Compute new divisor for N-pin */ 1353 ndiv = (u32)frequency / output_n_freq; 1354 } else { 1355 /* We are going to change frequency of N-pin but if 1356 * the requested freq is greater or equal than freq of P-pin 1357 * in the output pair we cannot compute divisor for the N-pin. 1358 * In this case indicate a failure. 1359 */ 1360 if (output_p_freq <= frequency) 1361 return -EINVAL; 1362 1363 /* Compute new divisor for N-pin */ 1364 ndiv = output_p_freq / (u32)frequency; 1365 } 1366 1367 /* Update divisor for the N-pin */ 1368 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_PERIOD, ndiv); 1369 if (rc) 1370 return rc; 1371 1372 /* For 50/50 duty cycle the divisor is equal to width */ 1373 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_ESYNC_WIDTH, ndiv); 1374 if (rc) 1375 return rc; 1376 1377 /* Commit output configuration */ 1378 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 1379 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1380 } 1381 1382 static int 1383 zl3073x_dpll_output_pin_phase_adjust_get(const struct dpll_pin *dpll_pin, 1384 void *pin_priv, 1385 const struct dpll_device *dpll, 1386 void *dpll_priv, 1387 s32 *phase_adjust, 1388 struct netlink_ext_ack *extack) 1389 { 1390 struct zl3073x_dpll *zldpll = dpll_priv; 1391 struct zl3073x_dev *zldev = zldpll->dev; 1392 struct zl3073x_dpll_pin *pin = pin_priv; 1393 s32 phase_comp; 1394 u8 out; 1395 int rc; 1396 1397 guard(mutex)(&zldev->multiop_lock); 1398 1399 /* Read output configuration */ 1400 out = zl3073x_output_pin_out_get(pin->id); 1401 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1402 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1403 if (rc) 1404 return rc; 1405 1406 /* Read current output phase compensation */ 1407 rc = zl3073x_read_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, &phase_comp); 1408 if (rc) 1409 return rc; 1410 1411 /* Convert value to ps and reverse two's complement negation applied 1412 * during 'set' 1413 */ 1414 *phase_adjust = -phase_comp * pin->phase_gran; 1415 1416 return rc; 1417 } 1418 1419 static int 1420 zl3073x_dpll_output_pin_phase_adjust_set(const struct dpll_pin *dpll_pin, 1421 void *pin_priv, 1422 const struct dpll_device *dpll, 1423 void *dpll_priv, 1424 s32 phase_adjust, 1425 struct netlink_ext_ack *extack) 1426 { 1427 struct zl3073x_dpll *zldpll = dpll_priv; 1428 struct zl3073x_dev *zldev = zldpll->dev; 1429 struct zl3073x_dpll_pin *pin = pin_priv; 1430 u8 out; 1431 int rc; 1432 1433 /* The value in the register is stored as two's complement negation 1434 * of requested value and expressed in half synth clock cycles. 1435 */ 1436 phase_adjust = -phase_adjust / pin->phase_gran; 1437 1438 guard(mutex)(&zldev->multiop_lock); 1439 1440 /* Read output configuration */ 1441 out = zl3073x_output_pin_out_get(pin->id); 1442 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 1443 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1444 if (rc) 1445 return rc; 1446 1447 /* Write the requested value into the compensation register */ 1448 rc = zl3073x_write_u32(zldev, ZL_REG_OUTPUT_PHASE_COMP, phase_adjust); 1449 if (rc) 1450 return rc; 1451 1452 /* Update output configuration from mailbox */ 1453 return zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_WR, 1454 ZL_REG_OUTPUT_MB_MASK, BIT(out)); 1455 } 1456 1457 static int 1458 zl3073x_dpll_output_pin_state_on_dpll_get(const struct dpll_pin *dpll_pin, 1459 void *pin_priv, 1460 const struct dpll_device *dpll, 1461 void *dpll_priv, 1462 enum dpll_pin_state *state, 1463 struct netlink_ext_ack *extack) 1464 { 1465 /* If the output pin is registered then it is always connected */ 1466 *state = DPLL_PIN_STATE_CONNECTED; 1467 1468 return 0; 1469 } 1470 1471 static int 1472 zl3073x_dpll_lock_status_get(const struct dpll_device *dpll, void *dpll_priv, 1473 enum dpll_lock_status *status, 1474 enum dpll_lock_status_error *status_error, 1475 struct netlink_ext_ack *extack) 1476 { 1477 struct zl3073x_dpll *zldpll = dpll_priv; 1478 struct zl3073x_dev *zldev = zldpll->dev; 1479 u8 mon_status, state; 1480 int rc; 1481 1482 switch (zldpll->refsel_mode) { 1483 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1484 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1485 /* In FREERUN and NCO modes the DPLL is always unlocked */ 1486 *status = DPLL_LOCK_STATUS_UNLOCKED; 1487 1488 return 0; 1489 default: 1490 break; 1491 } 1492 1493 /* Read DPLL monitor status */ 1494 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MON_STATUS(zldpll->id), 1495 &mon_status); 1496 if (rc) 1497 return rc; 1498 state = FIELD_GET(ZL_DPLL_MON_STATUS_STATE, mon_status); 1499 1500 switch (state) { 1501 case ZL_DPLL_MON_STATUS_STATE_LOCK: 1502 if (FIELD_GET(ZL_DPLL_MON_STATUS_HO_READY, mon_status)) 1503 *status = DPLL_LOCK_STATUS_LOCKED_HO_ACQ; 1504 else 1505 *status = DPLL_LOCK_STATUS_LOCKED; 1506 break; 1507 case ZL_DPLL_MON_STATUS_STATE_HOLDOVER: 1508 case ZL_DPLL_MON_STATUS_STATE_ACQUIRING: 1509 *status = DPLL_LOCK_STATUS_HOLDOVER; 1510 break; 1511 default: 1512 dev_warn(zldev->dev, "Unknown DPLL monitor status: 0x%02x\n", 1513 mon_status); 1514 *status = DPLL_LOCK_STATUS_UNLOCKED; 1515 break; 1516 } 1517 1518 return 0; 1519 } 1520 1521 static int 1522 zl3073x_dpll_mode_get(const struct dpll_device *dpll, void *dpll_priv, 1523 enum dpll_mode *mode, struct netlink_ext_ack *extack) 1524 { 1525 struct zl3073x_dpll *zldpll = dpll_priv; 1526 1527 switch (zldpll->refsel_mode) { 1528 case ZL_DPLL_MODE_REFSEL_MODE_FREERUN: 1529 case ZL_DPLL_MODE_REFSEL_MODE_HOLDOVER: 1530 case ZL_DPLL_MODE_REFSEL_MODE_NCO: 1531 case ZL_DPLL_MODE_REFSEL_MODE_REFLOCK: 1532 /* Use MANUAL for device FREERUN, HOLDOVER, NCO and 1533 * REFLOCK modes 1534 */ 1535 *mode = DPLL_MODE_MANUAL; 1536 break; 1537 case ZL_DPLL_MODE_REFSEL_MODE_AUTO: 1538 /* Use AUTO for device AUTO mode */ 1539 *mode = DPLL_MODE_AUTOMATIC; 1540 break; 1541 default: 1542 return -EINVAL; 1543 } 1544 1545 return 0; 1546 } 1547 1548 static int 1549 zl3073x_dpll_phase_offset_avg_factor_get(const struct dpll_device *dpll, 1550 void *dpll_priv, u32 *factor, 1551 struct netlink_ext_ack *extack) 1552 { 1553 struct zl3073x_dpll *zldpll = dpll_priv; 1554 1555 *factor = zl3073x_dev_phase_avg_factor_get(zldpll->dev); 1556 1557 return 0; 1558 } 1559 1560 static void 1561 zl3073x_dpll_change_work(struct work_struct *work) 1562 { 1563 struct zl3073x_dpll *zldpll; 1564 1565 zldpll = container_of(work, struct zl3073x_dpll, change_work); 1566 dpll_device_change_ntf(zldpll->dpll_dev); 1567 } 1568 1569 static int 1570 zl3073x_dpll_phase_offset_avg_factor_set(const struct dpll_device *dpll, 1571 void *dpll_priv, u32 factor, 1572 struct netlink_ext_ack *extack) 1573 { 1574 struct zl3073x_dpll *item, *zldpll = dpll_priv; 1575 int rc; 1576 1577 if (factor > 15) { 1578 NL_SET_ERR_MSG_FMT(extack, 1579 "Phase offset average factor has to be from range <0,15>"); 1580 return -EINVAL; 1581 } 1582 1583 rc = zl3073x_dev_phase_avg_factor_set(zldpll->dev, factor); 1584 if (rc) { 1585 NL_SET_ERR_MSG_FMT(extack, 1586 "Failed to set phase offset averaging factor"); 1587 return rc; 1588 } 1589 1590 /* The averaging factor is common for all DPLL channels so after change 1591 * we have to send a notification for other DPLL devices. 1592 */ 1593 list_for_each_entry(item, &zldpll->dev->dplls, list) { 1594 if (item != zldpll) 1595 schedule_work(&item->change_work); 1596 } 1597 1598 return 0; 1599 } 1600 1601 static int 1602 zl3073x_dpll_phase_offset_monitor_get(const struct dpll_device *dpll, 1603 void *dpll_priv, 1604 enum dpll_feature_state *state, 1605 struct netlink_ext_ack *extack) 1606 { 1607 struct zl3073x_dpll *zldpll = dpll_priv; 1608 1609 if (zldpll->phase_monitor) 1610 *state = DPLL_FEATURE_STATE_ENABLE; 1611 else 1612 *state = DPLL_FEATURE_STATE_DISABLE; 1613 1614 return 0; 1615 } 1616 1617 static int 1618 zl3073x_dpll_phase_offset_monitor_set(const struct dpll_device *dpll, 1619 void *dpll_priv, 1620 enum dpll_feature_state state, 1621 struct netlink_ext_ack *extack) 1622 { 1623 struct zl3073x_dpll *zldpll = dpll_priv; 1624 1625 zldpll->phase_monitor = (state == DPLL_FEATURE_STATE_ENABLE); 1626 1627 return 0; 1628 } 1629 1630 static const struct dpll_pin_ops zl3073x_dpll_input_pin_ops = { 1631 .direction_get = zl3073x_dpll_pin_direction_get, 1632 .esync_get = zl3073x_dpll_input_pin_esync_get, 1633 .esync_set = zl3073x_dpll_input_pin_esync_set, 1634 .ffo_get = zl3073x_dpll_input_pin_ffo_get, 1635 .frequency_get = zl3073x_dpll_input_pin_frequency_get, 1636 .frequency_set = zl3073x_dpll_input_pin_frequency_set, 1637 .phase_offset_get = zl3073x_dpll_input_pin_phase_offset_get, 1638 .phase_adjust_get = zl3073x_dpll_input_pin_phase_adjust_get, 1639 .phase_adjust_set = zl3073x_dpll_input_pin_phase_adjust_set, 1640 .prio_get = zl3073x_dpll_input_pin_prio_get, 1641 .prio_set = zl3073x_dpll_input_pin_prio_set, 1642 .state_on_dpll_get = zl3073x_dpll_input_pin_state_on_dpll_get, 1643 .state_on_dpll_set = zl3073x_dpll_input_pin_state_on_dpll_set, 1644 }; 1645 1646 static const struct dpll_pin_ops zl3073x_dpll_output_pin_ops = { 1647 .direction_get = zl3073x_dpll_pin_direction_get, 1648 .esync_get = zl3073x_dpll_output_pin_esync_get, 1649 .esync_set = zl3073x_dpll_output_pin_esync_set, 1650 .frequency_get = zl3073x_dpll_output_pin_frequency_get, 1651 .frequency_set = zl3073x_dpll_output_pin_frequency_set, 1652 .phase_adjust_get = zl3073x_dpll_output_pin_phase_adjust_get, 1653 .phase_adjust_set = zl3073x_dpll_output_pin_phase_adjust_set, 1654 .state_on_dpll_get = zl3073x_dpll_output_pin_state_on_dpll_get, 1655 }; 1656 1657 static const struct dpll_device_ops zl3073x_dpll_device_ops = { 1658 .lock_status_get = zl3073x_dpll_lock_status_get, 1659 .mode_get = zl3073x_dpll_mode_get, 1660 .phase_offset_avg_factor_get = zl3073x_dpll_phase_offset_avg_factor_get, 1661 .phase_offset_avg_factor_set = zl3073x_dpll_phase_offset_avg_factor_set, 1662 .phase_offset_monitor_get = zl3073x_dpll_phase_offset_monitor_get, 1663 .phase_offset_monitor_set = zl3073x_dpll_phase_offset_monitor_set, 1664 }; 1665 1666 /** 1667 * zl3073x_dpll_pin_alloc - allocate DPLL pin 1668 * @zldpll: pointer to zl3073x_dpll 1669 * @dir: pin direction 1670 * @id: pin id 1671 * 1672 * Allocates and initializes zl3073x_dpll_pin structure for given 1673 * pin id and direction. 1674 * 1675 * Return: pointer to allocated structure on success, error pointer on error 1676 */ 1677 static struct zl3073x_dpll_pin * 1678 zl3073x_dpll_pin_alloc(struct zl3073x_dpll *zldpll, enum dpll_pin_direction dir, 1679 u8 id) 1680 { 1681 struct zl3073x_dpll_pin *pin; 1682 1683 pin = kzalloc(sizeof(*pin), GFP_KERNEL); 1684 if (!pin) 1685 return ERR_PTR(-ENOMEM); 1686 1687 pin->dpll = zldpll; 1688 pin->dir = dir; 1689 pin->id = id; 1690 1691 return pin; 1692 } 1693 1694 /** 1695 * zl3073x_dpll_pin_free - deallocate DPLL pin 1696 * @pin: pin to free 1697 * 1698 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc. 1699 */ 1700 static void 1701 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin) 1702 { 1703 WARN(pin->dpll_pin, "DPLL pin is still registered\n"); 1704 1705 kfree(pin); 1706 } 1707 1708 /** 1709 * zl3073x_dpll_pin_register - register DPLL pin 1710 * @pin: pointer to DPLL pin 1711 * @index: absolute pin index for registration 1712 * 1713 * Registers given DPLL pin into DPLL sub-system. 1714 * 1715 * Return: 0 on success, <0 on error 1716 */ 1717 static int 1718 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index) 1719 { 1720 struct zl3073x_dpll *zldpll = pin->dpll; 1721 struct zl3073x_pin_props *props; 1722 const struct dpll_pin_ops *ops; 1723 int rc; 1724 1725 /* Get pin properties */ 1726 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id); 1727 if (IS_ERR(props)) 1728 return PTR_ERR(props); 1729 1730 /* Save package label, esync capability and phase adjust granularity */ 1731 strscpy(pin->label, props->package_label); 1732 pin->esync_control = props->esync_control; 1733 pin->phase_gran = props->dpll_props.phase_gran; 1734 1735 if (zl3073x_dpll_is_input_pin(pin)) { 1736 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio); 1737 if (rc) 1738 goto err_prio_get; 1739 1740 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) { 1741 /* Clamp prio to max value & mark pin non-selectable */ 1742 pin->prio = ZL_DPLL_REF_PRIO_MAX; 1743 pin->selectable = false; 1744 } else { 1745 /* Mark pin as selectable */ 1746 pin->selectable = true; 1747 } 1748 } 1749 1750 /* Create or get existing DPLL pin */ 1751 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE, 1752 &props->dpll_props); 1753 if (IS_ERR(pin->dpll_pin)) { 1754 rc = PTR_ERR(pin->dpll_pin); 1755 goto err_pin_get; 1756 } 1757 1758 if (zl3073x_dpll_is_input_pin(pin)) 1759 ops = &zl3073x_dpll_input_pin_ops; 1760 else 1761 ops = &zl3073x_dpll_output_pin_ops; 1762 1763 /* Register the pin */ 1764 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1765 if (rc) 1766 goto err_register; 1767 1768 /* Free pin properties */ 1769 zl3073x_pin_props_put(props); 1770 1771 return 0; 1772 1773 err_register: 1774 dpll_pin_put(pin->dpll_pin); 1775 err_prio_get: 1776 pin->dpll_pin = NULL; 1777 err_pin_get: 1778 zl3073x_pin_props_put(props); 1779 1780 return rc; 1781 } 1782 1783 /** 1784 * zl3073x_dpll_pin_unregister - unregister DPLL pin 1785 * @pin: pointer to DPLL pin 1786 * 1787 * Unregisters pin previously registered by @zl3073x_dpll_pin_register. 1788 */ 1789 static void 1790 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin) 1791 { 1792 struct zl3073x_dpll *zldpll = pin->dpll; 1793 const struct dpll_pin_ops *ops; 1794 1795 WARN(!pin->dpll_pin, "DPLL pin is not registered\n"); 1796 1797 if (zl3073x_dpll_is_input_pin(pin)) 1798 ops = &zl3073x_dpll_input_pin_ops; 1799 else 1800 ops = &zl3073x_dpll_output_pin_ops; 1801 1802 /* Unregister the pin */ 1803 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin); 1804 1805 dpll_pin_put(pin->dpll_pin); 1806 pin->dpll_pin = NULL; 1807 } 1808 1809 /** 1810 * zl3073x_dpll_pins_unregister - unregister all registered DPLL pins 1811 * @zldpll: pointer to zl3073x_dpll structure 1812 * 1813 * Enumerates all DPLL pins registered to given DPLL device and 1814 * unregisters them. 1815 */ 1816 static void 1817 zl3073x_dpll_pins_unregister(struct zl3073x_dpll *zldpll) 1818 { 1819 struct zl3073x_dpll_pin *pin, *next; 1820 1821 list_for_each_entry_safe(pin, next, &zldpll->pins, list) { 1822 zl3073x_dpll_pin_unregister(pin); 1823 list_del(&pin->list); 1824 zl3073x_dpll_pin_free(pin); 1825 } 1826 } 1827 1828 /** 1829 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable 1830 * @zldpll: pointer to zl3073x_dpll structure 1831 * @dir: pin direction 1832 * @index: pin index 1833 * 1834 * Checks if the given pin can be registered to given DPLL. For both 1835 * directions the pin can be registered if it is enabled. In case of 1836 * differential signal type only P-pin is reported as registrable. 1837 * And additionally for the output pin, the pin can be registered only 1838 * if it is connected to synthesizer that is driven by given DPLL. 1839 * 1840 * Return: true if the pin is registrable, false if not 1841 */ 1842 static bool 1843 zl3073x_dpll_pin_is_registrable(struct zl3073x_dpll *zldpll, 1844 enum dpll_pin_direction dir, u8 index) 1845 { 1846 struct zl3073x_dev *zldev = zldpll->dev; 1847 bool is_diff, is_enabled; 1848 const char *name; 1849 1850 if (dir == DPLL_PIN_DIRECTION_INPUT) { 1851 u8 ref = zl3073x_input_pin_ref_get(index); 1852 1853 name = "REF"; 1854 1855 /* Skip the pin if the DPLL is running in NCO mode */ 1856 if (zldpll->refsel_mode == ZL_DPLL_MODE_REFSEL_MODE_NCO) 1857 return false; 1858 1859 is_diff = zl3073x_ref_is_diff(zldev, ref); 1860 is_enabled = zl3073x_ref_is_enabled(zldev, ref); 1861 } else { 1862 /* Output P&N pair shares single HW output */ 1863 u8 out = zl3073x_output_pin_out_get(index); 1864 1865 name = "OUT"; 1866 1867 /* Skip the pin if it is connected to different DPLL channel */ 1868 if (zl3073x_out_dpll_get(zldev, out) != zldpll->id) { 1869 dev_dbg(zldev->dev, 1870 "%s%u is driven by different DPLL\n", name, 1871 out); 1872 1873 return false; 1874 } 1875 1876 is_diff = zl3073x_out_is_diff(zldev, out); 1877 is_enabled = zl3073x_output_pin_is_enabled(zldev, index); 1878 } 1879 1880 /* Skip N-pin if the corresponding input/output is differential */ 1881 if (is_diff && zl3073x_is_n_pin(index)) { 1882 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n", 1883 name, index / 2); 1884 1885 return false; 1886 } 1887 1888 /* Skip the pin if it is disabled */ 1889 if (!is_enabled) { 1890 dev_dbg(zldev->dev, "%s%u%c is disabled\n", name, index / 2, 1891 zl3073x_is_p_pin(index) ? 'P' : 'N'); 1892 1893 return false; 1894 } 1895 1896 return true; 1897 } 1898 1899 /** 1900 * zl3073x_dpll_pins_register - register all registerable DPLL pins 1901 * @zldpll: pointer to zl3073x_dpll structure 1902 * 1903 * Enumerates all possible input/output pins and registers all of them 1904 * that are registrable. 1905 * 1906 * Return: 0 on success, <0 on error 1907 */ 1908 static int 1909 zl3073x_dpll_pins_register(struct zl3073x_dpll *zldpll) 1910 { 1911 struct zl3073x_dpll_pin *pin; 1912 enum dpll_pin_direction dir; 1913 u8 id, index; 1914 int rc; 1915 1916 /* Process input pins */ 1917 for (index = 0; index < ZL3073X_NUM_PINS; index++) { 1918 /* First input pins and then output pins */ 1919 if (index < ZL3073X_NUM_INPUT_PINS) { 1920 id = index; 1921 dir = DPLL_PIN_DIRECTION_INPUT; 1922 } else { 1923 id = index - ZL3073X_NUM_INPUT_PINS; 1924 dir = DPLL_PIN_DIRECTION_OUTPUT; 1925 } 1926 1927 /* Check if the pin registrable to this DPLL */ 1928 if (!zl3073x_dpll_pin_is_registrable(zldpll, dir, id)) 1929 continue; 1930 1931 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id); 1932 if (IS_ERR(pin)) { 1933 rc = PTR_ERR(pin); 1934 goto error; 1935 } 1936 1937 rc = zl3073x_dpll_pin_register(pin, index); 1938 if (rc) 1939 goto error; 1940 1941 list_add(&pin->list, &zldpll->pins); 1942 } 1943 1944 return 0; 1945 1946 error: 1947 zl3073x_dpll_pins_unregister(zldpll); 1948 1949 return rc; 1950 } 1951 1952 /** 1953 * zl3073x_dpll_device_register - register DPLL device 1954 * @zldpll: pointer to zl3073x_dpll structure 1955 * 1956 * Registers given DPLL device into DPLL sub-system. 1957 * 1958 * Return: 0 on success, <0 on error 1959 */ 1960 static int 1961 zl3073x_dpll_device_register(struct zl3073x_dpll *zldpll) 1962 { 1963 struct zl3073x_dev *zldev = zldpll->dev; 1964 u8 dpll_mode_refsel; 1965 int rc; 1966 1967 /* Read DPLL mode and forcibly selected reference */ 1968 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MODE_REFSEL(zldpll->id), 1969 &dpll_mode_refsel); 1970 if (rc) 1971 return rc; 1972 1973 /* Extract mode and selected input reference */ 1974 zldpll->refsel_mode = FIELD_GET(ZL_DPLL_MODE_REFSEL_MODE, 1975 dpll_mode_refsel); 1976 zldpll->forced_ref = FIELD_GET(ZL_DPLL_MODE_REFSEL_REF, 1977 dpll_mode_refsel); 1978 1979 zldpll->dpll_dev = dpll_device_get(zldev->clock_id, zldpll->id, 1980 THIS_MODULE); 1981 if (IS_ERR(zldpll->dpll_dev)) { 1982 rc = PTR_ERR(zldpll->dpll_dev); 1983 zldpll->dpll_dev = NULL; 1984 1985 return rc; 1986 } 1987 1988 rc = dpll_device_register(zldpll->dpll_dev, 1989 zl3073x_prop_dpll_type_get(zldev, zldpll->id), 1990 &zl3073x_dpll_device_ops, zldpll); 1991 if (rc) { 1992 dpll_device_put(zldpll->dpll_dev); 1993 zldpll->dpll_dev = NULL; 1994 } 1995 1996 return rc; 1997 } 1998 1999 /** 2000 * zl3073x_dpll_device_unregister - unregister DPLL device 2001 * @zldpll: pointer to zl3073x_dpll structure 2002 * 2003 * Unregisters given DPLL device from DPLL sub-system previously registered 2004 * by @zl3073x_dpll_device_register. 2005 */ 2006 static void 2007 zl3073x_dpll_device_unregister(struct zl3073x_dpll *zldpll) 2008 { 2009 WARN(!zldpll->dpll_dev, "DPLL device is not registered\n"); 2010 2011 cancel_work_sync(&zldpll->change_work); 2012 2013 dpll_device_unregister(zldpll->dpll_dev, &zl3073x_dpll_device_ops, 2014 zldpll); 2015 dpll_device_put(zldpll->dpll_dev); 2016 zldpll->dpll_dev = NULL; 2017 } 2018 2019 /** 2020 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change 2021 * @pin: pin to check 2022 * 2023 * Check for the change of DPLL to connected pin phase offset change. 2024 * 2025 * Return: true on phase offset change, false otherwise 2026 */ 2027 static bool 2028 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin) 2029 { 2030 struct zl3073x_dpll *zldpll = pin->dpll; 2031 struct zl3073x_dev *zldev = zldpll->dev; 2032 unsigned int reg; 2033 s64 phase_offset; 2034 u8 ref; 2035 int rc; 2036 2037 ref = zl3073x_input_pin_ref_get(pin->id); 2038 2039 /* Select register to read phase offset value depending on pin and 2040 * phase monitor state: 2041 * 1) For connected pin use dpll_phase_err_data register 2042 * 2) For other pins use appropriate ref_phase register if the phase 2043 * monitor feature is enabled and reference monitor does not 2044 * report signal errors for given input pin 2045 */ 2046 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) { 2047 reg = ZL_REG_DPLL_PHASE_ERR_DATA(zldpll->id); 2048 } else if (zldpll->phase_monitor) { 2049 u8 status; 2050 2051 /* Get reference monitor status */ 2052 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), 2053 &status); 2054 if (rc) { 2055 dev_err(zldev->dev, 2056 "Failed to read %s refmon status: %pe\n", 2057 pin->label, ERR_PTR(rc)); 2058 2059 return false; 2060 } 2061 2062 if (status != ZL_REF_MON_STATUS_OK) 2063 return false; 2064 2065 reg = ZL_REG_REF_PHASE(ref); 2066 } else { 2067 /* The pin is not connected or phase monitor disabled */ 2068 return false; 2069 } 2070 2071 /* Read measured phase offset value */ 2072 rc = zl3073x_read_u48(zldev, reg, &phase_offset); 2073 if (rc) { 2074 dev_err(zldev->dev, "Failed to read ref phase offset: %pe\n", 2075 ERR_PTR(rc)); 2076 2077 return false; 2078 } 2079 2080 /* Convert to ps */ 2081 phase_offset = div_s64(sign_extend64(phase_offset, 47), 100); 2082 2083 /* Compare with previous value */ 2084 if (phase_offset != pin->phase_offset) { 2085 dev_dbg(zldev->dev, "%s phase offset changed: %lld -> %lld\n", 2086 pin->label, pin->phase_offset, phase_offset); 2087 pin->phase_offset = phase_offset; 2088 2089 return true; 2090 } 2091 2092 return false; 2093 } 2094 2095 /** 2096 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change 2097 * @pin: pin to check 2098 * 2099 * Check for the given pin's fractional frequency change. 2100 * 2101 * Return: true on fractional frequency offset change, false otherwise 2102 */ 2103 static bool 2104 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin) 2105 { 2106 struct zl3073x_dpll *zldpll = pin->dpll; 2107 struct zl3073x_dev *zldev = zldpll->dev; 2108 u8 ref, status; 2109 s64 ffo; 2110 int rc; 2111 2112 /* Get reference monitor status */ 2113 ref = zl3073x_input_pin_ref_get(pin->id); 2114 rc = zl3073x_read_u8(zldev, ZL_REG_REF_MON_STATUS(ref), &status); 2115 if (rc) { 2116 dev_err(zldev->dev, "Failed to read %s refmon status: %pe\n", 2117 pin->label, ERR_PTR(rc)); 2118 2119 return false; 2120 } 2121 2122 /* Do not report ffo changes if the reference monitor report errors */ 2123 if (status != ZL_REF_MON_STATUS_OK) 2124 return false; 2125 2126 /* Get the latest measured ref's ffo */ 2127 ffo = zl3073x_ref_ffo_get(zldev, ref); 2128 2129 /* Compare with previous value */ 2130 if (pin->freq_offset != ffo) { 2131 dev_dbg(zldev->dev, "%s freq offset changed: %lld -> %lld\n", 2132 pin->label, pin->freq_offset, ffo); 2133 pin->freq_offset = ffo; 2134 2135 return true; 2136 } 2137 2138 return false; 2139 } 2140 2141 /** 2142 * zl3073x_dpll_changes_check - check for changes and send notifications 2143 * @zldpll: pointer to zl3073x_dpll structure 2144 * 2145 * Checks for changes on given DPLL device and its registered DPLL pins 2146 * and sends notifications about them. 2147 * 2148 * This function is periodically called from @zl3073x_dev_periodic_work. 2149 */ 2150 void 2151 zl3073x_dpll_changes_check(struct zl3073x_dpll *zldpll) 2152 { 2153 struct zl3073x_dev *zldev = zldpll->dev; 2154 enum dpll_lock_status lock_status; 2155 struct device *dev = zldev->dev; 2156 struct zl3073x_dpll_pin *pin; 2157 int rc; 2158 2159 zldpll->check_count++; 2160 2161 /* Get current lock status for the DPLL */ 2162 rc = zl3073x_dpll_lock_status_get(zldpll->dpll_dev, zldpll, 2163 &lock_status, NULL, NULL); 2164 if (rc) { 2165 dev_err(dev, "Failed to get DPLL%u lock status: %pe\n", 2166 zldpll->id, ERR_PTR(rc)); 2167 return; 2168 } 2169 2170 /* If lock status was changed then notify DPLL core */ 2171 if (zldpll->lock_status != lock_status) { 2172 zldpll->lock_status = lock_status; 2173 dpll_device_change_ntf(zldpll->dpll_dev); 2174 } 2175 2176 /* Input pin monitoring does make sense only in automatic 2177 * or forced reference modes. 2178 */ 2179 if (zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_AUTO && 2180 zldpll->refsel_mode != ZL_DPLL_MODE_REFSEL_MODE_REFLOCK) 2181 return; 2182 2183 /* Update phase offset latch registers for this DPLL if the phase 2184 * offset monitor feature is enabled. 2185 */ 2186 if (zldpll->phase_monitor) { 2187 rc = zl3073x_ref_phase_offsets_update(zldev, zldpll->id); 2188 if (rc) { 2189 dev_err(zldev->dev, 2190 "Failed to update phase offsets: %pe\n", 2191 ERR_PTR(rc)); 2192 return; 2193 } 2194 } 2195 2196 list_for_each_entry(pin, &zldpll->pins, list) { 2197 enum dpll_pin_state state; 2198 bool pin_changed = false; 2199 2200 /* Output pins change checks are not necessary because output 2201 * states are constant. 2202 */ 2203 if (!zl3073x_dpll_is_input_pin(pin)) 2204 continue; 2205 2206 rc = zl3073x_dpll_ref_state_get(pin, &state); 2207 if (rc) { 2208 dev_err(dev, 2209 "Failed to get %s on DPLL%u state: %pe\n", 2210 pin->label, zldpll->id, ERR_PTR(rc)); 2211 return; 2212 } 2213 2214 if (state != pin->pin_state) { 2215 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label, 2216 pin->pin_state, state); 2217 pin->pin_state = state; 2218 pin_changed = true; 2219 } 2220 2221 /* Check for phase offset and ffo change once per second */ 2222 if (zldpll->check_count % 2 == 0) { 2223 if (zl3073x_dpll_pin_phase_offset_check(pin)) 2224 pin_changed = true; 2225 2226 if (zl3073x_dpll_pin_ffo_check(pin)) 2227 pin_changed = true; 2228 } 2229 2230 if (pin_changed) 2231 dpll_pin_change_ntf(pin->dpll_pin); 2232 } 2233 } 2234 2235 /** 2236 * zl3073x_dpll_init_fine_phase_adjust - do initial fine phase adjustments 2237 * @zldev: pointer to zl3073x device 2238 * 2239 * Performs initial fine phase adjustments needed per datasheet. 2240 * 2241 * Return: 0 on success, <0 on error 2242 */ 2243 int 2244 zl3073x_dpll_init_fine_phase_adjust(struct zl3073x_dev *zldev) 2245 { 2246 int rc; 2247 2248 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_MASK, 0x1f); 2249 if (rc) 2250 return rc; 2251 2252 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_INTVL, 0x01); 2253 if (rc) 2254 return rc; 2255 2256 rc = zl3073x_write_u16(zldev, ZL_REG_SYNTH_PHASE_SHIFT_DATA, 0xffff); 2257 if (rc) 2258 return rc; 2259 2260 rc = zl3073x_write_u8(zldev, ZL_REG_SYNTH_PHASE_SHIFT_CTRL, 0x01); 2261 if (rc) 2262 return rc; 2263 2264 return rc; 2265 } 2266 2267 /** 2268 * zl3073x_dpll_alloc - allocate DPLL device 2269 * @zldev: pointer to zl3073x device 2270 * @ch: DPLL channel number 2271 * 2272 * Allocates DPLL device structure for given DPLL channel. 2273 * 2274 * Return: pointer to DPLL device on success, error pointer on error 2275 */ 2276 struct zl3073x_dpll * 2277 zl3073x_dpll_alloc(struct zl3073x_dev *zldev, u8 ch) 2278 { 2279 struct zl3073x_dpll *zldpll; 2280 2281 zldpll = kzalloc(sizeof(*zldpll), GFP_KERNEL); 2282 if (!zldpll) 2283 return ERR_PTR(-ENOMEM); 2284 2285 zldpll->dev = zldev; 2286 zldpll->id = ch; 2287 INIT_LIST_HEAD(&zldpll->pins); 2288 INIT_WORK(&zldpll->change_work, zl3073x_dpll_change_work); 2289 2290 return zldpll; 2291 } 2292 2293 /** 2294 * zl3073x_dpll_free - free DPLL device 2295 * @zldpll: pointer to zl3073x_dpll structure 2296 * 2297 * Deallocates given DPLL device previously allocated by @zl3073x_dpll_alloc. 2298 */ 2299 void 2300 zl3073x_dpll_free(struct zl3073x_dpll *zldpll) 2301 { 2302 WARN(zldpll->dpll_dev, "DPLL device is still registered\n"); 2303 2304 kfree(zldpll); 2305 } 2306 2307 /** 2308 * zl3073x_dpll_register - register DPLL device and all its pins 2309 * @zldpll: pointer to zl3073x_dpll structure 2310 * 2311 * Registers given DPLL device and all its pins into DPLL sub-system. 2312 * 2313 * Return: 0 on success, <0 on error 2314 */ 2315 int 2316 zl3073x_dpll_register(struct zl3073x_dpll *zldpll) 2317 { 2318 int rc; 2319 2320 rc = zl3073x_dpll_device_register(zldpll); 2321 if (rc) 2322 return rc; 2323 2324 rc = zl3073x_dpll_pins_register(zldpll); 2325 if (rc) { 2326 zl3073x_dpll_device_unregister(zldpll); 2327 return rc; 2328 } 2329 2330 return 0; 2331 } 2332 2333 /** 2334 * zl3073x_dpll_unregister - unregister DPLL device and its pins 2335 * @zldpll: pointer to zl3073x_dpll structure 2336 * 2337 * Unregisters given DPLL device and all its pins from DPLL sub-system 2338 * previously registered by @zl3073x_dpll_register. 2339 */ 2340 void 2341 zl3073x_dpll_unregister(struct zl3073x_dpll *zldpll) 2342 { 2343 /* Unregister all pins and dpll */ 2344 zl3073x_dpll_pins_unregister(zldpll); 2345 zl3073x_dpll_device_unregister(zldpll); 2346 } 2347