1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/array_size.h> 4 #include <linux/bitfield.h> 5 #include <linux/bits.h> 6 #include <linux/dev_printk.h> 7 #include <linux/device.h> 8 #include <linux/export.h> 9 #include <linux/math64.h> 10 #include <linux/module.h> 11 #include <linux/netlink.h> 12 #include <linux/regmap.h> 13 #include <linux/sprintf.h> 14 #include <linux/string_choices.h> 15 #include <linux/unaligned.h> 16 #include <net/devlink.h> 17 18 #include "core.h" 19 #include "devlink.h" 20 #include "dpll.h" 21 #include "regs.h" 22 23 /* Chip IDs for zl30731 */ 24 static const u16 zl30731_ids[] = { 25 0x0E93, 26 0x1E93, 27 0x2E93, 28 }; 29 30 const struct zl3073x_chip_info zl30731_chip_info = { 31 .ids = zl30731_ids, 32 .num_ids = ARRAY_SIZE(zl30731_ids), 33 .num_channels = 1, 34 }; 35 EXPORT_SYMBOL_NS_GPL(zl30731_chip_info, "ZL3073X"); 36 37 /* Chip IDs for zl30732 */ 38 static const u16 zl30732_ids[] = { 39 0x0E30, 40 0x0E94, 41 0x1E94, 42 0x1F60, 43 0x2E94, 44 0x3FC4, 45 }; 46 47 const struct zl3073x_chip_info zl30732_chip_info = { 48 .ids = zl30732_ids, 49 .num_ids = ARRAY_SIZE(zl30732_ids), 50 .num_channels = 2, 51 }; 52 EXPORT_SYMBOL_NS_GPL(zl30732_chip_info, "ZL3073X"); 53 54 /* Chip IDs for zl30733 */ 55 static const u16 zl30733_ids[] = { 56 0x0E95, 57 0x1E95, 58 0x2E95, 59 }; 60 61 const struct zl3073x_chip_info zl30733_chip_info = { 62 .ids = zl30733_ids, 63 .num_ids = ARRAY_SIZE(zl30733_ids), 64 .num_channels = 3, 65 }; 66 EXPORT_SYMBOL_NS_GPL(zl30733_chip_info, "ZL3073X"); 67 68 /* Chip IDs for zl30734 */ 69 static const u16 zl30734_ids[] = { 70 0x0E96, 71 0x1E96, 72 0x2E96, 73 }; 74 75 const struct zl3073x_chip_info zl30734_chip_info = { 76 .ids = zl30734_ids, 77 .num_ids = ARRAY_SIZE(zl30734_ids), 78 .num_channels = 4, 79 }; 80 EXPORT_SYMBOL_NS_GPL(zl30734_chip_info, "ZL3073X"); 81 82 /* Chip IDs for zl30735 */ 83 static const u16 zl30735_ids[] = { 84 0x0E97, 85 0x1E97, 86 0x2E97, 87 }; 88 89 const struct zl3073x_chip_info zl30735_chip_info = { 90 .ids = zl30735_ids, 91 .num_ids = ARRAY_SIZE(zl30735_ids), 92 .num_channels = 5, 93 }; 94 EXPORT_SYMBOL_NS_GPL(zl30735_chip_info, "ZL3073X"); 95 96 #define ZL_RANGE_OFFSET 0x80 97 #define ZL_PAGE_SIZE 0x80 98 #define ZL_NUM_PAGES 15 99 #define ZL_PAGE_SEL 0x7F 100 #define ZL_PAGE_SEL_MASK GENMASK(3, 0) 101 #define ZL_NUM_REGS (ZL_NUM_PAGES * ZL_PAGE_SIZE) 102 103 /* Regmap range configuration */ 104 static const struct regmap_range_cfg zl3073x_regmap_range = { 105 .range_min = ZL_RANGE_OFFSET, 106 .range_max = ZL_RANGE_OFFSET + ZL_NUM_REGS - 1, 107 .selector_reg = ZL_PAGE_SEL, 108 .selector_mask = ZL_PAGE_SEL_MASK, 109 .selector_shift = 0, 110 .window_start = 0, 111 .window_len = ZL_PAGE_SIZE, 112 }; 113 114 static bool 115 zl3073x_is_volatile_reg(struct device *dev __maybe_unused, unsigned int reg) 116 { 117 /* Only page selector is non-volatile */ 118 return reg != ZL_PAGE_SEL; 119 } 120 121 const struct regmap_config zl3073x_regmap_config = { 122 .reg_bits = 8, 123 .val_bits = 8, 124 .max_register = ZL_RANGE_OFFSET + ZL_NUM_REGS - 1, 125 .ranges = &zl3073x_regmap_range, 126 .num_ranges = 1, 127 .cache_type = REGCACHE_MAPLE, 128 .volatile_reg = zl3073x_is_volatile_reg, 129 }; 130 EXPORT_SYMBOL_NS_GPL(zl3073x_regmap_config, "ZL3073X"); 131 132 /** 133 * zl3073x_ref_freq_factorize - factorize given frequency 134 * @freq: input frequency 135 * @base: base frequency 136 * @mult: multiplier 137 * 138 * Checks if the given frequency can be factorized using one of the 139 * supported base frequencies. If so the base frequency and multiplier 140 * are stored into appropriate parameters if they are not NULL. 141 * 142 * Return: 0 on success, -EINVAL if the frequency cannot be factorized 143 */ 144 int 145 zl3073x_ref_freq_factorize(u32 freq, u16 *base, u16 *mult) 146 { 147 static const u16 base_freqs[] = { 148 1, 2, 4, 5, 8, 10, 16, 20, 25, 32, 40, 50, 64, 80, 100, 125, 149 128, 160, 200, 250, 256, 320, 400, 500, 625, 640, 800, 1000, 150 1250, 1280, 1600, 2000, 2500, 3125, 3200, 4000, 5000, 6250, 151 6400, 8000, 10000, 12500, 15625, 16000, 20000, 25000, 31250, 152 32000, 40000, 50000, 62500, 153 }; 154 u32 div; 155 int i; 156 157 for (i = 0; i < ARRAY_SIZE(base_freqs); i++) { 158 div = freq / base_freqs[i]; 159 160 if (div <= U16_MAX && (freq % base_freqs[i]) == 0) { 161 if (base) 162 *base = base_freqs[i]; 163 if (mult) 164 *mult = div; 165 166 return 0; 167 } 168 } 169 170 return -EINVAL; 171 } 172 173 static bool 174 zl3073x_check_reg(struct zl3073x_dev *zldev, unsigned int reg, size_t size) 175 { 176 /* Check that multiop lock is held when accessing registers 177 * from page 10 and above. 178 */ 179 if (ZL_REG_PAGE(reg) >= 10) 180 lockdep_assert_held(&zldev->multiop_lock); 181 182 /* Check the index is in valid range for indexed register */ 183 if (ZL_REG_OFFSET(reg) > ZL_REG_MAX_OFFSET(reg)) { 184 dev_err(zldev->dev, "Index out of range for reg 0x%04lx\n", 185 ZL_REG_ADDR(reg)); 186 return false; 187 } 188 /* Check the requested size corresponds to register size */ 189 if (ZL_REG_SIZE(reg) != size) { 190 dev_err(zldev->dev, "Invalid size %zu for reg 0x%04lx\n", 191 size, ZL_REG_ADDR(reg)); 192 return false; 193 } 194 195 return true; 196 } 197 198 static int 199 zl3073x_read_reg(struct zl3073x_dev *zldev, unsigned int reg, void *val, 200 size_t size) 201 { 202 int rc; 203 204 if (!zl3073x_check_reg(zldev, reg, size)) 205 return -EINVAL; 206 207 /* Map the register address to virtual range */ 208 reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; 209 210 rc = regmap_bulk_read(zldev->regmap, reg, val, size); 211 if (rc) { 212 dev_err(zldev->dev, "Failed to read reg 0x%04x: %pe\n", reg, 213 ERR_PTR(rc)); 214 return rc; 215 } 216 217 return 0; 218 } 219 220 static int 221 zl3073x_write_reg(struct zl3073x_dev *zldev, unsigned int reg, const void *val, 222 size_t size) 223 { 224 int rc; 225 226 if (!zl3073x_check_reg(zldev, reg, size)) 227 return -EINVAL; 228 229 /* Map the register address to virtual range */ 230 reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; 231 232 rc = regmap_bulk_write(zldev->regmap, reg, val, size); 233 if (rc) { 234 dev_err(zldev->dev, "Failed to write reg 0x%04x: %pe\n", reg, 235 ERR_PTR(rc)); 236 return rc; 237 } 238 239 return 0; 240 } 241 242 /** 243 * zl3073x_read_u8 - read value from 8bit register 244 * @zldev: zl3073x device pointer 245 * @reg: register to write to 246 * @val: value to write 247 * 248 * Reads value from given 8bit register. 249 * 250 * Returns: 0 on success, <0 on error 251 */ 252 int zl3073x_read_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 *val) 253 { 254 return zl3073x_read_reg(zldev, reg, val, sizeof(*val)); 255 } 256 257 /** 258 * zl3073x_write_u8 - write value to 16bit register 259 * @zldev: zl3073x device pointer 260 * @reg: register to write to 261 * @val: value to write 262 * 263 * Writes value into given 8bit register. 264 * 265 * Returns: 0 on success, <0 on error 266 */ 267 int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val) 268 { 269 return zl3073x_write_reg(zldev, reg, &val, sizeof(val)); 270 } 271 272 /** 273 * zl3073x_read_u16 - read value from 16bit register 274 * @zldev: zl3073x device pointer 275 * @reg: register to write to 276 * @val: value to write 277 * 278 * Reads value from given 16bit register. 279 * 280 * Returns: 0 on success, <0 on error 281 */ 282 int zl3073x_read_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 *val) 283 { 284 int rc; 285 286 rc = zl3073x_read_reg(zldev, reg, val, sizeof(*val)); 287 if (!rc) 288 be16_to_cpus(val); 289 290 return rc; 291 } 292 293 /** 294 * zl3073x_write_u16 - write value to 16bit register 295 * @zldev: zl3073x device pointer 296 * @reg: register to write to 297 * @val: value to write 298 * 299 * Writes value into given 16bit register. 300 * 301 * Returns: 0 on success, <0 on error 302 */ 303 int zl3073x_write_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 val) 304 { 305 cpu_to_be16s(&val); 306 307 return zl3073x_write_reg(zldev, reg, &val, sizeof(val)); 308 } 309 310 /** 311 * zl3073x_read_u32 - read value from 32bit register 312 * @zldev: zl3073x device pointer 313 * @reg: register to write to 314 * @val: value to write 315 * 316 * Reads value from given 32bit register. 317 * 318 * Returns: 0 on success, <0 on error 319 */ 320 int zl3073x_read_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 *val) 321 { 322 int rc; 323 324 rc = zl3073x_read_reg(zldev, reg, val, sizeof(*val)); 325 if (!rc) 326 be32_to_cpus(val); 327 328 return rc; 329 } 330 331 /** 332 * zl3073x_write_u32 - write value to 32bit register 333 * @zldev: zl3073x device pointer 334 * @reg: register to write to 335 * @val: value to write 336 * 337 * Writes value into given 32bit register. 338 * 339 * Returns: 0 on success, <0 on error 340 */ 341 int zl3073x_write_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 val) 342 { 343 cpu_to_be32s(&val); 344 345 return zl3073x_write_reg(zldev, reg, &val, sizeof(val)); 346 } 347 348 /** 349 * zl3073x_read_u48 - read value from 48bit register 350 * @zldev: zl3073x device pointer 351 * @reg: register to write to 352 * @val: value to write 353 * 354 * Reads value from given 48bit register. 355 * 356 * Returns: 0 on success, <0 on error 357 */ 358 int zl3073x_read_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 *val) 359 { 360 u8 buf[6]; 361 int rc; 362 363 rc = zl3073x_read_reg(zldev, reg, buf, sizeof(buf)); 364 if (!rc) 365 *val = get_unaligned_be48(buf); 366 367 return rc; 368 } 369 370 /** 371 * zl3073x_write_u48 - write value to 48bit register 372 * @zldev: zl3073x device pointer 373 * @reg: register to write to 374 * @val: value to write 375 * 376 * Writes value into given 48bit register. 377 * The value must be from the interval -S48_MIN to U48_MAX. 378 * 379 * Returns: 0 on success, <0 on error 380 */ 381 int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val) 382 { 383 u8 buf[6]; 384 385 /* Check the value belongs to <S48_MIN, U48_MAX> 386 * Any value >= S48_MIN has bits 47..63 set. 387 */ 388 if (val > GENMASK_ULL(47, 0) && val < GENMASK_ULL(63, 47)) { 389 dev_err(zldev->dev, "Value 0x%0llx out of range\n", val); 390 return -EINVAL; 391 } 392 393 put_unaligned_be48(val, buf); 394 395 return zl3073x_write_reg(zldev, reg, buf, sizeof(buf)); 396 } 397 398 /** 399 * zl3073x_poll_zero_u8 - wait for register to be cleared by device 400 * @zldev: zl3073x device pointer 401 * @reg: register to poll (has to be 8bit register) 402 * @mask: bit mask for polling 403 * 404 * Waits for bits specified by @mask in register @reg value to be cleared 405 * by the device. 406 * 407 * Returns: 0 on success, <0 on error 408 */ 409 int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 mask) 410 { 411 /* Register polling sleep & timeout */ 412 #define ZL_POLL_SLEEP_US 10 413 #define ZL_POLL_TIMEOUT_US 2000000 414 unsigned int val; 415 416 /* Check the register is 8bit */ 417 if (ZL_REG_SIZE(reg) != 1) { 418 dev_err(zldev->dev, "Invalid reg 0x%04lx size for polling\n", 419 ZL_REG_ADDR(reg)); 420 return -EINVAL; 421 } 422 423 /* Map the register address to virtual range */ 424 reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; 425 426 return regmap_read_poll_timeout(zldev->regmap, reg, val, !(val & mask), 427 ZL_POLL_SLEEP_US, ZL_POLL_TIMEOUT_US); 428 } 429 430 int zl3073x_mb_op(struct zl3073x_dev *zldev, unsigned int op_reg, u8 op_val, 431 unsigned int mask_reg, u16 mask_val) 432 { 433 int rc; 434 435 /* Set mask for the operation */ 436 rc = zl3073x_write_u16(zldev, mask_reg, mask_val); 437 if (rc) 438 return rc; 439 440 /* Trigger the operation */ 441 rc = zl3073x_write_u8(zldev, op_reg, op_val); 442 if (rc) 443 return rc; 444 445 /* Wait for the operation to actually finish */ 446 return zl3073x_poll_zero_u8(zldev, op_reg, op_val); 447 } 448 449 /** 450 * zl3073x_ref_state_fetch - get input reference state 451 * @zldev: pointer to zl3073x_dev structure 452 * @index: input reference index to fetch state for 453 * 454 * Function fetches information for the given input reference that are 455 * invariant and stores them for later use. 456 * 457 * Return: 0 on success, <0 on error 458 */ 459 static int 460 zl3073x_ref_state_fetch(struct zl3073x_dev *zldev, u8 index) 461 { 462 struct zl3073x_ref *input = &zldev->ref[index]; 463 u8 ref_config; 464 int rc; 465 466 /* If the input is differential then the configuration for N-pin 467 * reference is ignored and P-pin config is used for both. 468 */ 469 if (zl3073x_is_n_pin(index) && 470 zl3073x_ref_is_diff(zldev, index - 1)) { 471 input->enabled = zl3073x_ref_is_enabled(zldev, index - 1); 472 input->diff = true; 473 474 return 0; 475 } 476 477 guard(mutex)(&zldev->multiop_lock); 478 479 /* Read reference configuration */ 480 rc = zl3073x_mb_op(zldev, ZL_REG_REF_MB_SEM, ZL_REF_MB_SEM_RD, 481 ZL_REG_REF_MB_MASK, BIT(index)); 482 if (rc) 483 return rc; 484 485 /* Read ref_config register */ 486 rc = zl3073x_read_u8(zldev, ZL_REG_REF_CONFIG, &ref_config); 487 if (rc) 488 return rc; 489 490 input->enabled = FIELD_GET(ZL_REF_CONFIG_ENABLE, ref_config); 491 input->diff = FIELD_GET(ZL_REF_CONFIG_DIFF_EN, ref_config); 492 493 dev_dbg(zldev->dev, "REF%u is %s and configured as %s\n", index, 494 str_enabled_disabled(input->enabled), 495 input->diff ? "differential" : "single-ended"); 496 497 return rc; 498 } 499 500 /** 501 * zl3073x_out_state_fetch - get output state 502 * @zldev: pointer to zl3073x_dev structure 503 * @index: output index to fetch state for 504 * 505 * Function fetches information for the given output (not output pin) 506 * that are invariant and stores them for later use. 507 * 508 * Return: 0 on success, <0 on error 509 */ 510 static int 511 zl3073x_out_state_fetch(struct zl3073x_dev *zldev, u8 index) 512 { 513 struct zl3073x_out *out = &zldev->out[index]; 514 u8 output_ctrl, output_mode; 515 int rc; 516 517 /* Read output configuration */ 518 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_CTRL(index), &output_ctrl); 519 if (rc) 520 return rc; 521 522 /* Store info about output enablement and synthesizer the output 523 * is connected to. 524 */ 525 out->enabled = FIELD_GET(ZL_OUTPUT_CTRL_EN, output_ctrl); 526 out->synth = FIELD_GET(ZL_OUTPUT_CTRL_SYNTH_SEL, output_ctrl); 527 528 dev_dbg(zldev->dev, "OUT%u is %s and connected to SYNTH%u\n", index, 529 str_enabled_disabled(out->enabled), out->synth); 530 531 guard(mutex)(&zldev->multiop_lock); 532 533 /* Read output configuration */ 534 rc = zl3073x_mb_op(zldev, ZL_REG_OUTPUT_MB_SEM, ZL_OUTPUT_MB_SEM_RD, 535 ZL_REG_OUTPUT_MB_MASK, BIT(index)); 536 if (rc) 537 return rc; 538 539 /* Read output_mode */ 540 rc = zl3073x_read_u8(zldev, ZL_REG_OUTPUT_MODE, &output_mode); 541 if (rc) 542 return rc; 543 544 /* Extract and store output signal format */ 545 out->signal_format = FIELD_GET(ZL_OUTPUT_MODE_SIGNAL_FORMAT, 546 output_mode); 547 548 dev_dbg(zldev->dev, "OUT%u has signal format 0x%02x\n", index, 549 out->signal_format); 550 551 return rc; 552 } 553 554 /** 555 * zl3073x_synth_state_fetch - get synth state 556 * @zldev: pointer to zl3073x_dev structure 557 * @index: synth index to fetch state for 558 * 559 * Function fetches information for the given synthesizer that are 560 * invariant and stores them for later use. 561 * 562 * Return: 0 on success, <0 on error 563 */ 564 static int 565 zl3073x_synth_state_fetch(struct zl3073x_dev *zldev, u8 index) 566 { 567 struct zl3073x_synth *synth = &zldev->synth[index]; 568 u16 base, m, n; 569 u8 synth_ctrl; 570 u32 mult; 571 int rc; 572 573 /* Read synth control register */ 574 rc = zl3073x_read_u8(zldev, ZL_REG_SYNTH_CTRL(index), &synth_ctrl); 575 if (rc) 576 return rc; 577 578 /* Store info about synth enablement and DPLL channel the synth is 579 * driven by. 580 */ 581 synth->enabled = FIELD_GET(ZL_SYNTH_CTRL_EN, synth_ctrl); 582 synth->dpll = FIELD_GET(ZL_SYNTH_CTRL_DPLL_SEL, synth_ctrl); 583 584 dev_dbg(zldev->dev, "SYNTH%u is %s and driven by DPLL%u\n", index, 585 str_enabled_disabled(synth->enabled), synth->dpll); 586 587 guard(mutex)(&zldev->multiop_lock); 588 589 /* Read synth configuration */ 590 rc = zl3073x_mb_op(zldev, ZL_REG_SYNTH_MB_SEM, ZL_SYNTH_MB_SEM_RD, 591 ZL_REG_SYNTH_MB_MASK, BIT(index)); 592 if (rc) 593 return rc; 594 595 /* The output frequency is determined by the following formula: 596 * base * multiplier * numerator / denominator 597 * 598 * Read registers with these values 599 */ 600 rc = zl3073x_read_u16(zldev, ZL_REG_SYNTH_FREQ_BASE, &base); 601 if (rc) 602 return rc; 603 604 rc = zl3073x_read_u32(zldev, ZL_REG_SYNTH_FREQ_MULT, &mult); 605 if (rc) 606 return rc; 607 608 rc = zl3073x_read_u16(zldev, ZL_REG_SYNTH_FREQ_M, &m); 609 if (rc) 610 return rc; 611 612 rc = zl3073x_read_u16(zldev, ZL_REG_SYNTH_FREQ_N, &n); 613 if (rc) 614 return rc; 615 616 /* Check denominator for zero to avoid div by 0 */ 617 if (!n) { 618 dev_err(zldev->dev, 619 "Zero divisor for SYNTH%u retrieved from device\n", 620 index); 621 return -EINVAL; 622 } 623 624 /* Compute and store synth frequency */ 625 zldev->synth[index].freq = div_u64(mul_u32_u32(base * m, mult), n); 626 627 dev_dbg(zldev->dev, "SYNTH%u frequency: %u Hz\n", index, 628 zldev->synth[index].freq); 629 630 return rc; 631 } 632 633 static int 634 zl3073x_dev_state_fetch(struct zl3073x_dev *zldev) 635 { 636 int rc; 637 u8 i; 638 639 for (i = 0; i < ZL3073X_NUM_REFS; i++) { 640 rc = zl3073x_ref_state_fetch(zldev, i); 641 if (rc) { 642 dev_err(zldev->dev, 643 "Failed to fetch input state: %pe\n", 644 ERR_PTR(rc)); 645 return rc; 646 } 647 } 648 649 for (i = 0; i < ZL3073X_NUM_SYNTHS; i++) { 650 rc = zl3073x_synth_state_fetch(zldev, i); 651 if (rc) { 652 dev_err(zldev->dev, 653 "Failed to fetch synth state: %pe\n", 654 ERR_PTR(rc)); 655 return rc; 656 } 657 } 658 659 for (i = 0; i < ZL3073X_NUM_OUTS; i++) { 660 rc = zl3073x_out_state_fetch(zldev, i); 661 if (rc) { 662 dev_err(zldev->dev, 663 "Failed to fetch output state: %pe\n", 664 ERR_PTR(rc)); 665 return rc; 666 } 667 } 668 669 return rc; 670 } 671 672 static void 673 zl3073x_dev_periodic_work(struct kthread_work *work) 674 { 675 struct zl3073x_dev *zldev = container_of(work, struct zl3073x_dev, 676 work.work); 677 struct zl3073x_dpll *zldpll; 678 679 list_for_each_entry(zldpll, &zldev->dplls, list) 680 zl3073x_dpll_changes_check(zldpll); 681 682 /* Run twice a second */ 683 kthread_queue_delayed_work(zldev->kworker, &zldev->work, 684 msecs_to_jiffies(500)); 685 } 686 687 static void zl3073x_dev_dpll_fini(void *ptr) 688 { 689 struct zl3073x_dpll *zldpll, *next; 690 struct zl3073x_dev *zldev = ptr; 691 692 /* Stop monitoring thread */ 693 if (zldev->kworker) { 694 kthread_cancel_delayed_work_sync(&zldev->work); 695 kthread_destroy_worker(zldev->kworker); 696 zldev->kworker = NULL; 697 } 698 699 /* Release DPLLs */ 700 list_for_each_entry_safe(zldpll, next, &zldev->dplls, list) { 701 zl3073x_dpll_unregister(zldpll); 702 list_del(&zldpll->list); 703 zl3073x_dpll_free(zldpll); 704 } 705 } 706 707 static int 708 zl3073x_devm_dpll_init(struct zl3073x_dev *zldev, u8 num_dplls) 709 { 710 struct kthread_worker *kworker; 711 struct zl3073x_dpll *zldpll; 712 unsigned int i; 713 int rc; 714 715 INIT_LIST_HEAD(&zldev->dplls); 716 717 /* Initialize all DPLLs */ 718 for (i = 0; i < num_dplls; i++) { 719 zldpll = zl3073x_dpll_alloc(zldev, i); 720 if (IS_ERR(zldpll)) { 721 dev_err_probe(zldev->dev, PTR_ERR(zldpll), 722 "Failed to alloc DPLL%u\n", i); 723 rc = PTR_ERR(zldpll); 724 goto error; 725 } 726 727 rc = zl3073x_dpll_register(zldpll); 728 if (rc) { 729 dev_err_probe(zldev->dev, rc, 730 "Failed to register DPLL%u\n", i); 731 zl3073x_dpll_free(zldpll); 732 goto error; 733 } 734 735 list_add_tail(&zldpll->list, &zldev->dplls); 736 } 737 738 /* Perform initial firmware fine phase correction */ 739 rc = zl3073x_dpll_init_fine_phase_adjust(zldev); 740 if (rc) { 741 dev_err_probe(zldev->dev, rc, 742 "Failed to init fine phase correction\n"); 743 goto error; 744 } 745 746 /* Initialize monitoring thread */ 747 kthread_init_delayed_work(&zldev->work, zl3073x_dev_periodic_work); 748 kworker = kthread_run_worker(0, "zl3073x-%s", dev_name(zldev->dev)); 749 if (IS_ERR(kworker)) { 750 rc = PTR_ERR(kworker); 751 goto error; 752 } 753 754 zldev->kworker = kworker; 755 kthread_queue_delayed_work(zldev->kworker, &zldev->work, 0); 756 757 /* Add devres action to release DPLL related resources */ 758 rc = devm_add_action_or_reset(zldev->dev, zl3073x_dev_dpll_fini, zldev); 759 if (rc) 760 goto error; 761 762 return 0; 763 764 error: 765 zl3073x_dev_dpll_fini(zldev); 766 767 return rc; 768 } 769 770 /** 771 * zl3073x_dev_probe - initialize zl3073x device 772 * @zldev: pointer to zl3073x device 773 * @chip_info: chip info based on compatible 774 * 775 * Common initialization of zl3073x device structure. 776 * 777 * Returns: 0 on success, <0 on error 778 */ 779 int zl3073x_dev_probe(struct zl3073x_dev *zldev, 780 const struct zl3073x_chip_info *chip_info) 781 { 782 u16 id, revision, fw_ver; 783 unsigned int i; 784 u32 cfg_ver; 785 int rc; 786 787 /* Read chip ID */ 788 rc = zl3073x_read_u16(zldev, ZL_REG_ID, &id); 789 if (rc) 790 return rc; 791 792 /* Check it matches */ 793 for (i = 0; i < chip_info->num_ids; i++) { 794 if (id == chip_info->ids[i]) 795 break; 796 } 797 798 if (i == chip_info->num_ids) { 799 return dev_err_probe(zldev->dev, -ENODEV, 800 "Unknown or non-match chip ID: 0x%0x\n", 801 id); 802 } 803 804 /* Read revision, firmware version and custom config version */ 805 rc = zl3073x_read_u16(zldev, ZL_REG_REVISION, &revision); 806 if (rc) 807 return rc; 808 rc = zl3073x_read_u16(zldev, ZL_REG_FW_VER, &fw_ver); 809 if (rc) 810 return rc; 811 rc = zl3073x_read_u32(zldev, ZL_REG_CUSTOM_CONFIG_VER, &cfg_ver); 812 if (rc) 813 return rc; 814 815 dev_dbg(zldev->dev, "ChipID(%X), ChipRev(%X), FwVer(%u)\n", id, 816 revision, fw_ver); 817 dev_dbg(zldev->dev, "Custom config version: %lu.%lu.%lu.%lu\n", 818 FIELD_GET(GENMASK(31, 24), cfg_ver), 819 FIELD_GET(GENMASK(23, 16), cfg_ver), 820 FIELD_GET(GENMASK(15, 8), cfg_ver), 821 FIELD_GET(GENMASK(7, 0), cfg_ver)); 822 823 /* Generate random clock ID as the device has not such property that 824 * could be used for this purpose. A user can later change this value 825 * using devlink. 826 */ 827 zldev->clock_id = get_random_u64(); 828 829 /* Initialize mutex for operations where multiple reads, writes 830 * and/or polls are required to be done atomically. 831 */ 832 rc = devm_mutex_init(zldev->dev, &zldev->multiop_lock); 833 if (rc) 834 return dev_err_probe(zldev->dev, rc, 835 "Failed to initialize mutex\n"); 836 837 /* Fetch device state */ 838 rc = zl3073x_dev_state_fetch(zldev); 839 if (rc) 840 return rc; 841 842 /* Register DPLL channels */ 843 rc = zl3073x_devm_dpll_init(zldev, chip_info->num_channels); 844 if (rc) 845 return rc; 846 847 /* Register the devlink instance and parameters */ 848 rc = zl3073x_devlink_register(zldev); 849 if (rc) 850 return dev_err_probe(zldev->dev, rc, 851 "Failed to register devlink instance\n"); 852 853 return 0; 854 } 855 EXPORT_SYMBOL_NS_GPL(zl3073x_dev_probe, "ZL3073X"); 856 857 MODULE_AUTHOR("Ivan Vecera <ivecera@redhat.com>"); 858 MODULE_DESCRIPTION("Microchip ZL3073x core driver"); 859 MODULE_LICENSE("GPL"); 860