1 // SPDX-License-Identifier: GPL-2.0-only 2 3 #include <linux/array_size.h> 4 #include <linux/bitfield.h> 5 #include <linux/bits.h> 6 #include <linux/dev_printk.h> 7 #include <linux/device.h> 8 #include <linux/export.h> 9 #include <linux/math64.h> 10 #include <linux/module.h> 11 #include <linux/netlink.h> 12 #include <linux/regmap.h> 13 #include <linux/sprintf.h> 14 #include <linux/string_choices.h> 15 #include <linux/unaligned.h> 16 #include <net/devlink.h> 17 18 #include "core.h" 19 #include "devlink.h" 20 #include "dpll.h" 21 #include "regs.h" 22 23 #define ZL_CHIP_INFO(_id, _nchannels, _flags) \ 24 { .id = (_id), .num_channels = (_nchannels), .flags = (_flags) } 25 26 static const struct zl3073x_chip_info zl3073x_chip_ids[] = { 27 ZL_CHIP_INFO(0x0E30, 2, ZL3073X_FLAG_REF_PHASE_COMP_32), 28 ZL_CHIP_INFO(0x0E3B, 3, ZL3073X_FLAG_REF_PHASE_COMP_32), 29 ZL_CHIP_INFO(0x0E93, 1, ZL3073X_FLAG_REF_PHASE_COMP_32), 30 ZL_CHIP_INFO(0x0E94, 2, ZL3073X_FLAG_REF_PHASE_COMP_32), 31 ZL_CHIP_INFO(0x0E95, 3, ZL3073X_FLAG_REF_PHASE_COMP_32), 32 ZL_CHIP_INFO(0x0E96, 4, ZL3073X_FLAG_REF_PHASE_COMP_32), 33 ZL_CHIP_INFO(0x0E97, 5, ZL3073X_FLAG_REF_PHASE_COMP_32), 34 ZL_CHIP_INFO(0x1E93, 1, ZL3073X_FLAG_DIE_TEMP), 35 ZL_CHIP_INFO(0x1E94, 2, ZL3073X_FLAG_DIE_TEMP), 36 ZL_CHIP_INFO(0x1E95, 3, ZL3073X_FLAG_DIE_TEMP), 37 ZL_CHIP_INFO(0x1E96, 4, ZL3073X_FLAG_DIE_TEMP), 38 ZL_CHIP_INFO(0x1E97, 5, ZL3073X_FLAG_DIE_TEMP), 39 ZL_CHIP_INFO(0x1F60, 2, ZL3073X_FLAG_REF_PHASE_COMP_32), 40 ZL_CHIP_INFO(0x2E93, 1, ZL3073X_FLAG_DIE_TEMP), 41 ZL_CHIP_INFO(0x2E94, 2, ZL3073X_FLAG_DIE_TEMP), 42 ZL_CHIP_INFO(0x2E95, 3, ZL3073X_FLAG_DIE_TEMP), 43 ZL_CHIP_INFO(0x2E96, 4, ZL3073X_FLAG_DIE_TEMP), 44 ZL_CHIP_INFO(0x2E97, 5, ZL3073X_FLAG_DIE_TEMP), 45 ZL_CHIP_INFO(0x3FC4, 2, ZL3073X_FLAG_DIE_TEMP), 46 }; 47 48 #define ZL_RANGE_OFFSET 0x80 49 #define ZL_PAGE_SIZE 0x80 50 #define ZL_NUM_PAGES 256 51 #define ZL_PAGE_SEL 0x7F 52 #define ZL_PAGE_SEL_MASK GENMASK(7, 0) 53 #define ZL_NUM_REGS (ZL_NUM_PAGES * ZL_PAGE_SIZE) 54 55 /* Regmap range configuration */ 56 static const struct regmap_range_cfg zl3073x_regmap_range = { 57 .range_min = ZL_RANGE_OFFSET, 58 .range_max = ZL_RANGE_OFFSET + ZL_NUM_REGS - 1, 59 .selector_reg = ZL_PAGE_SEL, 60 .selector_mask = ZL_PAGE_SEL_MASK, 61 .selector_shift = 0, 62 .window_start = 0, 63 .window_len = ZL_PAGE_SIZE, 64 }; 65 66 static bool 67 zl3073x_is_volatile_reg(struct device *dev __maybe_unused, unsigned int reg) 68 { 69 /* Only page selector is non-volatile */ 70 return reg != ZL_PAGE_SEL; 71 } 72 73 const struct regmap_config zl3073x_regmap_config = { 74 .reg_bits = 8, 75 .val_bits = 8, 76 .max_register = ZL_RANGE_OFFSET + ZL_NUM_REGS - 1, 77 .ranges = &zl3073x_regmap_range, 78 .num_ranges = 1, 79 .cache_type = REGCACHE_MAPLE, 80 .volatile_reg = zl3073x_is_volatile_reg, 81 }; 82 EXPORT_SYMBOL_NS_GPL(zl3073x_regmap_config, "ZL3073X"); 83 84 static bool 85 zl3073x_check_reg(struct zl3073x_dev *zldev, unsigned int reg, size_t size) 86 { 87 /* Check that multiop lock is held when accessing registers 88 * from page 10 and above except the page 255 that does not 89 * need this protection. 90 */ 91 if (ZL_REG_PAGE(reg) >= 10 && ZL_REG_PAGE(reg) < 255) 92 lockdep_assert_held(&zldev->multiop_lock); 93 94 /* Check the index is in valid range for indexed register */ 95 if (ZL_REG_OFFSET(reg) > ZL_REG_MAX_OFFSET(reg)) { 96 dev_err(zldev->dev, "Index out of range for reg 0x%04lx\n", 97 ZL_REG_ADDR(reg)); 98 return false; 99 } 100 /* Check the requested size corresponds to register size */ 101 if (ZL_REG_SIZE(reg) != size) { 102 dev_err(zldev->dev, "Invalid size %zu for reg 0x%04lx\n", 103 size, ZL_REG_ADDR(reg)); 104 return false; 105 } 106 107 return true; 108 } 109 110 static int 111 zl3073x_read_reg(struct zl3073x_dev *zldev, unsigned int reg, void *val, 112 size_t size) 113 { 114 int rc; 115 116 if (!zl3073x_check_reg(zldev, reg, size)) 117 return -EINVAL; 118 119 /* Map the register address to virtual range */ 120 reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; 121 122 rc = regmap_bulk_read(zldev->regmap, reg, val, size); 123 if (rc) { 124 dev_err(zldev->dev, "Failed to read reg 0x%04x: %pe\n", reg, 125 ERR_PTR(rc)); 126 return rc; 127 } 128 129 return 0; 130 } 131 132 static int 133 zl3073x_write_reg(struct zl3073x_dev *zldev, unsigned int reg, const void *val, 134 size_t size) 135 { 136 int rc; 137 138 if (!zl3073x_check_reg(zldev, reg, size)) 139 return -EINVAL; 140 141 /* Map the register address to virtual range */ 142 reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; 143 144 rc = regmap_bulk_write(zldev->regmap, reg, val, size); 145 if (rc) { 146 dev_err(zldev->dev, "Failed to write reg 0x%04x: %pe\n", reg, 147 ERR_PTR(rc)); 148 return rc; 149 } 150 151 return 0; 152 } 153 154 /** 155 * zl3073x_read_u8 - read value from 8bit register 156 * @zldev: zl3073x device pointer 157 * @reg: register to write to 158 * @val: value to write 159 * 160 * Reads value from given 8bit register. 161 * 162 * Returns: 0 on success, <0 on error 163 */ 164 int zl3073x_read_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 *val) 165 { 166 return zl3073x_read_reg(zldev, reg, val, sizeof(*val)); 167 } 168 169 /** 170 * zl3073x_write_u8 - write value to 16bit register 171 * @zldev: zl3073x device pointer 172 * @reg: register to write to 173 * @val: value to write 174 * 175 * Writes value into given 8bit register. 176 * 177 * Returns: 0 on success, <0 on error 178 */ 179 int zl3073x_write_u8(struct zl3073x_dev *zldev, unsigned int reg, u8 val) 180 { 181 return zl3073x_write_reg(zldev, reg, &val, sizeof(val)); 182 } 183 184 /** 185 * zl3073x_read_u16 - read value from 16bit register 186 * @zldev: zl3073x device pointer 187 * @reg: register to write to 188 * @val: value to write 189 * 190 * Reads value from given 16bit register. 191 * 192 * Returns: 0 on success, <0 on error 193 */ 194 int zl3073x_read_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 *val) 195 { 196 int rc; 197 198 rc = zl3073x_read_reg(zldev, reg, val, sizeof(*val)); 199 if (!rc) 200 be16_to_cpus(val); 201 202 return rc; 203 } 204 205 /** 206 * zl3073x_write_u16 - write value to 16bit register 207 * @zldev: zl3073x device pointer 208 * @reg: register to write to 209 * @val: value to write 210 * 211 * Writes value into given 16bit register. 212 * 213 * Returns: 0 on success, <0 on error 214 */ 215 int zl3073x_write_u16(struct zl3073x_dev *zldev, unsigned int reg, u16 val) 216 { 217 cpu_to_be16s(&val); 218 219 return zl3073x_write_reg(zldev, reg, &val, sizeof(val)); 220 } 221 222 /** 223 * zl3073x_read_u32 - read value from 32bit register 224 * @zldev: zl3073x device pointer 225 * @reg: register to write to 226 * @val: value to write 227 * 228 * Reads value from given 32bit register. 229 * 230 * Returns: 0 on success, <0 on error 231 */ 232 int zl3073x_read_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 *val) 233 { 234 int rc; 235 236 rc = zl3073x_read_reg(zldev, reg, val, sizeof(*val)); 237 if (!rc) 238 be32_to_cpus(val); 239 240 return rc; 241 } 242 243 /** 244 * zl3073x_write_u32 - write value to 32bit register 245 * @zldev: zl3073x device pointer 246 * @reg: register to write to 247 * @val: value to write 248 * 249 * Writes value into given 32bit register. 250 * 251 * Returns: 0 on success, <0 on error 252 */ 253 int zl3073x_write_u32(struct zl3073x_dev *zldev, unsigned int reg, u32 val) 254 { 255 cpu_to_be32s(&val); 256 257 return zl3073x_write_reg(zldev, reg, &val, sizeof(val)); 258 } 259 260 /** 261 * zl3073x_read_u48 - read value from 48bit register 262 * @zldev: zl3073x device pointer 263 * @reg: register to write to 264 * @val: value to write 265 * 266 * Reads value from given 48bit register. 267 * 268 * Returns: 0 on success, <0 on error 269 */ 270 int zl3073x_read_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 *val) 271 { 272 u8 buf[6]; 273 int rc; 274 275 rc = zl3073x_read_reg(zldev, reg, buf, sizeof(buf)); 276 if (!rc) 277 *val = get_unaligned_be48(buf); 278 279 return rc; 280 } 281 282 /** 283 * zl3073x_write_u48 - write value to 48bit register 284 * @zldev: zl3073x device pointer 285 * @reg: register to write to 286 * @val: value to write 287 * 288 * Writes value into given 48bit register. 289 * The value must be from the interval -S48_MIN to U48_MAX. 290 * 291 * Returns: 0 on success, <0 on error 292 */ 293 int zl3073x_write_u48(struct zl3073x_dev *zldev, unsigned int reg, u64 val) 294 { 295 u8 buf[6]; 296 297 /* Check the value belongs to <S48_MIN, U48_MAX> 298 * Any value >= S48_MIN has bits 47..63 set. 299 */ 300 if (val > GENMASK_ULL(47, 0) && val < GENMASK_ULL(63, 47)) { 301 dev_err(zldev->dev, "Value 0x%0llx out of range\n", val); 302 return -EINVAL; 303 } 304 305 put_unaligned_be48(val, buf); 306 307 return zl3073x_write_reg(zldev, reg, buf, sizeof(buf)); 308 } 309 310 /** 311 * zl3073x_poll_zero_u8 - wait for register to be cleared by device 312 * @zldev: zl3073x device pointer 313 * @reg: register to poll (has to be 8bit register) 314 * @mask: bit mask for polling 315 * @timeout_us: timeout in microseconds 316 * 317 * Waits for bits specified by @mask in register @reg value to be cleared 318 * by the device. 319 * 320 * Returns: 0 on success, <0 on error 321 */ 322 int zl3073x_poll_zero_u8(struct zl3073x_dev *zldev, unsigned int reg, 323 u8 mask, unsigned int timeout_us) 324 { 325 #define ZL_POLL_SLEEP_US 10 326 unsigned int val; 327 328 /* Check the register is 8bit */ 329 if (ZL_REG_SIZE(reg) != 1) { 330 dev_err(zldev->dev, "Invalid reg 0x%04lx size for polling\n", 331 ZL_REG_ADDR(reg)); 332 return -EINVAL; 333 } 334 335 /* Map the register address to virtual range */ 336 reg = ZL_REG_ADDR(reg) + ZL_RANGE_OFFSET; 337 338 return regmap_read_poll_timeout(zldev->regmap, reg, val, !(val & mask), 339 ZL_POLL_SLEEP_US, timeout_us); 340 } 341 342 int zl3073x_mb_op(struct zl3073x_dev *zldev, unsigned int op_reg, u8 op_val, 343 unsigned int mask_reg, u16 mask_val) 344 { 345 int rc; 346 347 /* Set mask for the operation */ 348 rc = zl3073x_write_u16(zldev, mask_reg, mask_val); 349 if (rc) 350 return rc; 351 352 /* Trigger the operation */ 353 rc = zl3073x_write_u8(zldev, op_reg, op_val); 354 if (rc) 355 return rc; 356 357 /* Wait for the operation to actually finish */ 358 return zl3073x_poll_zero_u8(zldev, op_reg, op_val, 359 ZL_POLL_MB_TIMEOUT_US); 360 } 361 362 /** 363 * zl3073x_do_hwreg_op - Perform HW register read/write operation 364 * @zldev: zl3073x device pointer 365 * @op: operation to perform 366 * 367 * Performs requested operation and waits for its completion. 368 * 369 * Return: 0 on success, <0 on error 370 */ 371 static int 372 zl3073x_do_hwreg_op(struct zl3073x_dev *zldev, u8 op) 373 { 374 int rc; 375 376 /* Set requested operation and set pending bit */ 377 rc = zl3073x_write_u8(zldev, ZL_REG_HWREG_OP, op | ZL_HWREG_OP_PENDING); 378 if (rc) 379 return rc; 380 381 /* Poll for completion - pending bit cleared */ 382 return zl3073x_poll_zero_u8(zldev, ZL_REG_HWREG_OP, ZL_HWREG_OP_PENDING, 383 ZL_POLL_HWREG_TIMEOUT_US); 384 } 385 386 /** 387 * zl3073x_read_hwreg - Read HW register 388 * @zldev: zl3073x device pointer 389 * @addr: HW register address 390 * @value: Value of the HW register 391 * 392 * Reads HW register value and stores it into @value. 393 * 394 * Return: 0 on success, <0 on error 395 */ 396 int zl3073x_read_hwreg(struct zl3073x_dev *zldev, u32 addr, u32 *value) 397 { 398 int rc; 399 400 /* Set address to read data from */ 401 rc = zl3073x_write_u32(zldev, ZL_REG_HWREG_ADDR, addr); 402 if (rc) 403 return rc; 404 405 /* Perform the read operation */ 406 rc = zl3073x_do_hwreg_op(zldev, ZL_HWREG_OP_READ); 407 if (rc) 408 return rc; 409 410 /* Read the received data */ 411 return zl3073x_read_u32(zldev, ZL_REG_HWREG_READ_DATA, value); 412 } 413 414 /** 415 * zl3073x_write_hwreg - Write value to HW register 416 * @zldev: zl3073x device pointer 417 * @addr: HW registers address 418 * @value: Value to be written to HW register 419 * 420 * Stores the requested value into HW register. 421 * 422 * Return: 0 on success, <0 on error 423 */ 424 int zl3073x_write_hwreg(struct zl3073x_dev *zldev, u32 addr, u32 value) 425 { 426 int rc; 427 428 /* Set address to write data to */ 429 rc = zl3073x_write_u32(zldev, ZL_REG_HWREG_ADDR, addr); 430 if (rc) 431 return rc; 432 433 /* Set data to be written */ 434 rc = zl3073x_write_u32(zldev, ZL_REG_HWREG_WRITE_DATA, value); 435 if (rc) 436 return rc; 437 438 /* Perform the write operation */ 439 return zl3073x_do_hwreg_op(zldev, ZL_HWREG_OP_WRITE); 440 } 441 442 /** 443 * zl3073x_update_hwreg - Update certain bits in HW register 444 * @zldev: zl3073x device pointer 445 * @addr: HW register address 446 * @value: Value to be written into HW register 447 * @mask: Bitmask indicating bits to be updated 448 * 449 * Reads given HW register, updates requested bits specified by value and 450 * mask and writes result back to HW register. 451 * 452 * Return: 0 on success, <0 on error 453 */ 454 int zl3073x_update_hwreg(struct zl3073x_dev *zldev, u32 addr, u32 value, 455 u32 mask) 456 { 457 u32 tmp; 458 int rc; 459 460 rc = zl3073x_read_hwreg(zldev, addr, &tmp); 461 if (rc) 462 return rc; 463 464 tmp &= ~mask; 465 tmp |= value & mask; 466 467 return zl3073x_write_hwreg(zldev, addr, tmp); 468 } 469 470 /** 471 * zl3073x_write_hwreg_seq - Write HW registers sequence 472 * @zldev: pointer to device structure 473 * @seq: pointer to first sequence item 474 * @num_items: number of items in sequence 475 * 476 * Writes given HW registers sequence. 477 * 478 * Return: 0 on success, <0 on error 479 */ 480 int zl3073x_write_hwreg_seq(struct zl3073x_dev *zldev, 481 const struct zl3073x_hwreg_seq_item *seq, 482 size_t num_items) 483 { 484 int i, rc = 0; 485 486 for (i = 0; i < num_items; i++) { 487 dev_dbg(zldev->dev, "Write 0x%0x [0x%0x] to 0x%0x", 488 seq[i].value, seq[i].mask, seq[i].addr); 489 490 if (seq[i].mask == U32_MAX) 491 /* Write value directly */ 492 rc = zl3073x_write_hwreg(zldev, seq[i].addr, 493 seq[i].value); 494 else 495 /* Update only bits specified by the mask */ 496 rc = zl3073x_update_hwreg(zldev, seq[i].addr, 497 seq[i].value, seq[i].mask); 498 if (rc) 499 return rc; 500 501 if (seq->wait) 502 msleep(seq->wait); 503 } 504 505 return rc; 506 } 507 508 static int 509 zl3073x_dev_state_fetch(struct zl3073x_dev *zldev) 510 { 511 int rc; 512 u8 i; 513 514 for (i = 0; i < ZL3073X_NUM_REFS; i++) { 515 rc = zl3073x_ref_state_fetch(zldev, i); 516 if (rc) { 517 dev_err(zldev->dev, 518 "Failed to fetch input state: %pe\n", 519 ERR_PTR(rc)); 520 return rc; 521 } 522 } 523 524 for (i = 0; i < ZL3073X_NUM_SYNTHS; i++) { 525 rc = zl3073x_synth_state_fetch(zldev, i); 526 if (rc) { 527 dev_err(zldev->dev, 528 "Failed to fetch synth state: %pe\n", 529 ERR_PTR(rc)); 530 return rc; 531 } 532 } 533 534 for (i = 0; i < ZL3073X_NUM_OUTS; i++) { 535 rc = zl3073x_out_state_fetch(zldev, i); 536 if (rc) { 537 dev_err(zldev->dev, 538 "Failed to fetch output state: %pe\n", 539 ERR_PTR(rc)); 540 return rc; 541 } 542 } 543 544 for (i = 0; i < zldev->info->num_channels; i++) { 545 rc = zl3073x_chan_state_fetch(zldev, i); 546 if (rc) { 547 dev_err(zldev->dev, 548 "Failed to fetch channel state: %pe\n", 549 ERR_PTR(rc)); 550 return rc; 551 } 552 } 553 554 return rc; 555 } 556 557 static void 558 zl3073x_dev_ref_states_update(struct zl3073x_dev *zldev) 559 { 560 int i, rc; 561 562 for (i = 0; i < ZL3073X_NUM_REFS; i++) { 563 rc = zl3073x_ref_state_update(zldev, i); 564 if (rc) 565 dev_warn(zldev->dev, 566 "Failed to get REF%u status: %pe\n", i, 567 ERR_PTR(rc)); 568 } 569 } 570 571 572 573 /** 574 * zl3073x_ref_phase_offsets_update - update reference phase offsets 575 * @zldev: pointer to zl3073x_dev structure 576 * @channel: DPLL channel number or -1 577 * 578 * The function asks device to update phase offsets latch registers with 579 * the latest measured values. There are 2 sets of latch registers: 580 * 581 * 1) Up to 5 DPLL-to-connected-ref registers that contain phase offset 582 * values between particular DPLL channel and its *connected* input 583 * reference. 584 * 585 * 2) 10 selected-DPLL-to-all-ref registers that contain phase offset values 586 * between selected DPLL channel and all input references. 587 * 588 * If the caller is interested in 2) then it has to pass DPLL channel number 589 * in @channel parameter. If it is interested only in 1) then it should pass 590 * @channel parameter with value of -1. 591 * 592 * Return: 0 on success, <0 on error 593 */ 594 int zl3073x_ref_phase_offsets_update(struct zl3073x_dev *zldev, int channel) 595 { 596 int rc; 597 598 /* Per datasheet we have to wait for 'dpll_ref_phase_err_rqst_rd' 599 * to be zero to ensure that the measured data are coherent. 600 */ 601 rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST, 602 ZL_REF_PHASE_ERR_READ_RQST_RD, 603 ZL_POLL_PHASE_ERR_TIMEOUT_US); 604 if (rc) 605 return rc; 606 607 /* Select DPLL channel if it is specified */ 608 if (channel != -1) { 609 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_IDX, channel); 610 if (rc) 611 return rc; 612 } 613 614 /* Request to update phase offsets measurement values */ 615 rc = zl3073x_write_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST, 616 ZL_REF_PHASE_ERR_READ_RQST_RD); 617 if (rc) 618 return rc; 619 620 /* Wait for finish */ 621 return zl3073x_poll_zero_u8(zldev, ZL_REG_REF_PHASE_ERR_READ_RQST, 622 ZL_REF_PHASE_ERR_READ_RQST_RD, 623 ZL_POLL_PHASE_ERR_TIMEOUT_US); 624 } 625 626 /** 627 * zl3073x_ref_freq_meas_latch - latch reference frequency measurements 628 * @zldev: pointer to zl3073x_dev structure 629 * @type: measurement type (ZL_REF_FREQ_MEAS_CTRL_*) 630 * 631 * The function waits for the previous measurement to finish, selects all 632 * references and requests a new measurement of the given type. 633 * 634 * Return: 0 on success, <0 on error 635 */ 636 static int 637 zl3073x_ref_freq_meas_latch(struct zl3073x_dev *zldev, u8 type) 638 { 639 int rc; 640 641 /* Wait for previous measurement to finish */ 642 rc = zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL, 643 ZL_REF_FREQ_MEAS_CTRL, 644 ZL_POLL_FREQ_MEAS_TIMEOUT_US); 645 if (rc) 646 return rc; 647 648 /* Select all references for measurement */ 649 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_3_0, 650 GENMASK(7, 0)); /* REF0P..REF3N */ 651 if (rc) 652 return rc; 653 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_MASK_4, 654 GENMASK(1, 0)); /* REF4P..REF4N */ 655 if (rc) 656 return rc; 657 658 /* Request measurement */ 659 rc = zl3073x_write_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL, type); 660 if (rc) 661 return rc; 662 663 /* Wait for finish */ 664 return zl3073x_poll_zero_u8(zldev, ZL_REG_REF_FREQ_MEAS_CTRL, 665 ZL_REF_FREQ_MEAS_CTRL, 666 ZL_POLL_FREQ_MEAS_TIMEOUT_US); 667 } 668 669 /** 670 * zl3073x_ref_freq_meas_update - update measured input reference frequencies 671 * @zldev: pointer to zl3073x_dev structure 672 * 673 * The function asks device to latch measured input reference frequencies 674 * and stores the results in the ref state. 675 * 676 * Return: 0 on success, <0 on error 677 */ 678 static int 679 zl3073x_ref_freq_meas_update(struct zl3073x_dev *zldev) 680 { 681 int i, rc; 682 683 rc = zl3073x_ref_freq_meas_latch(zldev, ZL_REF_FREQ_MEAS_CTRL_REF_FREQ); 684 if (rc) 685 return rc; 686 687 /* Read measured frequencies in Hz (unsigned 32-bit, LSB = 1 Hz) */ 688 for (i = 0; i < ZL3073X_NUM_REFS; i++) { 689 u32 value; 690 691 rc = zl3073x_read_u32(zldev, ZL_REG_REF_FREQ(i), &value); 692 if (rc) 693 return rc; 694 695 zldev->ref[i].meas_freq = value; 696 } 697 698 return 0; 699 } 700 701 static void 702 zl3073x_dev_periodic_work(struct kthread_work *work) 703 { 704 struct zl3073x_dev *zldev = container_of(work, struct zl3073x_dev, 705 work.work); 706 struct zl3073x_dpll *zldpll; 707 int rc; 708 709 /* Update input references' states */ 710 zl3073x_dev_ref_states_update(zldev); 711 712 /* Update DPLL-to-connected-ref phase offsets registers */ 713 rc = zl3073x_ref_phase_offsets_update(zldev, -1); 714 if (rc) 715 dev_warn(zldev->dev, "Failed to update phase offsets: %pe\n", 716 ERR_PTR(rc)); 717 718 /* Update measured input reference frequencies if frequency 719 * monitoring is enabled. 720 */ 721 if (READ_ONCE(zldev->freq_monitor)) { 722 rc = zl3073x_ref_freq_meas_update(zldev); 723 if (rc) 724 dev_warn(zldev->dev, 725 "Failed to update measured frequencies: %pe\n", 726 ERR_PTR(rc)); 727 } 728 729 list_for_each_entry(zldpll, &zldev->dplls, list) 730 zl3073x_dpll_changes_check(zldpll); 731 732 /* Run twice a second */ 733 kthread_queue_delayed_work(zldev->kworker, &zldev->work, 734 msecs_to_jiffies(500)); 735 } 736 737 int zl3073x_dev_phase_avg_factor_set(struct zl3073x_dev *zldev, u8 factor) 738 { 739 u8 dpll_meas_ctrl, value; 740 int rc; 741 742 /* Read DPLL phase measurement control register */ 743 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl); 744 if (rc) 745 return rc; 746 747 /* Convert requested factor to register value */ 748 value = (factor + 1) & 0x0f; 749 750 /* Update phase measurement control register */ 751 FIELD_MODIFY(ZL_DPLL_MEAS_CTRL_AVG_FACTOR, &dpll_meas_ctrl, value); 752 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl); 753 if (rc) 754 return rc; 755 756 /* Save the new factor */ 757 WRITE_ONCE(zldev->phase_avg_factor, factor); 758 759 return 0; 760 } 761 762 /** 763 * zl3073x_dev_phase_meas_setup - setup phase offset measurement 764 * @zldev: pointer to zl3073x_dev structure 765 * 766 * Enable phase offset measurement block, set measurement averaging factor 767 * and enable DPLL-to-its-ref phase measurement for all DPLLs. 768 * 769 * Returns: 0 on success, <0 on error 770 */ 771 static int 772 zl3073x_dev_phase_meas_setup(struct zl3073x_dev *zldev) 773 { 774 struct zl3073x_dpll *zldpll; 775 u8 dpll_meas_ctrl, mask = 0; 776 int rc; 777 778 /* Setup phase measurement averaging factor */ 779 rc = zl3073x_dev_phase_avg_factor_set(zldev, zldev->phase_avg_factor); 780 if (rc) 781 return rc; 782 783 /* Read DPLL phase measurement control register */ 784 rc = zl3073x_read_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, &dpll_meas_ctrl); 785 if (rc) 786 return rc; 787 788 /* Enable DPLL measurement block */ 789 dpll_meas_ctrl |= ZL_DPLL_MEAS_CTRL_EN; 790 791 /* Update phase measurement control register */ 792 rc = zl3073x_write_u8(zldev, ZL_REG_DPLL_MEAS_CTRL, dpll_meas_ctrl); 793 if (rc) 794 return rc; 795 796 /* Enable DPLL-to-connected-ref measurement for each channel */ 797 list_for_each_entry(zldpll, &zldev->dplls, list) 798 mask |= BIT(zldpll->id); 799 800 return zl3073x_write_u8(zldev, ZL_REG_DPLL_PHASE_ERR_READ_MASK, mask); 801 } 802 803 /** 804 * zl3073x_dev_start - Start normal operation 805 * @zldev: zl3073x device pointer 806 * @full: perform full initialization 807 * 808 * The function starts normal operation, which means registering all DPLLs and 809 * their pins, and starting monitoring. If full initialization is requested, 810 * the function additionally initializes the phase offset measurement block and 811 * fetches hardware-invariant parameters. 812 * 813 * Return: 0 on success, <0 on error 814 */ 815 int zl3073x_dev_start(struct zl3073x_dev *zldev, bool full) 816 { 817 struct zl3073x_dpll *zldpll; 818 u8 info; 819 int rc; 820 821 rc = zl3073x_read_u8(zldev, ZL_REG_INFO, &info); 822 if (rc) { 823 dev_err(zldev->dev, "Failed to read device status info\n"); 824 return rc; 825 } 826 827 if (!FIELD_GET(ZL_INFO_READY, info)) { 828 /* The ready bit indicates that the firmware was successfully 829 * configured and is ready for normal operation. If it is 830 * cleared then the configuration stored in flash is wrong 831 * or missing. In this situation the driver will expose 832 * only devlink interface to give an opportunity to flash 833 * the correct config. 834 */ 835 dev_info(zldev->dev, 836 "FW not fully ready - missing or corrupted config\n"); 837 838 return 0; 839 } 840 841 if (full) { 842 /* Fetch device state */ 843 rc = zl3073x_dev_state_fetch(zldev); 844 if (rc) 845 return rc; 846 847 /* Setup phase offset measurement block */ 848 rc = zl3073x_dev_phase_meas_setup(zldev); 849 if (rc) { 850 dev_err(zldev->dev, 851 "Failed to setup phase measurement\n"); 852 return rc; 853 } 854 } 855 856 /* Register all DPLLs */ 857 list_for_each_entry(zldpll, &zldev->dplls, list) { 858 rc = zl3073x_dpll_register(zldpll); 859 if (rc) { 860 dev_err_probe(zldev->dev, rc, 861 "Failed to register DPLL%u\n", 862 zldpll->id); 863 return rc; 864 } 865 } 866 867 /* Perform initial firmware fine phase correction */ 868 rc = zl3073x_dpll_init_fine_phase_adjust(zldev); 869 if (rc) { 870 dev_err_probe(zldev->dev, rc, 871 "Failed to init fine phase correction\n"); 872 return rc; 873 } 874 875 /* Start monitoring */ 876 kthread_queue_delayed_work(zldev->kworker, &zldev->work, 0); 877 878 return 0; 879 } 880 881 /** 882 * zl3073x_dev_stop - Stop normal operation 883 * @zldev: zl3073x device pointer 884 * 885 * The function stops the normal operation that mean deregistration of all 886 * DPLLs and their pins and stop monitoring. 887 * 888 * Return: 0 on success, <0 on error 889 */ 890 void zl3073x_dev_stop(struct zl3073x_dev *zldev) 891 { 892 struct zl3073x_dpll *zldpll; 893 894 /* Stop monitoring */ 895 kthread_cancel_delayed_work_sync(&zldev->work); 896 897 /* Unregister all DPLLs */ 898 list_for_each_entry(zldpll, &zldev->dplls, list) { 899 if (zldpll->dpll_dev) 900 zl3073x_dpll_unregister(zldpll); 901 } 902 } 903 904 static void zl3073x_dev_dpll_fini(void *ptr) 905 { 906 struct zl3073x_dpll *zldpll, *next; 907 struct zl3073x_dev *zldev = ptr; 908 909 /* Stop monitoring and unregister DPLLs */ 910 zl3073x_dev_stop(zldev); 911 912 /* Destroy monitoring thread */ 913 if (zldev->kworker) { 914 kthread_destroy_worker(zldev->kworker); 915 zldev->kworker = NULL; 916 } 917 918 /* Free all DPLLs */ 919 list_for_each_entry_safe(zldpll, next, &zldev->dplls, list) { 920 list_del(&zldpll->list); 921 zl3073x_dpll_free(zldpll); 922 } 923 } 924 925 static int 926 zl3073x_devm_dpll_init(struct zl3073x_dev *zldev) 927 { 928 struct kthread_worker *kworker; 929 struct zl3073x_dpll *zldpll; 930 unsigned int i; 931 int rc; 932 933 INIT_LIST_HEAD(&zldev->dplls); 934 935 /* Allocate all DPLLs */ 936 for (i = 0; i < zldev->info->num_channels; i++) { 937 zldpll = zl3073x_dpll_alloc(zldev, i); 938 if (IS_ERR(zldpll)) { 939 dev_err_probe(zldev->dev, PTR_ERR(zldpll), 940 "Failed to alloc DPLL%u\n", i); 941 rc = PTR_ERR(zldpll); 942 goto error; 943 } 944 945 list_add_tail(&zldpll->list, &zldev->dplls); 946 } 947 948 /* Initialize monitoring thread */ 949 kthread_init_delayed_work(&zldev->work, zl3073x_dev_periodic_work); 950 kworker = kthread_run_worker(0, "zl3073x-%s", dev_name(zldev->dev)); 951 if (IS_ERR(kworker)) { 952 rc = PTR_ERR(kworker); 953 goto error; 954 } 955 zldev->kworker = kworker; 956 957 /* Start normal operation */ 958 rc = zl3073x_dev_start(zldev, true); 959 if (rc) { 960 dev_err_probe(zldev->dev, rc, "Failed to start device\n"); 961 goto error; 962 } 963 964 /* Add devres action to release DPLL related resources */ 965 return devm_add_action_or_reset(zldev->dev, zl3073x_dev_dpll_fini, zldev); 966 967 error: 968 zl3073x_dev_dpll_fini(zldev); 969 970 return rc; 971 } 972 973 /** 974 * zl3073x_dev_probe - initialize zl3073x device 975 * @zldev: pointer to zl3073x device 976 * 977 * Common initialization of zl3073x device structure. 978 * 979 * Returns: 0 on success, <0 on error 980 */ 981 int zl3073x_dev_probe(struct zl3073x_dev *zldev) 982 { 983 u16 id, revision, fw_ver; 984 unsigned int i; 985 u32 cfg_ver; 986 int rc; 987 988 /* Read chip ID */ 989 rc = zl3073x_read_u16(zldev, ZL_REG_ID, &id); 990 if (rc) 991 return rc; 992 993 /* Detect chip variant */ 994 for (i = 0; i < ARRAY_SIZE(zl3073x_chip_ids); i++) { 995 if (zl3073x_chip_ids[i].id == id) 996 break; 997 } 998 999 if (i == ARRAY_SIZE(zl3073x_chip_ids)) 1000 return dev_err_probe(zldev->dev, -ENODEV, 1001 "Unknown chip ID: 0x%04x\n", id); 1002 1003 zldev->info = &zl3073x_chip_ids[i]; 1004 1005 /* Read revision, firmware version and custom config version */ 1006 rc = zl3073x_read_u16(zldev, ZL_REG_REVISION, &revision); 1007 if (rc) 1008 return rc; 1009 rc = zl3073x_read_u16(zldev, ZL_REG_FW_VER, &fw_ver); 1010 if (rc) 1011 return rc; 1012 rc = zl3073x_read_u32(zldev, ZL_REG_CUSTOM_CONFIG_VER, &cfg_ver); 1013 if (rc) 1014 return rc; 1015 1016 dev_dbg(zldev->dev, "ChipID(%X), ChipRev(%X), FwVer(%u)\n", id, 1017 revision, fw_ver); 1018 dev_dbg(zldev->dev, "Custom config version: %lu.%lu.%lu.%lu\n", 1019 FIELD_GET(GENMASK(31, 24), cfg_ver), 1020 FIELD_GET(GENMASK(23, 16), cfg_ver), 1021 FIELD_GET(GENMASK(15, 8), cfg_ver), 1022 FIELD_GET(GENMASK(7, 0), cfg_ver)); 1023 1024 /* Generate random clock ID as the device has not such property that 1025 * could be used for this purpose. A user can later change this value 1026 * using devlink. 1027 */ 1028 zldev->clock_id = get_random_u64(); 1029 1030 /* Default phase offset averaging factor */ 1031 zldev->phase_avg_factor = 2; 1032 1033 /* Initialize mutex for operations where multiple reads, writes 1034 * and/or polls are required to be done atomically. 1035 */ 1036 rc = devm_mutex_init(zldev->dev, &zldev->multiop_lock); 1037 if (rc) 1038 return dev_err_probe(zldev->dev, rc, 1039 "Failed to initialize mutex\n"); 1040 1041 /* Register DPLL channels */ 1042 rc = zl3073x_devm_dpll_init(zldev); 1043 if (rc) 1044 return rc; 1045 1046 /* Register the devlink instance and parameters */ 1047 rc = zl3073x_devlink_register(zldev); 1048 if (rc) 1049 return dev_err_probe(zldev->dev, rc, 1050 "Failed to register devlink instance\n"); 1051 1052 return 0; 1053 } 1054 EXPORT_SYMBOL_NS_GPL(zl3073x_dev_probe, "ZL3073X"); 1055 1056 MODULE_AUTHOR("Ivan Vecera <ivecera@redhat.com>"); 1057 MODULE_DESCRIPTION("Microchip ZL3073x core driver"); 1058 MODULE_LICENSE("GPL"); 1059