1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Generic netlink for DPLL management framework 4 * 5 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 6 * Copyright (c) 2023 Intel and affiliates 7 * 8 */ 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/netdevice.h> 12 #include <net/genetlink.h> 13 #include "dpll_core.h" 14 #include "dpll_netlink.h" 15 #include "dpll_nl.h" 16 #include <uapi/linux/dpll.h> 17 18 #define ASSERT_NOT_NULL(ptr) (WARN_ON(!ptr)) 19 20 #define xa_for_each_marked_start(xa, index, entry, filter, start) \ 21 for (index = start, entry = xa_find(xa, &index, ULONG_MAX, filter); \ 22 entry; entry = xa_find_after(xa, &index, ULONG_MAX, filter)) 23 24 struct dpll_dump_ctx { 25 unsigned long idx; 26 }; 27 28 static struct dpll_dump_ctx *dpll_dump_context(struct netlink_callback *cb) 29 { 30 return (struct dpll_dump_ctx *)cb->ctx; 31 } 32 33 static int 34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) 35 { 36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) 37 return -EMSGSIZE; 38 39 return 0; 40 } 41 42 static int 43 dpll_msg_add_dev_parent_handle(struct sk_buff *msg, u32 id) 44 { 45 if (nla_put_u32(msg, DPLL_A_PIN_PARENT_ID, id)) 46 return -EMSGSIZE; 47 48 return 0; 49 } 50 51 static bool dpll_pin_available(struct dpll_pin *pin) 52 { 53 struct dpll_pin_ref *par_ref; 54 unsigned long i; 55 56 if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) 57 return false; 58 xa_for_each(&pin->parent_refs, i, par_ref) 59 if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, 60 DPLL_REGISTERED)) 61 return true; 62 xa_for_each(&pin->dpll_refs, i, par_ref) 63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, 64 DPLL_REGISTERED)) 65 return true; 66 return false; 67 } 68 69 /** 70 * dpll_msg_add_pin_handle - attach pin handle attribute to a given message 71 * @msg: pointer to sk_buff message to attach a pin handle 72 * @pin: pin pointer 73 * 74 * Return: 75 * * 0 - success 76 * * -EMSGSIZE - no space in message to attach pin handle 77 */ 78 static int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin) 79 { 80 if (!pin) 81 return 0; 82 if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id)) 83 return -EMSGSIZE; 84 return 0; 85 } 86 87 static struct dpll_pin *dpll_netdev_pin(const struct net_device *dev) 88 { 89 return rcu_dereference_rtnl(dev->dpll_pin); 90 } 91 92 /** 93 * dpll_netdev_pin_handle_size - get size of pin handle attribute of a netdev 94 * @dev: netdev from which to get the pin 95 * 96 * Return: byte size of pin handle attribute, or 0 if @dev has no pin. 97 */ 98 size_t dpll_netdev_pin_handle_size(const struct net_device *dev) 99 { 100 return dpll_netdev_pin(dev) ? nla_total_size(4) : 0; /* DPLL_A_PIN_ID */ 101 } 102 103 int dpll_netdev_add_pin_handle(struct sk_buff *msg, 104 const struct net_device *dev) 105 { 106 return dpll_msg_add_pin_handle(msg, dpll_netdev_pin(dev)); 107 } 108 109 static int 110 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, 111 struct netlink_ext_ack *extack) 112 { 113 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 114 enum dpll_mode mode; 115 int ret; 116 117 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 118 if (ret) 119 return ret; 120 if (nla_put_u32(msg, DPLL_A_MODE, mode)) 121 return -EMSGSIZE; 122 123 return 0; 124 } 125 126 static int 127 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, 128 struct netlink_ext_ack *extack) 129 { 130 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 131 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 132 enum dpll_mode mode; 133 int ret; 134 135 if (ops->supported_modes_get) { 136 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, 137 extack); 138 if (ret) 139 return ret; 140 } else { 141 /* If the supported modes are not reported by the driver, the 142 * only supported mode is the one obtained by mode_get(). 143 */ 144 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 145 if (ret) 146 return ret; 147 148 __set_bit(mode, modes); 149 } 150 151 for_each_set_bit(mode, modes, DPLL_MODE_MAX + 1) 152 if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode)) 153 return -EMSGSIZE; 154 155 return 0; 156 } 157 158 static int 159 dpll_msg_add_phase_offset_monitor(struct sk_buff *msg, struct dpll_device *dpll, 160 struct netlink_ext_ack *extack) 161 { 162 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 163 enum dpll_feature_state state; 164 int ret; 165 166 if (ops->phase_offset_monitor_set && ops->phase_offset_monitor_get) { 167 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), 168 &state, extack); 169 if (ret) 170 return ret; 171 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_MONITOR, state)) 172 return -EMSGSIZE; 173 } 174 175 return 0; 176 } 177 178 static int 179 dpll_msg_add_freq_monitor(struct sk_buff *msg, struct dpll_device *dpll, 180 struct netlink_ext_ack *extack) 181 { 182 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 183 enum dpll_feature_state state; 184 int ret; 185 186 if (ops->freq_monitor_set && ops->freq_monitor_get) { 187 ret = ops->freq_monitor_get(dpll, dpll_priv(dpll), 188 &state, extack); 189 if (ret) 190 return ret; 191 if (nla_put_u32(msg, DPLL_A_FREQUENCY_MONITOR, state)) 192 return -EMSGSIZE; 193 } 194 195 return 0; 196 } 197 198 static int 199 dpll_msg_add_phase_offset_avg_factor(struct sk_buff *msg, 200 struct dpll_device *dpll, 201 struct netlink_ext_ack *extack) 202 { 203 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 204 u32 factor; 205 int ret; 206 207 if (ops->phase_offset_avg_factor_get) { 208 ret = ops->phase_offset_avg_factor_get(dpll, dpll_priv(dpll), 209 &factor, extack); 210 if (ret) 211 return ret; 212 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_AVG_FACTOR, factor)) 213 return -EMSGSIZE; 214 } 215 216 return 0; 217 } 218 219 static int 220 dpll_msg_add_lock_status(struct sk_buff *msg, struct dpll_device *dpll, 221 struct netlink_ext_ack *extack) 222 { 223 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 224 enum dpll_lock_status_error status_error = 0; 225 enum dpll_lock_status status; 226 int ret; 227 228 ret = ops->lock_status_get(dpll, dpll_priv(dpll), &status, 229 &status_error, extack); 230 if (ret) 231 return ret; 232 if (nla_put_u32(msg, DPLL_A_LOCK_STATUS, status)) 233 return -EMSGSIZE; 234 if (status_error && 235 (status == DPLL_LOCK_STATUS_UNLOCKED || 236 status == DPLL_LOCK_STATUS_HOLDOVER) && 237 nla_put_u32(msg, DPLL_A_LOCK_STATUS_ERROR, status_error)) 238 return -EMSGSIZE; 239 240 return 0; 241 } 242 243 static int 244 dpll_msg_add_temp(struct sk_buff *msg, struct dpll_device *dpll, 245 struct netlink_ext_ack *extack) 246 { 247 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 248 s32 temp; 249 int ret; 250 251 if (!ops->temp_get) 252 return 0; 253 ret = ops->temp_get(dpll, dpll_priv(dpll), &temp, extack); 254 if (ret) 255 return ret; 256 if (nla_put_s32(msg, DPLL_A_TEMP, temp)) 257 return -EMSGSIZE; 258 259 return 0; 260 } 261 262 static int 263 dpll_msg_add_clock_quality_level(struct sk_buff *msg, struct dpll_device *dpll, 264 struct netlink_ext_ack *extack) 265 { 266 DECLARE_BITMAP(qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) = { 0 }; 267 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 268 enum dpll_clock_quality_level ql; 269 int ret; 270 271 if (!ops->clock_quality_level_get) 272 return 0; 273 ret = ops->clock_quality_level_get(dpll, dpll_priv(dpll), qls, extack); 274 if (ret) 275 return ret; 276 for_each_set_bit(ql, qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) 277 if (nla_put_u32(msg, DPLL_A_CLOCK_QUALITY_LEVEL, ql)) 278 return -EMSGSIZE; 279 280 return 0; 281 } 282 283 static int 284 dpll_msg_add_pin_prio(struct sk_buff *msg, struct dpll_pin *pin, 285 struct dpll_pin_ref *ref, 286 struct netlink_ext_ack *extack) 287 { 288 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 289 struct dpll_device *dpll = ref->dpll; 290 u32 prio; 291 int ret; 292 293 if (!ops->prio_get) 294 return 0; 295 ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 296 dpll_priv(dpll), &prio, extack); 297 if (ret) 298 return ret; 299 if (nla_put_u32(msg, DPLL_A_PIN_PRIO, prio)) 300 return -EMSGSIZE; 301 302 return 0; 303 } 304 305 static int 306 dpll_msg_add_pin_on_dpll_state(struct sk_buff *msg, struct dpll_pin *pin, 307 struct dpll_pin_ref *ref, 308 struct netlink_ext_ack *extack) 309 { 310 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 311 struct dpll_device *dpll = ref->dpll; 312 enum dpll_pin_state state; 313 int ret; 314 315 if (!ops->state_on_dpll_get) 316 return 0; 317 ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 318 dpll, dpll_priv(dpll), &state, extack); 319 if (ret) 320 return ret; 321 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) 322 return -EMSGSIZE; 323 324 return 0; 325 } 326 327 static int 328 dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin, 329 struct dpll_pin_ref *ref, 330 struct netlink_ext_ack *extack) 331 { 332 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 333 struct dpll_device *dpll = ref->dpll; 334 enum dpll_pin_direction direction; 335 int ret; 336 337 ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 338 dpll_priv(dpll), &direction, extack); 339 if (ret) 340 return ret; 341 if (nla_put_u32(msg, DPLL_A_PIN_DIRECTION, direction)) 342 return -EMSGSIZE; 343 344 return 0; 345 } 346 347 static int 348 dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin, 349 struct dpll_pin_ref *ref, 350 struct netlink_ext_ack *extack) 351 { 352 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 353 struct dpll_device *dpll = ref->dpll; 354 s32 phase_adjust; 355 int ret; 356 357 if (!ops->phase_adjust_get) 358 return 0; 359 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 360 dpll, dpll_priv(dpll), 361 &phase_adjust, extack); 362 if (ret) 363 return ret; 364 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust)) 365 return -EMSGSIZE; 366 367 return 0; 368 } 369 370 static int 371 dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin, 372 struct dpll_pin_ref *ref, 373 struct netlink_ext_ack *extack) 374 { 375 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 376 struct dpll_device *dpll = ref->dpll; 377 s64 phase_offset; 378 int ret; 379 380 if (!ops->phase_offset_get) 381 return 0; 382 ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 383 dpll, dpll_priv(dpll), &phase_offset, 384 extack); 385 if (ret) 386 return ret; 387 if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset), 388 &phase_offset, DPLL_A_PIN_PAD)) 389 return -EMSGSIZE; 390 391 return 0; 392 } 393 394 static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin, 395 struct dpll_pin_ref *ref, 396 struct netlink_ext_ack *extack) 397 { 398 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 399 struct dpll_device *dpll = ref->dpll; 400 s64 ffo; 401 int ret; 402 403 if (!ops->ffo_get) 404 return 0; 405 ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 406 dpll, dpll_priv(dpll), &ffo, extack); 407 if (ret) { 408 if (ret == -ENODATA) 409 return 0; 410 return ret; 411 } 412 /* Put the FFO value in PPM to preserve compatibility with older 413 * programs. 414 */ 415 ret = nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 416 div_s64(ffo, 1000000)); 417 if (ret) 418 return -EMSGSIZE; 419 return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, 420 ffo); 421 } 422 423 static int dpll_msg_add_measured_freq(struct sk_buff *msg, struct dpll_pin *pin, 424 struct dpll_pin_ref *ref, 425 struct netlink_ext_ack *extack) 426 { 427 const struct dpll_device_ops *dev_ops = dpll_device_ops(ref->dpll); 428 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 429 struct dpll_device *dpll = ref->dpll; 430 enum dpll_feature_state state; 431 u64 measured_freq; 432 int ret; 433 434 if (!ops->measured_freq_get) 435 return 0; 436 ret = dev_ops->freq_monitor_get(dpll, dpll_priv(dpll), 437 &state, extack); 438 if (ret) 439 return ret; 440 if (state == DPLL_FEATURE_STATE_DISABLE) 441 return 0; 442 ret = ops->measured_freq_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 443 dpll, dpll_priv(dpll), &measured_freq, 444 extack); 445 if (ret) 446 return ret; 447 if (nla_put_64bit(msg, DPLL_A_PIN_MEASURED_FREQUENCY, 448 sizeof(measured_freq), &measured_freq, 449 DPLL_A_PIN_PAD)) 450 return -EMSGSIZE; 451 452 return 0; 453 } 454 455 static int 456 dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin, 457 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 458 { 459 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 460 struct dpll_device *dpll = ref->dpll; 461 struct nlattr *nest; 462 int fs, ret; 463 u64 freq; 464 465 if (!ops->frequency_get) 466 return 0; 467 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 468 dpll_priv(dpll), &freq, extack); 469 if (ret) 470 return ret; 471 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY, sizeof(freq), &freq, 472 DPLL_A_PIN_PAD)) 473 return -EMSGSIZE; 474 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) { 475 nest = nla_nest_start(msg, DPLL_A_PIN_FREQUENCY_SUPPORTED); 476 if (!nest) 477 return -EMSGSIZE; 478 freq = pin->prop.freq_supported[fs].min; 479 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, sizeof(freq), 480 &freq, DPLL_A_PIN_PAD)) { 481 nla_nest_cancel(msg, nest); 482 return -EMSGSIZE; 483 } 484 freq = pin->prop.freq_supported[fs].max; 485 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, sizeof(freq), 486 &freq, DPLL_A_PIN_PAD)) { 487 nla_nest_cancel(msg, nest); 488 return -EMSGSIZE; 489 } 490 nla_nest_end(msg, nest); 491 } 492 493 return 0; 494 } 495 496 static int 497 dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpll_pin *pin, 498 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 499 { 500 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 501 struct dpll_device *dpll = ref->dpll; 502 struct dpll_pin_esync esync; 503 struct nlattr *nest; 504 int ret, i; 505 506 if (!ops->esync_get) 507 return 0; 508 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 509 dpll_priv(dpll), &esync, extack); 510 if (ret == -EOPNOTSUPP) 511 return 0; 512 else if (ret) 513 return ret; 514 if (nla_put_64bit(msg, DPLL_A_PIN_ESYNC_FREQUENCY, sizeof(esync.freq), 515 &esync.freq, DPLL_A_PIN_PAD)) 516 return -EMSGSIZE; 517 if (nla_put_u32(msg, DPLL_A_PIN_ESYNC_PULSE, esync.pulse)) 518 return -EMSGSIZE; 519 for (i = 0; i < esync.range_num; i++) { 520 nest = nla_nest_start(msg, 521 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED); 522 if (!nest) 523 return -EMSGSIZE; 524 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, 525 sizeof(esync.range[i].min), 526 &esync.range[i].min, DPLL_A_PIN_PAD)) 527 goto nest_cancel; 528 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, 529 sizeof(esync.range[i].max), 530 &esync.range[i].max, DPLL_A_PIN_PAD)) 531 goto nest_cancel; 532 nla_nest_end(msg, nest); 533 } 534 return 0; 535 536 nest_cancel: 537 nla_nest_cancel(msg, nest); 538 return -EMSGSIZE; 539 } 540 541 static int 542 dpll_msg_add_pin_ref_sync(struct sk_buff *msg, struct dpll_pin *pin, 543 struct dpll_pin_ref *ref, 544 struct netlink_ext_ack *extack) 545 { 546 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 547 struct dpll_device *dpll = ref->dpll; 548 void *pin_priv, *ref_sync_pin_priv; 549 struct dpll_pin *ref_sync_pin; 550 enum dpll_pin_state state; 551 struct nlattr *nest; 552 unsigned long index; 553 int ret; 554 555 pin_priv = dpll_pin_on_dpll_priv(dpll, pin); 556 xa_for_each(&pin->ref_sync_pins, index, ref_sync_pin) { 557 if (!dpll_pin_available(ref_sync_pin)) 558 continue; 559 ref_sync_pin_priv = dpll_pin_on_dpll_priv(dpll, ref_sync_pin); 560 if (WARN_ON(!ops->ref_sync_get)) 561 return -EOPNOTSUPP; 562 ret = ops->ref_sync_get(pin, pin_priv, ref_sync_pin, 563 ref_sync_pin_priv, &state, extack); 564 if (ret) 565 return ret; 566 nest = nla_nest_start(msg, DPLL_A_PIN_REFERENCE_SYNC); 567 if (!nest) 568 return -EMSGSIZE; 569 if (nla_put_s32(msg, DPLL_A_PIN_ID, ref_sync_pin->id)) 570 goto nest_cancel; 571 if (nla_put_s32(msg, DPLL_A_PIN_STATE, state)) 572 goto nest_cancel; 573 nla_nest_end(msg, nest); 574 } 575 return 0; 576 577 nest_cancel: 578 nla_nest_cancel(msg, nest); 579 return -EMSGSIZE; 580 } 581 582 static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) 583 { 584 int fs; 585 586 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) 587 if (freq >= pin->prop.freq_supported[fs].min && 588 freq <= pin->prop.freq_supported[fs].max) 589 return true; 590 return false; 591 } 592 593 static int 594 dpll_msg_add_pin_parents(struct sk_buff *msg, struct dpll_pin *pin, 595 struct dpll_pin_ref *dpll_ref, 596 struct netlink_ext_ack *extack) 597 { 598 enum dpll_pin_state state; 599 struct dpll_pin_ref *ref; 600 struct dpll_pin *ppin; 601 struct nlattr *nest; 602 unsigned long index; 603 int ret; 604 605 xa_for_each(&pin->parent_refs, index, ref) { 606 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 607 void *parent_priv; 608 609 ppin = ref->pin; 610 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, ppin); 611 ret = ops->state_on_pin_get(pin, 612 dpll_pin_on_pin_priv(ppin, pin), 613 ppin, parent_priv, &state, extack); 614 if (ret) 615 return ret; 616 nest = nla_nest_start(msg, DPLL_A_PIN_PARENT_PIN); 617 if (!nest) 618 return -EMSGSIZE; 619 ret = dpll_msg_add_dev_parent_handle(msg, ppin->id); 620 if (ret) 621 goto nest_cancel; 622 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) { 623 ret = -EMSGSIZE; 624 goto nest_cancel; 625 } 626 nla_nest_end(msg, nest); 627 } 628 629 return 0; 630 631 nest_cancel: 632 nla_nest_cancel(msg, nest); 633 return ret; 634 } 635 636 static int 637 dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin, 638 struct netlink_ext_ack *extack) 639 { 640 struct dpll_pin_ref *ref; 641 struct nlattr *attr; 642 unsigned long index; 643 int ret; 644 645 xa_for_each(&pin->dpll_refs, index, ref) { 646 attr = nla_nest_start(msg, DPLL_A_PIN_PARENT_DEVICE); 647 if (!attr) 648 return -EMSGSIZE; 649 ret = dpll_msg_add_dev_parent_handle(msg, ref->dpll->id); 650 if (ret) 651 goto nest_cancel; 652 ret = dpll_msg_add_pin_on_dpll_state(msg, pin, ref, extack); 653 if (ret) 654 goto nest_cancel; 655 ret = dpll_msg_add_pin_prio(msg, pin, ref, extack); 656 if (ret) 657 goto nest_cancel; 658 ret = dpll_msg_add_pin_direction(msg, pin, ref, extack); 659 if (ret) 660 goto nest_cancel; 661 ret = dpll_msg_add_phase_offset(msg, pin, ref, extack); 662 if (ret) 663 goto nest_cancel; 664 nla_nest_end(msg, attr); 665 } 666 667 return 0; 668 669 nest_cancel: 670 nla_nest_end(msg, attr); 671 return ret; 672 } 673 674 static int 675 dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, 676 struct netlink_ext_ack *extack) 677 { 678 const struct dpll_pin_properties *prop = &pin->prop; 679 struct dpll_pin_ref *ref; 680 int ret; 681 682 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 683 ASSERT_NOT_NULL(ref); 684 685 ret = dpll_msg_add_pin_handle(msg, pin); 686 if (ret) 687 return ret; 688 if (nla_put_string(msg, DPLL_A_PIN_MODULE_NAME, 689 module_name(pin->module))) 690 return -EMSGSIZE; 691 if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id), 692 &pin->clock_id, DPLL_A_PIN_PAD)) 693 return -EMSGSIZE; 694 if (prop->board_label && 695 nla_put_string(msg, DPLL_A_PIN_BOARD_LABEL, prop->board_label)) 696 return -EMSGSIZE; 697 if (prop->panel_label && 698 nla_put_string(msg, DPLL_A_PIN_PANEL_LABEL, prop->panel_label)) 699 return -EMSGSIZE; 700 if (prop->package_label && 701 nla_put_string(msg, DPLL_A_PIN_PACKAGE_LABEL, 702 prop->package_label)) 703 return -EMSGSIZE; 704 if (nla_put_u32(msg, DPLL_A_PIN_TYPE, prop->type)) 705 return -EMSGSIZE; 706 if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities)) 707 return -EMSGSIZE; 708 ret = dpll_msg_add_pin_freq(msg, pin, ref, extack); 709 if (ret) 710 return ret; 711 if (prop->phase_gran && 712 nla_put_u32(msg, DPLL_A_PIN_PHASE_ADJUST_GRAN, 713 prop->phase_gran)) 714 return -EMSGSIZE; 715 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN, 716 prop->phase_range.min)) 717 return -EMSGSIZE; 718 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX, 719 prop->phase_range.max)) 720 return -EMSGSIZE; 721 ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack); 722 if (ret) 723 return ret; 724 ret = dpll_msg_add_ffo(msg, pin, ref, extack); 725 if (ret) 726 return ret; 727 ret = dpll_msg_add_measured_freq(msg, pin, ref, extack); 728 if (ret) 729 return ret; 730 ret = dpll_msg_add_pin_esync(msg, pin, ref, extack); 731 if (ret) 732 return ret; 733 if (!xa_empty(&pin->ref_sync_pins)) 734 ret = dpll_msg_add_pin_ref_sync(msg, pin, ref, extack); 735 if (ret) 736 return ret; 737 if (xa_empty(&pin->parent_refs)) 738 ret = dpll_msg_add_pin_dplls(msg, pin, extack); 739 else 740 ret = dpll_msg_add_pin_parents(msg, pin, ref, extack); 741 742 return ret; 743 } 744 745 static int 746 dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg, 747 struct netlink_ext_ack *extack) 748 { 749 int ret; 750 751 ret = dpll_msg_add_dev_handle(msg, dpll); 752 if (ret) 753 return ret; 754 if (nla_put_string(msg, DPLL_A_MODULE_NAME, module_name(dpll->module))) 755 return -EMSGSIZE; 756 if (nla_put_64bit(msg, DPLL_A_CLOCK_ID, sizeof(dpll->clock_id), 757 &dpll->clock_id, DPLL_A_PAD)) 758 return -EMSGSIZE; 759 ret = dpll_msg_add_temp(msg, dpll, extack); 760 if (ret) 761 return ret; 762 ret = dpll_msg_add_lock_status(msg, dpll, extack); 763 if (ret) 764 return ret; 765 ret = dpll_msg_add_clock_quality_level(msg, dpll, extack); 766 if (ret) 767 return ret; 768 ret = dpll_msg_add_mode(msg, dpll, extack); 769 if (ret) 770 return ret; 771 ret = dpll_msg_add_mode_supported(msg, dpll, extack); 772 if (ret) 773 return ret; 774 if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type)) 775 return -EMSGSIZE; 776 ret = dpll_msg_add_phase_offset_monitor(msg, dpll, extack); 777 if (ret) 778 return ret; 779 ret = dpll_msg_add_phase_offset_avg_factor(msg, dpll, extack); 780 if (ret) 781 return ret; 782 ret = dpll_msg_add_freq_monitor(msg, dpll, extack); 783 if (ret) 784 return ret; 785 786 return 0; 787 } 788 789 static int 790 dpll_device_event_send(enum dpll_cmd event, struct dpll_device *dpll) 791 { 792 struct sk_buff *msg; 793 int ret = -ENOMEM; 794 void *hdr; 795 796 if (WARN_ON(!xa_get_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED))) 797 return -ENODEV; 798 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 799 if (!msg) 800 return -ENOMEM; 801 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 802 if (!hdr) 803 goto err_free_msg; 804 ret = dpll_device_get_one(dpll, msg, NULL); 805 if (ret) 806 goto err_cancel_msg; 807 genlmsg_end(msg, hdr); 808 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 809 810 return 0; 811 812 err_cancel_msg: 813 genlmsg_cancel(msg, hdr); 814 err_free_msg: 815 nlmsg_free(msg); 816 817 return ret; 818 } 819 820 int dpll_device_create_ntf(struct dpll_device *dpll) 821 { 822 dpll_device_notify(dpll, DPLL_DEVICE_CREATED); 823 return dpll_device_event_send(DPLL_CMD_DEVICE_CREATE_NTF, dpll); 824 } 825 826 int dpll_device_delete_ntf(struct dpll_device *dpll) 827 { 828 dpll_device_notify(dpll, DPLL_DEVICE_DELETED); 829 return dpll_device_event_send(DPLL_CMD_DEVICE_DELETE_NTF, dpll); 830 } 831 832 static int 833 __dpll_device_change_ntf(struct dpll_device *dpll) 834 { 835 dpll_device_notify(dpll, DPLL_DEVICE_CHANGED); 836 return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); 837 } 838 839 /** 840 * dpll_device_change_ntf - notify that the dpll device has been changed 841 * @dpll: registered dpll pointer 842 * 843 * Context: acquires and holds a dpll_lock. 844 * Return: 0 if succeeds, error code otherwise. 845 */ 846 int dpll_device_change_ntf(struct dpll_device *dpll) 847 { 848 int ret; 849 850 mutex_lock(&dpll_lock); 851 ret = __dpll_device_change_ntf(dpll); 852 mutex_unlock(&dpll_lock); 853 854 return ret; 855 } 856 EXPORT_SYMBOL_GPL(dpll_device_change_ntf); 857 858 static int 859 dpll_pin_event_send(enum dpll_cmd event, struct dpll_pin *pin) 860 { 861 struct sk_buff *msg; 862 int ret = -ENOMEM; 863 void *hdr; 864 865 if (!dpll_pin_available(pin)) 866 return -ENODEV; 867 868 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 869 if (!msg) 870 return -ENOMEM; 871 872 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 873 if (!hdr) 874 goto err_free_msg; 875 ret = dpll_cmd_pin_get_one(msg, pin, NULL); 876 if (ret) 877 goto err_cancel_msg; 878 genlmsg_end(msg, hdr); 879 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 880 881 return 0; 882 883 err_cancel_msg: 884 genlmsg_cancel(msg, hdr); 885 err_free_msg: 886 nlmsg_free(msg); 887 888 return ret; 889 } 890 891 int dpll_pin_create_ntf(struct dpll_pin *pin) 892 { 893 dpll_pin_notify(pin, DPLL_PIN_CREATED); 894 return dpll_pin_event_send(DPLL_CMD_PIN_CREATE_NTF, pin); 895 } 896 897 int dpll_pin_delete_ntf(struct dpll_pin *pin) 898 { 899 dpll_pin_notify(pin, DPLL_PIN_DELETED); 900 return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); 901 } 902 903 int __dpll_pin_change_ntf(struct dpll_pin *pin) 904 { 905 dpll_pin_notify(pin, DPLL_PIN_CHANGED); 906 return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); 907 } 908 909 /** 910 * dpll_pin_change_ntf - notify that the pin has been changed 911 * @pin: registered pin pointer 912 * 913 * Context: acquires and holds a dpll_lock. 914 * Return: 0 if succeeds, error code otherwise. 915 */ 916 int dpll_pin_change_ntf(struct dpll_pin *pin) 917 { 918 int ret; 919 920 mutex_lock(&dpll_lock); 921 ret = __dpll_pin_change_ntf(pin); 922 mutex_unlock(&dpll_lock); 923 924 return ret; 925 } 926 EXPORT_SYMBOL_GPL(dpll_pin_change_ntf); 927 928 static int 929 dpll_mode_set(struct dpll_device *dpll, struct nlattr *a, 930 struct netlink_ext_ack *extack) 931 { 932 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 933 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 934 enum dpll_mode mode = nla_get_u32(a), old_mode; 935 int ret; 936 937 if (!(ops->mode_set && ops->supported_modes_get)) { 938 NL_SET_ERR_MSG_ATTR(extack, a, 939 "dpll device does not support mode switch"); 940 return -EOPNOTSUPP; 941 } 942 943 ret = ops->mode_get(dpll, dpll_priv(dpll), &old_mode, extack); 944 if (ret) { 945 NL_SET_ERR_MSG(extack, "unable to get current mode"); 946 return ret; 947 } 948 949 if (mode == old_mode) 950 return 0; 951 952 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, extack); 953 if (ret) { 954 NL_SET_ERR_MSG(extack, "unable to get supported modes"); 955 return ret; 956 } 957 958 if (!test_bit(mode, modes)) { 959 NL_SET_ERR_MSG(extack, 960 "dpll device does not support requested mode"); 961 return -EINVAL; 962 } 963 964 return ops->mode_set(dpll, dpll_priv(dpll), mode, extack); 965 } 966 967 static int 968 dpll_phase_offset_monitor_set(struct dpll_device *dpll, struct nlattr *a, 969 struct netlink_ext_ack *extack) 970 { 971 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 972 enum dpll_feature_state state = nla_get_u32(a), old_state; 973 int ret; 974 975 if (!(ops->phase_offset_monitor_set && ops->phase_offset_monitor_get)) { 976 NL_SET_ERR_MSG_ATTR(extack, a, "dpll device not capable of phase offset monitor"); 977 return -EOPNOTSUPP; 978 } 979 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), &old_state, 980 extack); 981 if (ret) { 982 NL_SET_ERR_MSG(extack, "unable to get current state of phase offset monitor"); 983 return ret; 984 } 985 if (state == old_state) 986 return 0; 987 988 return ops->phase_offset_monitor_set(dpll, dpll_priv(dpll), state, 989 extack); 990 } 991 992 static int 993 dpll_phase_offset_avg_factor_set(struct dpll_device *dpll, struct nlattr *a, 994 struct netlink_ext_ack *extack) 995 { 996 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 997 u32 factor = nla_get_u32(a); 998 999 if (!ops->phase_offset_avg_factor_set) { 1000 NL_SET_ERR_MSG_ATTR(extack, a, 1001 "device not capable of changing phase offset average factor"); 1002 return -EOPNOTSUPP; 1003 } 1004 1005 return ops->phase_offset_avg_factor_set(dpll, dpll_priv(dpll), factor, 1006 extack); 1007 } 1008 1009 static int 1010 dpll_freq_monitor_set(struct dpll_device *dpll, struct nlattr *a, 1011 struct netlink_ext_ack *extack) 1012 { 1013 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1014 enum dpll_feature_state state = nla_get_u32(a), old_state; 1015 int ret; 1016 1017 if (!(ops->freq_monitor_set && ops->freq_monitor_get)) { 1018 NL_SET_ERR_MSG_ATTR(extack, a, 1019 "dpll device not capable of frequency monitor"); 1020 return -EOPNOTSUPP; 1021 } 1022 ret = ops->freq_monitor_get(dpll, dpll_priv(dpll), &old_state, 1023 extack); 1024 if (ret) { 1025 NL_SET_ERR_MSG(extack, 1026 "unable to get current state of frequency monitor"); 1027 return ret; 1028 } 1029 if (state == old_state) 1030 return 0; 1031 1032 return ops->freq_monitor_set(dpll, dpll_priv(dpll), state, extack); 1033 } 1034 1035 static int 1036 dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a, 1037 struct netlink_ext_ack *extack) 1038 { 1039 u64 freq = nla_get_u64(a), old_freq; 1040 struct dpll_pin_ref *ref, *failed; 1041 const struct dpll_pin_ops *ops; 1042 struct dpll_device *dpll; 1043 unsigned long i; 1044 int ret; 1045 1046 if (!dpll_pin_is_freq_supported(pin, freq)) { 1047 NL_SET_ERR_MSG_ATTR(extack, a, "frequency is not supported by the device"); 1048 return -EINVAL; 1049 } 1050 1051 xa_for_each(&pin->dpll_refs, i, ref) { 1052 ops = dpll_pin_ops(ref); 1053 if (!ops->frequency_set || !ops->frequency_get) { 1054 NL_SET_ERR_MSG(extack, "frequency set not supported by the device"); 1055 return -EOPNOTSUPP; 1056 } 1057 } 1058 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1059 ops = dpll_pin_ops(ref); 1060 dpll = ref->dpll; 1061 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1062 dpll_priv(dpll), &old_freq, extack); 1063 if (ret) { 1064 NL_SET_ERR_MSG(extack, "unable to get old frequency value"); 1065 return ret; 1066 } 1067 if (freq == old_freq) 1068 return 0; 1069 1070 xa_for_each(&pin->dpll_refs, i, ref) { 1071 ops = dpll_pin_ops(ref); 1072 dpll = ref->dpll; 1073 ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1074 dpll, dpll_priv(dpll), freq, extack); 1075 if (ret) { 1076 failed = ref; 1077 NL_SET_ERR_MSG_FMT(extack, "frequency set failed for dpll_id:%u", 1078 dpll->id); 1079 goto rollback; 1080 } 1081 } 1082 __dpll_pin_change_ntf(pin); 1083 1084 return 0; 1085 1086 rollback: 1087 xa_for_each(&pin->dpll_refs, i, ref) { 1088 if (ref == failed) 1089 break; 1090 ops = dpll_pin_ops(ref); 1091 dpll = ref->dpll; 1092 if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1093 dpll, dpll_priv(dpll), old_freq, extack)) 1094 NL_SET_ERR_MSG(extack, "set frequency rollback failed"); 1095 } 1096 return ret; 1097 } 1098 1099 static int 1100 dpll_pin_esync_set(struct dpll_pin *pin, struct nlattr *a, 1101 struct netlink_ext_ack *extack) 1102 { 1103 struct dpll_pin_ref *ref, *failed; 1104 const struct dpll_pin_ops *ops; 1105 struct dpll_pin_esync esync; 1106 u64 freq = nla_get_u64(a); 1107 struct dpll_device *dpll; 1108 bool supported = false; 1109 unsigned long i; 1110 int ret; 1111 1112 xa_for_each(&pin->dpll_refs, i, ref) { 1113 ops = dpll_pin_ops(ref); 1114 if (!ops->esync_set || !ops->esync_get) { 1115 NL_SET_ERR_MSG(extack, 1116 "embedded sync feature is not supported by this device"); 1117 return -EOPNOTSUPP; 1118 } 1119 } 1120 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1121 ops = dpll_pin_ops(ref); 1122 dpll = ref->dpll; 1123 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1124 dpll_priv(dpll), &esync, extack); 1125 if (ret) { 1126 NL_SET_ERR_MSG(extack, "unable to get current embedded sync frequency value"); 1127 return ret; 1128 } 1129 if (freq == esync.freq) 1130 return 0; 1131 for (i = 0; i < esync.range_num; i++) 1132 if (freq <= esync.range[i].max && freq >= esync.range[i].min) 1133 supported = true; 1134 if (!supported) { 1135 NL_SET_ERR_MSG_ATTR(extack, a, 1136 "requested embedded sync frequency value is not supported by this device"); 1137 return -EINVAL; 1138 } 1139 1140 xa_for_each(&pin->dpll_refs, i, ref) { 1141 void *pin_dpll_priv; 1142 1143 ops = dpll_pin_ops(ref); 1144 dpll = ref->dpll; 1145 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1146 ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1147 freq, extack); 1148 if (ret) { 1149 failed = ref; 1150 NL_SET_ERR_MSG_FMT(extack, 1151 "embedded sync frequency set failed for dpll_id: %u", 1152 dpll->id); 1153 goto rollback; 1154 } 1155 } 1156 __dpll_pin_change_ntf(pin); 1157 1158 return 0; 1159 1160 rollback: 1161 xa_for_each(&pin->dpll_refs, i, ref) { 1162 void *pin_dpll_priv; 1163 1164 if (ref == failed) 1165 break; 1166 ops = dpll_pin_ops(ref); 1167 dpll = ref->dpll; 1168 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1169 if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1170 esync.freq, extack)) 1171 NL_SET_ERR_MSG(extack, "set embedded sync frequency rollback failed"); 1172 } 1173 return ret; 1174 } 1175 1176 static int 1177 dpll_pin_ref_sync_state_set(struct dpll_pin *pin, 1178 unsigned long ref_sync_pin_idx, 1179 const enum dpll_pin_state state, 1180 struct netlink_ext_ack *extack) 1181 1182 { 1183 struct dpll_pin_ref *ref, *failed; 1184 const struct dpll_pin_ops *ops; 1185 enum dpll_pin_state old_state; 1186 struct dpll_pin *ref_sync_pin; 1187 struct dpll_device *dpll; 1188 unsigned long i; 1189 int ret; 1190 1191 ref_sync_pin = xa_find(&pin->ref_sync_pins, &ref_sync_pin_idx, 1192 ULONG_MAX, XA_PRESENT); 1193 if (!ref_sync_pin) { 1194 NL_SET_ERR_MSG(extack, "reference sync pin not found"); 1195 return -EINVAL; 1196 } 1197 if (!dpll_pin_available(ref_sync_pin)) { 1198 NL_SET_ERR_MSG(extack, "reference sync pin not available"); 1199 return -EINVAL; 1200 } 1201 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1202 ASSERT_NOT_NULL(ref); 1203 ops = dpll_pin_ops(ref); 1204 if (!ops->ref_sync_set || !ops->ref_sync_get) { 1205 NL_SET_ERR_MSG(extack, "reference sync not supported by this pin"); 1206 return -EOPNOTSUPP; 1207 } 1208 dpll = ref->dpll; 1209 ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1210 ref_sync_pin, 1211 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1212 &old_state, extack); 1213 if (ret) { 1214 NL_SET_ERR_MSG(extack, "unable to get old reference sync state"); 1215 return ret; 1216 } 1217 if (state == old_state) 1218 return 0; 1219 xa_for_each(&pin->dpll_refs, i, ref) { 1220 ops = dpll_pin_ops(ref); 1221 dpll = ref->dpll; 1222 ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1223 ref_sync_pin, 1224 dpll_pin_on_dpll_priv(dpll, 1225 ref_sync_pin), 1226 state, extack); 1227 if (ret) { 1228 failed = ref; 1229 NL_SET_ERR_MSG_FMT(extack, "reference sync set failed for dpll_id:%u", 1230 dpll->id); 1231 goto rollback; 1232 } 1233 } 1234 __dpll_pin_change_ntf(pin); 1235 1236 return 0; 1237 1238 rollback: 1239 xa_for_each(&pin->dpll_refs, i, ref) { 1240 if (ref == failed) 1241 break; 1242 ops = dpll_pin_ops(ref); 1243 dpll = ref->dpll; 1244 if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1245 ref_sync_pin, 1246 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1247 old_state, extack)) 1248 NL_SET_ERR_MSG(extack, "set reference sync rollback failed"); 1249 } 1250 return ret; 1251 } 1252 1253 static int 1254 dpll_pin_ref_sync_set(struct dpll_pin *pin, struct nlattr *nest, 1255 struct netlink_ext_ack *extack) 1256 { 1257 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1258 enum dpll_pin_state state; 1259 u32 sync_pin_id; 1260 1261 nla_parse_nested(tb, DPLL_A_PIN_MAX, nest, 1262 dpll_reference_sync_nl_policy, extack); 1263 if (!tb[DPLL_A_PIN_ID]) { 1264 NL_SET_ERR_MSG(extack, "sync pin id expected"); 1265 return -EINVAL; 1266 } 1267 sync_pin_id = nla_get_u32(tb[DPLL_A_PIN_ID]); 1268 1269 if (!tb[DPLL_A_PIN_STATE]) { 1270 NL_SET_ERR_MSG(extack, "sync pin state expected"); 1271 return -EINVAL; 1272 } 1273 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1274 1275 return dpll_pin_ref_sync_state_set(pin, sync_pin_id, state, extack); 1276 } 1277 1278 static int 1279 dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, 1280 enum dpll_pin_state state, 1281 struct netlink_ext_ack *extack) 1282 { 1283 struct dpll_pin_ref *parent_ref; 1284 const struct dpll_pin_ops *ops; 1285 struct dpll_pin_ref *dpll_ref; 1286 void *pin_priv, *parent_priv; 1287 struct dpll_pin *parent; 1288 unsigned long i; 1289 int ret; 1290 1291 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1292 pin->prop.capabilities)) { 1293 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1294 return -EOPNOTSUPP; 1295 } 1296 parent = xa_load(&dpll_pin_xa, parent_idx); 1297 if (!parent) 1298 return -EINVAL; 1299 parent_ref = xa_load(&pin->parent_refs, parent->pin_idx); 1300 if (!parent_ref) 1301 return -EINVAL; 1302 xa_for_each(&parent->dpll_refs, i, dpll_ref) { 1303 ops = dpll_pin_ops(parent_ref); 1304 if (!ops->state_on_pin_set) 1305 return -EOPNOTSUPP; 1306 pin_priv = dpll_pin_on_pin_priv(parent, pin); 1307 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, parent); 1308 ret = ops->state_on_pin_set(pin, pin_priv, parent, parent_priv, 1309 state, extack); 1310 if (ret) 1311 return ret; 1312 } 1313 __dpll_pin_change_ntf(pin); 1314 1315 return 0; 1316 } 1317 1318 static int 1319 dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin, 1320 enum dpll_pin_state state, 1321 struct netlink_ext_ack *extack) 1322 { 1323 const struct dpll_pin_ops *ops; 1324 struct dpll_pin_ref *ref; 1325 int ret; 1326 1327 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1328 pin->prop.capabilities)) { 1329 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1330 return -EOPNOTSUPP; 1331 } 1332 ref = xa_load(&pin->dpll_refs, dpll->id); 1333 ASSERT_NOT_NULL(ref); 1334 ops = dpll_pin_ops(ref); 1335 if (!ops->state_on_dpll_set) 1336 return -EOPNOTSUPP; 1337 ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1338 dpll, dpll_priv(dpll), state, extack); 1339 if (ret) 1340 return ret; 1341 __dpll_pin_change_ntf(pin); 1342 1343 return 0; 1344 } 1345 1346 static int 1347 dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin, 1348 u32 prio, struct netlink_ext_ack *extack) 1349 { 1350 const struct dpll_pin_ops *ops; 1351 struct dpll_pin_ref *ref; 1352 int ret; 1353 1354 if (!(DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE & 1355 pin->prop.capabilities)) { 1356 NL_SET_ERR_MSG(extack, "prio changing is not allowed"); 1357 return -EOPNOTSUPP; 1358 } 1359 ref = xa_load(&pin->dpll_refs, dpll->id); 1360 ASSERT_NOT_NULL(ref); 1361 ops = dpll_pin_ops(ref); 1362 if (!ops->prio_set) 1363 return -EOPNOTSUPP; 1364 ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1365 dpll_priv(dpll), prio, extack); 1366 if (ret) 1367 return ret; 1368 __dpll_pin_change_ntf(pin); 1369 1370 return 0; 1371 } 1372 1373 static int 1374 dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll, 1375 enum dpll_pin_direction direction, 1376 struct netlink_ext_ack *extack) 1377 { 1378 const struct dpll_pin_ops *ops; 1379 struct dpll_pin_ref *ref; 1380 int ret; 1381 1382 if (!(DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE & 1383 pin->prop.capabilities)) { 1384 NL_SET_ERR_MSG(extack, "direction changing is not allowed"); 1385 return -EOPNOTSUPP; 1386 } 1387 ref = xa_load(&pin->dpll_refs, dpll->id); 1388 ASSERT_NOT_NULL(ref); 1389 ops = dpll_pin_ops(ref); 1390 if (!ops->direction_set) 1391 return -EOPNOTSUPP; 1392 ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1393 dpll, dpll_priv(dpll), direction, extack); 1394 if (ret) 1395 return ret; 1396 __dpll_pin_change_ntf(pin); 1397 1398 return 0; 1399 } 1400 1401 static int 1402 dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr, 1403 struct netlink_ext_ack *extack) 1404 { 1405 struct dpll_pin_ref *ref, *failed; 1406 const struct dpll_pin_ops *ops; 1407 s32 phase_adj, old_phase_adj; 1408 struct dpll_device *dpll; 1409 unsigned long i; 1410 int ret; 1411 1412 phase_adj = nla_get_s32(phase_adj_attr); 1413 if (phase_adj > pin->prop.phase_range.max || 1414 phase_adj < pin->prop.phase_range.min) { 1415 NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr, 1416 "phase adjust value of out range"); 1417 return -EINVAL; 1418 } 1419 if (pin->prop.phase_gran && phase_adj % (s32)pin->prop.phase_gran) { 1420 NL_SET_ERR_MSG_ATTR_FMT(extack, phase_adj_attr, 1421 "phase adjust value not multiple of %u", 1422 pin->prop.phase_gran); 1423 return -EINVAL; 1424 } 1425 1426 xa_for_each(&pin->dpll_refs, i, ref) { 1427 ops = dpll_pin_ops(ref); 1428 if (!ops->phase_adjust_set || !ops->phase_adjust_get) { 1429 NL_SET_ERR_MSG(extack, "phase adjust not supported"); 1430 return -EOPNOTSUPP; 1431 } 1432 } 1433 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1434 ops = dpll_pin_ops(ref); 1435 dpll = ref->dpll; 1436 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1437 dpll, dpll_priv(dpll), &old_phase_adj, 1438 extack); 1439 if (ret) { 1440 NL_SET_ERR_MSG(extack, "unable to get old phase adjust value"); 1441 return ret; 1442 } 1443 if (phase_adj == old_phase_adj) 1444 return 0; 1445 1446 xa_for_each(&pin->dpll_refs, i, ref) { 1447 ops = dpll_pin_ops(ref); 1448 dpll = ref->dpll; 1449 ret = ops->phase_adjust_set(pin, 1450 dpll_pin_on_dpll_priv(dpll, pin), 1451 dpll, dpll_priv(dpll), phase_adj, 1452 extack); 1453 if (ret) { 1454 failed = ref; 1455 NL_SET_ERR_MSG_FMT(extack, 1456 "phase adjust set failed for dpll_id:%u", 1457 dpll->id); 1458 goto rollback; 1459 } 1460 } 1461 __dpll_pin_change_ntf(pin); 1462 1463 return 0; 1464 1465 rollback: 1466 xa_for_each(&pin->dpll_refs, i, ref) { 1467 if (ref == failed) 1468 break; 1469 ops = dpll_pin_ops(ref); 1470 dpll = ref->dpll; 1471 if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1472 dpll, dpll_priv(dpll), old_phase_adj, 1473 extack)) 1474 NL_SET_ERR_MSG(extack, "set phase adjust rollback failed"); 1475 } 1476 return ret; 1477 } 1478 1479 static int 1480 dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1481 struct netlink_ext_ack *extack) 1482 { 1483 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1484 enum dpll_pin_direction direction; 1485 enum dpll_pin_state state; 1486 struct dpll_pin_ref *ref; 1487 struct dpll_device *dpll; 1488 u32 pdpll_idx, prio; 1489 int ret; 1490 1491 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1492 dpll_pin_parent_device_nl_policy, extack); 1493 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1494 NL_SET_ERR_MSG(extack, "device parent id expected"); 1495 return -EINVAL; 1496 } 1497 pdpll_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1498 dpll = xa_load(&dpll_device_xa, pdpll_idx); 1499 if (!dpll) { 1500 NL_SET_ERR_MSG(extack, "parent device not found"); 1501 return -EINVAL; 1502 } 1503 ref = xa_load(&pin->dpll_refs, dpll->id); 1504 if (!ref) { 1505 NL_SET_ERR_MSG(extack, "pin not connected to given parent device"); 1506 return -EINVAL; 1507 } 1508 if (tb[DPLL_A_PIN_STATE]) { 1509 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1510 ret = dpll_pin_state_set(dpll, pin, state, extack); 1511 if (ret) 1512 return ret; 1513 } 1514 if (tb[DPLL_A_PIN_PRIO]) { 1515 prio = nla_get_u32(tb[DPLL_A_PIN_PRIO]); 1516 ret = dpll_pin_prio_set(dpll, pin, prio, extack); 1517 if (ret) 1518 return ret; 1519 } 1520 if (tb[DPLL_A_PIN_DIRECTION]) { 1521 direction = nla_get_u32(tb[DPLL_A_PIN_DIRECTION]); 1522 ret = dpll_pin_direction_set(pin, dpll, direction, extack); 1523 if (ret) 1524 return ret; 1525 } 1526 return 0; 1527 } 1528 1529 static int 1530 dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1531 struct netlink_ext_ack *extack) 1532 { 1533 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1534 u32 ppin_idx; 1535 int ret; 1536 1537 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1538 dpll_pin_parent_pin_nl_policy, extack); 1539 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1540 NL_SET_ERR_MSG(extack, "device parent id expected"); 1541 return -EINVAL; 1542 } 1543 ppin_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1544 1545 if (tb[DPLL_A_PIN_STATE]) { 1546 enum dpll_pin_state state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1547 1548 ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack); 1549 if (ret) 1550 return ret; 1551 } 1552 1553 return 0; 1554 } 1555 1556 static int 1557 dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info) 1558 { 1559 struct nlattr *a; 1560 int rem, ret; 1561 1562 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1563 genlmsg_len(info->genlhdr), rem) { 1564 switch (nla_type(a)) { 1565 case DPLL_A_PIN_FREQUENCY: 1566 ret = dpll_pin_freq_set(pin, a, info->extack); 1567 if (ret) 1568 return ret; 1569 break; 1570 case DPLL_A_PIN_PHASE_ADJUST: 1571 ret = dpll_pin_phase_adj_set(pin, a, info->extack); 1572 if (ret) 1573 return ret; 1574 break; 1575 case DPLL_A_PIN_PARENT_DEVICE: 1576 ret = dpll_pin_parent_device_set(pin, a, info->extack); 1577 if (ret) 1578 return ret; 1579 break; 1580 case DPLL_A_PIN_PARENT_PIN: 1581 ret = dpll_pin_parent_pin_set(pin, a, info->extack); 1582 if (ret) 1583 return ret; 1584 break; 1585 case DPLL_A_PIN_ESYNC_FREQUENCY: 1586 ret = dpll_pin_esync_set(pin, a, info->extack); 1587 if (ret) 1588 return ret; 1589 break; 1590 case DPLL_A_PIN_REFERENCE_SYNC: 1591 ret = dpll_pin_ref_sync_set(pin, a, info->extack); 1592 if (ret) 1593 return ret; 1594 break; 1595 } 1596 } 1597 1598 return 0; 1599 } 1600 1601 static struct dpll_pin * 1602 dpll_pin_find(u64 clock_id, struct nlattr *mod_name_attr, 1603 enum dpll_pin_type type, struct nlattr *board_label, 1604 struct nlattr *panel_label, struct nlattr *package_label, 1605 struct netlink_ext_ack *extack) 1606 { 1607 bool board_match, panel_match, package_match; 1608 struct dpll_pin *pin_match = NULL, *pin; 1609 const struct dpll_pin_properties *prop; 1610 bool cid_match, mod_match, type_match; 1611 unsigned long i; 1612 1613 xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) { 1614 prop = &pin->prop; 1615 cid_match = clock_id ? pin->clock_id == clock_id : true; 1616 mod_match = mod_name_attr && module_name(pin->module) ? 1617 !nla_strcmp(mod_name_attr, 1618 module_name(pin->module)) : true; 1619 type_match = type ? prop->type == type : true; 1620 board_match = board_label ? (prop->board_label ? 1621 !nla_strcmp(board_label, prop->board_label) : false) : 1622 true; 1623 panel_match = panel_label ? (prop->panel_label ? 1624 !nla_strcmp(panel_label, prop->panel_label) : false) : 1625 true; 1626 package_match = package_label ? (prop->package_label ? 1627 !nla_strcmp(package_label, prop->package_label) : 1628 false) : true; 1629 if (cid_match && mod_match && type_match && board_match && 1630 panel_match && package_match) { 1631 if (pin_match) { 1632 NL_SET_ERR_MSG(extack, "multiple matches"); 1633 return ERR_PTR(-EINVAL); 1634 } 1635 pin_match = pin; 1636 } 1637 } 1638 if (!pin_match) { 1639 NL_SET_ERR_MSG(extack, "not found"); 1640 return ERR_PTR(-ENODEV); 1641 } 1642 return pin_match; 1643 } 1644 1645 static struct dpll_pin *dpll_pin_find_from_nlattr(struct genl_info *info) 1646 { 1647 struct nlattr *attr, *mod_name_attr = NULL, *board_label_attr = NULL, 1648 *panel_label_attr = NULL, *package_label_attr = NULL; 1649 enum dpll_pin_type type = 0; 1650 u64 clock_id = 0; 1651 int rem = 0; 1652 1653 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1654 genlmsg_len(info->genlhdr), rem) { 1655 switch (nla_type(attr)) { 1656 case DPLL_A_PIN_CLOCK_ID: 1657 if (clock_id) 1658 goto duplicated_attr; 1659 clock_id = nla_get_u64(attr); 1660 break; 1661 case DPLL_A_PIN_MODULE_NAME: 1662 if (mod_name_attr) 1663 goto duplicated_attr; 1664 mod_name_attr = attr; 1665 break; 1666 case DPLL_A_PIN_TYPE: 1667 if (type) 1668 goto duplicated_attr; 1669 type = nla_get_u32(attr); 1670 break; 1671 case DPLL_A_PIN_BOARD_LABEL: 1672 if (board_label_attr) 1673 goto duplicated_attr; 1674 board_label_attr = attr; 1675 break; 1676 case DPLL_A_PIN_PANEL_LABEL: 1677 if (panel_label_attr) 1678 goto duplicated_attr; 1679 panel_label_attr = attr; 1680 break; 1681 case DPLL_A_PIN_PACKAGE_LABEL: 1682 if (package_label_attr) 1683 goto duplicated_attr; 1684 package_label_attr = attr; 1685 break; 1686 default: 1687 break; 1688 } 1689 } 1690 if (!(clock_id || mod_name_attr || board_label_attr || 1691 panel_label_attr || package_label_attr)) { 1692 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1693 return ERR_PTR(-EINVAL); 1694 } 1695 return dpll_pin_find(clock_id, mod_name_attr, type, board_label_attr, 1696 panel_label_attr, package_label_attr, 1697 info->extack); 1698 duplicated_attr: 1699 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1700 return ERR_PTR(-EINVAL); 1701 } 1702 1703 int dpll_nl_pin_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1704 { 1705 struct dpll_pin *pin; 1706 struct sk_buff *msg; 1707 struct nlattr *hdr; 1708 int ret; 1709 1710 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1711 if (!msg) 1712 return -ENOMEM; 1713 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1714 DPLL_CMD_PIN_ID_GET); 1715 if (!hdr) { 1716 nlmsg_free(msg); 1717 return -EMSGSIZE; 1718 } 1719 pin = dpll_pin_find_from_nlattr(info); 1720 if (IS_ERR(pin)) { 1721 nlmsg_free(msg); 1722 return PTR_ERR(pin); 1723 } 1724 if (!dpll_pin_available(pin)) { 1725 nlmsg_free(msg); 1726 return -ENODEV; 1727 } 1728 ret = dpll_msg_add_pin_handle(msg, pin); 1729 if (ret) { 1730 nlmsg_free(msg); 1731 return ret; 1732 } 1733 genlmsg_end(msg, hdr); 1734 1735 return genlmsg_reply(msg, info); 1736 } 1737 1738 int dpll_nl_pin_get_doit(struct sk_buff *skb, struct genl_info *info) 1739 { 1740 struct dpll_pin *pin = info->user_ptr[0]; 1741 struct sk_buff *msg; 1742 struct nlattr *hdr; 1743 int ret; 1744 1745 if (!pin) 1746 return -ENODEV; 1747 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1748 if (!msg) 1749 return -ENOMEM; 1750 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1751 DPLL_CMD_PIN_GET); 1752 if (!hdr) { 1753 nlmsg_free(msg); 1754 return -EMSGSIZE; 1755 } 1756 ret = dpll_cmd_pin_get_one(msg, pin, info->extack); 1757 if (ret) { 1758 nlmsg_free(msg); 1759 return ret; 1760 } 1761 genlmsg_end(msg, hdr); 1762 1763 return genlmsg_reply(msg, info); 1764 } 1765 1766 int dpll_nl_pin_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1767 { 1768 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1769 struct dpll_pin *pin; 1770 struct nlattr *hdr; 1771 unsigned long i; 1772 int ret = 0; 1773 1774 mutex_lock(&dpll_lock); 1775 xa_for_each_marked_start(&dpll_pin_xa, i, pin, DPLL_REGISTERED, 1776 ctx->idx) { 1777 if (!dpll_pin_available(pin)) 1778 continue; 1779 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1780 cb->nlh->nlmsg_seq, 1781 &dpll_nl_family, NLM_F_MULTI, 1782 DPLL_CMD_PIN_GET); 1783 if (!hdr) { 1784 ret = -EMSGSIZE; 1785 break; 1786 } 1787 ret = dpll_cmd_pin_get_one(skb, pin, cb->extack); 1788 if (ret) { 1789 genlmsg_cancel(skb, hdr); 1790 break; 1791 } 1792 genlmsg_end(skb, hdr); 1793 } 1794 mutex_unlock(&dpll_lock); 1795 1796 if (ret == -EMSGSIZE) { 1797 ctx->idx = i; 1798 return skb->len; 1799 } 1800 return ret; 1801 } 1802 1803 int dpll_nl_pin_set_doit(struct sk_buff *skb, struct genl_info *info) 1804 { 1805 struct dpll_pin *pin = info->user_ptr[0]; 1806 1807 return dpll_pin_set_from_nlattr(pin, info); 1808 } 1809 1810 static struct dpll_device * 1811 dpll_device_find(u64 clock_id, struct nlattr *mod_name_attr, 1812 enum dpll_type type, struct netlink_ext_ack *extack) 1813 { 1814 struct dpll_device *dpll_match = NULL, *dpll; 1815 bool cid_match, mod_match, type_match; 1816 unsigned long i; 1817 1818 xa_for_each_marked(&dpll_device_xa, i, dpll, DPLL_REGISTERED) { 1819 cid_match = clock_id ? dpll->clock_id == clock_id : true; 1820 mod_match = mod_name_attr ? (module_name(dpll->module) ? 1821 !nla_strcmp(mod_name_attr, 1822 module_name(dpll->module)) : false) : true; 1823 type_match = type ? dpll->type == type : true; 1824 if (cid_match && mod_match && type_match) { 1825 if (dpll_match) { 1826 NL_SET_ERR_MSG(extack, "multiple matches"); 1827 return ERR_PTR(-EINVAL); 1828 } 1829 dpll_match = dpll; 1830 } 1831 } 1832 if (!dpll_match) { 1833 NL_SET_ERR_MSG(extack, "not found"); 1834 return ERR_PTR(-ENODEV); 1835 } 1836 1837 return dpll_match; 1838 } 1839 1840 static struct dpll_device * 1841 dpll_device_find_from_nlattr(struct genl_info *info) 1842 { 1843 struct nlattr *attr, *mod_name_attr = NULL; 1844 enum dpll_type type = 0; 1845 u64 clock_id = 0; 1846 int rem = 0; 1847 1848 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1849 genlmsg_len(info->genlhdr), rem) { 1850 switch (nla_type(attr)) { 1851 case DPLL_A_CLOCK_ID: 1852 if (clock_id) 1853 goto duplicated_attr; 1854 clock_id = nla_get_u64(attr); 1855 break; 1856 case DPLL_A_MODULE_NAME: 1857 if (mod_name_attr) 1858 goto duplicated_attr; 1859 mod_name_attr = attr; 1860 break; 1861 case DPLL_A_TYPE: 1862 if (type) 1863 goto duplicated_attr; 1864 type = nla_get_u32(attr); 1865 break; 1866 default: 1867 break; 1868 } 1869 } 1870 if (!clock_id && !mod_name_attr && !type) { 1871 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1872 return ERR_PTR(-EINVAL); 1873 } 1874 return dpll_device_find(clock_id, mod_name_attr, type, info->extack); 1875 duplicated_attr: 1876 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1877 return ERR_PTR(-EINVAL); 1878 } 1879 1880 int dpll_nl_device_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1881 { 1882 struct dpll_device *dpll; 1883 struct sk_buff *msg; 1884 struct nlattr *hdr; 1885 int ret; 1886 1887 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1888 if (!msg) 1889 return -ENOMEM; 1890 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1891 DPLL_CMD_DEVICE_ID_GET); 1892 if (!hdr) { 1893 nlmsg_free(msg); 1894 return -EMSGSIZE; 1895 } 1896 1897 dpll = dpll_device_find_from_nlattr(info); 1898 if (IS_ERR(dpll)) { 1899 nlmsg_free(msg); 1900 return PTR_ERR(dpll); 1901 } 1902 ret = dpll_msg_add_dev_handle(msg, dpll); 1903 if (ret) { 1904 nlmsg_free(msg); 1905 return ret; 1906 } 1907 genlmsg_end(msg, hdr); 1908 1909 return genlmsg_reply(msg, info); 1910 } 1911 1912 int dpll_nl_device_get_doit(struct sk_buff *skb, struct genl_info *info) 1913 { 1914 struct dpll_device *dpll = info->user_ptr[0]; 1915 struct sk_buff *msg; 1916 struct nlattr *hdr; 1917 int ret; 1918 1919 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1920 if (!msg) 1921 return -ENOMEM; 1922 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1923 DPLL_CMD_DEVICE_GET); 1924 if (!hdr) { 1925 nlmsg_free(msg); 1926 return -EMSGSIZE; 1927 } 1928 1929 ret = dpll_device_get_one(dpll, msg, info->extack); 1930 if (ret) { 1931 nlmsg_free(msg); 1932 return ret; 1933 } 1934 genlmsg_end(msg, hdr); 1935 1936 return genlmsg_reply(msg, info); 1937 } 1938 1939 static int 1940 dpll_set_from_nlattr(struct dpll_device *dpll, struct genl_info *info) 1941 { 1942 struct nlattr *a; 1943 int rem, ret; 1944 1945 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1946 genlmsg_len(info->genlhdr), rem) { 1947 switch (nla_type(a)) { 1948 case DPLL_A_MODE: 1949 ret = dpll_mode_set(dpll, a, info->extack); 1950 if (ret) 1951 return ret; 1952 break; 1953 case DPLL_A_PHASE_OFFSET_MONITOR: 1954 ret = dpll_phase_offset_monitor_set(dpll, a, 1955 info->extack); 1956 if (ret) 1957 return ret; 1958 break; 1959 case DPLL_A_PHASE_OFFSET_AVG_FACTOR: 1960 ret = dpll_phase_offset_avg_factor_set(dpll, a, 1961 info->extack); 1962 if (ret) 1963 return ret; 1964 break; 1965 case DPLL_A_FREQUENCY_MONITOR: 1966 ret = dpll_freq_monitor_set(dpll, a, 1967 info->extack); 1968 if (ret) 1969 return ret; 1970 break; 1971 } 1972 } 1973 1974 return 0; 1975 } 1976 1977 int dpll_nl_device_set_doit(struct sk_buff *skb, struct genl_info *info) 1978 { 1979 struct dpll_device *dpll = info->user_ptr[0]; 1980 1981 return dpll_set_from_nlattr(dpll, info); 1982 } 1983 1984 int dpll_nl_device_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1985 { 1986 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1987 struct dpll_device *dpll; 1988 struct nlattr *hdr; 1989 unsigned long i; 1990 int ret = 0; 1991 1992 mutex_lock(&dpll_lock); 1993 xa_for_each_marked_start(&dpll_device_xa, i, dpll, DPLL_REGISTERED, 1994 ctx->idx) { 1995 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1996 cb->nlh->nlmsg_seq, &dpll_nl_family, 1997 NLM_F_MULTI, DPLL_CMD_DEVICE_GET); 1998 if (!hdr) { 1999 ret = -EMSGSIZE; 2000 break; 2001 } 2002 ret = dpll_device_get_one(dpll, skb, cb->extack); 2003 if (ret) { 2004 genlmsg_cancel(skb, hdr); 2005 break; 2006 } 2007 genlmsg_end(skb, hdr); 2008 } 2009 mutex_unlock(&dpll_lock); 2010 2011 if (ret == -EMSGSIZE) { 2012 ctx->idx = i; 2013 return skb->len; 2014 } 2015 return ret; 2016 } 2017 2018 int dpll_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2019 struct genl_info *info) 2020 { 2021 u32 id; 2022 2023 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_ID)) 2024 return -EINVAL; 2025 2026 mutex_lock(&dpll_lock); 2027 id = nla_get_u32(info->attrs[DPLL_A_ID]); 2028 info->user_ptr[0] = dpll_device_get_by_id(id); 2029 if (!info->user_ptr[0]) { 2030 NL_SET_ERR_MSG(info->extack, "device not found"); 2031 goto unlock; 2032 } 2033 return 0; 2034 unlock: 2035 mutex_unlock(&dpll_lock); 2036 return -ENODEV; 2037 } 2038 2039 void dpll_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2040 struct genl_info *info) 2041 { 2042 mutex_unlock(&dpll_lock); 2043 } 2044 2045 int 2046 dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2047 struct genl_info *info) 2048 { 2049 mutex_lock(&dpll_lock); 2050 2051 return 0; 2052 } 2053 2054 void 2055 dpll_unlock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2056 struct genl_info *info) 2057 { 2058 mutex_unlock(&dpll_lock); 2059 } 2060 2061 int dpll_pin_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2062 struct genl_info *info) 2063 { 2064 int ret; 2065 2066 mutex_lock(&dpll_lock); 2067 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_PIN_ID)) { 2068 ret = -EINVAL; 2069 goto unlock_dev; 2070 } 2071 info->user_ptr[0] = xa_load(&dpll_pin_xa, 2072 nla_get_u32(info->attrs[DPLL_A_PIN_ID])); 2073 if (!info->user_ptr[0] || 2074 !dpll_pin_available(info->user_ptr[0])) { 2075 NL_SET_ERR_MSG(info->extack, "pin not found"); 2076 ret = -ENODEV; 2077 goto unlock_dev; 2078 } 2079 2080 return 0; 2081 2082 unlock_dev: 2083 mutex_unlock(&dpll_lock); 2084 return ret; 2085 } 2086 2087 void dpll_pin_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2088 struct genl_info *info) 2089 { 2090 mutex_unlock(&dpll_lock); 2091 } 2092