1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Generic netlink for DPLL management framework 4 * 5 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 6 * Copyright (c) 2023 Intel and affiliates 7 * 8 */ 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/netdevice.h> 12 #include <net/genetlink.h> 13 #include "dpll_core.h" 14 #include "dpll_netlink.h" 15 #include "dpll_nl.h" 16 #include <uapi/linux/dpll.h> 17 18 #define ASSERT_NOT_NULL(ptr) (WARN_ON(!ptr)) 19 20 #define xa_for_each_marked_start(xa, index, entry, filter, start) \ 21 for (index = start, entry = xa_find(xa, &index, ULONG_MAX, filter); \ 22 entry; entry = xa_find_after(xa, &index, ULONG_MAX, filter)) 23 24 struct dpll_dump_ctx { 25 unsigned long idx; 26 }; 27 28 static struct dpll_dump_ctx *dpll_dump_context(struct netlink_callback *cb) 29 { 30 return (struct dpll_dump_ctx *)cb->ctx; 31 } 32 33 static int 34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) 35 { 36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) 37 return -EMSGSIZE; 38 39 return 0; 40 } 41 42 static int 43 dpll_msg_add_dev_parent_handle(struct sk_buff *msg, u32 id) 44 { 45 if (nla_put_u32(msg, DPLL_A_PIN_PARENT_ID, id)) 46 return -EMSGSIZE; 47 48 return 0; 49 } 50 51 static bool dpll_pin_available(struct dpll_pin *pin) 52 { 53 struct dpll_pin_ref *par_ref; 54 unsigned long i; 55 56 if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) 57 return false; 58 xa_for_each(&pin->parent_refs, i, par_ref) 59 if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, 60 DPLL_REGISTERED)) 61 return true; 62 xa_for_each(&pin->dpll_refs, i, par_ref) 63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, 64 DPLL_REGISTERED)) 65 return true; 66 return false; 67 } 68 69 /** 70 * dpll_msg_add_pin_handle - attach pin handle attribute to a given message 71 * @msg: pointer to sk_buff message to attach a pin handle 72 * @pin: pin pointer 73 * 74 * Return: 75 * * 0 - success 76 * * -EMSGSIZE - no space in message to attach pin handle 77 */ 78 static int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin) 79 { 80 if (!pin) 81 return 0; 82 if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id)) 83 return -EMSGSIZE; 84 return 0; 85 } 86 87 static struct dpll_pin *dpll_netdev_pin(const struct net_device *dev) 88 { 89 return rcu_dereference_rtnl(dev->dpll_pin); 90 } 91 92 /** 93 * dpll_netdev_pin_handle_size - get size of pin handle attribute of a netdev 94 * @dev: netdev from which to get the pin 95 * 96 * Return: byte size of pin handle attribute, or 0 if @dev has no pin. 97 */ 98 size_t dpll_netdev_pin_handle_size(const struct net_device *dev) 99 { 100 return dpll_netdev_pin(dev) ? nla_total_size(4) : 0; /* DPLL_A_PIN_ID */ 101 } 102 103 int dpll_netdev_add_pin_handle(struct sk_buff *msg, 104 const struct net_device *dev) 105 { 106 return dpll_msg_add_pin_handle(msg, dpll_netdev_pin(dev)); 107 } 108 109 static int 110 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, 111 struct netlink_ext_ack *extack) 112 { 113 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 114 enum dpll_mode mode; 115 int ret; 116 117 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 118 if (ret) 119 return ret; 120 if (nla_put_u32(msg, DPLL_A_MODE, mode)) 121 return -EMSGSIZE; 122 123 return 0; 124 } 125 126 static int 127 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, 128 struct netlink_ext_ack *extack) 129 { 130 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 131 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 132 enum dpll_mode mode; 133 int ret; 134 135 if (ops->supported_modes_get) { 136 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, 137 extack); 138 if (ret) 139 return ret; 140 } else { 141 /* If the supported modes are not reported by the driver, the 142 * only supported mode is the one obtained by mode_get(). 143 */ 144 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 145 if (ret) 146 return ret; 147 148 __set_bit(mode, modes); 149 } 150 151 for_each_set_bit(mode, modes, DPLL_MODE_MAX + 1) 152 if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode)) 153 return -EMSGSIZE; 154 155 return 0; 156 } 157 158 static int 159 dpll_msg_add_phase_offset_monitor(struct sk_buff *msg, struct dpll_device *dpll, 160 struct netlink_ext_ack *extack) 161 { 162 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 163 enum dpll_feature_state state; 164 int ret; 165 166 if (ops->phase_offset_monitor_set && ops->phase_offset_monitor_get) { 167 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), 168 &state, extack); 169 if (ret) 170 return ret; 171 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_MONITOR, state)) 172 return -EMSGSIZE; 173 } 174 175 return 0; 176 } 177 178 static int 179 dpll_msg_add_phase_offset_avg_factor(struct sk_buff *msg, 180 struct dpll_device *dpll, 181 struct netlink_ext_ack *extack) 182 { 183 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 184 u32 factor; 185 int ret; 186 187 if (ops->phase_offset_avg_factor_get) { 188 ret = ops->phase_offset_avg_factor_get(dpll, dpll_priv(dpll), 189 &factor, extack); 190 if (ret) 191 return ret; 192 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_AVG_FACTOR, factor)) 193 return -EMSGSIZE; 194 } 195 196 return 0; 197 } 198 199 static int 200 dpll_msg_add_lock_status(struct sk_buff *msg, struct dpll_device *dpll, 201 struct netlink_ext_ack *extack) 202 { 203 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 204 enum dpll_lock_status_error status_error = 0; 205 enum dpll_lock_status status; 206 int ret; 207 208 ret = ops->lock_status_get(dpll, dpll_priv(dpll), &status, 209 &status_error, extack); 210 if (ret) 211 return ret; 212 if (nla_put_u32(msg, DPLL_A_LOCK_STATUS, status)) 213 return -EMSGSIZE; 214 if (status_error && 215 (status == DPLL_LOCK_STATUS_UNLOCKED || 216 status == DPLL_LOCK_STATUS_HOLDOVER) && 217 nla_put_u32(msg, DPLL_A_LOCK_STATUS_ERROR, status_error)) 218 return -EMSGSIZE; 219 220 return 0; 221 } 222 223 static int 224 dpll_msg_add_temp(struct sk_buff *msg, struct dpll_device *dpll, 225 struct netlink_ext_ack *extack) 226 { 227 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 228 s32 temp; 229 int ret; 230 231 if (!ops->temp_get) 232 return 0; 233 ret = ops->temp_get(dpll, dpll_priv(dpll), &temp, extack); 234 if (ret) 235 return ret; 236 if (nla_put_s32(msg, DPLL_A_TEMP, temp)) 237 return -EMSGSIZE; 238 239 return 0; 240 } 241 242 static int 243 dpll_msg_add_clock_quality_level(struct sk_buff *msg, struct dpll_device *dpll, 244 struct netlink_ext_ack *extack) 245 { 246 DECLARE_BITMAP(qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) = { 0 }; 247 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 248 enum dpll_clock_quality_level ql; 249 int ret; 250 251 if (!ops->clock_quality_level_get) 252 return 0; 253 ret = ops->clock_quality_level_get(dpll, dpll_priv(dpll), qls, extack); 254 if (ret) 255 return ret; 256 for_each_set_bit(ql, qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) 257 if (nla_put_u32(msg, DPLL_A_CLOCK_QUALITY_LEVEL, ql)) 258 return -EMSGSIZE; 259 260 return 0; 261 } 262 263 static int 264 dpll_msg_add_pin_prio(struct sk_buff *msg, struct dpll_pin *pin, 265 struct dpll_pin_ref *ref, 266 struct netlink_ext_ack *extack) 267 { 268 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 269 struct dpll_device *dpll = ref->dpll; 270 u32 prio; 271 int ret; 272 273 if (!ops->prio_get) 274 return 0; 275 ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 276 dpll_priv(dpll), &prio, extack); 277 if (ret) 278 return ret; 279 if (nla_put_u32(msg, DPLL_A_PIN_PRIO, prio)) 280 return -EMSGSIZE; 281 282 return 0; 283 } 284 285 static int 286 dpll_msg_add_pin_on_dpll_state(struct sk_buff *msg, struct dpll_pin *pin, 287 struct dpll_pin_ref *ref, 288 struct netlink_ext_ack *extack) 289 { 290 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 291 struct dpll_device *dpll = ref->dpll; 292 enum dpll_pin_state state; 293 int ret; 294 295 if (!ops->state_on_dpll_get) 296 return 0; 297 ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 298 dpll, dpll_priv(dpll), &state, extack); 299 if (ret) 300 return ret; 301 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) 302 return -EMSGSIZE; 303 304 return 0; 305 } 306 307 static int 308 dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin, 309 struct dpll_pin_ref *ref, 310 struct netlink_ext_ack *extack) 311 { 312 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 313 struct dpll_device *dpll = ref->dpll; 314 enum dpll_pin_direction direction; 315 int ret; 316 317 ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 318 dpll_priv(dpll), &direction, extack); 319 if (ret) 320 return ret; 321 if (nla_put_u32(msg, DPLL_A_PIN_DIRECTION, direction)) 322 return -EMSGSIZE; 323 324 return 0; 325 } 326 327 static int 328 dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin, 329 struct dpll_pin_ref *ref, 330 struct netlink_ext_ack *extack) 331 { 332 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 333 struct dpll_device *dpll = ref->dpll; 334 s32 phase_adjust; 335 int ret; 336 337 if (!ops->phase_adjust_get) 338 return 0; 339 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 340 dpll, dpll_priv(dpll), 341 &phase_adjust, extack); 342 if (ret) 343 return ret; 344 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust)) 345 return -EMSGSIZE; 346 347 return 0; 348 } 349 350 static int 351 dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin, 352 struct dpll_pin_ref *ref, 353 struct netlink_ext_ack *extack) 354 { 355 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 356 struct dpll_device *dpll = ref->dpll; 357 s64 phase_offset; 358 int ret; 359 360 if (!ops->phase_offset_get) 361 return 0; 362 ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 363 dpll, dpll_priv(dpll), &phase_offset, 364 extack); 365 if (ret) 366 return ret; 367 if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset), 368 &phase_offset, DPLL_A_PIN_PAD)) 369 return -EMSGSIZE; 370 371 return 0; 372 } 373 374 static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin, 375 struct dpll_pin_ref *ref, 376 struct netlink_ext_ack *extack) 377 { 378 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 379 struct dpll_device *dpll = ref->dpll; 380 s64 ffo; 381 int ret; 382 383 if (!ops->ffo_get) 384 return 0; 385 ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 386 dpll, dpll_priv(dpll), &ffo, extack); 387 if (ret) { 388 if (ret == -ENODATA) 389 return 0; 390 return ret; 391 } 392 return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, ffo); 393 } 394 395 static int 396 dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin, 397 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 398 { 399 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 400 struct dpll_device *dpll = ref->dpll; 401 struct nlattr *nest; 402 int fs, ret; 403 u64 freq; 404 405 if (!ops->frequency_get) 406 return 0; 407 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 408 dpll_priv(dpll), &freq, extack); 409 if (ret) 410 return ret; 411 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY, sizeof(freq), &freq, 412 DPLL_A_PIN_PAD)) 413 return -EMSGSIZE; 414 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) { 415 nest = nla_nest_start(msg, DPLL_A_PIN_FREQUENCY_SUPPORTED); 416 if (!nest) 417 return -EMSGSIZE; 418 freq = pin->prop.freq_supported[fs].min; 419 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, sizeof(freq), 420 &freq, DPLL_A_PIN_PAD)) { 421 nla_nest_cancel(msg, nest); 422 return -EMSGSIZE; 423 } 424 freq = pin->prop.freq_supported[fs].max; 425 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, sizeof(freq), 426 &freq, DPLL_A_PIN_PAD)) { 427 nla_nest_cancel(msg, nest); 428 return -EMSGSIZE; 429 } 430 nla_nest_end(msg, nest); 431 } 432 433 return 0; 434 } 435 436 static int 437 dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpll_pin *pin, 438 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 439 { 440 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 441 struct dpll_device *dpll = ref->dpll; 442 struct dpll_pin_esync esync; 443 struct nlattr *nest; 444 int ret, i; 445 446 if (!ops->esync_get) 447 return 0; 448 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 449 dpll_priv(dpll), &esync, extack); 450 if (ret == -EOPNOTSUPP) 451 return 0; 452 else if (ret) 453 return ret; 454 if (nla_put_64bit(msg, DPLL_A_PIN_ESYNC_FREQUENCY, sizeof(esync.freq), 455 &esync.freq, DPLL_A_PIN_PAD)) 456 return -EMSGSIZE; 457 if (nla_put_u32(msg, DPLL_A_PIN_ESYNC_PULSE, esync.pulse)) 458 return -EMSGSIZE; 459 for (i = 0; i < esync.range_num; i++) { 460 nest = nla_nest_start(msg, 461 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED); 462 if (!nest) 463 return -EMSGSIZE; 464 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, 465 sizeof(esync.range[i].min), 466 &esync.range[i].min, DPLL_A_PIN_PAD)) 467 goto nest_cancel; 468 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, 469 sizeof(esync.range[i].max), 470 &esync.range[i].max, DPLL_A_PIN_PAD)) 471 goto nest_cancel; 472 nla_nest_end(msg, nest); 473 } 474 return 0; 475 476 nest_cancel: 477 nla_nest_cancel(msg, nest); 478 return -EMSGSIZE; 479 } 480 481 static int 482 dpll_msg_add_pin_ref_sync(struct sk_buff *msg, struct dpll_pin *pin, 483 struct dpll_pin_ref *ref, 484 struct netlink_ext_ack *extack) 485 { 486 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 487 struct dpll_device *dpll = ref->dpll; 488 void *pin_priv, *ref_sync_pin_priv; 489 struct dpll_pin *ref_sync_pin; 490 enum dpll_pin_state state; 491 struct nlattr *nest; 492 unsigned long index; 493 int ret; 494 495 pin_priv = dpll_pin_on_dpll_priv(dpll, pin); 496 xa_for_each(&pin->ref_sync_pins, index, ref_sync_pin) { 497 if (!dpll_pin_available(ref_sync_pin)) 498 continue; 499 ref_sync_pin_priv = dpll_pin_on_dpll_priv(dpll, ref_sync_pin); 500 if (WARN_ON(!ops->ref_sync_get)) 501 return -EOPNOTSUPP; 502 ret = ops->ref_sync_get(pin, pin_priv, ref_sync_pin, 503 ref_sync_pin_priv, &state, extack); 504 if (ret) 505 return ret; 506 nest = nla_nest_start(msg, DPLL_A_PIN_REFERENCE_SYNC); 507 if (!nest) 508 return -EMSGSIZE; 509 if (nla_put_s32(msg, DPLL_A_PIN_ID, ref_sync_pin->id)) 510 goto nest_cancel; 511 if (nla_put_s32(msg, DPLL_A_PIN_STATE, state)) 512 goto nest_cancel; 513 nla_nest_end(msg, nest); 514 } 515 return 0; 516 517 nest_cancel: 518 nla_nest_cancel(msg, nest); 519 return -EMSGSIZE; 520 } 521 522 static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) 523 { 524 int fs; 525 526 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) 527 if (freq >= pin->prop.freq_supported[fs].min && 528 freq <= pin->prop.freq_supported[fs].max) 529 return true; 530 return false; 531 } 532 533 static int 534 dpll_msg_add_pin_parents(struct sk_buff *msg, struct dpll_pin *pin, 535 struct dpll_pin_ref *dpll_ref, 536 struct netlink_ext_ack *extack) 537 { 538 enum dpll_pin_state state; 539 struct dpll_pin_ref *ref; 540 struct dpll_pin *ppin; 541 struct nlattr *nest; 542 unsigned long index; 543 int ret; 544 545 xa_for_each(&pin->parent_refs, index, ref) { 546 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 547 void *parent_priv; 548 549 ppin = ref->pin; 550 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, ppin); 551 ret = ops->state_on_pin_get(pin, 552 dpll_pin_on_pin_priv(ppin, pin), 553 ppin, parent_priv, &state, extack); 554 if (ret) 555 return ret; 556 nest = nla_nest_start(msg, DPLL_A_PIN_PARENT_PIN); 557 if (!nest) 558 return -EMSGSIZE; 559 ret = dpll_msg_add_dev_parent_handle(msg, ppin->id); 560 if (ret) 561 goto nest_cancel; 562 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) { 563 ret = -EMSGSIZE; 564 goto nest_cancel; 565 } 566 nla_nest_end(msg, nest); 567 } 568 569 return 0; 570 571 nest_cancel: 572 nla_nest_cancel(msg, nest); 573 return ret; 574 } 575 576 static int 577 dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin, 578 struct netlink_ext_ack *extack) 579 { 580 struct dpll_pin_ref *ref; 581 struct nlattr *attr; 582 unsigned long index; 583 int ret; 584 585 xa_for_each(&pin->dpll_refs, index, ref) { 586 attr = nla_nest_start(msg, DPLL_A_PIN_PARENT_DEVICE); 587 if (!attr) 588 return -EMSGSIZE; 589 ret = dpll_msg_add_dev_parent_handle(msg, ref->dpll->id); 590 if (ret) 591 goto nest_cancel; 592 ret = dpll_msg_add_pin_on_dpll_state(msg, pin, ref, extack); 593 if (ret) 594 goto nest_cancel; 595 ret = dpll_msg_add_pin_prio(msg, pin, ref, extack); 596 if (ret) 597 goto nest_cancel; 598 ret = dpll_msg_add_pin_direction(msg, pin, ref, extack); 599 if (ret) 600 goto nest_cancel; 601 ret = dpll_msg_add_phase_offset(msg, pin, ref, extack); 602 if (ret) 603 goto nest_cancel; 604 nla_nest_end(msg, attr); 605 } 606 607 return 0; 608 609 nest_cancel: 610 nla_nest_end(msg, attr); 611 return ret; 612 } 613 614 static int 615 dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, 616 struct netlink_ext_ack *extack) 617 { 618 const struct dpll_pin_properties *prop = &pin->prop; 619 struct dpll_pin_ref *ref; 620 int ret; 621 622 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 623 ASSERT_NOT_NULL(ref); 624 625 ret = dpll_msg_add_pin_handle(msg, pin); 626 if (ret) 627 return ret; 628 if (nla_put_string(msg, DPLL_A_PIN_MODULE_NAME, 629 module_name(pin->module))) 630 return -EMSGSIZE; 631 if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id), 632 &pin->clock_id, DPLL_A_PIN_PAD)) 633 return -EMSGSIZE; 634 if (prop->board_label && 635 nla_put_string(msg, DPLL_A_PIN_BOARD_LABEL, prop->board_label)) 636 return -EMSGSIZE; 637 if (prop->panel_label && 638 nla_put_string(msg, DPLL_A_PIN_PANEL_LABEL, prop->panel_label)) 639 return -EMSGSIZE; 640 if (prop->package_label && 641 nla_put_string(msg, DPLL_A_PIN_PACKAGE_LABEL, 642 prop->package_label)) 643 return -EMSGSIZE; 644 if (nla_put_u32(msg, DPLL_A_PIN_TYPE, prop->type)) 645 return -EMSGSIZE; 646 if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities)) 647 return -EMSGSIZE; 648 ret = dpll_msg_add_pin_freq(msg, pin, ref, extack); 649 if (ret) 650 return ret; 651 if (prop->phase_gran && 652 nla_put_u32(msg, DPLL_A_PIN_PHASE_ADJUST_GRAN, 653 prop->phase_gran)) 654 return -EMSGSIZE; 655 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN, 656 prop->phase_range.min)) 657 return -EMSGSIZE; 658 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX, 659 prop->phase_range.max)) 660 return -EMSGSIZE; 661 ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack); 662 if (ret) 663 return ret; 664 ret = dpll_msg_add_ffo(msg, pin, ref, extack); 665 if (ret) 666 return ret; 667 ret = dpll_msg_add_pin_esync(msg, pin, ref, extack); 668 if (ret) 669 return ret; 670 if (!xa_empty(&pin->ref_sync_pins)) 671 ret = dpll_msg_add_pin_ref_sync(msg, pin, ref, extack); 672 if (ret) 673 return ret; 674 if (xa_empty(&pin->parent_refs)) 675 ret = dpll_msg_add_pin_dplls(msg, pin, extack); 676 else 677 ret = dpll_msg_add_pin_parents(msg, pin, ref, extack); 678 679 return ret; 680 } 681 682 static int 683 dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg, 684 struct netlink_ext_ack *extack) 685 { 686 int ret; 687 688 ret = dpll_msg_add_dev_handle(msg, dpll); 689 if (ret) 690 return ret; 691 if (nla_put_string(msg, DPLL_A_MODULE_NAME, module_name(dpll->module))) 692 return -EMSGSIZE; 693 if (nla_put_64bit(msg, DPLL_A_CLOCK_ID, sizeof(dpll->clock_id), 694 &dpll->clock_id, DPLL_A_PAD)) 695 return -EMSGSIZE; 696 ret = dpll_msg_add_temp(msg, dpll, extack); 697 if (ret) 698 return ret; 699 ret = dpll_msg_add_lock_status(msg, dpll, extack); 700 if (ret) 701 return ret; 702 ret = dpll_msg_add_clock_quality_level(msg, dpll, extack); 703 if (ret) 704 return ret; 705 ret = dpll_msg_add_mode(msg, dpll, extack); 706 if (ret) 707 return ret; 708 ret = dpll_msg_add_mode_supported(msg, dpll, extack); 709 if (ret) 710 return ret; 711 if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type)) 712 return -EMSGSIZE; 713 ret = dpll_msg_add_phase_offset_monitor(msg, dpll, extack); 714 if (ret) 715 return ret; 716 ret = dpll_msg_add_phase_offset_avg_factor(msg, dpll, extack); 717 if (ret) 718 return ret; 719 720 return 0; 721 } 722 723 static int 724 dpll_device_event_send(enum dpll_cmd event, struct dpll_device *dpll) 725 { 726 struct sk_buff *msg; 727 int ret = -ENOMEM; 728 void *hdr; 729 730 if (WARN_ON(!xa_get_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED))) 731 return -ENODEV; 732 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 733 if (!msg) 734 return -ENOMEM; 735 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 736 if (!hdr) 737 goto err_free_msg; 738 ret = dpll_device_get_one(dpll, msg, NULL); 739 if (ret) 740 goto err_cancel_msg; 741 genlmsg_end(msg, hdr); 742 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 743 744 return 0; 745 746 err_cancel_msg: 747 genlmsg_cancel(msg, hdr); 748 err_free_msg: 749 nlmsg_free(msg); 750 751 return ret; 752 } 753 754 int dpll_device_create_ntf(struct dpll_device *dpll) 755 { 756 return dpll_device_event_send(DPLL_CMD_DEVICE_CREATE_NTF, dpll); 757 } 758 759 int dpll_device_delete_ntf(struct dpll_device *dpll) 760 { 761 return dpll_device_event_send(DPLL_CMD_DEVICE_DELETE_NTF, dpll); 762 } 763 764 static int 765 __dpll_device_change_ntf(struct dpll_device *dpll) 766 { 767 return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); 768 } 769 770 /** 771 * dpll_device_change_ntf - notify that the dpll device has been changed 772 * @dpll: registered dpll pointer 773 * 774 * Context: acquires and holds a dpll_lock. 775 * Return: 0 if succeeds, error code otherwise. 776 */ 777 int dpll_device_change_ntf(struct dpll_device *dpll) 778 { 779 int ret; 780 781 mutex_lock(&dpll_lock); 782 ret = __dpll_device_change_ntf(dpll); 783 mutex_unlock(&dpll_lock); 784 785 return ret; 786 } 787 EXPORT_SYMBOL_GPL(dpll_device_change_ntf); 788 789 static int 790 dpll_pin_event_send(enum dpll_cmd event, struct dpll_pin *pin) 791 { 792 struct sk_buff *msg; 793 int ret = -ENOMEM; 794 void *hdr; 795 796 if (!dpll_pin_available(pin)) 797 return -ENODEV; 798 799 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 800 if (!msg) 801 return -ENOMEM; 802 803 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 804 if (!hdr) 805 goto err_free_msg; 806 ret = dpll_cmd_pin_get_one(msg, pin, NULL); 807 if (ret) 808 goto err_cancel_msg; 809 genlmsg_end(msg, hdr); 810 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 811 812 return 0; 813 814 err_cancel_msg: 815 genlmsg_cancel(msg, hdr); 816 err_free_msg: 817 nlmsg_free(msg); 818 819 return ret; 820 } 821 822 int dpll_pin_create_ntf(struct dpll_pin *pin) 823 { 824 return dpll_pin_event_send(DPLL_CMD_PIN_CREATE_NTF, pin); 825 } 826 827 int dpll_pin_delete_ntf(struct dpll_pin *pin) 828 { 829 return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); 830 } 831 832 int __dpll_pin_change_ntf(struct dpll_pin *pin) 833 { 834 return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); 835 } 836 837 /** 838 * dpll_pin_change_ntf - notify that the pin has been changed 839 * @pin: registered pin pointer 840 * 841 * Context: acquires and holds a dpll_lock. 842 * Return: 0 if succeeds, error code otherwise. 843 */ 844 int dpll_pin_change_ntf(struct dpll_pin *pin) 845 { 846 int ret; 847 848 mutex_lock(&dpll_lock); 849 ret = __dpll_pin_change_ntf(pin); 850 mutex_unlock(&dpll_lock); 851 852 return ret; 853 } 854 EXPORT_SYMBOL_GPL(dpll_pin_change_ntf); 855 856 static int 857 dpll_mode_set(struct dpll_device *dpll, struct nlattr *a, 858 struct netlink_ext_ack *extack) 859 { 860 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 861 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 862 enum dpll_mode mode = nla_get_u32(a), old_mode; 863 int ret; 864 865 if (!(ops->mode_set && ops->supported_modes_get)) { 866 NL_SET_ERR_MSG_ATTR(extack, a, 867 "dpll device does not support mode switch"); 868 return -EOPNOTSUPP; 869 } 870 871 ret = ops->mode_get(dpll, dpll_priv(dpll), &old_mode, extack); 872 if (ret) { 873 NL_SET_ERR_MSG(extack, "unable to get current mode"); 874 return ret; 875 } 876 877 if (mode == old_mode) 878 return 0; 879 880 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, extack); 881 if (ret) { 882 NL_SET_ERR_MSG(extack, "unable to get supported modes"); 883 return ret; 884 } 885 886 if (!test_bit(mode, modes)) { 887 NL_SET_ERR_MSG(extack, 888 "dpll device does not support requested mode"); 889 return -EINVAL; 890 } 891 892 return ops->mode_set(dpll, dpll_priv(dpll), mode, extack); 893 } 894 895 static int 896 dpll_phase_offset_monitor_set(struct dpll_device *dpll, struct nlattr *a, 897 struct netlink_ext_ack *extack) 898 { 899 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 900 enum dpll_feature_state state = nla_get_u32(a), old_state; 901 int ret; 902 903 if (!(ops->phase_offset_monitor_set && ops->phase_offset_monitor_get)) { 904 NL_SET_ERR_MSG_ATTR(extack, a, "dpll device not capable of phase offset monitor"); 905 return -EOPNOTSUPP; 906 } 907 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), &old_state, 908 extack); 909 if (ret) { 910 NL_SET_ERR_MSG(extack, "unable to get current state of phase offset monitor"); 911 return ret; 912 } 913 if (state == old_state) 914 return 0; 915 916 return ops->phase_offset_monitor_set(dpll, dpll_priv(dpll), state, 917 extack); 918 } 919 920 static int 921 dpll_phase_offset_avg_factor_set(struct dpll_device *dpll, struct nlattr *a, 922 struct netlink_ext_ack *extack) 923 { 924 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 925 u32 factor = nla_get_u32(a); 926 927 if (!ops->phase_offset_avg_factor_set) { 928 NL_SET_ERR_MSG_ATTR(extack, a, 929 "device not capable of changing phase offset average factor"); 930 return -EOPNOTSUPP; 931 } 932 933 return ops->phase_offset_avg_factor_set(dpll, dpll_priv(dpll), factor, 934 extack); 935 } 936 937 static int 938 dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a, 939 struct netlink_ext_ack *extack) 940 { 941 u64 freq = nla_get_u64(a), old_freq; 942 struct dpll_pin_ref *ref, *failed; 943 const struct dpll_pin_ops *ops; 944 struct dpll_device *dpll; 945 unsigned long i; 946 int ret; 947 948 if (!dpll_pin_is_freq_supported(pin, freq)) { 949 NL_SET_ERR_MSG_ATTR(extack, a, "frequency is not supported by the device"); 950 return -EINVAL; 951 } 952 953 xa_for_each(&pin->dpll_refs, i, ref) { 954 ops = dpll_pin_ops(ref); 955 if (!ops->frequency_set || !ops->frequency_get) { 956 NL_SET_ERR_MSG(extack, "frequency set not supported by the device"); 957 return -EOPNOTSUPP; 958 } 959 } 960 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 961 ops = dpll_pin_ops(ref); 962 dpll = ref->dpll; 963 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 964 dpll_priv(dpll), &old_freq, extack); 965 if (ret) { 966 NL_SET_ERR_MSG(extack, "unable to get old frequency value"); 967 return ret; 968 } 969 if (freq == old_freq) 970 return 0; 971 972 xa_for_each(&pin->dpll_refs, i, ref) { 973 ops = dpll_pin_ops(ref); 974 dpll = ref->dpll; 975 ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 976 dpll, dpll_priv(dpll), freq, extack); 977 if (ret) { 978 failed = ref; 979 NL_SET_ERR_MSG_FMT(extack, "frequency set failed for dpll_id:%u", 980 dpll->id); 981 goto rollback; 982 } 983 } 984 __dpll_pin_change_ntf(pin); 985 986 return 0; 987 988 rollback: 989 xa_for_each(&pin->dpll_refs, i, ref) { 990 if (ref == failed) 991 break; 992 ops = dpll_pin_ops(ref); 993 dpll = ref->dpll; 994 if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 995 dpll, dpll_priv(dpll), old_freq, extack)) 996 NL_SET_ERR_MSG(extack, "set frequency rollback failed"); 997 } 998 return ret; 999 } 1000 1001 static int 1002 dpll_pin_esync_set(struct dpll_pin *pin, struct nlattr *a, 1003 struct netlink_ext_ack *extack) 1004 { 1005 struct dpll_pin_ref *ref, *failed; 1006 const struct dpll_pin_ops *ops; 1007 struct dpll_pin_esync esync; 1008 u64 freq = nla_get_u64(a); 1009 struct dpll_device *dpll; 1010 bool supported = false; 1011 unsigned long i; 1012 int ret; 1013 1014 xa_for_each(&pin->dpll_refs, i, ref) { 1015 ops = dpll_pin_ops(ref); 1016 if (!ops->esync_set || !ops->esync_get) { 1017 NL_SET_ERR_MSG(extack, 1018 "embedded sync feature is not supported by this device"); 1019 return -EOPNOTSUPP; 1020 } 1021 } 1022 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1023 ops = dpll_pin_ops(ref); 1024 dpll = ref->dpll; 1025 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1026 dpll_priv(dpll), &esync, extack); 1027 if (ret) { 1028 NL_SET_ERR_MSG(extack, "unable to get current embedded sync frequency value"); 1029 return ret; 1030 } 1031 if (freq == esync.freq) 1032 return 0; 1033 for (i = 0; i < esync.range_num; i++) 1034 if (freq <= esync.range[i].max && freq >= esync.range[i].min) 1035 supported = true; 1036 if (!supported) { 1037 NL_SET_ERR_MSG_ATTR(extack, a, 1038 "requested embedded sync frequency value is not supported by this device"); 1039 return -EINVAL; 1040 } 1041 1042 xa_for_each(&pin->dpll_refs, i, ref) { 1043 void *pin_dpll_priv; 1044 1045 ops = dpll_pin_ops(ref); 1046 dpll = ref->dpll; 1047 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1048 ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1049 freq, extack); 1050 if (ret) { 1051 failed = ref; 1052 NL_SET_ERR_MSG_FMT(extack, 1053 "embedded sync frequency set failed for dpll_id: %u", 1054 dpll->id); 1055 goto rollback; 1056 } 1057 } 1058 __dpll_pin_change_ntf(pin); 1059 1060 return 0; 1061 1062 rollback: 1063 xa_for_each(&pin->dpll_refs, i, ref) { 1064 void *pin_dpll_priv; 1065 1066 if (ref == failed) 1067 break; 1068 ops = dpll_pin_ops(ref); 1069 dpll = ref->dpll; 1070 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1071 if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1072 esync.freq, extack)) 1073 NL_SET_ERR_MSG(extack, "set embedded sync frequency rollback failed"); 1074 } 1075 return ret; 1076 } 1077 1078 static int 1079 dpll_pin_ref_sync_state_set(struct dpll_pin *pin, 1080 unsigned long ref_sync_pin_idx, 1081 const enum dpll_pin_state state, 1082 struct netlink_ext_ack *extack) 1083 1084 { 1085 struct dpll_pin_ref *ref, *failed; 1086 const struct dpll_pin_ops *ops; 1087 enum dpll_pin_state old_state; 1088 struct dpll_pin *ref_sync_pin; 1089 struct dpll_device *dpll; 1090 unsigned long i; 1091 int ret; 1092 1093 ref_sync_pin = xa_find(&pin->ref_sync_pins, &ref_sync_pin_idx, 1094 ULONG_MAX, XA_PRESENT); 1095 if (!ref_sync_pin) { 1096 NL_SET_ERR_MSG(extack, "reference sync pin not found"); 1097 return -EINVAL; 1098 } 1099 if (!dpll_pin_available(ref_sync_pin)) { 1100 NL_SET_ERR_MSG(extack, "reference sync pin not available"); 1101 return -EINVAL; 1102 } 1103 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1104 ASSERT_NOT_NULL(ref); 1105 ops = dpll_pin_ops(ref); 1106 if (!ops->ref_sync_set || !ops->ref_sync_get) { 1107 NL_SET_ERR_MSG(extack, "reference sync not supported by this pin"); 1108 return -EOPNOTSUPP; 1109 } 1110 dpll = ref->dpll; 1111 ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1112 ref_sync_pin, 1113 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1114 &old_state, extack); 1115 if (ret) { 1116 NL_SET_ERR_MSG(extack, "unable to get old reference sync state"); 1117 return ret; 1118 } 1119 if (state == old_state) 1120 return 0; 1121 xa_for_each(&pin->dpll_refs, i, ref) { 1122 ops = dpll_pin_ops(ref); 1123 dpll = ref->dpll; 1124 ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1125 ref_sync_pin, 1126 dpll_pin_on_dpll_priv(dpll, 1127 ref_sync_pin), 1128 state, extack); 1129 if (ret) { 1130 failed = ref; 1131 NL_SET_ERR_MSG_FMT(extack, "reference sync set failed for dpll_id:%u", 1132 dpll->id); 1133 goto rollback; 1134 } 1135 } 1136 __dpll_pin_change_ntf(pin); 1137 1138 return 0; 1139 1140 rollback: 1141 xa_for_each(&pin->dpll_refs, i, ref) { 1142 if (ref == failed) 1143 break; 1144 ops = dpll_pin_ops(ref); 1145 dpll = ref->dpll; 1146 if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1147 ref_sync_pin, 1148 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1149 old_state, extack)) 1150 NL_SET_ERR_MSG(extack, "set reference sync rollback failed"); 1151 } 1152 return ret; 1153 } 1154 1155 static int 1156 dpll_pin_ref_sync_set(struct dpll_pin *pin, struct nlattr *nest, 1157 struct netlink_ext_ack *extack) 1158 { 1159 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1160 enum dpll_pin_state state; 1161 u32 sync_pin_id; 1162 1163 nla_parse_nested(tb, DPLL_A_PIN_MAX, nest, 1164 dpll_reference_sync_nl_policy, extack); 1165 if (!tb[DPLL_A_PIN_ID]) { 1166 NL_SET_ERR_MSG(extack, "sync pin id expected"); 1167 return -EINVAL; 1168 } 1169 sync_pin_id = nla_get_u32(tb[DPLL_A_PIN_ID]); 1170 1171 if (!tb[DPLL_A_PIN_STATE]) { 1172 NL_SET_ERR_MSG(extack, "sync pin state expected"); 1173 return -EINVAL; 1174 } 1175 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1176 1177 return dpll_pin_ref_sync_state_set(pin, sync_pin_id, state, extack); 1178 } 1179 1180 static int 1181 dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, 1182 enum dpll_pin_state state, 1183 struct netlink_ext_ack *extack) 1184 { 1185 struct dpll_pin_ref *parent_ref; 1186 const struct dpll_pin_ops *ops; 1187 struct dpll_pin_ref *dpll_ref; 1188 void *pin_priv, *parent_priv; 1189 struct dpll_pin *parent; 1190 unsigned long i; 1191 int ret; 1192 1193 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1194 pin->prop.capabilities)) { 1195 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1196 return -EOPNOTSUPP; 1197 } 1198 parent = xa_load(&dpll_pin_xa, parent_idx); 1199 if (!parent) 1200 return -EINVAL; 1201 parent_ref = xa_load(&pin->parent_refs, parent->pin_idx); 1202 if (!parent_ref) 1203 return -EINVAL; 1204 xa_for_each(&parent->dpll_refs, i, dpll_ref) { 1205 ops = dpll_pin_ops(parent_ref); 1206 if (!ops->state_on_pin_set) 1207 return -EOPNOTSUPP; 1208 pin_priv = dpll_pin_on_pin_priv(parent, pin); 1209 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, parent); 1210 ret = ops->state_on_pin_set(pin, pin_priv, parent, parent_priv, 1211 state, extack); 1212 if (ret) 1213 return ret; 1214 } 1215 __dpll_pin_change_ntf(pin); 1216 1217 return 0; 1218 } 1219 1220 static int 1221 dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin, 1222 enum dpll_pin_state state, 1223 struct netlink_ext_ack *extack) 1224 { 1225 const struct dpll_pin_ops *ops; 1226 struct dpll_pin_ref *ref; 1227 int ret; 1228 1229 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1230 pin->prop.capabilities)) { 1231 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1232 return -EOPNOTSUPP; 1233 } 1234 ref = xa_load(&pin->dpll_refs, dpll->id); 1235 ASSERT_NOT_NULL(ref); 1236 ops = dpll_pin_ops(ref); 1237 if (!ops->state_on_dpll_set) 1238 return -EOPNOTSUPP; 1239 ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1240 dpll, dpll_priv(dpll), state, extack); 1241 if (ret) 1242 return ret; 1243 __dpll_pin_change_ntf(pin); 1244 1245 return 0; 1246 } 1247 1248 static int 1249 dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin, 1250 u32 prio, struct netlink_ext_ack *extack) 1251 { 1252 const struct dpll_pin_ops *ops; 1253 struct dpll_pin_ref *ref; 1254 int ret; 1255 1256 if (!(DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE & 1257 pin->prop.capabilities)) { 1258 NL_SET_ERR_MSG(extack, "prio changing is not allowed"); 1259 return -EOPNOTSUPP; 1260 } 1261 ref = xa_load(&pin->dpll_refs, dpll->id); 1262 ASSERT_NOT_NULL(ref); 1263 ops = dpll_pin_ops(ref); 1264 if (!ops->prio_set) 1265 return -EOPNOTSUPP; 1266 ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1267 dpll_priv(dpll), prio, extack); 1268 if (ret) 1269 return ret; 1270 __dpll_pin_change_ntf(pin); 1271 1272 return 0; 1273 } 1274 1275 static int 1276 dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll, 1277 enum dpll_pin_direction direction, 1278 struct netlink_ext_ack *extack) 1279 { 1280 const struct dpll_pin_ops *ops; 1281 struct dpll_pin_ref *ref; 1282 int ret; 1283 1284 if (!(DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE & 1285 pin->prop.capabilities)) { 1286 NL_SET_ERR_MSG(extack, "direction changing is not allowed"); 1287 return -EOPNOTSUPP; 1288 } 1289 ref = xa_load(&pin->dpll_refs, dpll->id); 1290 ASSERT_NOT_NULL(ref); 1291 ops = dpll_pin_ops(ref); 1292 if (!ops->direction_set) 1293 return -EOPNOTSUPP; 1294 ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1295 dpll, dpll_priv(dpll), direction, extack); 1296 if (ret) 1297 return ret; 1298 __dpll_pin_change_ntf(pin); 1299 1300 return 0; 1301 } 1302 1303 static int 1304 dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr, 1305 struct netlink_ext_ack *extack) 1306 { 1307 struct dpll_pin_ref *ref, *failed; 1308 const struct dpll_pin_ops *ops; 1309 s32 phase_adj, old_phase_adj; 1310 struct dpll_device *dpll; 1311 unsigned long i; 1312 int ret; 1313 1314 phase_adj = nla_get_s32(phase_adj_attr); 1315 if (phase_adj > pin->prop.phase_range.max || 1316 phase_adj < pin->prop.phase_range.min) { 1317 NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr, 1318 "phase adjust value of out range"); 1319 return -EINVAL; 1320 } 1321 if (pin->prop.phase_gran && phase_adj % (s32)pin->prop.phase_gran) { 1322 NL_SET_ERR_MSG_ATTR_FMT(extack, phase_adj_attr, 1323 "phase adjust value not multiple of %u", 1324 pin->prop.phase_gran); 1325 return -EINVAL; 1326 } 1327 1328 xa_for_each(&pin->dpll_refs, i, ref) { 1329 ops = dpll_pin_ops(ref); 1330 if (!ops->phase_adjust_set || !ops->phase_adjust_get) { 1331 NL_SET_ERR_MSG(extack, "phase adjust not supported"); 1332 return -EOPNOTSUPP; 1333 } 1334 } 1335 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1336 ops = dpll_pin_ops(ref); 1337 dpll = ref->dpll; 1338 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1339 dpll, dpll_priv(dpll), &old_phase_adj, 1340 extack); 1341 if (ret) { 1342 NL_SET_ERR_MSG(extack, "unable to get old phase adjust value"); 1343 return ret; 1344 } 1345 if (phase_adj == old_phase_adj) 1346 return 0; 1347 1348 xa_for_each(&pin->dpll_refs, i, ref) { 1349 ops = dpll_pin_ops(ref); 1350 dpll = ref->dpll; 1351 ret = ops->phase_adjust_set(pin, 1352 dpll_pin_on_dpll_priv(dpll, pin), 1353 dpll, dpll_priv(dpll), phase_adj, 1354 extack); 1355 if (ret) { 1356 failed = ref; 1357 NL_SET_ERR_MSG_FMT(extack, 1358 "phase adjust set failed for dpll_id:%u", 1359 dpll->id); 1360 goto rollback; 1361 } 1362 } 1363 __dpll_pin_change_ntf(pin); 1364 1365 return 0; 1366 1367 rollback: 1368 xa_for_each(&pin->dpll_refs, i, ref) { 1369 if (ref == failed) 1370 break; 1371 ops = dpll_pin_ops(ref); 1372 dpll = ref->dpll; 1373 if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1374 dpll, dpll_priv(dpll), old_phase_adj, 1375 extack)) 1376 NL_SET_ERR_MSG(extack, "set phase adjust rollback failed"); 1377 } 1378 return ret; 1379 } 1380 1381 static int 1382 dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1383 struct netlink_ext_ack *extack) 1384 { 1385 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1386 enum dpll_pin_direction direction; 1387 enum dpll_pin_state state; 1388 struct dpll_pin_ref *ref; 1389 struct dpll_device *dpll; 1390 u32 pdpll_idx, prio; 1391 int ret; 1392 1393 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1394 dpll_pin_parent_device_nl_policy, extack); 1395 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1396 NL_SET_ERR_MSG(extack, "device parent id expected"); 1397 return -EINVAL; 1398 } 1399 pdpll_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1400 dpll = xa_load(&dpll_device_xa, pdpll_idx); 1401 if (!dpll) { 1402 NL_SET_ERR_MSG(extack, "parent device not found"); 1403 return -EINVAL; 1404 } 1405 ref = xa_load(&pin->dpll_refs, dpll->id); 1406 if (!ref) { 1407 NL_SET_ERR_MSG(extack, "pin not connected to given parent device"); 1408 return -EINVAL; 1409 } 1410 if (tb[DPLL_A_PIN_STATE]) { 1411 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1412 ret = dpll_pin_state_set(dpll, pin, state, extack); 1413 if (ret) 1414 return ret; 1415 } 1416 if (tb[DPLL_A_PIN_PRIO]) { 1417 prio = nla_get_u32(tb[DPLL_A_PIN_PRIO]); 1418 ret = dpll_pin_prio_set(dpll, pin, prio, extack); 1419 if (ret) 1420 return ret; 1421 } 1422 if (tb[DPLL_A_PIN_DIRECTION]) { 1423 direction = nla_get_u32(tb[DPLL_A_PIN_DIRECTION]); 1424 ret = dpll_pin_direction_set(pin, dpll, direction, extack); 1425 if (ret) 1426 return ret; 1427 } 1428 return 0; 1429 } 1430 1431 static int 1432 dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1433 struct netlink_ext_ack *extack) 1434 { 1435 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1436 u32 ppin_idx; 1437 int ret; 1438 1439 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1440 dpll_pin_parent_pin_nl_policy, extack); 1441 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1442 NL_SET_ERR_MSG(extack, "device parent id expected"); 1443 return -EINVAL; 1444 } 1445 ppin_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1446 1447 if (tb[DPLL_A_PIN_STATE]) { 1448 enum dpll_pin_state state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1449 1450 ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack); 1451 if (ret) 1452 return ret; 1453 } 1454 1455 return 0; 1456 } 1457 1458 static int 1459 dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info) 1460 { 1461 struct nlattr *a; 1462 int rem, ret; 1463 1464 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1465 genlmsg_len(info->genlhdr), rem) { 1466 switch (nla_type(a)) { 1467 case DPLL_A_PIN_FREQUENCY: 1468 ret = dpll_pin_freq_set(pin, a, info->extack); 1469 if (ret) 1470 return ret; 1471 break; 1472 case DPLL_A_PIN_PHASE_ADJUST: 1473 ret = dpll_pin_phase_adj_set(pin, a, info->extack); 1474 if (ret) 1475 return ret; 1476 break; 1477 case DPLL_A_PIN_PARENT_DEVICE: 1478 ret = dpll_pin_parent_device_set(pin, a, info->extack); 1479 if (ret) 1480 return ret; 1481 break; 1482 case DPLL_A_PIN_PARENT_PIN: 1483 ret = dpll_pin_parent_pin_set(pin, a, info->extack); 1484 if (ret) 1485 return ret; 1486 break; 1487 case DPLL_A_PIN_ESYNC_FREQUENCY: 1488 ret = dpll_pin_esync_set(pin, a, info->extack); 1489 if (ret) 1490 return ret; 1491 break; 1492 case DPLL_A_PIN_REFERENCE_SYNC: 1493 ret = dpll_pin_ref_sync_set(pin, a, info->extack); 1494 if (ret) 1495 return ret; 1496 break; 1497 } 1498 } 1499 1500 return 0; 1501 } 1502 1503 static struct dpll_pin * 1504 dpll_pin_find(u64 clock_id, struct nlattr *mod_name_attr, 1505 enum dpll_pin_type type, struct nlattr *board_label, 1506 struct nlattr *panel_label, struct nlattr *package_label, 1507 struct netlink_ext_ack *extack) 1508 { 1509 bool board_match, panel_match, package_match; 1510 struct dpll_pin *pin_match = NULL, *pin; 1511 const struct dpll_pin_properties *prop; 1512 bool cid_match, mod_match, type_match; 1513 unsigned long i; 1514 1515 xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) { 1516 prop = &pin->prop; 1517 cid_match = clock_id ? pin->clock_id == clock_id : true; 1518 mod_match = mod_name_attr && module_name(pin->module) ? 1519 !nla_strcmp(mod_name_attr, 1520 module_name(pin->module)) : true; 1521 type_match = type ? prop->type == type : true; 1522 board_match = board_label ? (prop->board_label ? 1523 !nla_strcmp(board_label, prop->board_label) : false) : 1524 true; 1525 panel_match = panel_label ? (prop->panel_label ? 1526 !nla_strcmp(panel_label, prop->panel_label) : false) : 1527 true; 1528 package_match = package_label ? (prop->package_label ? 1529 !nla_strcmp(package_label, prop->package_label) : 1530 false) : true; 1531 if (cid_match && mod_match && type_match && board_match && 1532 panel_match && package_match) { 1533 if (pin_match) { 1534 NL_SET_ERR_MSG(extack, "multiple matches"); 1535 return ERR_PTR(-EINVAL); 1536 } 1537 pin_match = pin; 1538 } 1539 } 1540 if (!pin_match) { 1541 NL_SET_ERR_MSG(extack, "not found"); 1542 return ERR_PTR(-ENODEV); 1543 } 1544 return pin_match; 1545 } 1546 1547 static struct dpll_pin *dpll_pin_find_from_nlattr(struct genl_info *info) 1548 { 1549 struct nlattr *attr, *mod_name_attr = NULL, *board_label_attr = NULL, 1550 *panel_label_attr = NULL, *package_label_attr = NULL; 1551 enum dpll_pin_type type = 0; 1552 u64 clock_id = 0; 1553 int rem = 0; 1554 1555 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1556 genlmsg_len(info->genlhdr), rem) { 1557 switch (nla_type(attr)) { 1558 case DPLL_A_PIN_CLOCK_ID: 1559 if (clock_id) 1560 goto duplicated_attr; 1561 clock_id = nla_get_u64(attr); 1562 break; 1563 case DPLL_A_PIN_MODULE_NAME: 1564 if (mod_name_attr) 1565 goto duplicated_attr; 1566 mod_name_attr = attr; 1567 break; 1568 case DPLL_A_PIN_TYPE: 1569 if (type) 1570 goto duplicated_attr; 1571 type = nla_get_u32(attr); 1572 break; 1573 case DPLL_A_PIN_BOARD_LABEL: 1574 if (board_label_attr) 1575 goto duplicated_attr; 1576 board_label_attr = attr; 1577 break; 1578 case DPLL_A_PIN_PANEL_LABEL: 1579 if (panel_label_attr) 1580 goto duplicated_attr; 1581 panel_label_attr = attr; 1582 break; 1583 case DPLL_A_PIN_PACKAGE_LABEL: 1584 if (package_label_attr) 1585 goto duplicated_attr; 1586 package_label_attr = attr; 1587 break; 1588 default: 1589 break; 1590 } 1591 } 1592 if (!(clock_id || mod_name_attr || board_label_attr || 1593 panel_label_attr || package_label_attr)) { 1594 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1595 return ERR_PTR(-EINVAL); 1596 } 1597 return dpll_pin_find(clock_id, mod_name_attr, type, board_label_attr, 1598 panel_label_attr, package_label_attr, 1599 info->extack); 1600 duplicated_attr: 1601 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1602 return ERR_PTR(-EINVAL); 1603 } 1604 1605 int dpll_nl_pin_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1606 { 1607 struct dpll_pin *pin; 1608 struct sk_buff *msg; 1609 struct nlattr *hdr; 1610 int ret; 1611 1612 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1613 if (!msg) 1614 return -ENOMEM; 1615 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1616 DPLL_CMD_PIN_ID_GET); 1617 if (!hdr) { 1618 nlmsg_free(msg); 1619 return -EMSGSIZE; 1620 } 1621 pin = dpll_pin_find_from_nlattr(info); 1622 if (IS_ERR(pin)) { 1623 nlmsg_free(msg); 1624 return PTR_ERR(pin); 1625 } 1626 if (!dpll_pin_available(pin)) { 1627 nlmsg_free(msg); 1628 return -ENODEV; 1629 } 1630 ret = dpll_msg_add_pin_handle(msg, pin); 1631 if (ret) { 1632 nlmsg_free(msg); 1633 return ret; 1634 } 1635 genlmsg_end(msg, hdr); 1636 1637 return genlmsg_reply(msg, info); 1638 } 1639 1640 int dpll_nl_pin_get_doit(struct sk_buff *skb, struct genl_info *info) 1641 { 1642 struct dpll_pin *pin = info->user_ptr[0]; 1643 struct sk_buff *msg; 1644 struct nlattr *hdr; 1645 int ret; 1646 1647 if (!pin) 1648 return -ENODEV; 1649 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1650 if (!msg) 1651 return -ENOMEM; 1652 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1653 DPLL_CMD_PIN_GET); 1654 if (!hdr) { 1655 nlmsg_free(msg); 1656 return -EMSGSIZE; 1657 } 1658 ret = dpll_cmd_pin_get_one(msg, pin, info->extack); 1659 if (ret) { 1660 nlmsg_free(msg); 1661 return ret; 1662 } 1663 genlmsg_end(msg, hdr); 1664 1665 return genlmsg_reply(msg, info); 1666 } 1667 1668 int dpll_nl_pin_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1669 { 1670 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1671 struct dpll_pin *pin; 1672 struct nlattr *hdr; 1673 unsigned long i; 1674 int ret = 0; 1675 1676 mutex_lock(&dpll_lock); 1677 xa_for_each_marked_start(&dpll_pin_xa, i, pin, DPLL_REGISTERED, 1678 ctx->idx) { 1679 if (!dpll_pin_available(pin)) 1680 continue; 1681 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1682 cb->nlh->nlmsg_seq, 1683 &dpll_nl_family, NLM_F_MULTI, 1684 DPLL_CMD_PIN_GET); 1685 if (!hdr) { 1686 ret = -EMSGSIZE; 1687 break; 1688 } 1689 ret = dpll_cmd_pin_get_one(skb, pin, cb->extack); 1690 if (ret) { 1691 genlmsg_cancel(skb, hdr); 1692 break; 1693 } 1694 genlmsg_end(skb, hdr); 1695 } 1696 mutex_unlock(&dpll_lock); 1697 1698 if (ret == -EMSGSIZE) { 1699 ctx->idx = i; 1700 return skb->len; 1701 } 1702 return ret; 1703 } 1704 1705 int dpll_nl_pin_set_doit(struct sk_buff *skb, struct genl_info *info) 1706 { 1707 struct dpll_pin *pin = info->user_ptr[0]; 1708 1709 return dpll_pin_set_from_nlattr(pin, info); 1710 } 1711 1712 static struct dpll_device * 1713 dpll_device_find(u64 clock_id, struct nlattr *mod_name_attr, 1714 enum dpll_type type, struct netlink_ext_ack *extack) 1715 { 1716 struct dpll_device *dpll_match = NULL, *dpll; 1717 bool cid_match, mod_match, type_match; 1718 unsigned long i; 1719 1720 xa_for_each_marked(&dpll_device_xa, i, dpll, DPLL_REGISTERED) { 1721 cid_match = clock_id ? dpll->clock_id == clock_id : true; 1722 mod_match = mod_name_attr ? (module_name(dpll->module) ? 1723 !nla_strcmp(mod_name_attr, 1724 module_name(dpll->module)) : false) : true; 1725 type_match = type ? dpll->type == type : true; 1726 if (cid_match && mod_match && type_match) { 1727 if (dpll_match) { 1728 NL_SET_ERR_MSG(extack, "multiple matches"); 1729 return ERR_PTR(-EINVAL); 1730 } 1731 dpll_match = dpll; 1732 } 1733 } 1734 if (!dpll_match) { 1735 NL_SET_ERR_MSG(extack, "not found"); 1736 return ERR_PTR(-ENODEV); 1737 } 1738 1739 return dpll_match; 1740 } 1741 1742 static struct dpll_device * 1743 dpll_device_find_from_nlattr(struct genl_info *info) 1744 { 1745 struct nlattr *attr, *mod_name_attr = NULL; 1746 enum dpll_type type = 0; 1747 u64 clock_id = 0; 1748 int rem = 0; 1749 1750 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1751 genlmsg_len(info->genlhdr), rem) { 1752 switch (nla_type(attr)) { 1753 case DPLL_A_CLOCK_ID: 1754 if (clock_id) 1755 goto duplicated_attr; 1756 clock_id = nla_get_u64(attr); 1757 break; 1758 case DPLL_A_MODULE_NAME: 1759 if (mod_name_attr) 1760 goto duplicated_attr; 1761 mod_name_attr = attr; 1762 break; 1763 case DPLL_A_TYPE: 1764 if (type) 1765 goto duplicated_attr; 1766 type = nla_get_u32(attr); 1767 break; 1768 default: 1769 break; 1770 } 1771 } 1772 if (!clock_id && !mod_name_attr && !type) { 1773 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1774 return ERR_PTR(-EINVAL); 1775 } 1776 return dpll_device_find(clock_id, mod_name_attr, type, info->extack); 1777 duplicated_attr: 1778 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1779 return ERR_PTR(-EINVAL); 1780 } 1781 1782 int dpll_nl_device_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1783 { 1784 struct dpll_device *dpll; 1785 struct sk_buff *msg; 1786 struct nlattr *hdr; 1787 int ret; 1788 1789 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1790 if (!msg) 1791 return -ENOMEM; 1792 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1793 DPLL_CMD_DEVICE_ID_GET); 1794 if (!hdr) { 1795 nlmsg_free(msg); 1796 return -EMSGSIZE; 1797 } 1798 1799 dpll = dpll_device_find_from_nlattr(info); 1800 if (IS_ERR(dpll)) { 1801 nlmsg_free(msg); 1802 return PTR_ERR(dpll); 1803 } 1804 ret = dpll_msg_add_dev_handle(msg, dpll); 1805 if (ret) { 1806 nlmsg_free(msg); 1807 return ret; 1808 } 1809 genlmsg_end(msg, hdr); 1810 1811 return genlmsg_reply(msg, info); 1812 } 1813 1814 int dpll_nl_device_get_doit(struct sk_buff *skb, struct genl_info *info) 1815 { 1816 struct dpll_device *dpll = info->user_ptr[0]; 1817 struct sk_buff *msg; 1818 struct nlattr *hdr; 1819 int ret; 1820 1821 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1822 if (!msg) 1823 return -ENOMEM; 1824 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1825 DPLL_CMD_DEVICE_GET); 1826 if (!hdr) { 1827 nlmsg_free(msg); 1828 return -EMSGSIZE; 1829 } 1830 1831 ret = dpll_device_get_one(dpll, msg, info->extack); 1832 if (ret) { 1833 nlmsg_free(msg); 1834 return ret; 1835 } 1836 genlmsg_end(msg, hdr); 1837 1838 return genlmsg_reply(msg, info); 1839 } 1840 1841 static int 1842 dpll_set_from_nlattr(struct dpll_device *dpll, struct genl_info *info) 1843 { 1844 struct nlattr *a; 1845 int rem, ret; 1846 1847 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1848 genlmsg_len(info->genlhdr), rem) { 1849 switch (nla_type(a)) { 1850 case DPLL_A_MODE: 1851 ret = dpll_mode_set(dpll, a, info->extack); 1852 if (ret) 1853 return ret; 1854 break; 1855 case DPLL_A_PHASE_OFFSET_MONITOR: 1856 ret = dpll_phase_offset_monitor_set(dpll, a, 1857 info->extack); 1858 if (ret) 1859 return ret; 1860 break; 1861 case DPLL_A_PHASE_OFFSET_AVG_FACTOR: 1862 ret = dpll_phase_offset_avg_factor_set(dpll, a, 1863 info->extack); 1864 if (ret) 1865 return ret; 1866 break; 1867 } 1868 } 1869 1870 return 0; 1871 } 1872 1873 int dpll_nl_device_set_doit(struct sk_buff *skb, struct genl_info *info) 1874 { 1875 struct dpll_device *dpll = info->user_ptr[0]; 1876 1877 return dpll_set_from_nlattr(dpll, info); 1878 } 1879 1880 int dpll_nl_device_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1881 { 1882 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1883 struct dpll_device *dpll; 1884 struct nlattr *hdr; 1885 unsigned long i; 1886 int ret = 0; 1887 1888 mutex_lock(&dpll_lock); 1889 xa_for_each_marked_start(&dpll_device_xa, i, dpll, DPLL_REGISTERED, 1890 ctx->idx) { 1891 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1892 cb->nlh->nlmsg_seq, &dpll_nl_family, 1893 NLM_F_MULTI, DPLL_CMD_DEVICE_GET); 1894 if (!hdr) { 1895 ret = -EMSGSIZE; 1896 break; 1897 } 1898 ret = dpll_device_get_one(dpll, skb, cb->extack); 1899 if (ret) { 1900 genlmsg_cancel(skb, hdr); 1901 break; 1902 } 1903 genlmsg_end(skb, hdr); 1904 } 1905 mutex_unlock(&dpll_lock); 1906 1907 if (ret == -EMSGSIZE) { 1908 ctx->idx = i; 1909 return skb->len; 1910 } 1911 return ret; 1912 } 1913 1914 int dpll_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1915 struct genl_info *info) 1916 { 1917 u32 id; 1918 1919 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_ID)) 1920 return -EINVAL; 1921 1922 mutex_lock(&dpll_lock); 1923 id = nla_get_u32(info->attrs[DPLL_A_ID]); 1924 info->user_ptr[0] = dpll_device_get_by_id(id); 1925 if (!info->user_ptr[0]) { 1926 NL_SET_ERR_MSG(info->extack, "device not found"); 1927 goto unlock; 1928 } 1929 return 0; 1930 unlock: 1931 mutex_unlock(&dpll_lock); 1932 return -ENODEV; 1933 } 1934 1935 void dpll_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1936 struct genl_info *info) 1937 { 1938 mutex_unlock(&dpll_lock); 1939 } 1940 1941 int 1942 dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1943 struct genl_info *info) 1944 { 1945 mutex_lock(&dpll_lock); 1946 1947 return 0; 1948 } 1949 1950 void 1951 dpll_unlock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1952 struct genl_info *info) 1953 { 1954 mutex_unlock(&dpll_lock); 1955 } 1956 1957 int dpll_pin_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1958 struct genl_info *info) 1959 { 1960 int ret; 1961 1962 mutex_lock(&dpll_lock); 1963 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_PIN_ID)) { 1964 ret = -EINVAL; 1965 goto unlock_dev; 1966 } 1967 info->user_ptr[0] = xa_load(&dpll_pin_xa, 1968 nla_get_u32(info->attrs[DPLL_A_PIN_ID])); 1969 if (!info->user_ptr[0] || 1970 !dpll_pin_available(info->user_ptr[0])) { 1971 NL_SET_ERR_MSG(info->extack, "pin not found"); 1972 ret = -ENODEV; 1973 goto unlock_dev; 1974 } 1975 1976 return 0; 1977 1978 unlock_dev: 1979 mutex_unlock(&dpll_lock); 1980 return ret; 1981 } 1982 1983 void dpll_pin_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1984 struct genl_info *info) 1985 { 1986 mutex_unlock(&dpll_lock); 1987 } 1988