1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Generic netlink for DPLL management framework 4 * 5 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 6 * Copyright (c) 2023 Intel and affiliates 7 * 8 */ 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/netdevice.h> 12 #include <net/genetlink.h> 13 #include "dpll_core.h" 14 #include "dpll_netlink.h" 15 #include "dpll_nl.h" 16 #include <uapi/linux/dpll.h> 17 18 #define ASSERT_NOT_NULL(ptr) (WARN_ON(!ptr)) 19 20 #define xa_for_each_marked_start(xa, index, entry, filter, start) \ 21 for (index = start, entry = xa_find(xa, &index, ULONG_MAX, filter); \ 22 entry; entry = xa_find_after(xa, &index, ULONG_MAX, filter)) 23 24 struct dpll_dump_ctx { 25 unsigned long idx; 26 }; 27 28 static struct dpll_dump_ctx *dpll_dump_context(struct netlink_callback *cb) 29 { 30 return (struct dpll_dump_ctx *)cb->ctx; 31 } 32 33 static int 34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) 35 { 36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) 37 return -EMSGSIZE; 38 39 return 0; 40 } 41 42 static int 43 dpll_msg_add_dev_parent_handle(struct sk_buff *msg, u32 id) 44 { 45 if (nla_put_u32(msg, DPLL_A_PIN_PARENT_ID, id)) 46 return -EMSGSIZE; 47 48 return 0; 49 } 50 51 static bool dpll_pin_available(struct dpll_pin *pin) 52 { 53 struct dpll_pin_ref *par_ref; 54 unsigned long i; 55 56 if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) 57 return false; 58 xa_for_each(&pin->parent_refs, i, par_ref) 59 if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, 60 DPLL_REGISTERED)) 61 return true; 62 xa_for_each(&pin->dpll_refs, i, par_ref) 63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, 64 DPLL_REGISTERED)) 65 return true; 66 return false; 67 } 68 69 /** 70 * dpll_msg_add_pin_handle - attach pin handle attribute to a given message 71 * @msg: pointer to sk_buff message to attach a pin handle 72 * @pin: pin pointer 73 * 74 * Return: 75 * * 0 - success 76 * * -EMSGSIZE - no space in message to attach pin handle 77 */ 78 static int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin) 79 { 80 if (!pin) 81 return 0; 82 if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id)) 83 return -EMSGSIZE; 84 return 0; 85 } 86 87 static struct dpll_pin *dpll_netdev_pin(const struct net_device *dev) 88 { 89 return rcu_dereference_rtnl(dev->dpll_pin); 90 } 91 92 int dpll_netdev_add_pin_handle(struct sk_buff *msg, 93 const struct net_device *dev) 94 { 95 return dpll_msg_add_pin_handle(msg, dpll_netdev_pin(dev)); 96 } 97 98 static int 99 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, 100 struct netlink_ext_ack *extack) 101 { 102 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 103 enum dpll_mode mode; 104 int ret; 105 106 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 107 if (ret) 108 return ret; 109 if (nla_put_u32(msg, DPLL_A_MODE, mode)) 110 return -EMSGSIZE; 111 112 return 0; 113 } 114 115 static int 116 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, 117 struct netlink_ext_ack *extack) 118 { 119 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 120 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 121 enum dpll_mode mode; 122 int ret; 123 124 if (ops->supported_modes_get) { 125 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, 126 extack); 127 if (ret) 128 return ret; 129 } else { 130 /* If the supported modes are not reported by the driver, the 131 * only supported mode is the one obtained by mode_get(). 132 */ 133 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 134 if (ret) 135 return ret; 136 137 __set_bit(mode, modes); 138 } 139 140 for_each_set_bit(mode, modes, DPLL_MODE_MAX + 1) 141 if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode)) 142 return -EMSGSIZE; 143 144 return 0; 145 } 146 147 static int 148 dpll_msg_add_phase_offset_monitor(struct sk_buff *msg, struct dpll_device *dpll, 149 struct netlink_ext_ack *extack) 150 { 151 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 152 enum dpll_feature_state state; 153 int ret; 154 155 if (ops->phase_offset_monitor_set && ops->phase_offset_monitor_get) { 156 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), 157 &state, extack); 158 if (ret) 159 return ret; 160 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_MONITOR, state)) 161 return -EMSGSIZE; 162 } 163 164 return 0; 165 } 166 167 static int 168 dpll_msg_add_freq_monitor(struct sk_buff *msg, struct dpll_device *dpll, 169 struct netlink_ext_ack *extack) 170 { 171 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 172 enum dpll_feature_state state; 173 int ret; 174 175 if (ops->freq_monitor_set && ops->freq_monitor_get) { 176 ret = ops->freq_monitor_get(dpll, dpll_priv(dpll), 177 &state, extack); 178 if (ret) 179 return ret; 180 if (nla_put_u32(msg, DPLL_A_FREQUENCY_MONITOR, state)) 181 return -EMSGSIZE; 182 } 183 184 return 0; 185 } 186 187 static int 188 dpll_msg_add_phase_offset_avg_factor(struct sk_buff *msg, 189 struct dpll_device *dpll, 190 struct netlink_ext_ack *extack) 191 { 192 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 193 u32 factor; 194 int ret; 195 196 if (ops->phase_offset_avg_factor_get) { 197 ret = ops->phase_offset_avg_factor_get(dpll, dpll_priv(dpll), 198 &factor, extack); 199 if (ret) 200 return ret; 201 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_AVG_FACTOR, factor)) 202 return -EMSGSIZE; 203 } 204 205 return 0; 206 } 207 208 static int 209 dpll_msg_add_lock_status(struct sk_buff *msg, struct dpll_device *dpll, 210 struct netlink_ext_ack *extack) 211 { 212 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 213 enum dpll_lock_status_error status_error = 0; 214 enum dpll_lock_status status; 215 int ret; 216 217 ret = ops->lock_status_get(dpll, dpll_priv(dpll), &status, 218 &status_error, extack); 219 if (ret) 220 return ret; 221 if (nla_put_u32(msg, DPLL_A_LOCK_STATUS, status)) 222 return -EMSGSIZE; 223 if (status_error && 224 (status == DPLL_LOCK_STATUS_UNLOCKED || 225 status == DPLL_LOCK_STATUS_HOLDOVER) && 226 nla_put_u32(msg, DPLL_A_LOCK_STATUS_ERROR, status_error)) 227 return -EMSGSIZE; 228 229 return 0; 230 } 231 232 static int 233 dpll_msg_add_temp(struct sk_buff *msg, struct dpll_device *dpll, 234 struct netlink_ext_ack *extack) 235 { 236 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 237 s32 temp; 238 int ret; 239 240 if (!ops->temp_get) 241 return 0; 242 ret = ops->temp_get(dpll, dpll_priv(dpll), &temp, extack); 243 if (ret) 244 return ret; 245 if (nla_put_s32(msg, DPLL_A_TEMP, temp)) 246 return -EMSGSIZE; 247 248 return 0; 249 } 250 251 static int 252 dpll_msg_add_clock_quality_level(struct sk_buff *msg, struct dpll_device *dpll, 253 struct netlink_ext_ack *extack) 254 { 255 DECLARE_BITMAP(qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) = { 0 }; 256 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 257 enum dpll_clock_quality_level ql; 258 int ret; 259 260 if (!ops->clock_quality_level_get) 261 return 0; 262 ret = ops->clock_quality_level_get(dpll, dpll_priv(dpll), qls, extack); 263 if (ret) 264 return ret; 265 for_each_set_bit(ql, qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) 266 if (nla_put_u32(msg, DPLL_A_CLOCK_QUALITY_LEVEL, ql)) 267 return -EMSGSIZE; 268 269 return 0; 270 } 271 272 static int 273 dpll_msg_add_pin_prio(struct sk_buff *msg, struct dpll_pin *pin, 274 struct dpll_pin_ref *ref, 275 struct netlink_ext_ack *extack) 276 { 277 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 278 struct dpll_device *dpll = ref->dpll; 279 u32 prio; 280 int ret; 281 282 if (!ops->prio_get) 283 return 0; 284 ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 285 dpll_priv(dpll), &prio, extack); 286 if (ret) 287 return ret; 288 if (nla_put_u32(msg, DPLL_A_PIN_PRIO, prio)) 289 return -EMSGSIZE; 290 291 return 0; 292 } 293 294 static int 295 dpll_msg_add_pin_on_dpll_state(struct sk_buff *msg, struct dpll_pin *pin, 296 struct dpll_pin_ref *ref, 297 struct netlink_ext_ack *extack) 298 { 299 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 300 struct dpll_device *dpll = ref->dpll; 301 enum dpll_pin_state state; 302 int ret; 303 304 if (!ops->state_on_dpll_get) 305 return 0; 306 ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 307 dpll, dpll_priv(dpll), &state, extack); 308 if (ret) 309 return ret; 310 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) 311 return -EMSGSIZE; 312 313 return 0; 314 } 315 316 static int 317 dpll_msg_add_pin_operstate(struct sk_buff *msg, struct dpll_pin *pin, 318 struct dpll_pin_ref *ref, 319 struct netlink_ext_ack *extack) 320 { 321 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 322 struct dpll_device *dpll = ref->dpll; 323 enum dpll_pin_operstate operstate; 324 int ret; 325 326 if (!ops->operstate_on_dpll_get) 327 return 0; 328 ret = ops->operstate_on_dpll_get(pin, 329 dpll_pin_on_dpll_priv(dpll, pin), 330 dpll, dpll_priv(dpll), 331 &operstate, extack); 332 if (ret) 333 return ret; 334 if (nla_put_u32(msg, DPLL_A_PIN_OPERSTATE, operstate)) 335 return -EMSGSIZE; 336 337 return 0; 338 } 339 340 static int 341 dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin, 342 struct dpll_pin_ref *ref, 343 struct netlink_ext_ack *extack) 344 { 345 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 346 struct dpll_device *dpll = ref->dpll; 347 enum dpll_pin_direction direction; 348 int ret; 349 350 ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 351 dpll_priv(dpll), &direction, extack); 352 if (ret) 353 return ret; 354 if (nla_put_u32(msg, DPLL_A_PIN_DIRECTION, direction)) 355 return -EMSGSIZE; 356 357 return 0; 358 } 359 360 static int 361 dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin, 362 struct dpll_pin_ref *ref, 363 struct netlink_ext_ack *extack) 364 { 365 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 366 struct dpll_device *dpll = ref->dpll; 367 s32 phase_adjust; 368 int ret; 369 370 if (!ops->phase_adjust_get) 371 return 0; 372 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 373 dpll, dpll_priv(dpll), 374 &phase_adjust, extack); 375 if (ret) 376 return ret; 377 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust)) 378 return -EMSGSIZE; 379 380 return 0; 381 } 382 383 static int 384 dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin, 385 struct dpll_pin_ref *ref, 386 struct netlink_ext_ack *extack) 387 { 388 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 389 struct dpll_device *dpll = ref->dpll; 390 s64 phase_offset; 391 int ret; 392 393 if (!ops->phase_offset_get) 394 return 0; 395 ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 396 dpll, dpll_priv(dpll), &phase_offset, 397 extack); 398 if (ret) 399 return ret; 400 if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset), 401 &phase_offset, DPLL_A_PIN_PAD)) 402 return -EMSGSIZE; 403 404 return 0; 405 } 406 407 static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin, 408 struct dpll_pin_ref *ref, 409 enum dpll_ffo_type type, 410 struct netlink_ext_ack *extack) 411 { 412 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 413 struct dpll_ffo_param ffo = { .type = type }; 414 int ret; 415 416 if (!ops->ffo_get || !(ops->supported_ffo & BIT(type))) 417 return 0; 418 ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(ref->dpll, pin), 419 ref->dpll, dpll_priv(ref->dpll), &ffo, extack); 420 if (ret) { 421 if (ret == -ENODATA) 422 return 0; 423 return ret; 424 } 425 if (nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 426 div_s64(ffo.ffo, 1000000))) 427 return -EMSGSIZE; 428 return nla_put_sint(msg, 429 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, 430 ffo.ffo); 431 } 432 433 static int dpll_msg_add_measured_freq(struct sk_buff *msg, struct dpll_pin *pin, 434 struct dpll_pin_ref *ref, 435 struct netlink_ext_ack *extack) 436 { 437 const struct dpll_device_ops *dev_ops = dpll_device_ops(ref->dpll); 438 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 439 struct dpll_device *dpll = ref->dpll; 440 enum dpll_feature_state state; 441 u64 measured_freq; 442 int ret; 443 444 if (!ops->measured_freq_get) 445 return 0; 446 ret = dev_ops->freq_monitor_get(dpll, dpll_priv(dpll), 447 &state, extack); 448 if (ret) 449 return ret; 450 if (state == DPLL_FEATURE_STATE_DISABLE) 451 return 0; 452 ret = ops->measured_freq_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 453 dpll, dpll_priv(dpll), &measured_freq, 454 extack); 455 if (ret) 456 return ret; 457 if (nla_put_64bit(msg, DPLL_A_PIN_MEASURED_FREQUENCY, 458 sizeof(measured_freq), &measured_freq, 459 DPLL_A_PIN_PAD)) 460 return -EMSGSIZE; 461 462 return 0; 463 } 464 465 static int 466 dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin, 467 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 468 { 469 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 470 struct dpll_device *dpll = ref->dpll; 471 struct nlattr *nest; 472 int fs, ret; 473 u64 freq; 474 475 if (!ops->frequency_get) 476 return 0; 477 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 478 dpll_priv(dpll), &freq, extack); 479 if (ret) 480 return ret; 481 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY, sizeof(freq), &freq, 482 DPLL_A_PIN_PAD)) 483 return -EMSGSIZE; 484 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) { 485 nest = nla_nest_start(msg, DPLL_A_PIN_FREQUENCY_SUPPORTED); 486 if (!nest) 487 return -EMSGSIZE; 488 freq = pin->prop.freq_supported[fs].min; 489 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, sizeof(freq), 490 &freq, DPLL_A_PIN_PAD)) { 491 nla_nest_cancel(msg, nest); 492 return -EMSGSIZE; 493 } 494 freq = pin->prop.freq_supported[fs].max; 495 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, sizeof(freq), 496 &freq, DPLL_A_PIN_PAD)) { 497 nla_nest_cancel(msg, nest); 498 return -EMSGSIZE; 499 } 500 nla_nest_end(msg, nest); 501 } 502 503 return 0; 504 } 505 506 static int 507 dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpll_pin *pin, 508 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 509 { 510 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 511 struct dpll_device *dpll = ref->dpll; 512 struct dpll_pin_esync esync; 513 struct nlattr *nest; 514 int ret, i; 515 516 if (!ops->esync_get) 517 return 0; 518 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 519 dpll_priv(dpll), &esync, extack); 520 if (ret == -EOPNOTSUPP) 521 return 0; 522 else if (ret) 523 return ret; 524 if (nla_put_64bit(msg, DPLL_A_PIN_ESYNC_FREQUENCY, sizeof(esync.freq), 525 &esync.freq, DPLL_A_PIN_PAD)) 526 return -EMSGSIZE; 527 if (nla_put_u32(msg, DPLL_A_PIN_ESYNC_PULSE, esync.pulse)) 528 return -EMSGSIZE; 529 for (i = 0; i < esync.range_num; i++) { 530 nest = nla_nest_start(msg, 531 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED); 532 if (!nest) 533 return -EMSGSIZE; 534 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, 535 sizeof(esync.range[i].min), 536 &esync.range[i].min, DPLL_A_PIN_PAD)) 537 goto nest_cancel; 538 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, 539 sizeof(esync.range[i].max), 540 &esync.range[i].max, DPLL_A_PIN_PAD)) 541 goto nest_cancel; 542 nla_nest_end(msg, nest); 543 } 544 return 0; 545 546 nest_cancel: 547 nla_nest_cancel(msg, nest); 548 return -EMSGSIZE; 549 } 550 551 static int 552 dpll_msg_add_pin_ref_sync(struct sk_buff *msg, struct dpll_pin *pin, 553 struct dpll_pin_ref *ref, 554 struct netlink_ext_ack *extack) 555 { 556 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 557 struct dpll_device *dpll = ref->dpll; 558 void *pin_priv, *ref_sync_pin_priv; 559 struct dpll_pin *ref_sync_pin; 560 enum dpll_pin_state state; 561 struct nlattr *nest; 562 unsigned long index; 563 int ret; 564 565 pin_priv = dpll_pin_on_dpll_priv(dpll, pin); 566 xa_for_each(&pin->ref_sync_pins, index, ref_sync_pin) { 567 if (!dpll_pin_available(ref_sync_pin)) 568 continue; 569 ref_sync_pin_priv = dpll_pin_on_dpll_priv(dpll, ref_sync_pin); 570 if (WARN_ON(!ops->ref_sync_get)) 571 return -EOPNOTSUPP; 572 ret = ops->ref_sync_get(pin, pin_priv, ref_sync_pin, 573 ref_sync_pin_priv, &state, extack); 574 if (ret) 575 return ret; 576 nest = nla_nest_start(msg, DPLL_A_PIN_REFERENCE_SYNC); 577 if (!nest) 578 return -EMSGSIZE; 579 if (nla_put_s32(msg, DPLL_A_PIN_ID, ref_sync_pin->id)) 580 goto nest_cancel; 581 if (nla_put_s32(msg, DPLL_A_PIN_STATE, state)) 582 goto nest_cancel; 583 nla_nest_end(msg, nest); 584 } 585 return 0; 586 587 nest_cancel: 588 nla_nest_cancel(msg, nest); 589 return -EMSGSIZE; 590 } 591 592 static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) 593 { 594 int fs; 595 596 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) 597 if (freq >= pin->prop.freq_supported[fs].min && 598 freq <= pin->prop.freq_supported[fs].max) 599 return true; 600 return false; 601 } 602 603 static int 604 dpll_msg_add_pin_parents(struct sk_buff *msg, struct dpll_pin *pin, 605 struct dpll_pin_ref *dpll_ref, 606 struct netlink_ext_ack *extack) 607 { 608 enum dpll_pin_state state; 609 struct dpll_pin_ref *ref; 610 struct dpll_pin *ppin; 611 struct nlattr *nest; 612 unsigned long index; 613 int ret; 614 615 xa_for_each(&pin->parent_refs, index, ref) { 616 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 617 void *parent_priv; 618 619 ppin = ref->pin; 620 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, ppin); 621 ret = ops->state_on_pin_get(pin, 622 dpll_pin_on_pin_priv(ppin, pin), 623 ppin, parent_priv, &state, extack); 624 if (ret) 625 return ret; 626 nest = nla_nest_start(msg, DPLL_A_PIN_PARENT_PIN); 627 if (!nest) 628 return -EMSGSIZE; 629 ret = dpll_msg_add_dev_parent_handle(msg, ppin->id); 630 if (ret) 631 goto nest_cancel; 632 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) { 633 ret = -EMSGSIZE; 634 goto nest_cancel; 635 } 636 nla_nest_end(msg, nest); 637 } 638 639 return 0; 640 641 nest_cancel: 642 nla_nest_cancel(msg, nest); 643 return ret; 644 } 645 646 static int 647 dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin, 648 struct netlink_ext_ack *extack) 649 { 650 struct dpll_pin_ref *ref; 651 struct nlattr *attr; 652 unsigned long index; 653 int ret; 654 655 xa_for_each(&pin->dpll_refs, index, ref) { 656 attr = nla_nest_start(msg, DPLL_A_PIN_PARENT_DEVICE); 657 if (!attr) 658 return -EMSGSIZE; 659 ret = dpll_msg_add_dev_parent_handle(msg, ref->dpll->id); 660 if (ret) 661 goto nest_cancel; 662 ret = dpll_msg_add_pin_on_dpll_state(msg, pin, ref, extack); 663 if (ret) 664 goto nest_cancel; 665 ret = dpll_msg_add_pin_operstate(msg, pin, ref, extack); 666 if (ret) 667 goto nest_cancel; 668 ret = dpll_msg_add_pin_prio(msg, pin, ref, extack); 669 if (ret) 670 goto nest_cancel; 671 ret = dpll_msg_add_pin_direction(msg, pin, ref, extack); 672 if (ret) 673 goto nest_cancel; 674 ret = dpll_msg_add_phase_offset(msg, pin, ref, extack); 675 if (ret) 676 goto nest_cancel; 677 ret = dpll_msg_add_ffo(msg, pin, ref, 678 DPLL_FFO_PIN_DEVICE, extack); 679 if (ret) 680 goto nest_cancel; 681 nla_nest_end(msg, attr); 682 } 683 684 return 0; 685 686 nest_cancel: 687 nla_nest_end(msg, attr); 688 return ret; 689 } 690 691 static int 692 dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, 693 struct netlink_ext_ack *extack) 694 { 695 const struct dpll_pin_properties *prop = &pin->prop; 696 struct dpll_pin_ref *ref; 697 int ret; 698 699 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 700 ASSERT_NOT_NULL(ref); 701 702 ret = dpll_msg_add_pin_handle(msg, pin); 703 if (ret) 704 return ret; 705 if (nla_put_string(msg, DPLL_A_PIN_MODULE_NAME, 706 module_name(pin->module))) 707 return -EMSGSIZE; 708 if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id), 709 &pin->clock_id, DPLL_A_PIN_PAD)) 710 return -EMSGSIZE; 711 if (prop->board_label && 712 nla_put_string(msg, DPLL_A_PIN_BOARD_LABEL, prop->board_label)) 713 return -EMSGSIZE; 714 if (prop->panel_label && 715 nla_put_string(msg, DPLL_A_PIN_PANEL_LABEL, prop->panel_label)) 716 return -EMSGSIZE; 717 if (prop->package_label && 718 nla_put_string(msg, DPLL_A_PIN_PACKAGE_LABEL, 719 prop->package_label)) 720 return -EMSGSIZE; 721 if (nla_put_u32(msg, DPLL_A_PIN_TYPE, prop->type)) 722 return -EMSGSIZE; 723 if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities)) 724 return -EMSGSIZE; 725 ret = dpll_msg_add_pin_freq(msg, pin, ref, extack); 726 if (ret) 727 return ret; 728 if (prop->phase_gran && 729 nla_put_u32(msg, DPLL_A_PIN_PHASE_ADJUST_GRAN, 730 prop->phase_gran)) 731 return -EMSGSIZE; 732 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN, 733 prop->phase_range.min)) 734 return -EMSGSIZE; 735 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX, 736 prop->phase_range.max)) 737 return -EMSGSIZE; 738 ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack); 739 if (ret) 740 return ret; 741 ret = dpll_msg_add_ffo(msg, pin, ref, 742 DPLL_FFO_PORT_RXTX_RATE, extack); 743 if (ret) 744 return ret; 745 ret = dpll_msg_add_measured_freq(msg, pin, ref, extack); 746 if (ret) 747 return ret; 748 ret = dpll_msg_add_pin_esync(msg, pin, ref, extack); 749 if (ret) 750 return ret; 751 if (!xa_empty(&pin->ref_sync_pins)) 752 ret = dpll_msg_add_pin_ref_sync(msg, pin, ref, extack); 753 if (ret) 754 return ret; 755 if (xa_empty(&pin->parent_refs)) 756 ret = dpll_msg_add_pin_dplls(msg, pin, extack); 757 else 758 ret = dpll_msg_add_pin_parents(msg, pin, ref, extack); 759 760 return ret; 761 } 762 763 static int 764 dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg, 765 struct netlink_ext_ack *extack) 766 { 767 int ret; 768 769 ret = dpll_msg_add_dev_handle(msg, dpll); 770 if (ret) 771 return ret; 772 if (nla_put_string(msg, DPLL_A_MODULE_NAME, module_name(dpll->module))) 773 return -EMSGSIZE; 774 if (nla_put_64bit(msg, DPLL_A_CLOCK_ID, sizeof(dpll->clock_id), 775 &dpll->clock_id, DPLL_A_PAD)) 776 return -EMSGSIZE; 777 ret = dpll_msg_add_temp(msg, dpll, extack); 778 if (ret) 779 return ret; 780 ret = dpll_msg_add_lock_status(msg, dpll, extack); 781 if (ret) 782 return ret; 783 ret = dpll_msg_add_clock_quality_level(msg, dpll, extack); 784 if (ret) 785 return ret; 786 ret = dpll_msg_add_mode(msg, dpll, extack); 787 if (ret) 788 return ret; 789 ret = dpll_msg_add_mode_supported(msg, dpll, extack); 790 if (ret) 791 return ret; 792 if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type)) 793 return -EMSGSIZE; 794 ret = dpll_msg_add_phase_offset_monitor(msg, dpll, extack); 795 if (ret) 796 return ret; 797 ret = dpll_msg_add_phase_offset_avg_factor(msg, dpll, extack); 798 if (ret) 799 return ret; 800 ret = dpll_msg_add_freq_monitor(msg, dpll, extack); 801 if (ret) 802 return ret; 803 804 return 0; 805 } 806 807 static int 808 dpll_device_event_send(enum dpll_cmd event, struct dpll_device *dpll) 809 { 810 struct sk_buff *msg; 811 int ret = -ENOMEM; 812 void *hdr; 813 814 if (WARN_ON(!xa_get_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED))) 815 return -ENODEV; 816 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 817 if (!msg) 818 return -ENOMEM; 819 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 820 if (!hdr) 821 goto err_free_msg; 822 ret = dpll_device_get_one(dpll, msg, NULL); 823 if (ret) 824 goto err_cancel_msg; 825 genlmsg_end(msg, hdr); 826 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 827 828 return 0; 829 830 err_cancel_msg: 831 genlmsg_cancel(msg, hdr); 832 err_free_msg: 833 nlmsg_free(msg); 834 835 return ret; 836 } 837 838 int dpll_device_create_ntf(struct dpll_device *dpll) 839 { 840 dpll_device_notify(dpll, DPLL_DEVICE_CREATED); 841 return dpll_device_event_send(DPLL_CMD_DEVICE_CREATE_NTF, dpll); 842 } 843 844 int dpll_device_delete_ntf(struct dpll_device *dpll) 845 { 846 dpll_device_notify(dpll, DPLL_DEVICE_DELETED); 847 return dpll_device_event_send(DPLL_CMD_DEVICE_DELETE_NTF, dpll); 848 } 849 850 static int 851 __dpll_device_change_ntf(struct dpll_device *dpll) 852 { 853 dpll_device_notify(dpll, DPLL_DEVICE_CHANGED); 854 return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); 855 } 856 857 /** 858 * dpll_device_change_ntf - notify that the dpll device has been changed 859 * @dpll: registered dpll pointer 860 * 861 * Context: acquires and holds a dpll_lock. 862 * Return: 0 if succeeds, error code otherwise. 863 */ 864 int dpll_device_change_ntf(struct dpll_device *dpll) 865 { 866 int ret; 867 868 mutex_lock(&dpll_lock); 869 ret = __dpll_device_change_ntf(dpll); 870 mutex_unlock(&dpll_lock); 871 872 return ret; 873 } 874 EXPORT_SYMBOL_GPL(dpll_device_change_ntf); 875 876 static int 877 dpll_pin_event_send(enum dpll_cmd event, struct dpll_pin *pin) 878 { 879 struct sk_buff *msg; 880 int ret = -ENOMEM; 881 void *hdr; 882 883 if (!dpll_pin_available(pin)) 884 return -ENODEV; 885 886 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 887 if (!msg) 888 return -ENOMEM; 889 890 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 891 if (!hdr) 892 goto err_free_msg; 893 ret = dpll_cmd_pin_get_one(msg, pin, NULL); 894 if (ret) 895 goto err_cancel_msg; 896 genlmsg_end(msg, hdr); 897 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 898 899 return 0; 900 901 err_cancel_msg: 902 genlmsg_cancel(msg, hdr); 903 err_free_msg: 904 nlmsg_free(msg); 905 906 return ret; 907 } 908 909 int dpll_pin_create_ntf(struct dpll_pin *pin) 910 { 911 dpll_pin_notify(pin, DPLL_PIN_CREATED); 912 return dpll_pin_event_send(DPLL_CMD_PIN_CREATE_NTF, pin); 913 } 914 915 int dpll_pin_delete_ntf(struct dpll_pin *pin) 916 { 917 dpll_pin_notify(pin, DPLL_PIN_DELETED); 918 return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); 919 } 920 921 /** 922 * __dpll_pin_change_ntf - notify that the pin has been changed 923 * @pin: registered pin pointer 924 * 925 * Context: caller must hold dpll_lock. Suitable for use inside pin 926 * callbacks which are already invoked under dpll_lock. 927 * Return: 0 if succeeds, error code otherwise. 928 */ 929 int __dpll_pin_change_ntf(struct dpll_pin *pin) 930 { 931 lockdep_assert_held(&dpll_lock); 932 dpll_pin_notify(pin, DPLL_PIN_CHANGED); 933 return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); 934 } 935 EXPORT_SYMBOL_GPL(__dpll_pin_change_ntf); 936 937 /** 938 * dpll_pin_change_ntf - notify that the pin has been changed 939 * @pin: registered pin pointer 940 * 941 * Context: acquires and holds a dpll_lock. 942 * Return: 0 if succeeds, error code otherwise. 943 */ 944 int dpll_pin_change_ntf(struct dpll_pin *pin) 945 { 946 int ret; 947 948 mutex_lock(&dpll_lock); 949 ret = __dpll_pin_change_ntf(pin); 950 mutex_unlock(&dpll_lock); 951 952 return ret; 953 } 954 EXPORT_SYMBOL_GPL(dpll_pin_change_ntf); 955 956 static int 957 dpll_mode_set(struct dpll_device *dpll, struct nlattr *a, 958 struct netlink_ext_ack *extack) 959 { 960 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 961 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 962 enum dpll_mode mode = nla_get_u32(a), old_mode; 963 int ret; 964 965 if (!(ops->mode_set && ops->supported_modes_get)) { 966 NL_SET_ERR_MSG_ATTR(extack, a, 967 "dpll device does not support mode switch"); 968 return -EOPNOTSUPP; 969 } 970 971 ret = ops->mode_get(dpll, dpll_priv(dpll), &old_mode, extack); 972 if (ret) { 973 NL_SET_ERR_MSG(extack, "unable to get current mode"); 974 return ret; 975 } 976 977 if (mode == old_mode) 978 return 0; 979 980 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, extack); 981 if (ret) { 982 NL_SET_ERR_MSG(extack, "unable to get supported modes"); 983 return ret; 984 } 985 986 if (!test_bit(mode, modes)) { 987 NL_SET_ERR_MSG(extack, 988 "dpll device does not support requested mode"); 989 return -EINVAL; 990 } 991 992 return ops->mode_set(dpll, dpll_priv(dpll), mode, extack); 993 } 994 995 static int 996 dpll_phase_offset_monitor_set(struct dpll_device *dpll, struct nlattr *a, 997 struct netlink_ext_ack *extack) 998 { 999 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1000 enum dpll_feature_state state = nla_get_u32(a), old_state; 1001 int ret; 1002 1003 if (!(ops->phase_offset_monitor_set && ops->phase_offset_monitor_get)) { 1004 NL_SET_ERR_MSG_ATTR(extack, a, "dpll device not capable of phase offset monitor"); 1005 return -EOPNOTSUPP; 1006 } 1007 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), &old_state, 1008 extack); 1009 if (ret) { 1010 NL_SET_ERR_MSG(extack, "unable to get current state of phase offset monitor"); 1011 return ret; 1012 } 1013 if (state == old_state) 1014 return 0; 1015 1016 return ops->phase_offset_monitor_set(dpll, dpll_priv(dpll), state, 1017 extack); 1018 } 1019 1020 static int 1021 dpll_phase_offset_avg_factor_set(struct dpll_device *dpll, struct nlattr *a, 1022 struct netlink_ext_ack *extack) 1023 { 1024 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1025 u32 factor = nla_get_u32(a); 1026 1027 if (!ops->phase_offset_avg_factor_set) { 1028 NL_SET_ERR_MSG_ATTR(extack, a, 1029 "device not capable of changing phase offset average factor"); 1030 return -EOPNOTSUPP; 1031 } 1032 1033 return ops->phase_offset_avg_factor_set(dpll, dpll_priv(dpll), factor, 1034 extack); 1035 } 1036 1037 static int 1038 dpll_freq_monitor_set(struct dpll_device *dpll, struct nlattr *a, 1039 struct netlink_ext_ack *extack) 1040 { 1041 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1042 enum dpll_feature_state state = nla_get_u32(a), old_state; 1043 int ret; 1044 1045 if (!(ops->freq_monitor_set && ops->freq_monitor_get)) { 1046 NL_SET_ERR_MSG_ATTR(extack, a, 1047 "dpll device not capable of frequency monitor"); 1048 return -EOPNOTSUPP; 1049 } 1050 ret = ops->freq_monitor_get(dpll, dpll_priv(dpll), &old_state, 1051 extack); 1052 if (ret) { 1053 NL_SET_ERR_MSG(extack, 1054 "unable to get current state of frequency monitor"); 1055 return ret; 1056 } 1057 if (state == old_state) 1058 return 0; 1059 1060 return ops->freq_monitor_set(dpll, dpll_priv(dpll), state, extack); 1061 } 1062 1063 static int 1064 dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a, 1065 struct netlink_ext_ack *extack) 1066 { 1067 u64 freq = nla_get_u64(a), old_freq; 1068 struct dpll_pin_ref *ref, *failed; 1069 const struct dpll_pin_ops *ops; 1070 struct dpll_device *dpll; 1071 unsigned long i; 1072 int ret; 1073 1074 if (!dpll_pin_is_freq_supported(pin, freq)) { 1075 NL_SET_ERR_MSG_ATTR(extack, a, "frequency is not supported by the device"); 1076 return -EINVAL; 1077 } 1078 1079 xa_for_each(&pin->dpll_refs, i, ref) { 1080 ops = dpll_pin_ops(ref); 1081 if (!ops->frequency_set || !ops->frequency_get) { 1082 NL_SET_ERR_MSG(extack, "frequency set not supported by the device"); 1083 return -EOPNOTSUPP; 1084 } 1085 } 1086 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1087 ops = dpll_pin_ops(ref); 1088 dpll = ref->dpll; 1089 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1090 dpll_priv(dpll), &old_freq, extack); 1091 if (ret) { 1092 NL_SET_ERR_MSG(extack, "unable to get old frequency value"); 1093 return ret; 1094 } 1095 if (freq == old_freq) 1096 return 0; 1097 1098 xa_for_each(&pin->dpll_refs, i, ref) { 1099 ops = dpll_pin_ops(ref); 1100 dpll = ref->dpll; 1101 ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1102 dpll, dpll_priv(dpll), freq, extack); 1103 if (ret) { 1104 failed = ref; 1105 NL_SET_ERR_MSG_FMT(extack, "frequency set failed for dpll_id:%u", 1106 dpll->id); 1107 goto rollback; 1108 } 1109 } 1110 __dpll_pin_change_ntf(pin); 1111 1112 return 0; 1113 1114 rollback: 1115 xa_for_each(&pin->dpll_refs, i, ref) { 1116 if (ref == failed) 1117 break; 1118 ops = dpll_pin_ops(ref); 1119 dpll = ref->dpll; 1120 if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1121 dpll, dpll_priv(dpll), old_freq, extack)) 1122 NL_SET_ERR_MSG(extack, "set frequency rollback failed"); 1123 } 1124 return ret; 1125 } 1126 1127 static int 1128 dpll_pin_esync_set(struct dpll_pin *pin, struct nlattr *a, 1129 struct netlink_ext_ack *extack) 1130 { 1131 struct dpll_pin_ref *ref, *failed; 1132 const struct dpll_pin_ops *ops; 1133 struct dpll_pin_esync esync; 1134 u64 freq = nla_get_u64(a); 1135 struct dpll_device *dpll; 1136 bool supported = false; 1137 unsigned long i; 1138 int ret; 1139 1140 xa_for_each(&pin->dpll_refs, i, ref) { 1141 ops = dpll_pin_ops(ref); 1142 if (!ops->esync_set || !ops->esync_get) { 1143 NL_SET_ERR_MSG(extack, 1144 "embedded sync feature is not supported by this device"); 1145 return -EOPNOTSUPP; 1146 } 1147 } 1148 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1149 ops = dpll_pin_ops(ref); 1150 dpll = ref->dpll; 1151 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1152 dpll_priv(dpll), &esync, extack); 1153 if (ret) { 1154 NL_SET_ERR_MSG(extack, "unable to get current embedded sync frequency value"); 1155 return ret; 1156 } 1157 if (freq == esync.freq) 1158 return 0; 1159 for (i = 0; i < esync.range_num; i++) 1160 if (freq <= esync.range[i].max && freq >= esync.range[i].min) 1161 supported = true; 1162 if (!supported) { 1163 NL_SET_ERR_MSG_ATTR(extack, a, 1164 "requested embedded sync frequency value is not supported by this device"); 1165 return -EINVAL; 1166 } 1167 1168 xa_for_each(&pin->dpll_refs, i, ref) { 1169 void *pin_dpll_priv; 1170 1171 ops = dpll_pin_ops(ref); 1172 dpll = ref->dpll; 1173 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1174 ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1175 freq, extack); 1176 if (ret) { 1177 failed = ref; 1178 NL_SET_ERR_MSG_FMT(extack, 1179 "embedded sync frequency set failed for dpll_id: %u", 1180 dpll->id); 1181 goto rollback; 1182 } 1183 } 1184 __dpll_pin_change_ntf(pin); 1185 1186 return 0; 1187 1188 rollback: 1189 xa_for_each(&pin->dpll_refs, i, ref) { 1190 void *pin_dpll_priv; 1191 1192 if (ref == failed) 1193 break; 1194 ops = dpll_pin_ops(ref); 1195 dpll = ref->dpll; 1196 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1197 if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1198 esync.freq, extack)) 1199 NL_SET_ERR_MSG(extack, "set embedded sync frequency rollback failed"); 1200 } 1201 return ret; 1202 } 1203 1204 static int 1205 dpll_pin_ref_sync_state_set(struct dpll_pin *pin, 1206 unsigned long ref_sync_pin_idx, 1207 const enum dpll_pin_state state, 1208 struct netlink_ext_ack *extack) 1209 1210 { 1211 struct dpll_pin_ref *ref, *failed; 1212 const struct dpll_pin_ops *ops; 1213 enum dpll_pin_state old_state; 1214 struct dpll_pin *ref_sync_pin; 1215 struct dpll_device *dpll; 1216 unsigned long i; 1217 int ret; 1218 1219 ref_sync_pin = xa_find(&pin->ref_sync_pins, &ref_sync_pin_idx, 1220 ULONG_MAX, XA_PRESENT); 1221 if (!ref_sync_pin) { 1222 NL_SET_ERR_MSG(extack, "reference sync pin not found"); 1223 return -EINVAL; 1224 } 1225 if (!dpll_pin_available(ref_sync_pin)) { 1226 NL_SET_ERR_MSG(extack, "reference sync pin not available"); 1227 return -EINVAL; 1228 } 1229 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1230 ASSERT_NOT_NULL(ref); 1231 ops = dpll_pin_ops(ref); 1232 if (!ops->ref_sync_set || !ops->ref_sync_get) { 1233 NL_SET_ERR_MSG(extack, "reference sync not supported by this pin"); 1234 return -EOPNOTSUPP; 1235 } 1236 dpll = ref->dpll; 1237 ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1238 ref_sync_pin, 1239 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1240 &old_state, extack); 1241 if (ret) { 1242 NL_SET_ERR_MSG(extack, "unable to get old reference sync state"); 1243 return ret; 1244 } 1245 if (state == old_state) 1246 return 0; 1247 xa_for_each(&pin->dpll_refs, i, ref) { 1248 ops = dpll_pin_ops(ref); 1249 dpll = ref->dpll; 1250 ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1251 ref_sync_pin, 1252 dpll_pin_on_dpll_priv(dpll, 1253 ref_sync_pin), 1254 state, extack); 1255 if (ret) { 1256 failed = ref; 1257 NL_SET_ERR_MSG_FMT(extack, "reference sync set failed for dpll_id:%u", 1258 dpll->id); 1259 goto rollback; 1260 } 1261 } 1262 __dpll_pin_change_ntf(pin); 1263 1264 return 0; 1265 1266 rollback: 1267 xa_for_each(&pin->dpll_refs, i, ref) { 1268 if (ref == failed) 1269 break; 1270 ops = dpll_pin_ops(ref); 1271 dpll = ref->dpll; 1272 if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1273 ref_sync_pin, 1274 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1275 old_state, extack)) 1276 NL_SET_ERR_MSG(extack, "set reference sync rollback failed"); 1277 } 1278 return ret; 1279 } 1280 1281 static int 1282 dpll_pin_ref_sync_set(struct dpll_pin *pin, struct nlattr *nest, 1283 struct netlink_ext_ack *extack) 1284 { 1285 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1286 enum dpll_pin_state state; 1287 u32 sync_pin_id; 1288 1289 nla_parse_nested(tb, DPLL_A_PIN_MAX, nest, 1290 dpll_reference_sync_nl_policy, extack); 1291 if (!tb[DPLL_A_PIN_ID]) { 1292 NL_SET_ERR_MSG(extack, "sync pin id expected"); 1293 return -EINVAL; 1294 } 1295 sync_pin_id = nla_get_u32(tb[DPLL_A_PIN_ID]); 1296 1297 if (!tb[DPLL_A_PIN_STATE]) { 1298 NL_SET_ERR_MSG(extack, "sync pin state expected"); 1299 return -EINVAL; 1300 } 1301 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1302 1303 return dpll_pin_ref_sync_state_set(pin, sync_pin_id, state, extack); 1304 } 1305 1306 static int 1307 dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, 1308 enum dpll_pin_state state, 1309 struct netlink_ext_ack *extack) 1310 { 1311 struct dpll_pin_ref *parent_ref; 1312 const struct dpll_pin_ops *ops; 1313 struct dpll_pin_ref *dpll_ref; 1314 void *pin_priv, *parent_priv; 1315 struct dpll_pin *parent; 1316 unsigned long i; 1317 int ret; 1318 1319 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1320 pin->prop.capabilities)) { 1321 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1322 return -EOPNOTSUPP; 1323 } 1324 parent = xa_load(&dpll_pin_xa, parent_idx); 1325 if (!parent) 1326 return -EINVAL; 1327 parent_ref = xa_load(&pin->parent_refs, parent->pin_idx); 1328 if (!parent_ref) 1329 return -EINVAL; 1330 xa_for_each(&parent->dpll_refs, i, dpll_ref) { 1331 ops = dpll_pin_ops(parent_ref); 1332 if (!ops->state_on_pin_set) 1333 return -EOPNOTSUPP; 1334 pin_priv = dpll_pin_on_pin_priv(parent, pin); 1335 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, parent); 1336 ret = ops->state_on_pin_set(pin, pin_priv, parent, parent_priv, 1337 state, extack); 1338 if (ret) 1339 return ret; 1340 } 1341 __dpll_pin_change_ntf(pin); 1342 1343 return 0; 1344 } 1345 1346 static int 1347 dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin, 1348 enum dpll_pin_state state, 1349 struct netlink_ext_ack *extack) 1350 { 1351 const struct dpll_pin_ops *ops; 1352 struct dpll_pin_ref *ref; 1353 int ret; 1354 1355 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1356 pin->prop.capabilities)) { 1357 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1358 return -EOPNOTSUPP; 1359 } 1360 ref = xa_load(&pin->dpll_refs, dpll->id); 1361 ASSERT_NOT_NULL(ref); 1362 ops = dpll_pin_ops(ref); 1363 if (!ops->state_on_dpll_set) 1364 return -EOPNOTSUPP; 1365 ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1366 dpll, dpll_priv(dpll), state, extack); 1367 if (ret) 1368 return ret; 1369 __dpll_pin_change_ntf(pin); 1370 1371 return 0; 1372 } 1373 1374 static int 1375 dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin, 1376 u32 prio, struct netlink_ext_ack *extack) 1377 { 1378 const struct dpll_pin_ops *ops; 1379 struct dpll_pin_ref *ref; 1380 int ret; 1381 1382 if (!(DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE & 1383 pin->prop.capabilities)) { 1384 NL_SET_ERR_MSG(extack, "prio changing is not allowed"); 1385 return -EOPNOTSUPP; 1386 } 1387 ref = xa_load(&pin->dpll_refs, dpll->id); 1388 ASSERT_NOT_NULL(ref); 1389 ops = dpll_pin_ops(ref); 1390 if (!ops->prio_set) 1391 return -EOPNOTSUPP; 1392 ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1393 dpll_priv(dpll), prio, extack); 1394 if (ret) 1395 return ret; 1396 __dpll_pin_change_ntf(pin); 1397 1398 return 0; 1399 } 1400 1401 static int 1402 dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll, 1403 enum dpll_pin_direction direction, 1404 struct netlink_ext_ack *extack) 1405 { 1406 const struct dpll_pin_ops *ops; 1407 struct dpll_pin_ref *ref; 1408 int ret; 1409 1410 if (!(DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE & 1411 pin->prop.capabilities)) { 1412 NL_SET_ERR_MSG(extack, "direction changing is not allowed"); 1413 return -EOPNOTSUPP; 1414 } 1415 ref = xa_load(&pin->dpll_refs, dpll->id); 1416 ASSERT_NOT_NULL(ref); 1417 ops = dpll_pin_ops(ref); 1418 if (!ops->direction_set) 1419 return -EOPNOTSUPP; 1420 ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1421 dpll, dpll_priv(dpll), direction, extack); 1422 if (ret) 1423 return ret; 1424 __dpll_pin_change_ntf(pin); 1425 1426 return 0; 1427 } 1428 1429 static int 1430 dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr, 1431 struct netlink_ext_ack *extack) 1432 { 1433 struct dpll_pin_ref *ref, *failed; 1434 const struct dpll_pin_ops *ops; 1435 s32 phase_adj, old_phase_adj; 1436 struct dpll_device *dpll; 1437 unsigned long i; 1438 int ret; 1439 1440 phase_adj = nla_get_s32(phase_adj_attr); 1441 if (phase_adj > pin->prop.phase_range.max || 1442 phase_adj < pin->prop.phase_range.min) { 1443 NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr, 1444 "phase adjust value of out range"); 1445 return -EINVAL; 1446 } 1447 if (pin->prop.phase_gran && phase_adj % (s32)pin->prop.phase_gran) { 1448 NL_SET_ERR_MSG_ATTR_FMT(extack, phase_adj_attr, 1449 "phase adjust value not multiple of %u", 1450 pin->prop.phase_gran); 1451 return -EINVAL; 1452 } 1453 1454 xa_for_each(&pin->dpll_refs, i, ref) { 1455 ops = dpll_pin_ops(ref); 1456 if (!ops->phase_adjust_set || !ops->phase_adjust_get) { 1457 NL_SET_ERR_MSG(extack, "phase adjust not supported"); 1458 return -EOPNOTSUPP; 1459 } 1460 } 1461 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1462 ops = dpll_pin_ops(ref); 1463 dpll = ref->dpll; 1464 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1465 dpll, dpll_priv(dpll), &old_phase_adj, 1466 extack); 1467 if (ret) { 1468 NL_SET_ERR_MSG(extack, "unable to get old phase adjust value"); 1469 return ret; 1470 } 1471 if (phase_adj == old_phase_adj) 1472 return 0; 1473 1474 xa_for_each(&pin->dpll_refs, i, ref) { 1475 ops = dpll_pin_ops(ref); 1476 dpll = ref->dpll; 1477 ret = ops->phase_adjust_set(pin, 1478 dpll_pin_on_dpll_priv(dpll, pin), 1479 dpll, dpll_priv(dpll), phase_adj, 1480 extack); 1481 if (ret) { 1482 failed = ref; 1483 NL_SET_ERR_MSG_FMT(extack, 1484 "phase adjust set failed for dpll_id:%u", 1485 dpll->id); 1486 goto rollback; 1487 } 1488 } 1489 __dpll_pin_change_ntf(pin); 1490 1491 return 0; 1492 1493 rollback: 1494 xa_for_each(&pin->dpll_refs, i, ref) { 1495 if (ref == failed) 1496 break; 1497 ops = dpll_pin_ops(ref); 1498 dpll = ref->dpll; 1499 if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1500 dpll, dpll_priv(dpll), old_phase_adj, 1501 extack)) 1502 NL_SET_ERR_MSG(extack, "set phase adjust rollback failed"); 1503 } 1504 return ret; 1505 } 1506 1507 static int 1508 dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1509 struct netlink_ext_ack *extack) 1510 { 1511 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1512 enum dpll_pin_direction direction; 1513 enum dpll_pin_state state; 1514 struct dpll_pin_ref *ref; 1515 struct dpll_device *dpll; 1516 u32 pdpll_idx, prio; 1517 int ret; 1518 1519 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1520 dpll_pin_parent_device_nl_policy, extack); 1521 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1522 NL_SET_ERR_MSG(extack, "device parent id expected"); 1523 return -EINVAL; 1524 } 1525 pdpll_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1526 dpll = xa_load(&dpll_device_xa, pdpll_idx); 1527 if (!dpll) { 1528 NL_SET_ERR_MSG(extack, "parent device not found"); 1529 return -EINVAL; 1530 } 1531 ref = xa_load(&pin->dpll_refs, dpll->id); 1532 if (!ref) { 1533 NL_SET_ERR_MSG(extack, "pin not connected to given parent device"); 1534 return -EINVAL; 1535 } 1536 if (tb[DPLL_A_PIN_STATE]) { 1537 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1538 ret = dpll_pin_state_set(dpll, pin, state, extack); 1539 if (ret) 1540 return ret; 1541 } 1542 if (tb[DPLL_A_PIN_PRIO]) { 1543 prio = nla_get_u32(tb[DPLL_A_PIN_PRIO]); 1544 ret = dpll_pin_prio_set(dpll, pin, prio, extack); 1545 if (ret) 1546 return ret; 1547 } 1548 if (tb[DPLL_A_PIN_DIRECTION]) { 1549 direction = nla_get_u32(tb[DPLL_A_PIN_DIRECTION]); 1550 ret = dpll_pin_direction_set(pin, dpll, direction, extack); 1551 if (ret) 1552 return ret; 1553 } 1554 return 0; 1555 } 1556 1557 static int 1558 dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1559 struct netlink_ext_ack *extack) 1560 { 1561 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1562 u32 ppin_idx; 1563 int ret; 1564 1565 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1566 dpll_pin_parent_pin_nl_policy, extack); 1567 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1568 NL_SET_ERR_MSG(extack, "device parent id expected"); 1569 return -EINVAL; 1570 } 1571 ppin_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1572 1573 if (tb[DPLL_A_PIN_STATE]) { 1574 enum dpll_pin_state state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1575 1576 ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack); 1577 if (ret) 1578 return ret; 1579 } 1580 1581 return 0; 1582 } 1583 1584 static int 1585 dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info) 1586 { 1587 struct nlattr *a; 1588 int rem, ret; 1589 1590 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1591 genlmsg_len(info->genlhdr), rem) { 1592 switch (nla_type(a)) { 1593 case DPLL_A_PIN_FREQUENCY: 1594 ret = dpll_pin_freq_set(pin, a, info->extack); 1595 if (ret) 1596 return ret; 1597 break; 1598 case DPLL_A_PIN_PHASE_ADJUST: 1599 ret = dpll_pin_phase_adj_set(pin, a, info->extack); 1600 if (ret) 1601 return ret; 1602 break; 1603 case DPLL_A_PIN_PARENT_DEVICE: 1604 ret = dpll_pin_parent_device_set(pin, a, info->extack); 1605 if (ret) 1606 return ret; 1607 break; 1608 case DPLL_A_PIN_PARENT_PIN: 1609 ret = dpll_pin_parent_pin_set(pin, a, info->extack); 1610 if (ret) 1611 return ret; 1612 break; 1613 case DPLL_A_PIN_ESYNC_FREQUENCY: 1614 ret = dpll_pin_esync_set(pin, a, info->extack); 1615 if (ret) 1616 return ret; 1617 break; 1618 case DPLL_A_PIN_REFERENCE_SYNC: 1619 ret = dpll_pin_ref_sync_set(pin, a, info->extack); 1620 if (ret) 1621 return ret; 1622 break; 1623 } 1624 } 1625 1626 return 0; 1627 } 1628 1629 static struct dpll_pin * 1630 dpll_pin_find(u64 clock_id, struct nlattr *mod_name_attr, 1631 enum dpll_pin_type type, struct nlattr *board_label, 1632 struct nlattr *panel_label, struct nlattr *package_label, 1633 struct netlink_ext_ack *extack) 1634 { 1635 bool board_match, panel_match, package_match; 1636 struct dpll_pin *pin_match = NULL, *pin; 1637 const struct dpll_pin_properties *prop; 1638 bool cid_match, mod_match, type_match; 1639 unsigned long i; 1640 1641 xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) { 1642 prop = &pin->prop; 1643 cid_match = clock_id ? pin->clock_id == clock_id : true; 1644 mod_match = mod_name_attr && module_name(pin->module) ? 1645 !nla_strcmp(mod_name_attr, 1646 module_name(pin->module)) : true; 1647 type_match = type ? prop->type == type : true; 1648 board_match = board_label ? (prop->board_label ? 1649 !nla_strcmp(board_label, prop->board_label) : false) : 1650 true; 1651 panel_match = panel_label ? (prop->panel_label ? 1652 !nla_strcmp(panel_label, prop->panel_label) : false) : 1653 true; 1654 package_match = package_label ? (prop->package_label ? 1655 !nla_strcmp(package_label, prop->package_label) : 1656 false) : true; 1657 if (cid_match && mod_match && type_match && board_match && 1658 panel_match && package_match) { 1659 if (pin_match) { 1660 NL_SET_ERR_MSG(extack, "multiple matches"); 1661 return ERR_PTR(-EINVAL); 1662 } 1663 pin_match = pin; 1664 } 1665 } 1666 if (!pin_match) { 1667 NL_SET_ERR_MSG(extack, "not found"); 1668 return ERR_PTR(-ENODEV); 1669 } 1670 return pin_match; 1671 } 1672 1673 static struct dpll_pin *dpll_pin_find_from_nlattr(struct genl_info *info) 1674 { 1675 struct nlattr *attr, *mod_name_attr = NULL, *board_label_attr = NULL, 1676 *panel_label_attr = NULL, *package_label_attr = NULL; 1677 enum dpll_pin_type type = 0; 1678 u64 clock_id = 0; 1679 int rem = 0; 1680 1681 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1682 genlmsg_len(info->genlhdr), rem) { 1683 switch (nla_type(attr)) { 1684 case DPLL_A_PIN_CLOCK_ID: 1685 if (clock_id) 1686 goto duplicated_attr; 1687 clock_id = nla_get_u64(attr); 1688 break; 1689 case DPLL_A_PIN_MODULE_NAME: 1690 if (mod_name_attr) 1691 goto duplicated_attr; 1692 mod_name_attr = attr; 1693 break; 1694 case DPLL_A_PIN_TYPE: 1695 if (type) 1696 goto duplicated_attr; 1697 type = nla_get_u32(attr); 1698 break; 1699 case DPLL_A_PIN_BOARD_LABEL: 1700 if (board_label_attr) 1701 goto duplicated_attr; 1702 board_label_attr = attr; 1703 break; 1704 case DPLL_A_PIN_PANEL_LABEL: 1705 if (panel_label_attr) 1706 goto duplicated_attr; 1707 panel_label_attr = attr; 1708 break; 1709 case DPLL_A_PIN_PACKAGE_LABEL: 1710 if (package_label_attr) 1711 goto duplicated_attr; 1712 package_label_attr = attr; 1713 break; 1714 default: 1715 break; 1716 } 1717 } 1718 if (!(clock_id || mod_name_attr || board_label_attr || 1719 panel_label_attr || package_label_attr)) { 1720 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1721 return ERR_PTR(-EINVAL); 1722 } 1723 return dpll_pin_find(clock_id, mod_name_attr, type, board_label_attr, 1724 panel_label_attr, package_label_attr, 1725 info->extack); 1726 duplicated_attr: 1727 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1728 return ERR_PTR(-EINVAL); 1729 } 1730 1731 int dpll_nl_pin_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1732 { 1733 struct dpll_pin *pin; 1734 struct sk_buff *msg; 1735 struct nlattr *hdr; 1736 int ret; 1737 1738 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1739 if (!msg) 1740 return -ENOMEM; 1741 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1742 DPLL_CMD_PIN_ID_GET); 1743 if (!hdr) { 1744 nlmsg_free(msg); 1745 return -EMSGSIZE; 1746 } 1747 pin = dpll_pin_find_from_nlattr(info); 1748 if (IS_ERR(pin)) { 1749 nlmsg_free(msg); 1750 return PTR_ERR(pin); 1751 } 1752 if (!dpll_pin_available(pin)) { 1753 nlmsg_free(msg); 1754 return -ENODEV; 1755 } 1756 ret = dpll_msg_add_pin_handle(msg, pin); 1757 if (ret) { 1758 nlmsg_free(msg); 1759 return ret; 1760 } 1761 genlmsg_end(msg, hdr); 1762 1763 return genlmsg_reply(msg, info); 1764 } 1765 1766 int dpll_nl_pin_get_doit(struct sk_buff *skb, struct genl_info *info) 1767 { 1768 struct dpll_pin *pin = info->user_ptr[0]; 1769 struct sk_buff *msg; 1770 struct nlattr *hdr; 1771 int ret; 1772 1773 if (!pin) 1774 return -ENODEV; 1775 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1776 if (!msg) 1777 return -ENOMEM; 1778 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1779 DPLL_CMD_PIN_GET); 1780 if (!hdr) { 1781 nlmsg_free(msg); 1782 return -EMSGSIZE; 1783 } 1784 ret = dpll_cmd_pin_get_one(msg, pin, info->extack); 1785 if (ret) { 1786 nlmsg_free(msg); 1787 return ret; 1788 } 1789 genlmsg_end(msg, hdr); 1790 1791 return genlmsg_reply(msg, info); 1792 } 1793 1794 int dpll_nl_pin_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1795 { 1796 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1797 struct dpll_pin *pin; 1798 struct nlattr *hdr; 1799 unsigned long i; 1800 int ret = 0; 1801 1802 mutex_lock(&dpll_lock); 1803 xa_for_each_marked_start(&dpll_pin_xa, i, pin, DPLL_REGISTERED, 1804 ctx->idx) { 1805 if (!dpll_pin_available(pin)) 1806 continue; 1807 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1808 cb->nlh->nlmsg_seq, 1809 &dpll_nl_family, NLM_F_MULTI, 1810 DPLL_CMD_PIN_GET); 1811 if (!hdr) { 1812 ret = -EMSGSIZE; 1813 break; 1814 } 1815 ret = dpll_cmd_pin_get_one(skb, pin, cb->extack); 1816 if (ret) { 1817 genlmsg_cancel(skb, hdr); 1818 break; 1819 } 1820 genlmsg_end(skb, hdr); 1821 } 1822 mutex_unlock(&dpll_lock); 1823 1824 if (ret == -EMSGSIZE) { 1825 ctx->idx = i; 1826 return skb->len; 1827 } 1828 return ret; 1829 } 1830 1831 int dpll_nl_pin_set_doit(struct sk_buff *skb, struct genl_info *info) 1832 { 1833 struct dpll_pin *pin = info->user_ptr[0]; 1834 1835 return dpll_pin_set_from_nlattr(pin, info); 1836 } 1837 1838 static struct dpll_device * 1839 dpll_device_find(u64 clock_id, struct nlattr *mod_name_attr, 1840 enum dpll_type type, struct netlink_ext_ack *extack) 1841 { 1842 struct dpll_device *dpll_match = NULL, *dpll; 1843 bool cid_match, mod_match, type_match; 1844 unsigned long i; 1845 1846 xa_for_each_marked(&dpll_device_xa, i, dpll, DPLL_REGISTERED) { 1847 cid_match = clock_id ? dpll->clock_id == clock_id : true; 1848 mod_match = mod_name_attr ? (module_name(dpll->module) ? 1849 !nla_strcmp(mod_name_attr, 1850 module_name(dpll->module)) : false) : true; 1851 type_match = type ? dpll->type == type : true; 1852 if (cid_match && mod_match && type_match) { 1853 if (dpll_match) { 1854 NL_SET_ERR_MSG(extack, "multiple matches"); 1855 return ERR_PTR(-EINVAL); 1856 } 1857 dpll_match = dpll; 1858 } 1859 } 1860 if (!dpll_match) { 1861 NL_SET_ERR_MSG(extack, "not found"); 1862 return ERR_PTR(-ENODEV); 1863 } 1864 1865 return dpll_match; 1866 } 1867 1868 static struct dpll_device * 1869 dpll_device_find_from_nlattr(struct genl_info *info) 1870 { 1871 struct nlattr *attr, *mod_name_attr = NULL; 1872 enum dpll_type type = 0; 1873 u64 clock_id = 0; 1874 int rem = 0; 1875 1876 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1877 genlmsg_len(info->genlhdr), rem) { 1878 switch (nla_type(attr)) { 1879 case DPLL_A_CLOCK_ID: 1880 if (clock_id) 1881 goto duplicated_attr; 1882 clock_id = nla_get_u64(attr); 1883 break; 1884 case DPLL_A_MODULE_NAME: 1885 if (mod_name_attr) 1886 goto duplicated_attr; 1887 mod_name_attr = attr; 1888 break; 1889 case DPLL_A_TYPE: 1890 if (type) 1891 goto duplicated_attr; 1892 type = nla_get_u32(attr); 1893 break; 1894 default: 1895 break; 1896 } 1897 } 1898 if (!clock_id && !mod_name_attr && !type) { 1899 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1900 return ERR_PTR(-EINVAL); 1901 } 1902 return dpll_device_find(clock_id, mod_name_attr, type, info->extack); 1903 duplicated_attr: 1904 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1905 return ERR_PTR(-EINVAL); 1906 } 1907 1908 int dpll_nl_device_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1909 { 1910 struct dpll_device *dpll; 1911 struct sk_buff *msg; 1912 struct nlattr *hdr; 1913 int ret; 1914 1915 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1916 if (!msg) 1917 return -ENOMEM; 1918 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1919 DPLL_CMD_DEVICE_ID_GET); 1920 if (!hdr) { 1921 nlmsg_free(msg); 1922 return -EMSGSIZE; 1923 } 1924 1925 dpll = dpll_device_find_from_nlattr(info); 1926 if (IS_ERR(dpll)) { 1927 nlmsg_free(msg); 1928 return PTR_ERR(dpll); 1929 } 1930 ret = dpll_msg_add_dev_handle(msg, dpll); 1931 if (ret) { 1932 nlmsg_free(msg); 1933 return ret; 1934 } 1935 genlmsg_end(msg, hdr); 1936 1937 return genlmsg_reply(msg, info); 1938 } 1939 1940 int dpll_nl_device_get_doit(struct sk_buff *skb, struct genl_info *info) 1941 { 1942 struct dpll_device *dpll = info->user_ptr[0]; 1943 struct sk_buff *msg; 1944 struct nlattr *hdr; 1945 int ret; 1946 1947 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1948 if (!msg) 1949 return -ENOMEM; 1950 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1951 DPLL_CMD_DEVICE_GET); 1952 if (!hdr) { 1953 nlmsg_free(msg); 1954 return -EMSGSIZE; 1955 } 1956 1957 ret = dpll_device_get_one(dpll, msg, info->extack); 1958 if (ret) { 1959 nlmsg_free(msg); 1960 return ret; 1961 } 1962 genlmsg_end(msg, hdr); 1963 1964 return genlmsg_reply(msg, info); 1965 } 1966 1967 static int 1968 dpll_set_from_nlattr(struct dpll_device *dpll, struct genl_info *info) 1969 { 1970 struct nlattr *a; 1971 int rem, ret; 1972 1973 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1974 genlmsg_len(info->genlhdr), rem) { 1975 switch (nla_type(a)) { 1976 case DPLL_A_MODE: 1977 ret = dpll_mode_set(dpll, a, info->extack); 1978 if (ret) 1979 return ret; 1980 break; 1981 case DPLL_A_PHASE_OFFSET_MONITOR: 1982 ret = dpll_phase_offset_monitor_set(dpll, a, 1983 info->extack); 1984 if (ret) 1985 return ret; 1986 break; 1987 case DPLL_A_PHASE_OFFSET_AVG_FACTOR: 1988 ret = dpll_phase_offset_avg_factor_set(dpll, a, 1989 info->extack); 1990 if (ret) 1991 return ret; 1992 break; 1993 case DPLL_A_FREQUENCY_MONITOR: 1994 ret = dpll_freq_monitor_set(dpll, a, 1995 info->extack); 1996 if (ret) 1997 return ret; 1998 break; 1999 } 2000 } 2001 2002 return 0; 2003 } 2004 2005 int dpll_nl_device_set_doit(struct sk_buff *skb, struct genl_info *info) 2006 { 2007 struct dpll_device *dpll = info->user_ptr[0]; 2008 2009 return dpll_set_from_nlattr(dpll, info); 2010 } 2011 2012 int dpll_nl_device_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 2013 { 2014 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 2015 struct dpll_device *dpll; 2016 struct nlattr *hdr; 2017 unsigned long i; 2018 int ret = 0; 2019 2020 mutex_lock(&dpll_lock); 2021 xa_for_each_marked_start(&dpll_device_xa, i, dpll, DPLL_REGISTERED, 2022 ctx->idx) { 2023 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 2024 cb->nlh->nlmsg_seq, &dpll_nl_family, 2025 NLM_F_MULTI, DPLL_CMD_DEVICE_GET); 2026 if (!hdr) { 2027 ret = -EMSGSIZE; 2028 break; 2029 } 2030 ret = dpll_device_get_one(dpll, skb, cb->extack); 2031 if (ret) { 2032 genlmsg_cancel(skb, hdr); 2033 break; 2034 } 2035 genlmsg_end(skb, hdr); 2036 } 2037 mutex_unlock(&dpll_lock); 2038 2039 if (ret == -EMSGSIZE) { 2040 ctx->idx = i; 2041 return skb->len; 2042 } 2043 return ret; 2044 } 2045 2046 int dpll_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2047 struct genl_info *info) 2048 { 2049 u32 id; 2050 2051 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_ID)) 2052 return -EINVAL; 2053 2054 mutex_lock(&dpll_lock); 2055 id = nla_get_u32(info->attrs[DPLL_A_ID]); 2056 info->user_ptr[0] = dpll_device_get_by_id(id); 2057 if (!info->user_ptr[0]) { 2058 NL_SET_ERR_MSG(info->extack, "device not found"); 2059 goto unlock; 2060 } 2061 return 0; 2062 unlock: 2063 mutex_unlock(&dpll_lock); 2064 return -ENODEV; 2065 } 2066 2067 void dpll_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2068 struct genl_info *info) 2069 { 2070 mutex_unlock(&dpll_lock); 2071 } 2072 2073 int 2074 dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2075 struct genl_info *info) 2076 { 2077 mutex_lock(&dpll_lock); 2078 2079 return 0; 2080 } 2081 2082 void 2083 dpll_unlock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2084 struct genl_info *info) 2085 { 2086 mutex_unlock(&dpll_lock); 2087 } 2088 2089 int dpll_pin_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2090 struct genl_info *info) 2091 { 2092 int ret; 2093 2094 mutex_lock(&dpll_lock); 2095 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_PIN_ID)) { 2096 ret = -EINVAL; 2097 goto unlock_dev; 2098 } 2099 info->user_ptr[0] = xa_load(&dpll_pin_xa, 2100 nla_get_u32(info->attrs[DPLL_A_PIN_ID])); 2101 if (!info->user_ptr[0] || 2102 !dpll_pin_available(info->user_ptr[0])) { 2103 NL_SET_ERR_MSG(info->extack, "pin not found"); 2104 ret = -ENODEV; 2105 goto unlock_dev; 2106 } 2107 2108 return 0; 2109 2110 unlock_dev: 2111 mutex_unlock(&dpll_lock); 2112 return ret; 2113 } 2114 2115 void dpll_pin_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2116 struct genl_info *info) 2117 { 2118 mutex_unlock(&dpll_lock); 2119 } 2120