1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Generic netlink for DPLL management framework 4 * 5 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 6 * Copyright (c) 2023 Intel and affiliates 7 * 8 */ 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/netdevice.h> 12 #include <net/genetlink.h> 13 #include "dpll_core.h" 14 #include "dpll_netlink.h" 15 #include "dpll_nl.h" 16 #include <uapi/linux/dpll.h> 17 18 #define ASSERT_NOT_NULL(ptr) (WARN_ON(!ptr)) 19 20 #define xa_for_each_marked_start(xa, index, entry, filter, start) \ 21 for (index = start, entry = xa_find(xa, &index, ULONG_MAX, filter); \ 22 entry; entry = xa_find_after(xa, &index, ULONG_MAX, filter)) 23 24 struct dpll_dump_ctx { 25 unsigned long idx; 26 }; 27 28 static struct dpll_dump_ctx *dpll_dump_context(struct netlink_callback *cb) 29 { 30 return (struct dpll_dump_ctx *)cb->ctx; 31 } 32 33 static int 34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) 35 { 36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) 37 return -EMSGSIZE; 38 39 return 0; 40 } 41 42 static int 43 dpll_msg_add_dev_parent_handle(struct sk_buff *msg, u32 id) 44 { 45 if (nla_put_u32(msg, DPLL_A_PIN_PARENT_ID, id)) 46 return -EMSGSIZE; 47 48 return 0; 49 } 50 51 static bool dpll_pin_available(struct dpll_pin *pin) 52 { 53 struct dpll_pin_ref *par_ref; 54 unsigned long i; 55 56 if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) 57 return false; 58 xa_for_each(&pin->parent_refs, i, par_ref) 59 if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, 60 DPLL_REGISTERED)) 61 return true; 62 xa_for_each(&pin->dpll_refs, i, par_ref) 63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, 64 DPLL_REGISTERED)) 65 return true; 66 return false; 67 } 68 69 /** 70 * dpll_msg_add_pin_handle - attach pin handle attribute to a given message 71 * @msg: pointer to sk_buff message to attach a pin handle 72 * @pin: pin pointer 73 * 74 * Return: 75 * * 0 - success 76 * * -EMSGSIZE - no space in message to attach pin handle 77 */ 78 static int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin) 79 { 80 if (!pin) 81 return 0; 82 if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id)) 83 return -EMSGSIZE; 84 return 0; 85 } 86 87 static struct dpll_pin *dpll_netdev_pin(const struct net_device *dev) 88 { 89 return rcu_dereference_rtnl(dev->dpll_pin); 90 } 91 92 int dpll_netdev_add_pin_handle(struct sk_buff *msg, 93 const struct net_device *dev) 94 { 95 return dpll_msg_add_pin_handle(msg, dpll_netdev_pin(dev)); 96 } 97 98 static int 99 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, 100 struct netlink_ext_ack *extack) 101 { 102 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 103 enum dpll_mode mode; 104 int ret; 105 106 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 107 if (ret) 108 return ret; 109 if (nla_put_u32(msg, DPLL_A_MODE, mode)) 110 return -EMSGSIZE; 111 112 return 0; 113 } 114 115 static int 116 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, 117 struct netlink_ext_ack *extack) 118 { 119 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 120 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 121 enum dpll_mode mode; 122 int ret; 123 124 if (ops->supported_modes_get) { 125 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, 126 extack); 127 if (ret) 128 return ret; 129 } else { 130 /* If the supported modes are not reported by the driver, the 131 * only supported mode is the one obtained by mode_get(). 132 */ 133 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 134 if (ret) 135 return ret; 136 137 __set_bit(mode, modes); 138 } 139 140 for_each_set_bit(mode, modes, DPLL_MODE_MAX + 1) 141 if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode)) 142 return -EMSGSIZE; 143 144 return 0; 145 } 146 147 static int 148 dpll_msg_add_phase_offset_monitor(struct sk_buff *msg, struct dpll_device *dpll, 149 struct netlink_ext_ack *extack) 150 { 151 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 152 enum dpll_feature_state state; 153 int ret; 154 155 if (ops->phase_offset_monitor_set && ops->phase_offset_monitor_get) { 156 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), 157 &state, extack); 158 if (ret) 159 return ret; 160 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_MONITOR, state)) 161 return -EMSGSIZE; 162 } 163 164 return 0; 165 } 166 167 static int 168 dpll_msg_add_freq_monitor(struct sk_buff *msg, struct dpll_device *dpll, 169 struct netlink_ext_ack *extack) 170 { 171 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 172 enum dpll_feature_state state; 173 int ret; 174 175 if (ops->freq_monitor_set && ops->freq_monitor_get) { 176 ret = ops->freq_monitor_get(dpll, dpll_priv(dpll), 177 &state, extack); 178 if (ret) 179 return ret; 180 if (nla_put_u32(msg, DPLL_A_FREQUENCY_MONITOR, state)) 181 return -EMSGSIZE; 182 } 183 184 return 0; 185 } 186 187 static int 188 dpll_msg_add_phase_offset_avg_factor(struct sk_buff *msg, 189 struct dpll_device *dpll, 190 struct netlink_ext_ack *extack) 191 { 192 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 193 u32 factor; 194 int ret; 195 196 if (ops->phase_offset_avg_factor_get) { 197 ret = ops->phase_offset_avg_factor_get(dpll, dpll_priv(dpll), 198 &factor, extack); 199 if (ret) 200 return ret; 201 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_AVG_FACTOR, factor)) 202 return -EMSGSIZE; 203 } 204 205 return 0; 206 } 207 208 static int 209 dpll_msg_add_lock_status(struct sk_buff *msg, struct dpll_device *dpll, 210 struct netlink_ext_ack *extack) 211 { 212 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 213 enum dpll_lock_status_error status_error = 0; 214 enum dpll_lock_status status; 215 int ret; 216 217 ret = ops->lock_status_get(dpll, dpll_priv(dpll), &status, 218 &status_error, extack); 219 if (ret) 220 return ret; 221 if (nla_put_u32(msg, DPLL_A_LOCK_STATUS, status)) 222 return -EMSGSIZE; 223 if (status_error && 224 (status == DPLL_LOCK_STATUS_UNLOCKED || 225 status == DPLL_LOCK_STATUS_HOLDOVER) && 226 nla_put_u32(msg, DPLL_A_LOCK_STATUS_ERROR, status_error)) 227 return -EMSGSIZE; 228 229 return 0; 230 } 231 232 static int 233 dpll_msg_add_temp(struct sk_buff *msg, struct dpll_device *dpll, 234 struct netlink_ext_ack *extack) 235 { 236 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 237 s32 temp; 238 int ret; 239 240 if (!ops->temp_get) 241 return 0; 242 ret = ops->temp_get(dpll, dpll_priv(dpll), &temp, extack); 243 if (ret) 244 return ret; 245 if (nla_put_s32(msg, DPLL_A_TEMP, temp)) 246 return -EMSGSIZE; 247 248 return 0; 249 } 250 251 static int 252 dpll_msg_add_clock_quality_level(struct sk_buff *msg, struct dpll_device *dpll, 253 struct netlink_ext_ack *extack) 254 { 255 DECLARE_BITMAP(qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) = { 0 }; 256 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 257 enum dpll_clock_quality_level ql; 258 int ret; 259 260 if (!ops->clock_quality_level_get) 261 return 0; 262 ret = ops->clock_quality_level_get(dpll, dpll_priv(dpll), qls, extack); 263 if (ret) 264 return ret; 265 for_each_set_bit(ql, qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) 266 if (nla_put_u32(msg, DPLL_A_CLOCK_QUALITY_LEVEL, ql)) 267 return -EMSGSIZE; 268 269 return 0; 270 } 271 272 static int 273 dpll_msg_add_pin_prio(struct sk_buff *msg, struct dpll_pin *pin, 274 struct dpll_pin_ref *ref, 275 struct netlink_ext_ack *extack) 276 { 277 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 278 struct dpll_device *dpll = ref->dpll; 279 u32 prio; 280 int ret; 281 282 if (!ops->prio_get) 283 return 0; 284 ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 285 dpll_priv(dpll), &prio, extack); 286 if (ret) 287 return ret; 288 if (nla_put_u32(msg, DPLL_A_PIN_PRIO, prio)) 289 return -EMSGSIZE; 290 291 return 0; 292 } 293 294 static int 295 dpll_msg_add_pin_on_dpll_state(struct sk_buff *msg, struct dpll_pin *pin, 296 struct dpll_pin_ref *ref, 297 struct netlink_ext_ack *extack) 298 { 299 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 300 struct dpll_device *dpll = ref->dpll; 301 enum dpll_pin_state state; 302 int ret; 303 304 if (!ops->state_on_dpll_get) 305 return 0; 306 ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 307 dpll, dpll_priv(dpll), &state, extack); 308 if (ret) 309 return ret; 310 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) 311 return -EMSGSIZE; 312 313 return 0; 314 } 315 316 static int 317 dpll_msg_add_pin_operstate(struct sk_buff *msg, struct dpll_pin *pin, 318 struct dpll_pin_ref *ref, 319 struct netlink_ext_ack *extack) 320 { 321 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 322 struct dpll_device *dpll = ref->dpll; 323 enum dpll_pin_operstate operstate; 324 int ret; 325 326 if (!ops->operstate_on_dpll_get) 327 return 0; 328 ret = ops->operstate_on_dpll_get(pin, 329 dpll_pin_on_dpll_priv(dpll, pin), 330 dpll, dpll_priv(dpll), 331 &operstate, extack); 332 if (ret) 333 return ret; 334 if (nla_put_u32(msg, DPLL_A_PIN_OPERSTATE, operstate)) 335 return -EMSGSIZE; 336 337 return 0; 338 } 339 340 static int 341 dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin, 342 struct dpll_pin_ref *ref, 343 struct netlink_ext_ack *extack) 344 { 345 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 346 struct dpll_device *dpll = ref->dpll; 347 enum dpll_pin_direction direction; 348 int ret; 349 350 ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 351 dpll_priv(dpll), &direction, extack); 352 if (ret) 353 return ret; 354 if (nla_put_u32(msg, DPLL_A_PIN_DIRECTION, direction)) 355 return -EMSGSIZE; 356 357 return 0; 358 } 359 360 static int 361 dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin, 362 struct dpll_pin_ref *ref, 363 struct netlink_ext_ack *extack) 364 { 365 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 366 struct dpll_device *dpll = ref->dpll; 367 s32 phase_adjust; 368 int ret; 369 370 if (!ops->phase_adjust_get) 371 return 0; 372 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 373 dpll, dpll_priv(dpll), 374 &phase_adjust, extack); 375 if (ret) 376 return ret; 377 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust)) 378 return -EMSGSIZE; 379 380 return 0; 381 } 382 383 static int 384 dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin, 385 struct dpll_pin_ref *ref, 386 struct netlink_ext_ack *extack) 387 { 388 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 389 struct dpll_device *dpll = ref->dpll; 390 s64 phase_offset; 391 int ret; 392 393 if (!ops->phase_offset_get) 394 return 0; 395 ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 396 dpll, dpll_priv(dpll), &phase_offset, 397 extack); 398 if (ret) 399 return ret; 400 if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset), 401 &phase_offset, DPLL_A_PIN_PAD)) 402 return -EMSGSIZE; 403 404 return 0; 405 } 406 407 static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin, 408 struct dpll_pin_ref *ref, 409 enum dpll_ffo_type type, 410 struct netlink_ext_ack *extack) 411 { 412 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 413 struct dpll_ffo_param ffo = { .type = type }; 414 int ret; 415 416 if (!ops->ffo_get || !(ops->supported_ffo & BIT(type))) 417 return 0; 418 ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(ref->dpll, pin), 419 ref->dpll, dpll_priv(ref->dpll), &ffo, extack); 420 if (ret) { 421 if (ret == -ENODATA) 422 return 0; 423 return ret; 424 } 425 if (nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 426 div_s64(ffo.ffo, 1000000))) 427 return -EMSGSIZE; 428 return nla_put_sint(msg, 429 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, 430 ffo.ffo); 431 } 432 433 static int dpll_msg_add_measured_freq(struct sk_buff *msg, struct dpll_pin *pin, 434 struct dpll_pin_ref *ref, 435 struct netlink_ext_ack *extack) 436 { 437 const struct dpll_device_ops *dev_ops = dpll_device_ops(ref->dpll); 438 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 439 struct dpll_device *dpll = ref->dpll; 440 enum dpll_feature_state state; 441 u64 measured_freq; 442 int ret; 443 444 if (!ops->measured_freq_get) 445 return 0; 446 ret = dev_ops->freq_monitor_get(dpll, dpll_priv(dpll), 447 &state, extack); 448 if (ret) 449 return ret; 450 if (state == DPLL_FEATURE_STATE_DISABLE) 451 return 0; 452 ret = ops->measured_freq_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 453 dpll, dpll_priv(dpll), &measured_freq, 454 extack); 455 if (ret) 456 return ret; 457 if (nla_put_64bit(msg, DPLL_A_PIN_MEASURED_FREQUENCY, 458 sizeof(measured_freq), &measured_freq, 459 DPLL_A_PIN_PAD)) 460 return -EMSGSIZE; 461 462 return 0; 463 } 464 465 static int 466 dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin, 467 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 468 { 469 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 470 struct dpll_device *dpll = ref->dpll; 471 struct nlattr *nest; 472 int fs, ret; 473 u64 freq; 474 475 if (!ops->frequency_get) 476 return 0; 477 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 478 dpll_priv(dpll), &freq, extack); 479 if (ret) 480 return ret; 481 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY, sizeof(freq), &freq, 482 DPLL_A_PIN_PAD)) 483 return -EMSGSIZE; 484 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) { 485 nest = nla_nest_start(msg, DPLL_A_PIN_FREQUENCY_SUPPORTED); 486 if (!nest) 487 return -EMSGSIZE; 488 freq = pin->prop.freq_supported[fs].min; 489 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, sizeof(freq), 490 &freq, DPLL_A_PIN_PAD)) { 491 nla_nest_cancel(msg, nest); 492 return -EMSGSIZE; 493 } 494 freq = pin->prop.freq_supported[fs].max; 495 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, sizeof(freq), 496 &freq, DPLL_A_PIN_PAD)) { 497 nla_nest_cancel(msg, nest); 498 return -EMSGSIZE; 499 } 500 nla_nest_end(msg, nest); 501 } 502 503 return 0; 504 } 505 506 static int 507 dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpll_pin *pin, 508 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 509 { 510 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 511 struct dpll_device *dpll = ref->dpll; 512 struct dpll_pin_esync esync; 513 struct nlattr *nest; 514 int ret, i; 515 516 if (!ops->esync_get) 517 return 0; 518 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 519 dpll_priv(dpll), &esync, extack); 520 if (ret == -EOPNOTSUPP) 521 return 0; 522 else if (ret) 523 return ret; 524 if (nla_put_64bit(msg, DPLL_A_PIN_ESYNC_FREQUENCY, sizeof(esync.freq), 525 &esync.freq, DPLL_A_PIN_PAD)) 526 return -EMSGSIZE; 527 if (nla_put_u32(msg, DPLL_A_PIN_ESYNC_PULSE, esync.pulse)) 528 return -EMSGSIZE; 529 for (i = 0; i < esync.range_num; i++) { 530 nest = nla_nest_start(msg, 531 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED); 532 if (!nest) 533 return -EMSGSIZE; 534 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, 535 sizeof(esync.range[i].min), 536 &esync.range[i].min, DPLL_A_PIN_PAD)) 537 goto nest_cancel; 538 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, 539 sizeof(esync.range[i].max), 540 &esync.range[i].max, DPLL_A_PIN_PAD)) 541 goto nest_cancel; 542 nla_nest_end(msg, nest); 543 } 544 return 0; 545 546 nest_cancel: 547 nla_nest_cancel(msg, nest); 548 return -EMSGSIZE; 549 } 550 551 static int 552 dpll_msg_add_pin_ref_sync(struct sk_buff *msg, struct dpll_pin *pin, 553 struct dpll_pin_ref *ref, 554 struct netlink_ext_ack *extack) 555 { 556 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 557 struct dpll_device *dpll = ref->dpll; 558 void *pin_priv, *ref_sync_pin_priv; 559 struct dpll_pin *ref_sync_pin; 560 enum dpll_pin_state state; 561 struct nlattr *nest; 562 unsigned long index; 563 int ret; 564 565 pin_priv = dpll_pin_on_dpll_priv(dpll, pin); 566 xa_for_each(&pin->ref_sync_pins, index, ref_sync_pin) { 567 if (!dpll_pin_available(ref_sync_pin)) 568 continue; 569 ref_sync_pin_priv = dpll_pin_on_dpll_priv(dpll, ref_sync_pin); 570 /* Pin may have been unregistered from this dpll already */ 571 if (!ref_sync_pin_priv) 572 continue; 573 if (WARN_ON(!ops->ref_sync_get)) 574 return -EOPNOTSUPP; 575 ret = ops->ref_sync_get(pin, pin_priv, ref_sync_pin, 576 ref_sync_pin_priv, &state, extack); 577 if (ret) 578 return ret; 579 nest = nla_nest_start(msg, DPLL_A_PIN_REFERENCE_SYNC); 580 if (!nest) 581 return -EMSGSIZE; 582 if (nla_put_s32(msg, DPLL_A_PIN_ID, ref_sync_pin->id)) 583 goto nest_cancel; 584 if (nla_put_s32(msg, DPLL_A_PIN_STATE, state)) 585 goto nest_cancel; 586 nla_nest_end(msg, nest); 587 } 588 return 0; 589 590 nest_cancel: 591 nla_nest_cancel(msg, nest); 592 return -EMSGSIZE; 593 } 594 595 static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) 596 { 597 int fs; 598 599 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) 600 if (freq >= pin->prop.freq_supported[fs].min && 601 freq <= pin->prop.freq_supported[fs].max) 602 return true; 603 return false; 604 } 605 606 static int 607 dpll_msg_add_pin_parents(struct sk_buff *msg, struct dpll_pin *pin, 608 struct dpll_pin_ref *dpll_ref, 609 struct netlink_ext_ack *extack) 610 { 611 enum dpll_pin_state state; 612 struct dpll_pin_ref *ref; 613 struct dpll_pin *ppin; 614 struct nlattr *nest; 615 unsigned long index; 616 int ret; 617 618 xa_for_each(&pin->parent_refs, index, ref) { 619 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 620 void *parent_priv; 621 622 ppin = ref->pin; 623 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, ppin); 624 ret = ops->state_on_pin_get(pin, 625 dpll_pin_on_pin_priv(ppin, pin), 626 ppin, parent_priv, &state, extack); 627 if (ret) 628 return ret; 629 nest = nla_nest_start(msg, DPLL_A_PIN_PARENT_PIN); 630 if (!nest) 631 return -EMSGSIZE; 632 ret = dpll_msg_add_dev_parent_handle(msg, ppin->id); 633 if (ret) 634 goto nest_cancel; 635 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) { 636 ret = -EMSGSIZE; 637 goto nest_cancel; 638 } 639 nla_nest_end(msg, nest); 640 } 641 642 return 0; 643 644 nest_cancel: 645 nla_nest_cancel(msg, nest); 646 return ret; 647 } 648 649 static int 650 dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin, 651 struct netlink_ext_ack *extack) 652 { 653 struct dpll_pin_ref *ref; 654 struct nlattr *attr; 655 unsigned long index; 656 int ret; 657 658 xa_for_each(&pin->dpll_refs, index, ref) { 659 attr = nla_nest_start(msg, DPLL_A_PIN_PARENT_DEVICE); 660 if (!attr) 661 return -EMSGSIZE; 662 ret = dpll_msg_add_dev_parent_handle(msg, ref->dpll->id); 663 if (ret) 664 goto nest_cancel; 665 ret = dpll_msg_add_pin_on_dpll_state(msg, pin, ref, extack); 666 if (ret) 667 goto nest_cancel; 668 ret = dpll_msg_add_pin_operstate(msg, pin, ref, extack); 669 if (ret) 670 goto nest_cancel; 671 ret = dpll_msg_add_pin_prio(msg, pin, ref, extack); 672 if (ret) 673 goto nest_cancel; 674 ret = dpll_msg_add_pin_direction(msg, pin, ref, extack); 675 if (ret) 676 goto nest_cancel; 677 ret = dpll_msg_add_phase_offset(msg, pin, ref, extack); 678 if (ret) 679 goto nest_cancel; 680 ret = dpll_msg_add_ffo(msg, pin, ref, 681 DPLL_FFO_PIN_DEVICE, extack); 682 if (ret) 683 goto nest_cancel; 684 nla_nest_end(msg, attr); 685 } 686 687 return 0; 688 689 nest_cancel: 690 nla_nest_end(msg, attr); 691 return ret; 692 } 693 694 static int 695 dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, 696 struct netlink_ext_ack *extack) 697 { 698 const struct dpll_pin_properties *prop = &pin->prop; 699 struct dpll_pin_ref *ref; 700 int ret; 701 702 ref = dpll_pin_own_dpll_ref_first(pin); 703 if (!ref) 704 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 705 ASSERT_NOT_NULL(ref); 706 707 ret = dpll_msg_add_pin_handle(msg, pin); 708 if (ret) 709 return ret; 710 if (nla_put_string(msg, DPLL_A_PIN_MODULE_NAME, 711 pin->module_name)) 712 return -EMSGSIZE; 713 if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id), 714 &pin->clock_id, DPLL_A_PIN_PAD)) 715 return -EMSGSIZE; 716 if (prop->board_label && 717 nla_put_string(msg, DPLL_A_PIN_BOARD_LABEL, prop->board_label)) 718 return -EMSGSIZE; 719 if (prop->panel_label && 720 nla_put_string(msg, DPLL_A_PIN_PANEL_LABEL, prop->panel_label)) 721 return -EMSGSIZE; 722 if (prop->package_label && 723 nla_put_string(msg, DPLL_A_PIN_PACKAGE_LABEL, 724 prop->package_label)) 725 return -EMSGSIZE; 726 if (nla_put_u32(msg, DPLL_A_PIN_TYPE, prop->type)) 727 return -EMSGSIZE; 728 if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities)) 729 return -EMSGSIZE; 730 ret = dpll_msg_add_pin_freq(msg, pin, ref, extack); 731 if (ret) 732 return ret; 733 if (prop->phase_gran && 734 nla_put_u32(msg, DPLL_A_PIN_PHASE_ADJUST_GRAN, 735 prop->phase_gran)) 736 return -EMSGSIZE; 737 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN, 738 prop->phase_range.min)) 739 return -EMSGSIZE; 740 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX, 741 prop->phase_range.max)) 742 return -EMSGSIZE; 743 ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack); 744 if (ret) 745 return ret; 746 ret = dpll_msg_add_ffo(msg, pin, ref, 747 DPLL_FFO_PORT_RXTX_RATE, extack); 748 if (ret) 749 return ret; 750 ret = dpll_msg_add_measured_freq(msg, pin, ref, extack); 751 if (ret) 752 return ret; 753 ret = dpll_msg_add_pin_esync(msg, pin, ref, extack); 754 if (ret) 755 return ret; 756 if (!xa_empty(&pin->ref_sync_pins)) 757 ret = dpll_msg_add_pin_ref_sync(msg, pin, ref, extack); 758 if (ret) 759 return ret; 760 if (xa_empty(&pin->parent_refs)) 761 ret = dpll_msg_add_pin_dplls(msg, pin, extack); 762 else 763 ret = dpll_msg_add_pin_parents(msg, pin, ref, extack); 764 765 return ret; 766 } 767 768 static int 769 dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg, 770 struct netlink_ext_ack *extack) 771 { 772 int ret; 773 774 ret = dpll_msg_add_dev_handle(msg, dpll); 775 if (ret) 776 return ret; 777 if (nla_put_string(msg, DPLL_A_MODULE_NAME, module_name(dpll->module))) 778 return -EMSGSIZE; 779 if (nla_put_64bit(msg, DPLL_A_CLOCK_ID, sizeof(dpll->clock_id), 780 &dpll->clock_id, DPLL_A_PAD)) 781 return -EMSGSIZE; 782 ret = dpll_msg_add_temp(msg, dpll, extack); 783 if (ret) 784 return ret; 785 ret = dpll_msg_add_lock_status(msg, dpll, extack); 786 if (ret) 787 return ret; 788 ret = dpll_msg_add_clock_quality_level(msg, dpll, extack); 789 if (ret) 790 return ret; 791 ret = dpll_msg_add_mode(msg, dpll, extack); 792 if (ret) 793 return ret; 794 ret = dpll_msg_add_mode_supported(msg, dpll, extack); 795 if (ret) 796 return ret; 797 if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type)) 798 return -EMSGSIZE; 799 ret = dpll_msg_add_phase_offset_monitor(msg, dpll, extack); 800 if (ret) 801 return ret; 802 ret = dpll_msg_add_phase_offset_avg_factor(msg, dpll, extack); 803 if (ret) 804 return ret; 805 ret = dpll_msg_add_freq_monitor(msg, dpll, extack); 806 if (ret) 807 return ret; 808 809 return 0; 810 } 811 812 static int 813 dpll_device_event_send(enum dpll_cmd event, struct dpll_device *dpll) 814 { 815 struct sk_buff *msg; 816 int ret = -ENOMEM; 817 void *hdr; 818 819 if (WARN_ON(!xa_get_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED))) 820 return -ENODEV; 821 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 822 if (!msg) 823 return -ENOMEM; 824 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 825 if (!hdr) 826 goto err_free_msg; 827 ret = dpll_device_get_one(dpll, msg, NULL); 828 if (ret) 829 goto err_cancel_msg; 830 genlmsg_end(msg, hdr); 831 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 832 833 return 0; 834 835 err_cancel_msg: 836 genlmsg_cancel(msg, hdr); 837 err_free_msg: 838 nlmsg_free(msg); 839 840 return ret; 841 } 842 843 int dpll_device_create_ntf(struct dpll_device *dpll) 844 { 845 dpll_device_notify(dpll, DPLL_DEVICE_CREATED); 846 return dpll_device_event_send(DPLL_CMD_DEVICE_CREATE_NTF, dpll); 847 } 848 849 int dpll_device_delete_ntf(struct dpll_device *dpll) 850 { 851 dpll_device_notify(dpll, DPLL_DEVICE_DELETED); 852 return dpll_device_event_send(DPLL_CMD_DEVICE_DELETE_NTF, dpll); 853 } 854 855 /** 856 * __dpll_device_change_ntf - notify that the dpll device has been changed 857 * @dpll: registered dpll pointer 858 * 859 * Context: caller must hold dpll_lock. Suitable for use inside device 860 * callbacks which are already invoked under dpll_lock. 861 * Return: 0 if succeeds, error code otherwise. 862 */ 863 int __dpll_device_change_ntf(struct dpll_device *dpll) 864 { 865 lockdep_assert_held(&dpll_lock); 866 dpll_device_notify(dpll, DPLL_DEVICE_CHANGED); 867 return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); 868 } 869 EXPORT_SYMBOL_GPL(__dpll_device_change_ntf); 870 871 /** 872 * dpll_device_change_ntf - notify that the dpll device has been changed 873 * @dpll: registered dpll pointer 874 * 875 * Context: acquires and holds a dpll_lock. 876 * Return: 0 if succeeds, error code otherwise. 877 */ 878 int dpll_device_change_ntf(struct dpll_device *dpll) 879 { 880 int ret; 881 882 mutex_lock(&dpll_lock); 883 ret = __dpll_device_change_ntf(dpll); 884 mutex_unlock(&dpll_lock); 885 886 return ret; 887 } 888 EXPORT_SYMBOL_GPL(dpll_device_change_ntf); 889 890 static int 891 dpll_pin_event_send(enum dpll_cmd event, struct dpll_pin *pin) 892 { 893 struct sk_buff *msg; 894 int ret = -ENOMEM; 895 void *hdr; 896 897 if (!dpll_pin_available(pin)) 898 return -ENODEV; 899 900 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 901 if (!msg) 902 return -ENOMEM; 903 904 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 905 if (!hdr) 906 goto err_free_msg; 907 ret = dpll_cmd_pin_get_one(msg, pin, NULL); 908 if (ret) 909 goto err_cancel_msg; 910 genlmsg_end(msg, hdr); 911 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 912 913 return 0; 914 915 err_cancel_msg: 916 genlmsg_cancel(msg, hdr); 917 err_free_msg: 918 nlmsg_free(msg); 919 920 return ret; 921 } 922 923 int dpll_pin_create_ntf(struct dpll_pin *pin, u64 src_clock_id) 924 { 925 dpll_pin_notify(pin, src_clock_id, DPLL_PIN_CREATED); 926 return dpll_pin_event_send(DPLL_CMD_PIN_CREATE_NTF, pin); 927 } 928 929 int dpll_pin_delete_ntf(struct dpll_pin *pin, u64 src_clock_id) 930 { 931 dpll_pin_notify(pin, src_clock_id, DPLL_PIN_DELETED); 932 return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); 933 } 934 935 /** 936 * __dpll_pin_change_ntf - notify that the pin has been changed 937 * @pin: registered pin pointer 938 * 939 * Context: caller must hold dpll_lock. Suitable for use inside pin 940 * callbacks which are already invoked under dpll_lock. 941 * Return: 0 if succeeds, error code otherwise. 942 */ 943 int __dpll_pin_change_ntf(struct dpll_pin *pin) 944 { 945 lockdep_assert_held(&dpll_lock); 946 dpll_pin_notify(pin, pin->clock_id, DPLL_PIN_CHANGED); 947 return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); 948 } 949 EXPORT_SYMBOL_GPL(__dpll_pin_change_ntf); 950 951 /** 952 * dpll_pin_change_ntf - notify that the pin has been changed 953 * @pin: registered pin pointer 954 * 955 * Context: acquires and holds a dpll_lock. 956 * Return: 0 if succeeds, error code otherwise. 957 */ 958 int dpll_pin_change_ntf(struct dpll_pin *pin) 959 { 960 int ret; 961 962 mutex_lock(&dpll_lock); 963 ret = __dpll_pin_change_ntf(pin); 964 mutex_unlock(&dpll_lock); 965 966 return ret; 967 } 968 EXPORT_SYMBOL_GPL(dpll_pin_change_ntf); 969 970 static int 971 dpll_mode_set(struct dpll_device *dpll, struct nlattr *a, 972 struct netlink_ext_ack *extack) 973 { 974 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 975 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 976 enum dpll_mode mode = nla_get_u32(a), old_mode; 977 int ret; 978 979 if (!(ops->mode_set && ops->supported_modes_get)) { 980 NL_SET_ERR_MSG_ATTR(extack, a, 981 "dpll device does not support mode switch"); 982 return -EOPNOTSUPP; 983 } 984 985 ret = ops->mode_get(dpll, dpll_priv(dpll), &old_mode, extack); 986 if (ret) { 987 NL_SET_ERR_MSG(extack, "unable to get current mode"); 988 return ret; 989 } 990 991 if (mode == old_mode) 992 return 0; 993 994 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, extack); 995 if (ret) { 996 NL_SET_ERR_MSG(extack, "unable to get supported modes"); 997 return ret; 998 } 999 1000 if (!test_bit(mode, modes)) { 1001 NL_SET_ERR_MSG(extack, 1002 "dpll device does not support requested mode"); 1003 return -EINVAL; 1004 } 1005 1006 return ops->mode_set(dpll, dpll_priv(dpll), mode, extack); 1007 } 1008 1009 static int 1010 dpll_phase_offset_monitor_set(struct dpll_device *dpll, struct nlattr *a, 1011 struct netlink_ext_ack *extack) 1012 { 1013 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1014 enum dpll_feature_state state = nla_get_u32(a), old_state; 1015 int ret; 1016 1017 if (!(ops->phase_offset_monitor_set && ops->phase_offset_monitor_get)) { 1018 NL_SET_ERR_MSG_ATTR(extack, a, "dpll device not capable of phase offset monitor"); 1019 return -EOPNOTSUPP; 1020 } 1021 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), &old_state, 1022 extack); 1023 if (ret) { 1024 NL_SET_ERR_MSG(extack, "unable to get current state of phase offset monitor"); 1025 return ret; 1026 } 1027 if (state == old_state) 1028 return 0; 1029 1030 return ops->phase_offset_monitor_set(dpll, dpll_priv(dpll), state, 1031 extack); 1032 } 1033 1034 static int 1035 dpll_phase_offset_avg_factor_set(struct dpll_device *dpll, struct nlattr *a, 1036 struct netlink_ext_ack *extack) 1037 { 1038 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1039 u32 factor = nla_get_u32(a); 1040 1041 if (!ops->phase_offset_avg_factor_set) { 1042 NL_SET_ERR_MSG_ATTR(extack, a, 1043 "device not capable of changing phase offset average factor"); 1044 return -EOPNOTSUPP; 1045 } 1046 1047 return ops->phase_offset_avg_factor_set(dpll, dpll_priv(dpll), factor, 1048 extack); 1049 } 1050 1051 static int 1052 dpll_freq_monitor_set(struct dpll_device *dpll, struct nlattr *a, 1053 struct netlink_ext_ack *extack) 1054 { 1055 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1056 enum dpll_feature_state state = nla_get_u32(a), old_state; 1057 int ret; 1058 1059 if (!(ops->freq_monitor_set && ops->freq_monitor_get)) { 1060 NL_SET_ERR_MSG_ATTR(extack, a, 1061 "dpll device not capable of frequency monitor"); 1062 return -EOPNOTSUPP; 1063 } 1064 ret = ops->freq_monitor_get(dpll, dpll_priv(dpll), &old_state, 1065 extack); 1066 if (ret) { 1067 NL_SET_ERR_MSG(extack, 1068 "unable to get current state of frequency monitor"); 1069 return ret; 1070 } 1071 if (state == old_state) 1072 return 0; 1073 1074 return ops->freq_monitor_set(dpll, dpll_priv(dpll), state, extack); 1075 } 1076 1077 static int 1078 dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a, 1079 struct netlink_ext_ack *extack) 1080 { 1081 u64 freq = nla_get_u64(a), old_freq; 1082 const struct dpll_pin_ops *ops; 1083 struct dpll_pin_ref *ref; 1084 struct dpll_device *dpll; 1085 int ret; 1086 1087 if (!dpll_pin_is_freq_supported(pin, freq)) { 1088 NL_SET_ERR_MSG_ATTR(extack, a, "frequency is not supported by the device"); 1089 return -EINVAL; 1090 } 1091 1092 ref = dpll_pin_own_dpll_ref_first(pin); 1093 if (!ref) { 1094 NL_SET_ERR_MSG(extack, "pin owner dpll not found"); 1095 return -ENODEV; 1096 } 1097 ops = dpll_pin_ops(ref); 1098 if (!ops->frequency_set || !ops->frequency_get) { 1099 NL_SET_ERR_MSG(extack, 1100 "frequency set not supported by the device"); 1101 return -EOPNOTSUPP; 1102 } 1103 dpll = ref->dpll; 1104 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1105 dpll_priv(dpll), &old_freq, extack); 1106 if (ret) { 1107 NL_SET_ERR_MSG(extack, "unable to get old frequency value"); 1108 return ret; 1109 } 1110 if (freq == old_freq) 1111 return 0; 1112 1113 ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1114 dpll, dpll_priv(dpll), freq, extack); 1115 if (ret) { 1116 NL_SET_ERR_MSG_FMT(extack, 1117 "frequency set failed for dpll_id:%u", 1118 dpll->id); 1119 return ret; 1120 } 1121 __dpll_pin_change_ntf(pin); 1122 1123 return 0; 1124 } 1125 1126 static int 1127 dpll_pin_esync_set(struct dpll_pin *pin, struct nlattr *a, 1128 struct netlink_ext_ack *extack) 1129 { 1130 const struct dpll_pin_ops *ops; 1131 struct dpll_pin_esync esync; 1132 u64 freq = nla_get_u64(a); 1133 struct dpll_pin_ref *ref; 1134 struct dpll_device *dpll; 1135 bool supported = false; 1136 int ret, i; 1137 1138 ref = dpll_pin_own_dpll_ref_first(pin); 1139 if (!ref) { 1140 NL_SET_ERR_MSG(extack, "pin owner dpll not found"); 1141 return -ENODEV; 1142 } 1143 ops = dpll_pin_ops(ref); 1144 if (!ops->esync_set || !ops->esync_get) { 1145 NL_SET_ERR_MSG(extack, 1146 "embedded sync feature is not supported by this device"); 1147 return -EOPNOTSUPP; 1148 } 1149 dpll = ref->dpll; 1150 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1151 dpll_priv(dpll), &esync, extack); 1152 if (ret) { 1153 NL_SET_ERR_MSG(extack, "unable to get current embedded sync frequency value"); 1154 return ret; 1155 } 1156 if (freq == esync.freq) 1157 return 0; 1158 for (i = 0; i < esync.range_num; i++) 1159 if (freq <= esync.range[i].max && freq >= esync.range[i].min) 1160 supported = true; 1161 if (!supported) { 1162 NL_SET_ERR_MSG_ATTR(extack, a, 1163 "requested embedded sync frequency value is not supported by this device"); 1164 return -EINVAL; 1165 } 1166 1167 ret = ops->esync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1168 dpll_priv(dpll), freq, extack); 1169 if (ret) { 1170 NL_SET_ERR_MSG_FMT(extack, 1171 "embedded sync frequency set failed for dpll_id: %u", 1172 dpll->id); 1173 return ret; 1174 } 1175 __dpll_pin_change_ntf(pin); 1176 1177 return 0; 1178 } 1179 1180 static int 1181 dpll_pin_ref_sync_state_set(struct dpll_pin *pin, 1182 unsigned long ref_sync_pin_idx, 1183 const enum dpll_pin_state state, 1184 struct netlink_ext_ack *extack) 1185 { 1186 const struct dpll_pin_ops *ops; 1187 enum dpll_pin_state old_state; 1188 struct dpll_pin *ref_sync_pin; 1189 struct dpll_pin_ref *ref; 1190 struct dpll_device *dpll; 1191 int ret; 1192 1193 ref_sync_pin = xa_find(&pin->ref_sync_pins, &ref_sync_pin_idx, 1194 ULONG_MAX, XA_PRESENT); 1195 if (!ref_sync_pin) { 1196 NL_SET_ERR_MSG(extack, "reference sync pin not found"); 1197 return -EINVAL; 1198 } 1199 if (!dpll_pin_available(ref_sync_pin)) { 1200 NL_SET_ERR_MSG(extack, "reference sync pin not available"); 1201 return -EINVAL; 1202 } 1203 ref = dpll_pin_own_dpll_ref_first(pin); 1204 if (!ref) { 1205 NL_SET_ERR_MSG(extack, "pin owner dpll not found"); 1206 return -ENODEV; 1207 } 1208 ops = dpll_pin_ops(ref); 1209 if (!ops->ref_sync_set || !ops->ref_sync_get) { 1210 NL_SET_ERR_MSG(extack, "reference sync not supported by this pin"); 1211 return -EOPNOTSUPP; 1212 } 1213 dpll = ref->dpll; 1214 ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1215 ref_sync_pin, 1216 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1217 &old_state, extack); 1218 if (ret) { 1219 NL_SET_ERR_MSG(extack, "unable to get old reference sync state"); 1220 return ret; 1221 } 1222 if (state == old_state) 1223 return 0; 1224 1225 ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1226 ref_sync_pin, 1227 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1228 state, extack); 1229 if (ret) { 1230 NL_SET_ERR_MSG_FMT(extack, 1231 "reference sync set failed for dpll_id:%u", 1232 dpll->id); 1233 return ret; 1234 } 1235 __dpll_pin_change_ntf(pin); 1236 1237 return 0; 1238 } 1239 1240 static int 1241 dpll_pin_ref_sync_set(struct dpll_pin *pin, struct nlattr *nest, 1242 struct netlink_ext_ack *extack) 1243 { 1244 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1245 enum dpll_pin_state state; 1246 u32 sync_pin_id; 1247 1248 nla_parse_nested(tb, DPLL_A_PIN_MAX, nest, 1249 dpll_reference_sync_nl_policy, extack); 1250 if (!tb[DPLL_A_PIN_ID]) { 1251 NL_SET_ERR_MSG(extack, "sync pin id expected"); 1252 return -EINVAL; 1253 } 1254 sync_pin_id = nla_get_u32(tb[DPLL_A_PIN_ID]); 1255 1256 if (!tb[DPLL_A_PIN_STATE]) { 1257 NL_SET_ERR_MSG(extack, "sync pin state expected"); 1258 return -EINVAL; 1259 } 1260 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1261 1262 return dpll_pin_ref_sync_state_set(pin, sync_pin_id, state, extack); 1263 } 1264 1265 static int 1266 dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, 1267 enum dpll_pin_state state, 1268 struct netlink_ext_ack *extack) 1269 { 1270 struct dpll_pin_ref *parent_ref; 1271 const struct dpll_pin_ops *ops; 1272 struct dpll_pin_ref *dpll_ref; 1273 void *pin_priv, *parent_priv; 1274 struct dpll_pin *parent; 1275 unsigned long i; 1276 int ret; 1277 1278 /* fwnode pins may not set the capability bit upfront; let the ops 1279 * layer return -EOPNOTSUPP if the operation is unsupported. 1280 */ 1281 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1282 pin->prop.capabilities) && !pin->fwnode) { 1283 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1284 return -EOPNOTSUPP; 1285 } 1286 parent = xa_load(&dpll_pin_xa, parent_idx); 1287 if (!parent) 1288 return -EINVAL; 1289 parent_ref = xa_load(&pin->parent_refs, parent->pin_idx); 1290 if (!parent_ref) 1291 return -EINVAL; 1292 xa_for_each(&parent->dpll_refs, i, dpll_ref) { 1293 ops = dpll_pin_ops(parent_ref); 1294 if (!ops->state_on_pin_set) 1295 return -EOPNOTSUPP; 1296 pin_priv = dpll_pin_on_pin_priv(parent, pin); 1297 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, parent); 1298 ret = ops->state_on_pin_set(pin, pin_priv, parent, parent_priv, 1299 state, extack); 1300 if (ret) 1301 return ret; 1302 } 1303 __dpll_pin_change_ntf(pin); 1304 1305 return 0; 1306 } 1307 1308 static int 1309 dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin, 1310 enum dpll_pin_state state, 1311 struct netlink_ext_ack *extack) 1312 { 1313 const struct dpll_pin_ops *ops; 1314 struct dpll_pin_ref *ref; 1315 int ret; 1316 1317 /* fwnode pins may not set the capability bit upfront; let the ops 1318 * layer return -EOPNOTSUPP if the operation is unsupported. 1319 */ 1320 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1321 pin->prop.capabilities) && !pin->fwnode) { 1322 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1323 return -EOPNOTSUPP; 1324 } 1325 ref = xa_load(&pin->dpll_refs, dpll->id); 1326 ASSERT_NOT_NULL(ref); 1327 ops = dpll_pin_ops(ref); 1328 if (!ops->state_on_dpll_set) 1329 return -EOPNOTSUPP; 1330 ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1331 dpll, dpll_priv(dpll), state, extack); 1332 if (ret) 1333 return ret; 1334 __dpll_pin_change_ntf(pin); 1335 1336 return 0; 1337 } 1338 1339 static int 1340 dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin, 1341 u32 prio, struct netlink_ext_ack *extack) 1342 { 1343 const struct dpll_pin_ops *ops; 1344 struct dpll_pin_ref *ref; 1345 int ret; 1346 1347 if (!(DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE & 1348 pin->prop.capabilities)) { 1349 NL_SET_ERR_MSG(extack, "prio changing is not allowed"); 1350 return -EOPNOTSUPP; 1351 } 1352 ref = xa_load(&pin->dpll_refs, dpll->id); 1353 ASSERT_NOT_NULL(ref); 1354 ops = dpll_pin_ops(ref); 1355 if (!ops->prio_set) 1356 return -EOPNOTSUPP; 1357 ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1358 dpll_priv(dpll), prio, extack); 1359 if (ret) 1360 return ret; 1361 __dpll_pin_change_ntf(pin); 1362 1363 return 0; 1364 } 1365 1366 static int 1367 dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll, 1368 enum dpll_pin_direction direction, 1369 struct netlink_ext_ack *extack) 1370 { 1371 const struct dpll_pin_ops *ops; 1372 struct dpll_pin_ref *ref; 1373 int ret; 1374 1375 if (!(DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE & 1376 pin->prop.capabilities)) { 1377 NL_SET_ERR_MSG(extack, "direction changing is not allowed"); 1378 return -EOPNOTSUPP; 1379 } 1380 ref = xa_load(&pin->dpll_refs, dpll->id); 1381 ASSERT_NOT_NULL(ref); 1382 ops = dpll_pin_ops(ref); 1383 if (!ops->direction_set) 1384 return -EOPNOTSUPP; 1385 ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1386 dpll, dpll_priv(dpll), direction, extack); 1387 if (ret) 1388 return ret; 1389 __dpll_pin_change_ntf(pin); 1390 1391 return 0; 1392 } 1393 1394 static int 1395 dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr, 1396 struct netlink_ext_ack *extack) 1397 { 1398 const struct dpll_pin_ops *ops; 1399 s32 phase_adj, old_phase_adj; 1400 struct dpll_pin_ref *ref; 1401 struct dpll_device *dpll; 1402 int ret; 1403 1404 phase_adj = nla_get_s32(phase_adj_attr); 1405 if (phase_adj > pin->prop.phase_range.max || 1406 phase_adj < pin->prop.phase_range.min) { 1407 NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr, 1408 "phase adjust value of out range"); 1409 return -EINVAL; 1410 } 1411 if (pin->prop.phase_gran && phase_adj % (s32)pin->prop.phase_gran) { 1412 NL_SET_ERR_MSG_ATTR_FMT(extack, phase_adj_attr, 1413 "phase adjust value not multiple of %u", 1414 pin->prop.phase_gran); 1415 return -EINVAL; 1416 } 1417 1418 ref = dpll_pin_own_dpll_ref_first(pin); 1419 if (!ref) { 1420 NL_SET_ERR_MSG(extack, "pin owner dpll not found"); 1421 return -ENODEV; 1422 } 1423 ops = dpll_pin_ops(ref); 1424 if (!ops->phase_adjust_set || !ops->phase_adjust_get) { 1425 NL_SET_ERR_MSG(extack, "phase adjust not supported"); 1426 return -EOPNOTSUPP; 1427 } 1428 dpll = ref->dpll; 1429 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1430 dpll, dpll_priv(dpll), &old_phase_adj, 1431 extack); 1432 if (ret) { 1433 NL_SET_ERR_MSG(extack, "unable to get old phase adjust value"); 1434 return ret; 1435 } 1436 if (phase_adj == old_phase_adj) 1437 return 0; 1438 1439 ret = ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1440 dpll, dpll_priv(dpll), phase_adj, extack); 1441 if (ret) { 1442 NL_SET_ERR_MSG_FMT(extack, 1443 "phase adjust set failed for dpll_id:%u", 1444 dpll->id); 1445 return ret; 1446 } 1447 __dpll_pin_change_ntf(pin); 1448 1449 return 0; 1450 } 1451 1452 static int 1453 dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1454 struct netlink_ext_ack *extack) 1455 { 1456 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1457 enum dpll_pin_direction direction; 1458 enum dpll_pin_state state; 1459 struct dpll_pin_ref *ref; 1460 struct dpll_device *dpll; 1461 u32 pdpll_idx, prio; 1462 int ret; 1463 1464 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1465 dpll_pin_parent_device_nl_policy, extack); 1466 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1467 NL_SET_ERR_MSG(extack, "device parent id expected"); 1468 return -EINVAL; 1469 } 1470 pdpll_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1471 dpll = xa_load(&dpll_device_xa, pdpll_idx); 1472 if (!dpll) { 1473 NL_SET_ERR_MSG(extack, "parent device not found"); 1474 return -EINVAL; 1475 } 1476 ref = xa_load(&pin->dpll_refs, dpll->id); 1477 if (!ref) { 1478 NL_SET_ERR_MSG(extack, "pin not connected to given parent device"); 1479 return -EINVAL; 1480 } 1481 if (tb[DPLL_A_PIN_STATE]) { 1482 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1483 ret = dpll_pin_state_set(dpll, pin, state, extack); 1484 if (ret) 1485 return ret; 1486 } 1487 if (tb[DPLL_A_PIN_PRIO]) { 1488 prio = nla_get_u32(tb[DPLL_A_PIN_PRIO]); 1489 ret = dpll_pin_prio_set(dpll, pin, prio, extack); 1490 if (ret) 1491 return ret; 1492 } 1493 if (tb[DPLL_A_PIN_DIRECTION]) { 1494 direction = nla_get_u32(tb[DPLL_A_PIN_DIRECTION]); 1495 ret = dpll_pin_direction_set(pin, dpll, direction, extack); 1496 if (ret) 1497 return ret; 1498 } 1499 return 0; 1500 } 1501 1502 static int 1503 dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1504 struct netlink_ext_ack *extack) 1505 { 1506 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1507 u32 ppin_idx; 1508 int ret; 1509 1510 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1511 dpll_pin_parent_pin_nl_policy, extack); 1512 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1513 NL_SET_ERR_MSG(extack, "device parent id expected"); 1514 return -EINVAL; 1515 } 1516 ppin_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1517 1518 if (tb[DPLL_A_PIN_STATE]) { 1519 enum dpll_pin_state state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1520 1521 ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack); 1522 if (ret) 1523 return ret; 1524 } 1525 1526 return 0; 1527 } 1528 1529 static int 1530 dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info) 1531 { 1532 struct nlattr *a; 1533 int rem, ret; 1534 1535 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1536 genlmsg_len(info->genlhdr), rem) { 1537 switch (nla_type(a)) { 1538 case DPLL_A_PIN_FREQUENCY: 1539 ret = dpll_pin_freq_set(pin, a, info->extack); 1540 if (ret) 1541 return ret; 1542 break; 1543 case DPLL_A_PIN_PHASE_ADJUST: 1544 ret = dpll_pin_phase_adj_set(pin, a, info->extack); 1545 if (ret) 1546 return ret; 1547 break; 1548 case DPLL_A_PIN_PARENT_DEVICE: 1549 ret = dpll_pin_parent_device_set(pin, a, info->extack); 1550 if (ret) 1551 return ret; 1552 break; 1553 case DPLL_A_PIN_PARENT_PIN: 1554 ret = dpll_pin_parent_pin_set(pin, a, info->extack); 1555 if (ret) 1556 return ret; 1557 break; 1558 case DPLL_A_PIN_ESYNC_FREQUENCY: 1559 ret = dpll_pin_esync_set(pin, a, info->extack); 1560 if (ret) 1561 return ret; 1562 break; 1563 case DPLL_A_PIN_REFERENCE_SYNC: 1564 ret = dpll_pin_ref_sync_set(pin, a, info->extack); 1565 if (ret) 1566 return ret; 1567 break; 1568 } 1569 } 1570 1571 return 0; 1572 } 1573 1574 static struct dpll_pin * 1575 dpll_pin_find(u64 clock_id, struct nlattr *mod_name_attr, 1576 enum dpll_pin_type type, struct nlattr *board_label, 1577 struct nlattr *panel_label, struct nlattr *package_label, 1578 struct netlink_ext_ack *extack) 1579 { 1580 bool board_match, panel_match, package_match; 1581 struct dpll_pin *pin_match = NULL, *pin; 1582 const struct dpll_pin_properties *prop; 1583 bool cid_match, mod_match, type_match; 1584 unsigned long i; 1585 1586 xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) { 1587 prop = &pin->prop; 1588 cid_match = clock_id ? pin->clock_id == clock_id : true; 1589 mod_match = mod_name_attr && pin->module_name[0] ? 1590 !nla_strcmp(mod_name_attr, 1591 pin->module_name) : true; 1592 type_match = type ? prop->type == type : true; 1593 board_match = board_label ? (prop->board_label ? 1594 !nla_strcmp(board_label, prop->board_label) : false) : 1595 true; 1596 panel_match = panel_label ? (prop->panel_label ? 1597 !nla_strcmp(panel_label, prop->panel_label) : false) : 1598 true; 1599 package_match = package_label ? (prop->package_label ? 1600 !nla_strcmp(package_label, prop->package_label) : 1601 false) : true; 1602 if (cid_match && mod_match && type_match && board_match && 1603 panel_match && package_match) { 1604 if (pin_match) { 1605 NL_SET_ERR_MSG(extack, "multiple matches"); 1606 return ERR_PTR(-EINVAL); 1607 } 1608 pin_match = pin; 1609 } 1610 } 1611 if (!pin_match) { 1612 NL_SET_ERR_MSG(extack, "not found"); 1613 return ERR_PTR(-ENODEV); 1614 } 1615 return pin_match; 1616 } 1617 1618 static struct dpll_pin *dpll_pin_find_from_nlattr(struct genl_info *info) 1619 { 1620 struct nlattr *attr, *mod_name_attr = NULL, *board_label_attr = NULL, 1621 *panel_label_attr = NULL, *package_label_attr = NULL; 1622 enum dpll_pin_type type = 0; 1623 u64 clock_id = 0; 1624 int rem = 0; 1625 1626 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1627 genlmsg_len(info->genlhdr), rem) { 1628 switch (nla_type(attr)) { 1629 case DPLL_A_PIN_CLOCK_ID: 1630 if (clock_id) 1631 goto duplicated_attr; 1632 clock_id = nla_get_u64(attr); 1633 break; 1634 case DPLL_A_PIN_MODULE_NAME: 1635 if (mod_name_attr) 1636 goto duplicated_attr; 1637 mod_name_attr = attr; 1638 break; 1639 case DPLL_A_PIN_TYPE: 1640 if (type) 1641 goto duplicated_attr; 1642 type = nla_get_u32(attr); 1643 break; 1644 case DPLL_A_PIN_BOARD_LABEL: 1645 if (board_label_attr) 1646 goto duplicated_attr; 1647 board_label_attr = attr; 1648 break; 1649 case DPLL_A_PIN_PANEL_LABEL: 1650 if (panel_label_attr) 1651 goto duplicated_attr; 1652 panel_label_attr = attr; 1653 break; 1654 case DPLL_A_PIN_PACKAGE_LABEL: 1655 if (package_label_attr) 1656 goto duplicated_attr; 1657 package_label_attr = attr; 1658 break; 1659 default: 1660 break; 1661 } 1662 } 1663 if (!(clock_id || mod_name_attr || board_label_attr || 1664 panel_label_attr || package_label_attr)) { 1665 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1666 return ERR_PTR(-EINVAL); 1667 } 1668 return dpll_pin_find(clock_id, mod_name_attr, type, board_label_attr, 1669 panel_label_attr, package_label_attr, 1670 info->extack); 1671 duplicated_attr: 1672 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1673 return ERR_PTR(-EINVAL); 1674 } 1675 1676 int dpll_nl_pin_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1677 { 1678 struct dpll_pin *pin; 1679 struct sk_buff *msg; 1680 struct nlattr *hdr; 1681 int ret; 1682 1683 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1684 if (!msg) 1685 return -ENOMEM; 1686 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1687 DPLL_CMD_PIN_ID_GET); 1688 if (!hdr) { 1689 nlmsg_free(msg); 1690 return -EMSGSIZE; 1691 } 1692 pin = dpll_pin_find_from_nlattr(info); 1693 if (IS_ERR(pin)) { 1694 nlmsg_free(msg); 1695 return PTR_ERR(pin); 1696 } 1697 if (!dpll_pin_available(pin)) { 1698 nlmsg_free(msg); 1699 return -ENODEV; 1700 } 1701 ret = dpll_msg_add_pin_handle(msg, pin); 1702 if (ret) { 1703 nlmsg_free(msg); 1704 return ret; 1705 } 1706 genlmsg_end(msg, hdr); 1707 1708 return genlmsg_reply(msg, info); 1709 } 1710 1711 int dpll_nl_pin_get_doit(struct sk_buff *skb, struct genl_info *info) 1712 { 1713 struct dpll_pin *pin = info->user_ptr[0]; 1714 struct sk_buff *msg; 1715 struct nlattr *hdr; 1716 int ret; 1717 1718 if (!pin) 1719 return -ENODEV; 1720 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1721 if (!msg) 1722 return -ENOMEM; 1723 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1724 DPLL_CMD_PIN_GET); 1725 if (!hdr) { 1726 nlmsg_free(msg); 1727 return -EMSGSIZE; 1728 } 1729 ret = dpll_cmd_pin_get_one(msg, pin, info->extack); 1730 if (ret) { 1731 nlmsg_free(msg); 1732 return ret; 1733 } 1734 genlmsg_end(msg, hdr); 1735 1736 return genlmsg_reply(msg, info); 1737 } 1738 1739 int dpll_nl_pin_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1740 { 1741 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1742 struct dpll_pin *pin; 1743 struct nlattr *hdr; 1744 unsigned long i; 1745 int ret = 0; 1746 1747 mutex_lock(&dpll_lock); 1748 xa_for_each_marked_start(&dpll_pin_xa, i, pin, DPLL_REGISTERED, 1749 ctx->idx) { 1750 if (!dpll_pin_available(pin)) 1751 continue; 1752 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1753 cb->nlh->nlmsg_seq, 1754 &dpll_nl_family, NLM_F_MULTI, 1755 DPLL_CMD_PIN_GET); 1756 if (!hdr) { 1757 ret = -EMSGSIZE; 1758 break; 1759 } 1760 ret = dpll_cmd_pin_get_one(skb, pin, cb->extack); 1761 if (ret) { 1762 genlmsg_cancel(skb, hdr); 1763 break; 1764 } 1765 genlmsg_end(skb, hdr); 1766 } 1767 mutex_unlock(&dpll_lock); 1768 1769 if (ret == -EMSGSIZE) { 1770 ctx->idx = i; 1771 return skb->len; 1772 } 1773 return ret; 1774 } 1775 1776 int dpll_nl_pin_set_doit(struct sk_buff *skb, struct genl_info *info) 1777 { 1778 struct dpll_pin *pin = info->user_ptr[0]; 1779 1780 return dpll_pin_set_from_nlattr(pin, info); 1781 } 1782 1783 static struct dpll_device * 1784 dpll_device_find(u64 clock_id, struct nlattr *mod_name_attr, 1785 enum dpll_type type, struct netlink_ext_ack *extack) 1786 { 1787 struct dpll_device *dpll_match = NULL, *dpll; 1788 bool cid_match, mod_match, type_match; 1789 unsigned long i; 1790 1791 xa_for_each_marked(&dpll_device_xa, i, dpll, DPLL_REGISTERED) { 1792 cid_match = clock_id ? dpll->clock_id == clock_id : true; 1793 mod_match = mod_name_attr ? (module_name(dpll->module) ? 1794 !nla_strcmp(mod_name_attr, 1795 module_name(dpll->module)) : false) : true; 1796 type_match = type ? dpll->type == type : true; 1797 if (cid_match && mod_match && type_match) { 1798 if (dpll_match) { 1799 NL_SET_ERR_MSG(extack, "multiple matches"); 1800 return ERR_PTR(-EINVAL); 1801 } 1802 dpll_match = dpll; 1803 } 1804 } 1805 if (!dpll_match) { 1806 NL_SET_ERR_MSG(extack, "not found"); 1807 return ERR_PTR(-ENODEV); 1808 } 1809 1810 return dpll_match; 1811 } 1812 1813 static struct dpll_device * 1814 dpll_device_find_from_nlattr(struct genl_info *info) 1815 { 1816 struct nlattr *attr, *mod_name_attr = NULL; 1817 enum dpll_type type = 0; 1818 u64 clock_id = 0; 1819 int rem = 0; 1820 1821 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1822 genlmsg_len(info->genlhdr), rem) { 1823 switch (nla_type(attr)) { 1824 case DPLL_A_CLOCK_ID: 1825 if (clock_id) 1826 goto duplicated_attr; 1827 clock_id = nla_get_u64(attr); 1828 break; 1829 case DPLL_A_MODULE_NAME: 1830 if (mod_name_attr) 1831 goto duplicated_attr; 1832 mod_name_attr = attr; 1833 break; 1834 case DPLL_A_TYPE: 1835 if (type) 1836 goto duplicated_attr; 1837 type = nla_get_u32(attr); 1838 break; 1839 default: 1840 break; 1841 } 1842 } 1843 if (!clock_id && !mod_name_attr && !type) { 1844 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1845 return ERR_PTR(-EINVAL); 1846 } 1847 return dpll_device_find(clock_id, mod_name_attr, type, info->extack); 1848 duplicated_attr: 1849 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1850 return ERR_PTR(-EINVAL); 1851 } 1852 1853 int dpll_nl_device_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1854 { 1855 struct dpll_device *dpll; 1856 struct sk_buff *msg; 1857 struct nlattr *hdr; 1858 int ret; 1859 1860 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1861 if (!msg) 1862 return -ENOMEM; 1863 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1864 DPLL_CMD_DEVICE_ID_GET); 1865 if (!hdr) { 1866 nlmsg_free(msg); 1867 return -EMSGSIZE; 1868 } 1869 1870 dpll = dpll_device_find_from_nlattr(info); 1871 if (IS_ERR(dpll)) { 1872 nlmsg_free(msg); 1873 return PTR_ERR(dpll); 1874 } 1875 ret = dpll_msg_add_dev_handle(msg, dpll); 1876 if (ret) { 1877 nlmsg_free(msg); 1878 return ret; 1879 } 1880 genlmsg_end(msg, hdr); 1881 1882 return genlmsg_reply(msg, info); 1883 } 1884 1885 int dpll_nl_device_get_doit(struct sk_buff *skb, struct genl_info *info) 1886 { 1887 struct dpll_device *dpll = info->user_ptr[0]; 1888 struct sk_buff *msg; 1889 struct nlattr *hdr; 1890 int ret; 1891 1892 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1893 if (!msg) 1894 return -ENOMEM; 1895 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1896 DPLL_CMD_DEVICE_GET); 1897 if (!hdr) { 1898 nlmsg_free(msg); 1899 return -EMSGSIZE; 1900 } 1901 1902 ret = dpll_device_get_one(dpll, msg, info->extack); 1903 if (ret) { 1904 nlmsg_free(msg); 1905 return ret; 1906 } 1907 genlmsg_end(msg, hdr); 1908 1909 return genlmsg_reply(msg, info); 1910 } 1911 1912 static int 1913 dpll_set_from_nlattr(struct dpll_device *dpll, struct genl_info *info) 1914 { 1915 struct nlattr *a; 1916 int rem, ret; 1917 1918 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1919 genlmsg_len(info->genlhdr), rem) { 1920 switch (nla_type(a)) { 1921 case DPLL_A_MODE: 1922 ret = dpll_mode_set(dpll, a, info->extack); 1923 if (ret) 1924 return ret; 1925 break; 1926 case DPLL_A_PHASE_OFFSET_MONITOR: 1927 ret = dpll_phase_offset_monitor_set(dpll, a, 1928 info->extack); 1929 if (ret) 1930 return ret; 1931 break; 1932 case DPLL_A_PHASE_OFFSET_AVG_FACTOR: 1933 ret = dpll_phase_offset_avg_factor_set(dpll, a, 1934 info->extack); 1935 if (ret) 1936 return ret; 1937 break; 1938 case DPLL_A_FREQUENCY_MONITOR: 1939 ret = dpll_freq_monitor_set(dpll, a, 1940 info->extack); 1941 if (ret) 1942 return ret; 1943 break; 1944 } 1945 } 1946 1947 return 0; 1948 } 1949 1950 int dpll_nl_device_set_doit(struct sk_buff *skb, struct genl_info *info) 1951 { 1952 struct dpll_device *dpll = info->user_ptr[0]; 1953 1954 return dpll_set_from_nlattr(dpll, info); 1955 } 1956 1957 int dpll_nl_device_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1958 { 1959 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1960 struct dpll_device *dpll; 1961 struct nlattr *hdr; 1962 unsigned long i; 1963 int ret = 0; 1964 1965 mutex_lock(&dpll_lock); 1966 xa_for_each_marked_start(&dpll_device_xa, i, dpll, DPLL_REGISTERED, 1967 ctx->idx) { 1968 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1969 cb->nlh->nlmsg_seq, &dpll_nl_family, 1970 NLM_F_MULTI, DPLL_CMD_DEVICE_GET); 1971 if (!hdr) { 1972 ret = -EMSGSIZE; 1973 break; 1974 } 1975 ret = dpll_device_get_one(dpll, skb, cb->extack); 1976 if (ret) { 1977 genlmsg_cancel(skb, hdr); 1978 break; 1979 } 1980 genlmsg_end(skb, hdr); 1981 } 1982 mutex_unlock(&dpll_lock); 1983 1984 if (ret == -EMSGSIZE) { 1985 ctx->idx = i; 1986 return skb->len; 1987 } 1988 return ret; 1989 } 1990 1991 int dpll_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1992 struct genl_info *info) 1993 { 1994 u32 id; 1995 1996 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_ID)) 1997 return -EINVAL; 1998 1999 mutex_lock(&dpll_lock); 2000 id = nla_get_u32(info->attrs[DPLL_A_ID]); 2001 info->user_ptr[0] = dpll_device_get_by_id(id); 2002 if (!info->user_ptr[0]) { 2003 NL_SET_ERR_MSG(info->extack, "device not found"); 2004 goto unlock; 2005 } 2006 return 0; 2007 unlock: 2008 mutex_unlock(&dpll_lock); 2009 return -ENODEV; 2010 } 2011 2012 void dpll_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2013 struct genl_info *info) 2014 { 2015 mutex_unlock(&dpll_lock); 2016 } 2017 2018 int 2019 dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2020 struct genl_info *info) 2021 { 2022 mutex_lock(&dpll_lock); 2023 2024 return 0; 2025 } 2026 2027 void 2028 dpll_unlock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2029 struct genl_info *info) 2030 { 2031 mutex_unlock(&dpll_lock); 2032 } 2033 2034 int dpll_pin_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2035 struct genl_info *info) 2036 { 2037 int ret; 2038 2039 mutex_lock(&dpll_lock); 2040 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_PIN_ID)) { 2041 ret = -EINVAL; 2042 goto unlock_dev; 2043 } 2044 info->user_ptr[0] = xa_load(&dpll_pin_xa, 2045 nla_get_u32(info->attrs[DPLL_A_PIN_ID])); 2046 if (!info->user_ptr[0] || 2047 !dpll_pin_available(info->user_ptr[0])) { 2048 NL_SET_ERR_MSG(info->extack, "pin not found"); 2049 ret = -ENODEV; 2050 goto unlock_dev; 2051 } 2052 2053 return 0; 2054 2055 unlock_dev: 2056 mutex_unlock(&dpll_lock); 2057 return ret; 2058 } 2059 2060 void dpll_pin_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2061 struct genl_info *info) 2062 { 2063 mutex_unlock(&dpll_lock); 2064 } 2065