1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Generic netlink for DPLL management framework 4 * 5 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 6 * Copyright (c) 2023 Intel and affiliates 7 * 8 */ 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/netdevice.h> 12 #include <net/genetlink.h> 13 #include "dpll_core.h" 14 #include "dpll_netlink.h" 15 #include "dpll_nl.h" 16 #include <uapi/linux/dpll.h> 17 18 #define ASSERT_NOT_NULL(ptr) (WARN_ON(!ptr)) 19 20 #define xa_for_each_marked_start(xa, index, entry, filter, start) \ 21 for (index = start, entry = xa_find(xa, &index, ULONG_MAX, filter); \ 22 entry; entry = xa_find_after(xa, &index, ULONG_MAX, filter)) 23 24 struct dpll_dump_ctx { 25 unsigned long idx; 26 }; 27 28 static struct dpll_dump_ctx *dpll_dump_context(struct netlink_callback *cb) 29 { 30 return (struct dpll_dump_ctx *)cb->ctx; 31 } 32 33 static int 34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) 35 { 36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) 37 return -EMSGSIZE; 38 39 return 0; 40 } 41 42 static int 43 dpll_msg_add_dev_parent_handle(struct sk_buff *msg, u32 id) 44 { 45 if (nla_put_u32(msg, DPLL_A_PIN_PARENT_ID, id)) 46 return -EMSGSIZE; 47 48 return 0; 49 } 50 51 static bool dpll_pin_available(struct dpll_pin *pin) 52 { 53 struct dpll_pin_ref *par_ref; 54 unsigned long i; 55 56 if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) 57 return false; 58 xa_for_each(&pin->parent_refs, i, par_ref) 59 if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, 60 DPLL_REGISTERED)) 61 return true; 62 xa_for_each(&pin->dpll_refs, i, par_ref) 63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, 64 DPLL_REGISTERED)) 65 return true; 66 return false; 67 } 68 69 /** 70 * dpll_msg_add_pin_handle - attach pin handle attribute to a given message 71 * @msg: pointer to sk_buff message to attach a pin handle 72 * @pin: pin pointer 73 * 74 * Return: 75 * * 0 - success 76 * * -EMSGSIZE - no space in message to attach pin handle 77 */ 78 static int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin) 79 { 80 if (!pin) 81 return 0; 82 if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id)) 83 return -EMSGSIZE; 84 return 0; 85 } 86 87 static struct dpll_pin *dpll_netdev_pin(const struct net_device *dev) 88 { 89 return rcu_dereference_rtnl(dev->dpll_pin); 90 } 91 92 /** 93 * dpll_netdev_pin_handle_size - get size of pin handle attribute of a netdev 94 * @dev: netdev from which to get the pin 95 * 96 * Return: byte size of pin handle attribute, or 0 if @dev has no pin. 97 */ 98 size_t dpll_netdev_pin_handle_size(const struct net_device *dev) 99 { 100 return dpll_netdev_pin(dev) ? nla_total_size(4) : 0; /* DPLL_A_PIN_ID */ 101 } 102 103 int dpll_netdev_add_pin_handle(struct sk_buff *msg, 104 const struct net_device *dev) 105 { 106 return dpll_msg_add_pin_handle(msg, dpll_netdev_pin(dev)); 107 } 108 109 static int 110 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, 111 struct netlink_ext_ack *extack) 112 { 113 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 114 enum dpll_mode mode; 115 int ret; 116 117 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 118 if (ret) 119 return ret; 120 if (nla_put_u32(msg, DPLL_A_MODE, mode)) 121 return -EMSGSIZE; 122 123 return 0; 124 } 125 126 static int 127 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, 128 struct netlink_ext_ack *extack) 129 { 130 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 131 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 132 enum dpll_mode mode; 133 int ret; 134 135 if (ops->supported_modes_get) { 136 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, 137 extack); 138 if (ret) 139 return ret; 140 } else { 141 /* If the supported modes are not reported by the driver, the 142 * only supported mode is the one obtained by mode_get(). 143 */ 144 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 145 if (ret) 146 return ret; 147 148 __set_bit(mode, modes); 149 } 150 151 for_each_set_bit(mode, modes, DPLL_MODE_MAX + 1) 152 if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode)) 153 return -EMSGSIZE; 154 155 return 0; 156 } 157 158 static int 159 dpll_msg_add_phase_offset_monitor(struct sk_buff *msg, struct dpll_device *dpll, 160 struct netlink_ext_ack *extack) 161 { 162 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 163 enum dpll_feature_state state; 164 int ret; 165 166 if (ops->phase_offset_monitor_set && ops->phase_offset_monitor_get) { 167 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), 168 &state, extack); 169 if (ret) 170 return ret; 171 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_MONITOR, state)) 172 return -EMSGSIZE; 173 } 174 175 return 0; 176 } 177 178 static int 179 dpll_msg_add_phase_offset_avg_factor(struct sk_buff *msg, 180 struct dpll_device *dpll, 181 struct netlink_ext_ack *extack) 182 { 183 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 184 u32 factor; 185 int ret; 186 187 if (ops->phase_offset_avg_factor_get) { 188 ret = ops->phase_offset_avg_factor_get(dpll, dpll_priv(dpll), 189 &factor, extack); 190 if (ret) 191 return ret; 192 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_AVG_FACTOR, factor)) 193 return -EMSGSIZE; 194 } 195 196 return 0; 197 } 198 199 static int 200 dpll_msg_add_lock_status(struct sk_buff *msg, struct dpll_device *dpll, 201 struct netlink_ext_ack *extack) 202 { 203 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 204 enum dpll_lock_status_error status_error = 0; 205 enum dpll_lock_status status; 206 int ret; 207 208 ret = ops->lock_status_get(dpll, dpll_priv(dpll), &status, 209 &status_error, extack); 210 if (ret) 211 return ret; 212 if (nla_put_u32(msg, DPLL_A_LOCK_STATUS, status)) 213 return -EMSGSIZE; 214 if (status_error && 215 (status == DPLL_LOCK_STATUS_UNLOCKED || 216 status == DPLL_LOCK_STATUS_HOLDOVER) && 217 nla_put_u32(msg, DPLL_A_LOCK_STATUS_ERROR, status_error)) 218 return -EMSGSIZE; 219 220 return 0; 221 } 222 223 static int 224 dpll_msg_add_temp(struct sk_buff *msg, struct dpll_device *dpll, 225 struct netlink_ext_ack *extack) 226 { 227 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 228 s32 temp; 229 int ret; 230 231 if (!ops->temp_get) 232 return 0; 233 ret = ops->temp_get(dpll, dpll_priv(dpll), &temp, extack); 234 if (ret) 235 return ret; 236 if (nla_put_s32(msg, DPLL_A_TEMP, temp)) 237 return -EMSGSIZE; 238 239 return 0; 240 } 241 242 static int 243 dpll_msg_add_clock_quality_level(struct sk_buff *msg, struct dpll_device *dpll, 244 struct netlink_ext_ack *extack) 245 { 246 DECLARE_BITMAP(qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) = { 0 }; 247 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 248 enum dpll_clock_quality_level ql; 249 int ret; 250 251 if (!ops->clock_quality_level_get) 252 return 0; 253 ret = ops->clock_quality_level_get(dpll, dpll_priv(dpll), qls, extack); 254 if (ret) 255 return ret; 256 for_each_set_bit(ql, qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) 257 if (nla_put_u32(msg, DPLL_A_CLOCK_QUALITY_LEVEL, ql)) 258 return -EMSGSIZE; 259 260 return 0; 261 } 262 263 static int 264 dpll_msg_add_pin_prio(struct sk_buff *msg, struct dpll_pin *pin, 265 struct dpll_pin_ref *ref, 266 struct netlink_ext_ack *extack) 267 { 268 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 269 struct dpll_device *dpll = ref->dpll; 270 u32 prio; 271 int ret; 272 273 if (!ops->prio_get) 274 return 0; 275 ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 276 dpll_priv(dpll), &prio, extack); 277 if (ret) 278 return ret; 279 if (nla_put_u32(msg, DPLL_A_PIN_PRIO, prio)) 280 return -EMSGSIZE; 281 282 return 0; 283 } 284 285 static int 286 dpll_msg_add_pin_on_dpll_state(struct sk_buff *msg, struct dpll_pin *pin, 287 struct dpll_pin_ref *ref, 288 struct netlink_ext_ack *extack) 289 { 290 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 291 struct dpll_device *dpll = ref->dpll; 292 enum dpll_pin_state state; 293 int ret; 294 295 if (!ops->state_on_dpll_get) 296 return 0; 297 ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 298 dpll, dpll_priv(dpll), &state, extack); 299 if (ret) 300 return ret; 301 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) 302 return -EMSGSIZE; 303 304 return 0; 305 } 306 307 static int 308 dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin, 309 struct dpll_pin_ref *ref, 310 struct netlink_ext_ack *extack) 311 { 312 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 313 struct dpll_device *dpll = ref->dpll; 314 enum dpll_pin_direction direction; 315 int ret; 316 317 ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 318 dpll_priv(dpll), &direction, extack); 319 if (ret) 320 return ret; 321 if (nla_put_u32(msg, DPLL_A_PIN_DIRECTION, direction)) 322 return -EMSGSIZE; 323 324 return 0; 325 } 326 327 static int 328 dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin, 329 struct dpll_pin_ref *ref, 330 struct netlink_ext_ack *extack) 331 { 332 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 333 struct dpll_device *dpll = ref->dpll; 334 s32 phase_adjust; 335 int ret; 336 337 if (!ops->phase_adjust_get) 338 return 0; 339 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 340 dpll, dpll_priv(dpll), 341 &phase_adjust, extack); 342 if (ret) 343 return ret; 344 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust)) 345 return -EMSGSIZE; 346 347 return 0; 348 } 349 350 static int 351 dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin, 352 struct dpll_pin_ref *ref, 353 struct netlink_ext_ack *extack) 354 { 355 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 356 struct dpll_device *dpll = ref->dpll; 357 s64 phase_offset; 358 int ret; 359 360 if (!ops->phase_offset_get) 361 return 0; 362 ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 363 dpll, dpll_priv(dpll), &phase_offset, 364 extack); 365 if (ret) 366 return ret; 367 if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset), 368 &phase_offset, DPLL_A_PIN_PAD)) 369 return -EMSGSIZE; 370 371 return 0; 372 } 373 374 static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin, 375 struct dpll_pin_ref *ref, 376 struct netlink_ext_ack *extack) 377 { 378 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 379 struct dpll_device *dpll = ref->dpll; 380 s64 ffo; 381 int ret; 382 383 if (!ops->ffo_get) 384 return 0; 385 ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 386 dpll, dpll_priv(dpll), &ffo, extack); 387 if (ret) { 388 if (ret == -ENODATA) 389 return 0; 390 return ret; 391 } 392 /* Put the FFO value in PPM to preserve compatibility with older 393 * programs. 394 */ 395 ret = nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 396 div_s64(ffo, 1000000)); 397 if (ret) 398 return -EMSGSIZE; 399 return nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, 400 ffo); 401 } 402 403 static int 404 dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin, 405 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 406 { 407 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 408 struct dpll_device *dpll = ref->dpll; 409 struct nlattr *nest; 410 int fs, ret; 411 u64 freq; 412 413 if (!ops->frequency_get) 414 return 0; 415 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 416 dpll_priv(dpll), &freq, extack); 417 if (ret) 418 return ret; 419 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY, sizeof(freq), &freq, 420 DPLL_A_PIN_PAD)) 421 return -EMSGSIZE; 422 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) { 423 nest = nla_nest_start(msg, DPLL_A_PIN_FREQUENCY_SUPPORTED); 424 if (!nest) 425 return -EMSGSIZE; 426 freq = pin->prop.freq_supported[fs].min; 427 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, sizeof(freq), 428 &freq, DPLL_A_PIN_PAD)) { 429 nla_nest_cancel(msg, nest); 430 return -EMSGSIZE; 431 } 432 freq = pin->prop.freq_supported[fs].max; 433 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, sizeof(freq), 434 &freq, DPLL_A_PIN_PAD)) { 435 nla_nest_cancel(msg, nest); 436 return -EMSGSIZE; 437 } 438 nla_nest_end(msg, nest); 439 } 440 441 return 0; 442 } 443 444 static int 445 dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpll_pin *pin, 446 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 447 { 448 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 449 struct dpll_device *dpll = ref->dpll; 450 struct dpll_pin_esync esync; 451 struct nlattr *nest; 452 int ret, i; 453 454 if (!ops->esync_get) 455 return 0; 456 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 457 dpll_priv(dpll), &esync, extack); 458 if (ret == -EOPNOTSUPP) 459 return 0; 460 else if (ret) 461 return ret; 462 if (nla_put_64bit(msg, DPLL_A_PIN_ESYNC_FREQUENCY, sizeof(esync.freq), 463 &esync.freq, DPLL_A_PIN_PAD)) 464 return -EMSGSIZE; 465 if (nla_put_u32(msg, DPLL_A_PIN_ESYNC_PULSE, esync.pulse)) 466 return -EMSGSIZE; 467 for (i = 0; i < esync.range_num; i++) { 468 nest = nla_nest_start(msg, 469 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED); 470 if (!nest) 471 return -EMSGSIZE; 472 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, 473 sizeof(esync.range[i].min), 474 &esync.range[i].min, DPLL_A_PIN_PAD)) 475 goto nest_cancel; 476 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, 477 sizeof(esync.range[i].max), 478 &esync.range[i].max, DPLL_A_PIN_PAD)) 479 goto nest_cancel; 480 nla_nest_end(msg, nest); 481 } 482 return 0; 483 484 nest_cancel: 485 nla_nest_cancel(msg, nest); 486 return -EMSGSIZE; 487 } 488 489 static int 490 dpll_msg_add_pin_ref_sync(struct sk_buff *msg, struct dpll_pin *pin, 491 struct dpll_pin_ref *ref, 492 struct netlink_ext_ack *extack) 493 { 494 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 495 struct dpll_device *dpll = ref->dpll; 496 void *pin_priv, *ref_sync_pin_priv; 497 struct dpll_pin *ref_sync_pin; 498 enum dpll_pin_state state; 499 struct nlattr *nest; 500 unsigned long index; 501 int ret; 502 503 pin_priv = dpll_pin_on_dpll_priv(dpll, pin); 504 xa_for_each(&pin->ref_sync_pins, index, ref_sync_pin) { 505 if (!dpll_pin_available(ref_sync_pin)) 506 continue; 507 ref_sync_pin_priv = dpll_pin_on_dpll_priv(dpll, ref_sync_pin); 508 if (WARN_ON(!ops->ref_sync_get)) 509 return -EOPNOTSUPP; 510 ret = ops->ref_sync_get(pin, pin_priv, ref_sync_pin, 511 ref_sync_pin_priv, &state, extack); 512 if (ret) 513 return ret; 514 nest = nla_nest_start(msg, DPLL_A_PIN_REFERENCE_SYNC); 515 if (!nest) 516 return -EMSGSIZE; 517 if (nla_put_s32(msg, DPLL_A_PIN_ID, ref_sync_pin->id)) 518 goto nest_cancel; 519 if (nla_put_s32(msg, DPLL_A_PIN_STATE, state)) 520 goto nest_cancel; 521 nla_nest_end(msg, nest); 522 } 523 return 0; 524 525 nest_cancel: 526 nla_nest_cancel(msg, nest); 527 return -EMSGSIZE; 528 } 529 530 static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) 531 { 532 int fs; 533 534 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) 535 if (freq >= pin->prop.freq_supported[fs].min && 536 freq <= pin->prop.freq_supported[fs].max) 537 return true; 538 return false; 539 } 540 541 static int 542 dpll_msg_add_pin_parents(struct sk_buff *msg, struct dpll_pin *pin, 543 struct dpll_pin_ref *dpll_ref, 544 struct netlink_ext_ack *extack) 545 { 546 enum dpll_pin_state state; 547 struct dpll_pin_ref *ref; 548 struct dpll_pin *ppin; 549 struct nlattr *nest; 550 unsigned long index; 551 int ret; 552 553 xa_for_each(&pin->parent_refs, index, ref) { 554 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 555 void *parent_priv; 556 557 ppin = ref->pin; 558 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, ppin); 559 ret = ops->state_on_pin_get(pin, 560 dpll_pin_on_pin_priv(ppin, pin), 561 ppin, parent_priv, &state, extack); 562 if (ret) 563 return ret; 564 nest = nla_nest_start(msg, DPLL_A_PIN_PARENT_PIN); 565 if (!nest) 566 return -EMSGSIZE; 567 ret = dpll_msg_add_dev_parent_handle(msg, ppin->id); 568 if (ret) 569 goto nest_cancel; 570 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) { 571 ret = -EMSGSIZE; 572 goto nest_cancel; 573 } 574 nla_nest_end(msg, nest); 575 } 576 577 return 0; 578 579 nest_cancel: 580 nla_nest_cancel(msg, nest); 581 return ret; 582 } 583 584 static int 585 dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin, 586 struct netlink_ext_ack *extack) 587 { 588 struct dpll_pin_ref *ref; 589 struct nlattr *attr; 590 unsigned long index; 591 int ret; 592 593 xa_for_each(&pin->dpll_refs, index, ref) { 594 attr = nla_nest_start(msg, DPLL_A_PIN_PARENT_DEVICE); 595 if (!attr) 596 return -EMSGSIZE; 597 ret = dpll_msg_add_dev_parent_handle(msg, ref->dpll->id); 598 if (ret) 599 goto nest_cancel; 600 ret = dpll_msg_add_pin_on_dpll_state(msg, pin, ref, extack); 601 if (ret) 602 goto nest_cancel; 603 ret = dpll_msg_add_pin_prio(msg, pin, ref, extack); 604 if (ret) 605 goto nest_cancel; 606 ret = dpll_msg_add_pin_direction(msg, pin, ref, extack); 607 if (ret) 608 goto nest_cancel; 609 ret = dpll_msg_add_phase_offset(msg, pin, ref, extack); 610 if (ret) 611 goto nest_cancel; 612 nla_nest_end(msg, attr); 613 } 614 615 return 0; 616 617 nest_cancel: 618 nla_nest_end(msg, attr); 619 return ret; 620 } 621 622 static int 623 dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, 624 struct netlink_ext_ack *extack) 625 { 626 const struct dpll_pin_properties *prop = &pin->prop; 627 struct dpll_pin_ref *ref; 628 int ret; 629 630 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 631 ASSERT_NOT_NULL(ref); 632 633 ret = dpll_msg_add_pin_handle(msg, pin); 634 if (ret) 635 return ret; 636 if (nla_put_string(msg, DPLL_A_PIN_MODULE_NAME, 637 module_name(pin->module))) 638 return -EMSGSIZE; 639 if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id), 640 &pin->clock_id, DPLL_A_PIN_PAD)) 641 return -EMSGSIZE; 642 if (prop->board_label && 643 nla_put_string(msg, DPLL_A_PIN_BOARD_LABEL, prop->board_label)) 644 return -EMSGSIZE; 645 if (prop->panel_label && 646 nla_put_string(msg, DPLL_A_PIN_PANEL_LABEL, prop->panel_label)) 647 return -EMSGSIZE; 648 if (prop->package_label && 649 nla_put_string(msg, DPLL_A_PIN_PACKAGE_LABEL, 650 prop->package_label)) 651 return -EMSGSIZE; 652 if (nla_put_u32(msg, DPLL_A_PIN_TYPE, prop->type)) 653 return -EMSGSIZE; 654 if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities)) 655 return -EMSGSIZE; 656 ret = dpll_msg_add_pin_freq(msg, pin, ref, extack); 657 if (ret) 658 return ret; 659 if (prop->phase_gran && 660 nla_put_u32(msg, DPLL_A_PIN_PHASE_ADJUST_GRAN, 661 prop->phase_gran)) 662 return -EMSGSIZE; 663 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN, 664 prop->phase_range.min)) 665 return -EMSGSIZE; 666 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX, 667 prop->phase_range.max)) 668 return -EMSGSIZE; 669 ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack); 670 if (ret) 671 return ret; 672 ret = dpll_msg_add_ffo(msg, pin, ref, extack); 673 if (ret) 674 return ret; 675 ret = dpll_msg_add_pin_esync(msg, pin, ref, extack); 676 if (ret) 677 return ret; 678 if (!xa_empty(&pin->ref_sync_pins)) 679 ret = dpll_msg_add_pin_ref_sync(msg, pin, ref, extack); 680 if (ret) 681 return ret; 682 if (xa_empty(&pin->parent_refs)) 683 ret = dpll_msg_add_pin_dplls(msg, pin, extack); 684 else 685 ret = dpll_msg_add_pin_parents(msg, pin, ref, extack); 686 687 return ret; 688 } 689 690 static int 691 dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg, 692 struct netlink_ext_ack *extack) 693 { 694 int ret; 695 696 ret = dpll_msg_add_dev_handle(msg, dpll); 697 if (ret) 698 return ret; 699 if (nla_put_string(msg, DPLL_A_MODULE_NAME, module_name(dpll->module))) 700 return -EMSGSIZE; 701 if (nla_put_64bit(msg, DPLL_A_CLOCK_ID, sizeof(dpll->clock_id), 702 &dpll->clock_id, DPLL_A_PAD)) 703 return -EMSGSIZE; 704 ret = dpll_msg_add_temp(msg, dpll, extack); 705 if (ret) 706 return ret; 707 ret = dpll_msg_add_lock_status(msg, dpll, extack); 708 if (ret) 709 return ret; 710 ret = dpll_msg_add_clock_quality_level(msg, dpll, extack); 711 if (ret) 712 return ret; 713 ret = dpll_msg_add_mode(msg, dpll, extack); 714 if (ret) 715 return ret; 716 ret = dpll_msg_add_mode_supported(msg, dpll, extack); 717 if (ret) 718 return ret; 719 if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type)) 720 return -EMSGSIZE; 721 ret = dpll_msg_add_phase_offset_monitor(msg, dpll, extack); 722 if (ret) 723 return ret; 724 ret = dpll_msg_add_phase_offset_avg_factor(msg, dpll, extack); 725 if (ret) 726 return ret; 727 728 return 0; 729 } 730 731 static int 732 dpll_device_event_send(enum dpll_cmd event, struct dpll_device *dpll) 733 { 734 struct sk_buff *msg; 735 int ret = -ENOMEM; 736 void *hdr; 737 738 if (WARN_ON(!xa_get_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED))) 739 return -ENODEV; 740 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 741 if (!msg) 742 return -ENOMEM; 743 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 744 if (!hdr) 745 goto err_free_msg; 746 ret = dpll_device_get_one(dpll, msg, NULL); 747 if (ret) 748 goto err_cancel_msg; 749 genlmsg_end(msg, hdr); 750 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 751 752 return 0; 753 754 err_cancel_msg: 755 genlmsg_cancel(msg, hdr); 756 err_free_msg: 757 nlmsg_free(msg); 758 759 return ret; 760 } 761 762 int dpll_device_create_ntf(struct dpll_device *dpll) 763 { 764 return dpll_device_event_send(DPLL_CMD_DEVICE_CREATE_NTF, dpll); 765 } 766 767 int dpll_device_delete_ntf(struct dpll_device *dpll) 768 { 769 return dpll_device_event_send(DPLL_CMD_DEVICE_DELETE_NTF, dpll); 770 } 771 772 static int 773 __dpll_device_change_ntf(struct dpll_device *dpll) 774 { 775 return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); 776 } 777 778 /** 779 * dpll_device_change_ntf - notify that the dpll device has been changed 780 * @dpll: registered dpll pointer 781 * 782 * Context: acquires and holds a dpll_lock. 783 * Return: 0 if succeeds, error code otherwise. 784 */ 785 int dpll_device_change_ntf(struct dpll_device *dpll) 786 { 787 int ret; 788 789 mutex_lock(&dpll_lock); 790 ret = __dpll_device_change_ntf(dpll); 791 mutex_unlock(&dpll_lock); 792 793 return ret; 794 } 795 EXPORT_SYMBOL_GPL(dpll_device_change_ntf); 796 797 static int 798 dpll_pin_event_send(enum dpll_cmd event, struct dpll_pin *pin) 799 { 800 struct sk_buff *msg; 801 int ret = -ENOMEM; 802 void *hdr; 803 804 if (!dpll_pin_available(pin)) 805 return -ENODEV; 806 807 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 808 if (!msg) 809 return -ENOMEM; 810 811 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 812 if (!hdr) 813 goto err_free_msg; 814 ret = dpll_cmd_pin_get_one(msg, pin, NULL); 815 if (ret) 816 goto err_cancel_msg; 817 genlmsg_end(msg, hdr); 818 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 819 820 return 0; 821 822 err_cancel_msg: 823 genlmsg_cancel(msg, hdr); 824 err_free_msg: 825 nlmsg_free(msg); 826 827 return ret; 828 } 829 830 int dpll_pin_create_ntf(struct dpll_pin *pin) 831 { 832 return dpll_pin_event_send(DPLL_CMD_PIN_CREATE_NTF, pin); 833 } 834 835 int dpll_pin_delete_ntf(struct dpll_pin *pin) 836 { 837 return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); 838 } 839 840 int __dpll_pin_change_ntf(struct dpll_pin *pin) 841 { 842 return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); 843 } 844 845 /** 846 * dpll_pin_change_ntf - notify that the pin has been changed 847 * @pin: registered pin pointer 848 * 849 * Context: acquires and holds a dpll_lock. 850 * Return: 0 if succeeds, error code otherwise. 851 */ 852 int dpll_pin_change_ntf(struct dpll_pin *pin) 853 { 854 int ret; 855 856 mutex_lock(&dpll_lock); 857 ret = __dpll_pin_change_ntf(pin); 858 mutex_unlock(&dpll_lock); 859 860 return ret; 861 } 862 EXPORT_SYMBOL_GPL(dpll_pin_change_ntf); 863 864 static int 865 dpll_mode_set(struct dpll_device *dpll, struct nlattr *a, 866 struct netlink_ext_ack *extack) 867 { 868 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 869 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 870 enum dpll_mode mode = nla_get_u32(a), old_mode; 871 int ret; 872 873 if (!(ops->mode_set && ops->supported_modes_get)) { 874 NL_SET_ERR_MSG_ATTR(extack, a, 875 "dpll device does not support mode switch"); 876 return -EOPNOTSUPP; 877 } 878 879 ret = ops->mode_get(dpll, dpll_priv(dpll), &old_mode, extack); 880 if (ret) { 881 NL_SET_ERR_MSG(extack, "unable to get current mode"); 882 return ret; 883 } 884 885 if (mode == old_mode) 886 return 0; 887 888 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, extack); 889 if (ret) { 890 NL_SET_ERR_MSG(extack, "unable to get supported modes"); 891 return ret; 892 } 893 894 if (!test_bit(mode, modes)) { 895 NL_SET_ERR_MSG(extack, 896 "dpll device does not support requested mode"); 897 return -EINVAL; 898 } 899 900 return ops->mode_set(dpll, dpll_priv(dpll), mode, extack); 901 } 902 903 static int 904 dpll_phase_offset_monitor_set(struct dpll_device *dpll, struct nlattr *a, 905 struct netlink_ext_ack *extack) 906 { 907 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 908 enum dpll_feature_state state = nla_get_u32(a), old_state; 909 int ret; 910 911 if (!(ops->phase_offset_monitor_set && ops->phase_offset_monitor_get)) { 912 NL_SET_ERR_MSG_ATTR(extack, a, "dpll device not capable of phase offset monitor"); 913 return -EOPNOTSUPP; 914 } 915 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), &old_state, 916 extack); 917 if (ret) { 918 NL_SET_ERR_MSG(extack, "unable to get current state of phase offset monitor"); 919 return ret; 920 } 921 if (state == old_state) 922 return 0; 923 924 return ops->phase_offset_monitor_set(dpll, dpll_priv(dpll), state, 925 extack); 926 } 927 928 static int 929 dpll_phase_offset_avg_factor_set(struct dpll_device *dpll, struct nlattr *a, 930 struct netlink_ext_ack *extack) 931 { 932 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 933 u32 factor = nla_get_u32(a); 934 935 if (!ops->phase_offset_avg_factor_set) { 936 NL_SET_ERR_MSG_ATTR(extack, a, 937 "device not capable of changing phase offset average factor"); 938 return -EOPNOTSUPP; 939 } 940 941 return ops->phase_offset_avg_factor_set(dpll, dpll_priv(dpll), factor, 942 extack); 943 } 944 945 static int 946 dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a, 947 struct netlink_ext_ack *extack) 948 { 949 u64 freq = nla_get_u64(a), old_freq; 950 struct dpll_pin_ref *ref, *failed; 951 const struct dpll_pin_ops *ops; 952 struct dpll_device *dpll; 953 unsigned long i; 954 int ret; 955 956 if (!dpll_pin_is_freq_supported(pin, freq)) { 957 NL_SET_ERR_MSG_ATTR(extack, a, "frequency is not supported by the device"); 958 return -EINVAL; 959 } 960 961 xa_for_each(&pin->dpll_refs, i, ref) { 962 ops = dpll_pin_ops(ref); 963 if (!ops->frequency_set || !ops->frequency_get) { 964 NL_SET_ERR_MSG(extack, "frequency set not supported by the device"); 965 return -EOPNOTSUPP; 966 } 967 } 968 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 969 ops = dpll_pin_ops(ref); 970 dpll = ref->dpll; 971 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 972 dpll_priv(dpll), &old_freq, extack); 973 if (ret) { 974 NL_SET_ERR_MSG(extack, "unable to get old frequency value"); 975 return ret; 976 } 977 if (freq == old_freq) 978 return 0; 979 980 xa_for_each(&pin->dpll_refs, i, ref) { 981 ops = dpll_pin_ops(ref); 982 dpll = ref->dpll; 983 ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 984 dpll, dpll_priv(dpll), freq, extack); 985 if (ret) { 986 failed = ref; 987 NL_SET_ERR_MSG_FMT(extack, "frequency set failed for dpll_id:%u", 988 dpll->id); 989 goto rollback; 990 } 991 } 992 __dpll_pin_change_ntf(pin); 993 994 return 0; 995 996 rollback: 997 xa_for_each(&pin->dpll_refs, i, ref) { 998 if (ref == failed) 999 break; 1000 ops = dpll_pin_ops(ref); 1001 dpll = ref->dpll; 1002 if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1003 dpll, dpll_priv(dpll), old_freq, extack)) 1004 NL_SET_ERR_MSG(extack, "set frequency rollback failed"); 1005 } 1006 return ret; 1007 } 1008 1009 static int 1010 dpll_pin_esync_set(struct dpll_pin *pin, struct nlattr *a, 1011 struct netlink_ext_ack *extack) 1012 { 1013 struct dpll_pin_ref *ref, *failed; 1014 const struct dpll_pin_ops *ops; 1015 struct dpll_pin_esync esync; 1016 u64 freq = nla_get_u64(a); 1017 struct dpll_device *dpll; 1018 bool supported = false; 1019 unsigned long i; 1020 int ret; 1021 1022 xa_for_each(&pin->dpll_refs, i, ref) { 1023 ops = dpll_pin_ops(ref); 1024 if (!ops->esync_set || !ops->esync_get) { 1025 NL_SET_ERR_MSG(extack, 1026 "embedded sync feature is not supported by this device"); 1027 return -EOPNOTSUPP; 1028 } 1029 } 1030 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1031 ops = dpll_pin_ops(ref); 1032 dpll = ref->dpll; 1033 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1034 dpll_priv(dpll), &esync, extack); 1035 if (ret) { 1036 NL_SET_ERR_MSG(extack, "unable to get current embedded sync frequency value"); 1037 return ret; 1038 } 1039 if (freq == esync.freq) 1040 return 0; 1041 for (i = 0; i < esync.range_num; i++) 1042 if (freq <= esync.range[i].max && freq >= esync.range[i].min) 1043 supported = true; 1044 if (!supported) { 1045 NL_SET_ERR_MSG_ATTR(extack, a, 1046 "requested embedded sync frequency value is not supported by this device"); 1047 return -EINVAL; 1048 } 1049 1050 xa_for_each(&pin->dpll_refs, i, ref) { 1051 void *pin_dpll_priv; 1052 1053 ops = dpll_pin_ops(ref); 1054 dpll = ref->dpll; 1055 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1056 ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1057 freq, extack); 1058 if (ret) { 1059 failed = ref; 1060 NL_SET_ERR_MSG_FMT(extack, 1061 "embedded sync frequency set failed for dpll_id: %u", 1062 dpll->id); 1063 goto rollback; 1064 } 1065 } 1066 __dpll_pin_change_ntf(pin); 1067 1068 return 0; 1069 1070 rollback: 1071 xa_for_each(&pin->dpll_refs, i, ref) { 1072 void *pin_dpll_priv; 1073 1074 if (ref == failed) 1075 break; 1076 ops = dpll_pin_ops(ref); 1077 dpll = ref->dpll; 1078 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1079 if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1080 esync.freq, extack)) 1081 NL_SET_ERR_MSG(extack, "set embedded sync frequency rollback failed"); 1082 } 1083 return ret; 1084 } 1085 1086 static int 1087 dpll_pin_ref_sync_state_set(struct dpll_pin *pin, 1088 unsigned long ref_sync_pin_idx, 1089 const enum dpll_pin_state state, 1090 struct netlink_ext_ack *extack) 1091 1092 { 1093 struct dpll_pin_ref *ref, *failed; 1094 const struct dpll_pin_ops *ops; 1095 enum dpll_pin_state old_state; 1096 struct dpll_pin *ref_sync_pin; 1097 struct dpll_device *dpll; 1098 unsigned long i; 1099 int ret; 1100 1101 ref_sync_pin = xa_find(&pin->ref_sync_pins, &ref_sync_pin_idx, 1102 ULONG_MAX, XA_PRESENT); 1103 if (!ref_sync_pin) { 1104 NL_SET_ERR_MSG(extack, "reference sync pin not found"); 1105 return -EINVAL; 1106 } 1107 if (!dpll_pin_available(ref_sync_pin)) { 1108 NL_SET_ERR_MSG(extack, "reference sync pin not available"); 1109 return -EINVAL; 1110 } 1111 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1112 ASSERT_NOT_NULL(ref); 1113 ops = dpll_pin_ops(ref); 1114 if (!ops->ref_sync_set || !ops->ref_sync_get) { 1115 NL_SET_ERR_MSG(extack, "reference sync not supported by this pin"); 1116 return -EOPNOTSUPP; 1117 } 1118 dpll = ref->dpll; 1119 ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1120 ref_sync_pin, 1121 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1122 &old_state, extack); 1123 if (ret) { 1124 NL_SET_ERR_MSG(extack, "unable to get old reference sync state"); 1125 return ret; 1126 } 1127 if (state == old_state) 1128 return 0; 1129 xa_for_each(&pin->dpll_refs, i, ref) { 1130 ops = dpll_pin_ops(ref); 1131 dpll = ref->dpll; 1132 ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1133 ref_sync_pin, 1134 dpll_pin_on_dpll_priv(dpll, 1135 ref_sync_pin), 1136 state, extack); 1137 if (ret) { 1138 failed = ref; 1139 NL_SET_ERR_MSG_FMT(extack, "reference sync set failed for dpll_id:%u", 1140 dpll->id); 1141 goto rollback; 1142 } 1143 } 1144 __dpll_pin_change_ntf(pin); 1145 1146 return 0; 1147 1148 rollback: 1149 xa_for_each(&pin->dpll_refs, i, ref) { 1150 if (ref == failed) 1151 break; 1152 ops = dpll_pin_ops(ref); 1153 dpll = ref->dpll; 1154 if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1155 ref_sync_pin, 1156 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1157 old_state, extack)) 1158 NL_SET_ERR_MSG(extack, "set reference sync rollback failed"); 1159 } 1160 return ret; 1161 } 1162 1163 static int 1164 dpll_pin_ref_sync_set(struct dpll_pin *pin, struct nlattr *nest, 1165 struct netlink_ext_ack *extack) 1166 { 1167 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1168 enum dpll_pin_state state; 1169 u32 sync_pin_id; 1170 1171 nla_parse_nested(tb, DPLL_A_PIN_MAX, nest, 1172 dpll_reference_sync_nl_policy, extack); 1173 if (!tb[DPLL_A_PIN_ID]) { 1174 NL_SET_ERR_MSG(extack, "sync pin id expected"); 1175 return -EINVAL; 1176 } 1177 sync_pin_id = nla_get_u32(tb[DPLL_A_PIN_ID]); 1178 1179 if (!tb[DPLL_A_PIN_STATE]) { 1180 NL_SET_ERR_MSG(extack, "sync pin state expected"); 1181 return -EINVAL; 1182 } 1183 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1184 1185 return dpll_pin_ref_sync_state_set(pin, sync_pin_id, state, extack); 1186 } 1187 1188 static int 1189 dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, 1190 enum dpll_pin_state state, 1191 struct netlink_ext_ack *extack) 1192 { 1193 struct dpll_pin_ref *parent_ref; 1194 const struct dpll_pin_ops *ops; 1195 struct dpll_pin_ref *dpll_ref; 1196 void *pin_priv, *parent_priv; 1197 struct dpll_pin *parent; 1198 unsigned long i; 1199 int ret; 1200 1201 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1202 pin->prop.capabilities)) { 1203 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1204 return -EOPNOTSUPP; 1205 } 1206 parent = xa_load(&dpll_pin_xa, parent_idx); 1207 if (!parent) 1208 return -EINVAL; 1209 parent_ref = xa_load(&pin->parent_refs, parent->pin_idx); 1210 if (!parent_ref) 1211 return -EINVAL; 1212 xa_for_each(&parent->dpll_refs, i, dpll_ref) { 1213 ops = dpll_pin_ops(parent_ref); 1214 if (!ops->state_on_pin_set) 1215 return -EOPNOTSUPP; 1216 pin_priv = dpll_pin_on_pin_priv(parent, pin); 1217 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, parent); 1218 ret = ops->state_on_pin_set(pin, pin_priv, parent, parent_priv, 1219 state, extack); 1220 if (ret) 1221 return ret; 1222 } 1223 __dpll_pin_change_ntf(pin); 1224 1225 return 0; 1226 } 1227 1228 static int 1229 dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin, 1230 enum dpll_pin_state state, 1231 struct netlink_ext_ack *extack) 1232 { 1233 const struct dpll_pin_ops *ops; 1234 struct dpll_pin_ref *ref; 1235 int ret; 1236 1237 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1238 pin->prop.capabilities)) { 1239 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1240 return -EOPNOTSUPP; 1241 } 1242 ref = xa_load(&pin->dpll_refs, dpll->id); 1243 ASSERT_NOT_NULL(ref); 1244 ops = dpll_pin_ops(ref); 1245 if (!ops->state_on_dpll_set) 1246 return -EOPNOTSUPP; 1247 ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1248 dpll, dpll_priv(dpll), state, extack); 1249 if (ret) 1250 return ret; 1251 __dpll_pin_change_ntf(pin); 1252 1253 return 0; 1254 } 1255 1256 static int 1257 dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin, 1258 u32 prio, struct netlink_ext_ack *extack) 1259 { 1260 const struct dpll_pin_ops *ops; 1261 struct dpll_pin_ref *ref; 1262 int ret; 1263 1264 if (!(DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE & 1265 pin->prop.capabilities)) { 1266 NL_SET_ERR_MSG(extack, "prio changing is not allowed"); 1267 return -EOPNOTSUPP; 1268 } 1269 ref = xa_load(&pin->dpll_refs, dpll->id); 1270 ASSERT_NOT_NULL(ref); 1271 ops = dpll_pin_ops(ref); 1272 if (!ops->prio_set) 1273 return -EOPNOTSUPP; 1274 ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1275 dpll_priv(dpll), prio, extack); 1276 if (ret) 1277 return ret; 1278 __dpll_pin_change_ntf(pin); 1279 1280 return 0; 1281 } 1282 1283 static int 1284 dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll, 1285 enum dpll_pin_direction direction, 1286 struct netlink_ext_ack *extack) 1287 { 1288 const struct dpll_pin_ops *ops; 1289 struct dpll_pin_ref *ref; 1290 int ret; 1291 1292 if (!(DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE & 1293 pin->prop.capabilities)) { 1294 NL_SET_ERR_MSG(extack, "direction changing is not allowed"); 1295 return -EOPNOTSUPP; 1296 } 1297 ref = xa_load(&pin->dpll_refs, dpll->id); 1298 ASSERT_NOT_NULL(ref); 1299 ops = dpll_pin_ops(ref); 1300 if (!ops->direction_set) 1301 return -EOPNOTSUPP; 1302 ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1303 dpll, dpll_priv(dpll), direction, extack); 1304 if (ret) 1305 return ret; 1306 __dpll_pin_change_ntf(pin); 1307 1308 return 0; 1309 } 1310 1311 static int 1312 dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr, 1313 struct netlink_ext_ack *extack) 1314 { 1315 struct dpll_pin_ref *ref, *failed; 1316 const struct dpll_pin_ops *ops; 1317 s32 phase_adj, old_phase_adj; 1318 struct dpll_device *dpll; 1319 unsigned long i; 1320 int ret; 1321 1322 phase_adj = nla_get_s32(phase_adj_attr); 1323 if (phase_adj > pin->prop.phase_range.max || 1324 phase_adj < pin->prop.phase_range.min) { 1325 NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr, 1326 "phase adjust value of out range"); 1327 return -EINVAL; 1328 } 1329 if (pin->prop.phase_gran && phase_adj % (s32)pin->prop.phase_gran) { 1330 NL_SET_ERR_MSG_ATTR_FMT(extack, phase_adj_attr, 1331 "phase adjust value not multiple of %u", 1332 pin->prop.phase_gran); 1333 return -EINVAL; 1334 } 1335 1336 xa_for_each(&pin->dpll_refs, i, ref) { 1337 ops = dpll_pin_ops(ref); 1338 if (!ops->phase_adjust_set || !ops->phase_adjust_get) { 1339 NL_SET_ERR_MSG(extack, "phase adjust not supported"); 1340 return -EOPNOTSUPP; 1341 } 1342 } 1343 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1344 ops = dpll_pin_ops(ref); 1345 dpll = ref->dpll; 1346 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1347 dpll, dpll_priv(dpll), &old_phase_adj, 1348 extack); 1349 if (ret) { 1350 NL_SET_ERR_MSG(extack, "unable to get old phase adjust value"); 1351 return ret; 1352 } 1353 if (phase_adj == old_phase_adj) 1354 return 0; 1355 1356 xa_for_each(&pin->dpll_refs, i, ref) { 1357 ops = dpll_pin_ops(ref); 1358 dpll = ref->dpll; 1359 ret = ops->phase_adjust_set(pin, 1360 dpll_pin_on_dpll_priv(dpll, pin), 1361 dpll, dpll_priv(dpll), phase_adj, 1362 extack); 1363 if (ret) { 1364 failed = ref; 1365 NL_SET_ERR_MSG_FMT(extack, 1366 "phase adjust set failed for dpll_id:%u", 1367 dpll->id); 1368 goto rollback; 1369 } 1370 } 1371 __dpll_pin_change_ntf(pin); 1372 1373 return 0; 1374 1375 rollback: 1376 xa_for_each(&pin->dpll_refs, i, ref) { 1377 if (ref == failed) 1378 break; 1379 ops = dpll_pin_ops(ref); 1380 dpll = ref->dpll; 1381 if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1382 dpll, dpll_priv(dpll), old_phase_adj, 1383 extack)) 1384 NL_SET_ERR_MSG(extack, "set phase adjust rollback failed"); 1385 } 1386 return ret; 1387 } 1388 1389 static int 1390 dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1391 struct netlink_ext_ack *extack) 1392 { 1393 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1394 enum dpll_pin_direction direction; 1395 enum dpll_pin_state state; 1396 struct dpll_pin_ref *ref; 1397 struct dpll_device *dpll; 1398 u32 pdpll_idx, prio; 1399 int ret; 1400 1401 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1402 dpll_pin_parent_device_nl_policy, extack); 1403 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1404 NL_SET_ERR_MSG(extack, "device parent id expected"); 1405 return -EINVAL; 1406 } 1407 pdpll_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1408 dpll = xa_load(&dpll_device_xa, pdpll_idx); 1409 if (!dpll) { 1410 NL_SET_ERR_MSG(extack, "parent device not found"); 1411 return -EINVAL; 1412 } 1413 ref = xa_load(&pin->dpll_refs, dpll->id); 1414 if (!ref) { 1415 NL_SET_ERR_MSG(extack, "pin not connected to given parent device"); 1416 return -EINVAL; 1417 } 1418 if (tb[DPLL_A_PIN_STATE]) { 1419 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1420 ret = dpll_pin_state_set(dpll, pin, state, extack); 1421 if (ret) 1422 return ret; 1423 } 1424 if (tb[DPLL_A_PIN_PRIO]) { 1425 prio = nla_get_u32(tb[DPLL_A_PIN_PRIO]); 1426 ret = dpll_pin_prio_set(dpll, pin, prio, extack); 1427 if (ret) 1428 return ret; 1429 } 1430 if (tb[DPLL_A_PIN_DIRECTION]) { 1431 direction = nla_get_u32(tb[DPLL_A_PIN_DIRECTION]); 1432 ret = dpll_pin_direction_set(pin, dpll, direction, extack); 1433 if (ret) 1434 return ret; 1435 } 1436 return 0; 1437 } 1438 1439 static int 1440 dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1441 struct netlink_ext_ack *extack) 1442 { 1443 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1444 u32 ppin_idx; 1445 int ret; 1446 1447 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1448 dpll_pin_parent_pin_nl_policy, extack); 1449 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1450 NL_SET_ERR_MSG(extack, "device parent id expected"); 1451 return -EINVAL; 1452 } 1453 ppin_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1454 1455 if (tb[DPLL_A_PIN_STATE]) { 1456 enum dpll_pin_state state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1457 1458 ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack); 1459 if (ret) 1460 return ret; 1461 } 1462 1463 return 0; 1464 } 1465 1466 static int 1467 dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info) 1468 { 1469 struct nlattr *a; 1470 int rem, ret; 1471 1472 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1473 genlmsg_len(info->genlhdr), rem) { 1474 switch (nla_type(a)) { 1475 case DPLL_A_PIN_FREQUENCY: 1476 ret = dpll_pin_freq_set(pin, a, info->extack); 1477 if (ret) 1478 return ret; 1479 break; 1480 case DPLL_A_PIN_PHASE_ADJUST: 1481 ret = dpll_pin_phase_adj_set(pin, a, info->extack); 1482 if (ret) 1483 return ret; 1484 break; 1485 case DPLL_A_PIN_PARENT_DEVICE: 1486 ret = dpll_pin_parent_device_set(pin, a, info->extack); 1487 if (ret) 1488 return ret; 1489 break; 1490 case DPLL_A_PIN_PARENT_PIN: 1491 ret = dpll_pin_parent_pin_set(pin, a, info->extack); 1492 if (ret) 1493 return ret; 1494 break; 1495 case DPLL_A_PIN_ESYNC_FREQUENCY: 1496 ret = dpll_pin_esync_set(pin, a, info->extack); 1497 if (ret) 1498 return ret; 1499 break; 1500 case DPLL_A_PIN_REFERENCE_SYNC: 1501 ret = dpll_pin_ref_sync_set(pin, a, info->extack); 1502 if (ret) 1503 return ret; 1504 break; 1505 } 1506 } 1507 1508 return 0; 1509 } 1510 1511 static struct dpll_pin * 1512 dpll_pin_find(u64 clock_id, struct nlattr *mod_name_attr, 1513 enum dpll_pin_type type, struct nlattr *board_label, 1514 struct nlattr *panel_label, struct nlattr *package_label, 1515 struct netlink_ext_ack *extack) 1516 { 1517 bool board_match, panel_match, package_match; 1518 struct dpll_pin *pin_match = NULL, *pin; 1519 const struct dpll_pin_properties *prop; 1520 bool cid_match, mod_match, type_match; 1521 unsigned long i; 1522 1523 xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) { 1524 prop = &pin->prop; 1525 cid_match = clock_id ? pin->clock_id == clock_id : true; 1526 mod_match = mod_name_attr && module_name(pin->module) ? 1527 !nla_strcmp(mod_name_attr, 1528 module_name(pin->module)) : true; 1529 type_match = type ? prop->type == type : true; 1530 board_match = board_label ? (prop->board_label ? 1531 !nla_strcmp(board_label, prop->board_label) : false) : 1532 true; 1533 panel_match = panel_label ? (prop->panel_label ? 1534 !nla_strcmp(panel_label, prop->panel_label) : false) : 1535 true; 1536 package_match = package_label ? (prop->package_label ? 1537 !nla_strcmp(package_label, prop->package_label) : 1538 false) : true; 1539 if (cid_match && mod_match && type_match && board_match && 1540 panel_match && package_match) { 1541 if (pin_match) { 1542 NL_SET_ERR_MSG(extack, "multiple matches"); 1543 return ERR_PTR(-EINVAL); 1544 } 1545 pin_match = pin; 1546 } 1547 } 1548 if (!pin_match) { 1549 NL_SET_ERR_MSG(extack, "not found"); 1550 return ERR_PTR(-ENODEV); 1551 } 1552 return pin_match; 1553 } 1554 1555 static struct dpll_pin *dpll_pin_find_from_nlattr(struct genl_info *info) 1556 { 1557 struct nlattr *attr, *mod_name_attr = NULL, *board_label_attr = NULL, 1558 *panel_label_attr = NULL, *package_label_attr = NULL; 1559 enum dpll_pin_type type = 0; 1560 u64 clock_id = 0; 1561 int rem = 0; 1562 1563 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1564 genlmsg_len(info->genlhdr), rem) { 1565 switch (nla_type(attr)) { 1566 case DPLL_A_PIN_CLOCK_ID: 1567 if (clock_id) 1568 goto duplicated_attr; 1569 clock_id = nla_get_u64(attr); 1570 break; 1571 case DPLL_A_PIN_MODULE_NAME: 1572 if (mod_name_attr) 1573 goto duplicated_attr; 1574 mod_name_attr = attr; 1575 break; 1576 case DPLL_A_PIN_TYPE: 1577 if (type) 1578 goto duplicated_attr; 1579 type = nla_get_u32(attr); 1580 break; 1581 case DPLL_A_PIN_BOARD_LABEL: 1582 if (board_label_attr) 1583 goto duplicated_attr; 1584 board_label_attr = attr; 1585 break; 1586 case DPLL_A_PIN_PANEL_LABEL: 1587 if (panel_label_attr) 1588 goto duplicated_attr; 1589 panel_label_attr = attr; 1590 break; 1591 case DPLL_A_PIN_PACKAGE_LABEL: 1592 if (package_label_attr) 1593 goto duplicated_attr; 1594 package_label_attr = attr; 1595 break; 1596 default: 1597 break; 1598 } 1599 } 1600 if (!(clock_id || mod_name_attr || board_label_attr || 1601 panel_label_attr || package_label_attr)) { 1602 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1603 return ERR_PTR(-EINVAL); 1604 } 1605 return dpll_pin_find(clock_id, mod_name_attr, type, board_label_attr, 1606 panel_label_attr, package_label_attr, 1607 info->extack); 1608 duplicated_attr: 1609 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1610 return ERR_PTR(-EINVAL); 1611 } 1612 1613 int dpll_nl_pin_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1614 { 1615 struct dpll_pin *pin; 1616 struct sk_buff *msg; 1617 struct nlattr *hdr; 1618 int ret; 1619 1620 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1621 if (!msg) 1622 return -ENOMEM; 1623 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1624 DPLL_CMD_PIN_ID_GET); 1625 if (!hdr) { 1626 nlmsg_free(msg); 1627 return -EMSGSIZE; 1628 } 1629 pin = dpll_pin_find_from_nlattr(info); 1630 if (IS_ERR(pin)) { 1631 nlmsg_free(msg); 1632 return PTR_ERR(pin); 1633 } 1634 if (!dpll_pin_available(pin)) { 1635 nlmsg_free(msg); 1636 return -ENODEV; 1637 } 1638 ret = dpll_msg_add_pin_handle(msg, pin); 1639 if (ret) { 1640 nlmsg_free(msg); 1641 return ret; 1642 } 1643 genlmsg_end(msg, hdr); 1644 1645 return genlmsg_reply(msg, info); 1646 } 1647 1648 int dpll_nl_pin_get_doit(struct sk_buff *skb, struct genl_info *info) 1649 { 1650 struct dpll_pin *pin = info->user_ptr[0]; 1651 struct sk_buff *msg; 1652 struct nlattr *hdr; 1653 int ret; 1654 1655 if (!pin) 1656 return -ENODEV; 1657 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1658 if (!msg) 1659 return -ENOMEM; 1660 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1661 DPLL_CMD_PIN_GET); 1662 if (!hdr) { 1663 nlmsg_free(msg); 1664 return -EMSGSIZE; 1665 } 1666 ret = dpll_cmd_pin_get_one(msg, pin, info->extack); 1667 if (ret) { 1668 nlmsg_free(msg); 1669 return ret; 1670 } 1671 genlmsg_end(msg, hdr); 1672 1673 return genlmsg_reply(msg, info); 1674 } 1675 1676 int dpll_nl_pin_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1677 { 1678 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1679 struct dpll_pin *pin; 1680 struct nlattr *hdr; 1681 unsigned long i; 1682 int ret = 0; 1683 1684 mutex_lock(&dpll_lock); 1685 xa_for_each_marked_start(&dpll_pin_xa, i, pin, DPLL_REGISTERED, 1686 ctx->idx) { 1687 if (!dpll_pin_available(pin)) 1688 continue; 1689 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1690 cb->nlh->nlmsg_seq, 1691 &dpll_nl_family, NLM_F_MULTI, 1692 DPLL_CMD_PIN_GET); 1693 if (!hdr) { 1694 ret = -EMSGSIZE; 1695 break; 1696 } 1697 ret = dpll_cmd_pin_get_one(skb, pin, cb->extack); 1698 if (ret) { 1699 genlmsg_cancel(skb, hdr); 1700 break; 1701 } 1702 genlmsg_end(skb, hdr); 1703 } 1704 mutex_unlock(&dpll_lock); 1705 1706 if (ret == -EMSGSIZE) { 1707 ctx->idx = i; 1708 return skb->len; 1709 } 1710 return ret; 1711 } 1712 1713 int dpll_nl_pin_set_doit(struct sk_buff *skb, struct genl_info *info) 1714 { 1715 struct dpll_pin *pin = info->user_ptr[0]; 1716 1717 return dpll_pin_set_from_nlattr(pin, info); 1718 } 1719 1720 static struct dpll_device * 1721 dpll_device_find(u64 clock_id, struct nlattr *mod_name_attr, 1722 enum dpll_type type, struct netlink_ext_ack *extack) 1723 { 1724 struct dpll_device *dpll_match = NULL, *dpll; 1725 bool cid_match, mod_match, type_match; 1726 unsigned long i; 1727 1728 xa_for_each_marked(&dpll_device_xa, i, dpll, DPLL_REGISTERED) { 1729 cid_match = clock_id ? dpll->clock_id == clock_id : true; 1730 mod_match = mod_name_attr ? (module_name(dpll->module) ? 1731 !nla_strcmp(mod_name_attr, 1732 module_name(dpll->module)) : false) : true; 1733 type_match = type ? dpll->type == type : true; 1734 if (cid_match && mod_match && type_match) { 1735 if (dpll_match) { 1736 NL_SET_ERR_MSG(extack, "multiple matches"); 1737 return ERR_PTR(-EINVAL); 1738 } 1739 dpll_match = dpll; 1740 } 1741 } 1742 if (!dpll_match) { 1743 NL_SET_ERR_MSG(extack, "not found"); 1744 return ERR_PTR(-ENODEV); 1745 } 1746 1747 return dpll_match; 1748 } 1749 1750 static struct dpll_device * 1751 dpll_device_find_from_nlattr(struct genl_info *info) 1752 { 1753 struct nlattr *attr, *mod_name_attr = NULL; 1754 enum dpll_type type = 0; 1755 u64 clock_id = 0; 1756 int rem = 0; 1757 1758 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1759 genlmsg_len(info->genlhdr), rem) { 1760 switch (nla_type(attr)) { 1761 case DPLL_A_CLOCK_ID: 1762 if (clock_id) 1763 goto duplicated_attr; 1764 clock_id = nla_get_u64(attr); 1765 break; 1766 case DPLL_A_MODULE_NAME: 1767 if (mod_name_attr) 1768 goto duplicated_attr; 1769 mod_name_attr = attr; 1770 break; 1771 case DPLL_A_TYPE: 1772 if (type) 1773 goto duplicated_attr; 1774 type = nla_get_u32(attr); 1775 break; 1776 default: 1777 break; 1778 } 1779 } 1780 if (!clock_id && !mod_name_attr && !type) { 1781 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1782 return ERR_PTR(-EINVAL); 1783 } 1784 return dpll_device_find(clock_id, mod_name_attr, type, info->extack); 1785 duplicated_attr: 1786 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1787 return ERR_PTR(-EINVAL); 1788 } 1789 1790 int dpll_nl_device_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1791 { 1792 struct dpll_device *dpll; 1793 struct sk_buff *msg; 1794 struct nlattr *hdr; 1795 int ret; 1796 1797 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1798 if (!msg) 1799 return -ENOMEM; 1800 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1801 DPLL_CMD_DEVICE_ID_GET); 1802 if (!hdr) { 1803 nlmsg_free(msg); 1804 return -EMSGSIZE; 1805 } 1806 1807 dpll = dpll_device_find_from_nlattr(info); 1808 if (IS_ERR(dpll)) { 1809 nlmsg_free(msg); 1810 return PTR_ERR(dpll); 1811 } 1812 ret = dpll_msg_add_dev_handle(msg, dpll); 1813 if (ret) { 1814 nlmsg_free(msg); 1815 return ret; 1816 } 1817 genlmsg_end(msg, hdr); 1818 1819 return genlmsg_reply(msg, info); 1820 } 1821 1822 int dpll_nl_device_get_doit(struct sk_buff *skb, struct genl_info *info) 1823 { 1824 struct dpll_device *dpll = info->user_ptr[0]; 1825 struct sk_buff *msg; 1826 struct nlattr *hdr; 1827 int ret; 1828 1829 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1830 if (!msg) 1831 return -ENOMEM; 1832 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1833 DPLL_CMD_DEVICE_GET); 1834 if (!hdr) { 1835 nlmsg_free(msg); 1836 return -EMSGSIZE; 1837 } 1838 1839 ret = dpll_device_get_one(dpll, msg, info->extack); 1840 if (ret) { 1841 nlmsg_free(msg); 1842 return ret; 1843 } 1844 genlmsg_end(msg, hdr); 1845 1846 return genlmsg_reply(msg, info); 1847 } 1848 1849 static int 1850 dpll_set_from_nlattr(struct dpll_device *dpll, struct genl_info *info) 1851 { 1852 struct nlattr *a; 1853 int rem, ret; 1854 1855 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1856 genlmsg_len(info->genlhdr), rem) { 1857 switch (nla_type(a)) { 1858 case DPLL_A_MODE: 1859 ret = dpll_mode_set(dpll, a, info->extack); 1860 if (ret) 1861 return ret; 1862 break; 1863 case DPLL_A_PHASE_OFFSET_MONITOR: 1864 ret = dpll_phase_offset_monitor_set(dpll, a, 1865 info->extack); 1866 if (ret) 1867 return ret; 1868 break; 1869 case DPLL_A_PHASE_OFFSET_AVG_FACTOR: 1870 ret = dpll_phase_offset_avg_factor_set(dpll, a, 1871 info->extack); 1872 if (ret) 1873 return ret; 1874 break; 1875 } 1876 } 1877 1878 return 0; 1879 } 1880 1881 int dpll_nl_device_set_doit(struct sk_buff *skb, struct genl_info *info) 1882 { 1883 struct dpll_device *dpll = info->user_ptr[0]; 1884 1885 return dpll_set_from_nlattr(dpll, info); 1886 } 1887 1888 int dpll_nl_device_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1889 { 1890 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1891 struct dpll_device *dpll; 1892 struct nlattr *hdr; 1893 unsigned long i; 1894 int ret = 0; 1895 1896 mutex_lock(&dpll_lock); 1897 xa_for_each_marked_start(&dpll_device_xa, i, dpll, DPLL_REGISTERED, 1898 ctx->idx) { 1899 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1900 cb->nlh->nlmsg_seq, &dpll_nl_family, 1901 NLM_F_MULTI, DPLL_CMD_DEVICE_GET); 1902 if (!hdr) { 1903 ret = -EMSGSIZE; 1904 break; 1905 } 1906 ret = dpll_device_get_one(dpll, skb, cb->extack); 1907 if (ret) { 1908 genlmsg_cancel(skb, hdr); 1909 break; 1910 } 1911 genlmsg_end(skb, hdr); 1912 } 1913 mutex_unlock(&dpll_lock); 1914 1915 if (ret == -EMSGSIZE) { 1916 ctx->idx = i; 1917 return skb->len; 1918 } 1919 return ret; 1920 } 1921 1922 int dpll_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1923 struct genl_info *info) 1924 { 1925 u32 id; 1926 1927 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_ID)) 1928 return -EINVAL; 1929 1930 mutex_lock(&dpll_lock); 1931 id = nla_get_u32(info->attrs[DPLL_A_ID]); 1932 info->user_ptr[0] = dpll_device_get_by_id(id); 1933 if (!info->user_ptr[0]) { 1934 NL_SET_ERR_MSG(info->extack, "device not found"); 1935 goto unlock; 1936 } 1937 return 0; 1938 unlock: 1939 mutex_unlock(&dpll_lock); 1940 return -ENODEV; 1941 } 1942 1943 void dpll_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1944 struct genl_info *info) 1945 { 1946 mutex_unlock(&dpll_lock); 1947 } 1948 1949 int 1950 dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1951 struct genl_info *info) 1952 { 1953 mutex_lock(&dpll_lock); 1954 1955 return 0; 1956 } 1957 1958 void 1959 dpll_unlock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1960 struct genl_info *info) 1961 { 1962 mutex_unlock(&dpll_lock); 1963 } 1964 1965 int dpll_pin_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1966 struct genl_info *info) 1967 { 1968 int ret; 1969 1970 mutex_lock(&dpll_lock); 1971 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_PIN_ID)) { 1972 ret = -EINVAL; 1973 goto unlock_dev; 1974 } 1975 info->user_ptr[0] = xa_load(&dpll_pin_xa, 1976 nla_get_u32(info->attrs[DPLL_A_PIN_ID])); 1977 if (!info->user_ptr[0] || 1978 !dpll_pin_available(info->user_ptr[0])) { 1979 NL_SET_ERR_MSG(info->extack, "pin not found"); 1980 ret = -ENODEV; 1981 goto unlock_dev; 1982 } 1983 1984 return 0; 1985 1986 unlock_dev: 1987 mutex_unlock(&dpll_lock); 1988 return ret; 1989 } 1990 1991 void dpll_pin_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 1992 struct genl_info *info) 1993 { 1994 mutex_unlock(&dpll_lock); 1995 } 1996