1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Generic netlink for DPLL management framework 4 * 5 * Copyright (c) 2023 Meta Platforms, Inc. and affiliates 6 * Copyright (c) 2023 Intel and affiliates 7 * 8 */ 9 #include <linux/module.h> 10 #include <linux/kernel.h> 11 #include <linux/netdevice.h> 12 #include <net/genetlink.h> 13 #include "dpll_core.h" 14 #include "dpll_netlink.h" 15 #include "dpll_nl.h" 16 #include <uapi/linux/dpll.h> 17 18 #define ASSERT_NOT_NULL(ptr) (WARN_ON(!ptr)) 19 20 #define xa_for_each_marked_start(xa, index, entry, filter, start) \ 21 for (index = start, entry = xa_find(xa, &index, ULONG_MAX, filter); \ 22 entry; entry = xa_find_after(xa, &index, ULONG_MAX, filter)) 23 24 struct dpll_dump_ctx { 25 unsigned long idx; 26 }; 27 28 static struct dpll_dump_ctx *dpll_dump_context(struct netlink_callback *cb) 29 { 30 return (struct dpll_dump_ctx *)cb->ctx; 31 } 32 33 static int 34 dpll_msg_add_dev_handle(struct sk_buff *msg, struct dpll_device *dpll) 35 { 36 if (nla_put_u32(msg, DPLL_A_ID, dpll->id)) 37 return -EMSGSIZE; 38 39 return 0; 40 } 41 42 static int 43 dpll_msg_add_dev_parent_handle(struct sk_buff *msg, u32 id) 44 { 45 if (nla_put_u32(msg, DPLL_A_PIN_PARENT_ID, id)) 46 return -EMSGSIZE; 47 48 return 0; 49 } 50 51 static bool dpll_pin_available(struct dpll_pin *pin) 52 { 53 struct dpll_pin_ref *par_ref; 54 unsigned long i; 55 56 if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED)) 57 return false; 58 xa_for_each(&pin->parent_refs, i, par_ref) 59 if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id, 60 DPLL_REGISTERED)) 61 return true; 62 xa_for_each(&pin->dpll_refs, i, par_ref) 63 if (xa_get_mark(&dpll_device_xa, par_ref->dpll->id, 64 DPLL_REGISTERED)) 65 return true; 66 return false; 67 } 68 69 /** 70 * dpll_msg_add_pin_handle - attach pin handle attribute to a given message 71 * @msg: pointer to sk_buff message to attach a pin handle 72 * @pin: pin pointer 73 * 74 * Return: 75 * * 0 - success 76 * * -EMSGSIZE - no space in message to attach pin handle 77 */ 78 static int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin) 79 { 80 if (!pin) 81 return 0; 82 if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id)) 83 return -EMSGSIZE; 84 return 0; 85 } 86 87 static struct dpll_pin *dpll_netdev_pin(const struct net_device *dev) 88 { 89 return rcu_dereference_rtnl(dev->dpll_pin); 90 } 91 92 /** 93 * dpll_netdev_pin_handle_size - get size of pin handle attribute of a netdev 94 * @dev: netdev from which to get the pin 95 * 96 * Return: byte size of pin handle attribute, or 0 if @dev has no pin. 97 */ 98 size_t dpll_netdev_pin_handle_size(const struct net_device *dev) 99 { 100 return dpll_netdev_pin(dev) ? nla_total_size(4) : 0; /* DPLL_A_PIN_ID */ 101 } 102 103 int dpll_netdev_add_pin_handle(struct sk_buff *msg, 104 const struct net_device *dev) 105 { 106 return dpll_msg_add_pin_handle(msg, dpll_netdev_pin(dev)); 107 } 108 109 static int 110 dpll_msg_add_mode(struct sk_buff *msg, struct dpll_device *dpll, 111 struct netlink_ext_ack *extack) 112 { 113 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 114 enum dpll_mode mode; 115 int ret; 116 117 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 118 if (ret) 119 return ret; 120 if (nla_put_u32(msg, DPLL_A_MODE, mode)) 121 return -EMSGSIZE; 122 123 return 0; 124 } 125 126 static int 127 dpll_msg_add_mode_supported(struct sk_buff *msg, struct dpll_device *dpll, 128 struct netlink_ext_ack *extack) 129 { 130 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 131 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 132 enum dpll_mode mode; 133 int ret; 134 135 if (ops->supported_modes_get) { 136 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, 137 extack); 138 if (ret) 139 return ret; 140 } else { 141 /* If the supported modes are not reported by the driver, the 142 * only supported mode is the one obtained by mode_get(). 143 */ 144 ret = ops->mode_get(dpll, dpll_priv(dpll), &mode, extack); 145 if (ret) 146 return ret; 147 148 __set_bit(mode, modes); 149 } 150 151 for_each_set_bit(mode, modes, DPLL_MODE_MAX + 1) 152 if (nla_put_u32(msg, DPLL_A_MODE_SUPPORTED, mode)) 153 return -EMSGSIZE; 154 155 return 0; 156 } 157 158 static int 159 dpll_msg_add_phase_offset_monitor(struct sk_buff *msg, struct dpll_device *dpll, 160 struct netlink_ext_ack *extack) 161 { 162 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 163 enum dpll_feature_state state; 164 int ret; 165 166 if (ops->phase_offset_monitor_set && ops->phase_offset_monitor_get) { 167 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), 168 &state, extack); 169 if (ret) 170 return ret; 171 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_MONITOR, state)) 172 return -EMSGSIZE; 173 } 174 175 return 0; 176 } 177 178 static int 179 dpll_msg_add_freq_monitor(struct sk_buff *msg, struct dpll_device *dpll, 180 struct netlink_ext_ack *extack) 181 { 182 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 183 enum dpll_feature_state state; 184 int ret; 185 186 if (ops->freq_monitor_set && ops->freq_monitor_get) { 187 ret = ops->freq_monitor_get(dpll, dpll_priv(dpll), 188 &state, extack); 189 if (ret) 190 return ret; 191 if (nla_put_u32(msg, DPLL_A_FREQUENCY_MONITOR, state)) 192 return -EMSGSIZE; 193 } 194 195 return 0; 196 } 197 198 static int 199 dpll_msg_add_phase_offset_avg_factor(struct sk_buff *msg, 200 struct dpll_device *dpll, 201 struct netlink_ext_ack *extack) 202 { 203 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 204 u32 factor; 205 int ret; 206 207 if (ops->phase_offset_avg_factor_get) { 208 ret = ops->phase_offset_avg_factor_get(dpll, dpll_priv(dpll), 209 &factor, extack); 210 if (ret) 211 return ret; 212 if (nla_put_u32(msg, DPLL_A_PHASE_OFFSET_AVG_FACTOR, factor)) 213 return -EMSGSIZE; 214 } 215 216 return 0; 217 } 218 219 static int 220 dpll_msg_add_lock_status(struct sk_buff *msg, struct dpll_device *dpll, 221 struct netlink_ext_ack *extack) 222 { 223 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 224 enum dpll_lock_status_error status_error = 0; 225 enum dpll_lock_status status; 226 int ret; 227 228 ret = ops->lock_status_get(dpll, dpll_priv(dpll), &status, 229 &status_error, extack); 230 if (ret) 231 return ret; 232 if (nla_put_u32(msg, DPLL_A_LOCK_STATUS, status)) 233 return -EMSGSIZE; 234 if (status_error && 235 (status == DPLL_LOCK_STATUS_UNLOCKED || 236 status == DPLL_LOCK_STATUS_HOLDOVER) && 237 nla_put_u32(msg, DPLL_A_LOCK_STATUS_ERROR, status_error)) 238 return -EMSGSIZE; 239 240 return 0; 241 } 242 243 static int 244 dpll_msg_add_temp(struct sk_buff *msg, struct dpll_device *dpll, 245 struct netlink_ext_ack *extack) 246 { 247 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 248 s32 temp; 249 int ret; 250 251 if (!ops->temp_get) 252 return 0; 253 ret = ops->temp_get(dpll, dpll_priv(dpll), &temp, extack); 254 if (ret) 255 return ret; 256 if (nla_put_s32(msg, DPLL_A_TEMP, temp)) 257 return -EMSGSIZE; 258 259 return 0; 260 } 261 262 static int 263 dpll_msg_add_clock_quality_level(struct sk_buff *msg, struct dpll_device *dpll, 264 struct netlink_ext_ack *extack) 265 { 266 DECLARE_BITMAP(qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) = { 0 }; 267 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 268 enum dpll_clock_quality_level ql; 269 int ret; 270 271 if (!ops->clock_quality_level_get) 272 return 0; 273 ret = ops->clock_quality_level_get(dpll, dpll_priv(dpll), qls, extack); 274 if (ret) 275 return ret; 276 for_each_set_bit(ql, qls, DPLL_CLOCK_QUALITY_LEVEL_MAX + 1) 277 if (nla_put_u32(msg, DPLL_A_CLOCK_QUALITY_LEVEL, ql)) 278 return -EMSGSIZE; 279 280 return 0; 281 } 282 283 static int 284 dpll_msg_add_pin_prio(struct sk_buff *msg, struct dpll_pin *pin, 285 struct dpll_pin_ref *ref, 286 struct netlink_ext_ack *extack) 287 { 288 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 289 struct dpll_device *dpll = ref->dpll; 290 u32 prio; 291 int ret; 292 293 if (!ops->prio_get) 294 return 0; 295 ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 296 dpll_priv(dpll), &prio, extack); 297 if (ret) 298 return ret; 299 if (nla_put_u32(msg, DPLL_A_PIN_PRIO, prio)) 300 return -EMSGSIZE; 301 302 return 0; 303 } 304 305 static int 306 dpll_msg_add_pin_on_dpll_state(struct sk_buff *msg, struct dpll_pin *pin, 307 struct dpll_pin_ref *ref, 308 struct netlink_ext_ack *extack) 309 { 310 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 311 struct dpll_device *dpll = ref->dpll; 312 enum dpll_pin_state state; 313 int ret; 314 315 if (!ops->state_on_dpll_get) 316 return 0; 317 ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 318 dpll, dpll_priv(dpll), &state, extack); 319 if (ret) 320 return ret; 321 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) 322 return -EMSGSIZE; 323 324 return 0; 325 } 326 327 static int 328 dpll_msg_add_pin_operstate(struct sk_buff *msg, struct dpll_pin *pin, 329 struct dpll_pin_ref *ref, 330 struct netlink_ext_ack *extack) 331 { 332 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 333 struct dpll_device *dpll = ref->dpll; 334 enum dpll_pin_operstate operstate; 335 int ret; 336 337 if (!ops->operstate_on_dpll_get) 338 return 0; 339 ret = ops->operstate_on_dpll_get(pin, 340 dpll_pin_on_dpll_priv(dpll, pin), 341 dpll, dpll_priv(dpll), 342 &operstate, extack); 343 if (ret) 344 return ret; 345 if (nla_put_u32(msg, DPLL_A_PIN_OPERSTATE, operstate)) 346 return -EMSGSIZE; 347 348 return 0; 349 } 350 351 static int 352 dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin, 353 struct dpll_pin_ref *ref, 354 struct netlink_ext_ack *extack) 355 { 356 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 357 struct dpll_device *dpll = ref->dpll; 358 enum dpll_pin_direction direction; 359 int ret; 360 361 ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 362 dpll_priv(dpll), &direction, extack); 363 if (ret) 364 return ret; 365 if (nla_put_u32(msg, DPLL_A_PIN_DIRECTION, direction)) 366 return -EMSGSIZE; 367 368 return 0; 369 } 370 371 static int 372 dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin, 373 struct dpll_pin_ref *ref, 374 struct netlink_ext_ack *extack) 375 { 376 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 377 struct dpll_device *dpll = ref->dpll; 378 s32 phase_adjust; 379 int ret; 380 381 if (!ops->phase_adjust_get) 382 return 0; 383 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 384 dpll, dpll_priv(dpll), 385 &phase_adjust, extack); 386 if (ret) 387 return ret; 388 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST, phase_adjust)) 389 return -EMSGSIZE; 390 391 return 0; 392 } 393 394 static int 395 dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin, 396 struct dpll_pin_ref *ref, 397 struct netlink_ext_ack *extack) 398 { 399 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 400 struct dpll_device *dpll = ref->dpll; 401 s64 phase_offset; 402 int ret; 403 404 if (!ops->phase_offset_get) 405 return 0; 406 ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 407 dpll, dpll_priv(dpll), &phase_offset, 408 extack); 409 if (ret) 410 return ret; 411 if (nla_put_64bit(msg, DPLL_A_PIN_PHASE_OFFSET, sizeof(phase_offset), 412 &phase_offset, DPLL_A_PIN_PAD)) 413 return -EMSGSIZE; 414 415 return 0; 416 } 417 418 static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin, 419 struct dpll_pin_ref *ref, 420 enum dpll_ffo_type type, 421 struct netlink_ext_ack *extack) 422 { 423 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 424 struct dpll_ffo_param ffo = { .type = type }; 425 int ret; 426 427 if (!ops->ffo_get || !(ops->supported_ffo & BIT(type))) 428 return 0; 429 ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(ref->dpll, pin), 430 ref->dpll, dpll_priv(ref->dpll), &ffo, extack); 431 if (ret) { 432 if (ret == -ENODATA) 433 return 0; 434 return ret; 435 } 436 if (nla_put_sint(msg, DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET, 437 div_s64(ffo.ffo, 1000000))) 438 return -EMSGSIZE; 439 return nla_put_sint(msg, 440 DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT, 441 ffo.ffo); 442 } 443 444 static int dpll_msg_add_measured_freq(struct sk_buff *msg, struct dpll_pin *pin, 445 struct dpll_pin_ref *ref, 446 struct netlink_ext_ack *extack) 447 { 448 const struct dpll_device_ops *dev_ops = dpll_device_ops(ref->dpll); 449 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 450 struct dpll_device *dpll = ref->dpll; 451 enum dpll_feature_state state; 452 u64 measured_freq; 453 int ret; 454 455 if (!ops->measured_freq_get) 456 return 0; 457 ret = dev_ops->freq_monitor_get(dpll, dpll_priv(dpll), 458 &state, extack); 459 if (ret) 460 return ret; 461 if (state == DPLL_FEATURE_STATE_DISABLE) 462 return 0; 463 ret = ops->measured_freq_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 464 dpll, dpll_priv(dpll), &measured_freq, 465 extack); 466 if (ret) 467 return ret; 468 if (nla_put_64bit(msg, DPLL_A_PIN_MEASURED_FREQUENCY, 469 sizeof(measured_freq), &measured_freq, 470 DPLL_A_PIN_PAD)) 471 return -EMSGSIZE; 472 473 return 0; 474 } 475 476 static int 477 dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin, 478 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 479 { 480 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 481 struct dpll_device *dpll = ref->dpll; 482 struct nlattr *nest; 483 int fs, ret; 484 u64 freq; 485 486 if (!ops->frequency_get) 487 return 0; 488 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 489 dpll_priv(dpll), &freq, extack); 490 if (ret) 491 return ret; 492 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY, sizeof(freq), &freq, 493 DPLL_A_PIN_PAD)) 494 return -EMSGSIZE; 495 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) { 496 nest = nla_nest_start(msg, DPLL_A_PIN_FREQUENCY_SUPPORTED); 497 if (!nest) 498 return -EMSGSIZE; 499 freq = pin->prop.freq_supported[fs].min; 500 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, sizeof(freq), 501 &freq, DPLL_A_PIN_PAD)) { 502 nla_nest_cancel(msg, nest); 503 return -EMSGSIZE; 504 } 505 freq = pin->prop.freq_supported[fs].max; 506 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, sizeof(freq), 507 &freq, DPLL_A_PIN_PAD)) { 508 nla_nest_cancel(msg, nest); 509 return -EMSGSIZE; 510 } 511 nla_nest_end(msg, nest); 512 } 513 514 return 0; 515 } 516 517 static int 518 dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpll_pin *pin, 519 struct dpll_pin_ref *ref, struct netlink_ext_ack *extack) 520 { 521 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 522 struct dpll_device *dpll = ref->dpll; 523 struct dpll_pin_esync esync; 524 struct nlattr *nest; 525 int ret, i; 526 527 if (!ops->esync_get) 528 return 0; 529 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 530 dpll_priv(dpll), &esync, extack); 531 if (ret == -EOPNOTSUPP) 532 return 0; 533 else if (ret) 534 return ret; 535 if (nla_put_64bit(msg, DPLL_A_PIN_ESYNC_FREQUENCY, sizeof(esync.freq), 536 &esync.freq, DPLL_A_PIN_PAD)) 537 return -EMSGSIZE; 538 if (nla_put_u32(msg, DPLL_A_PIN_ESYNC_PULSE, esync.pulse)) 539 return -EMSGSIZE; 540 for (i = 0; i < esync.range_num; i++) { 541 nest = nla_nest_start(msg, 542 DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED); 543 if (!nest) 544 return -EMSGSIZE; 545 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MIN, 546 sizeof(esync.range[i].min), 547 &esync.range[i].min, DPLL_A_PIN_PAD)) 548 goto nest_cancel; 549 if (nla_put_64bit(msg, DPLL_A_PIN_FREQUENCY_MAX, 550 sizeof(esync.range[i].max), 551 &esync.range[i].max, DPLL_A_PIN_PAD)) 552 goto nest_cancel; 553 nla_nest_end(msg, nest); 554 } 555 return 0; 556 557 nest_cancel: 558 nla_nest_cancel(msg, nest); 559 return -EMSGSIZE; 560 } 561 562 static int 563 dpll_msg_add_pin_ref_sync(struct sk_buff *msg, struct dpll_pin *pin, 564 struct dpll_pin_ref *ref, 565 struct netlink_ext_ack *extack) 566 { 567 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 568 struct dpll_device *dpll = ref->dpll; 569 void *pin_priv, *ref_sync_pin_priv; 570 struct dpll_pin *ref_sync_pin; 571 enum dpll_pin_state state; 572 struct nlattr *nest; 573 unsigned long index; 574 int ret; 575 576 pin_priv = dpll_pin_on_dpll_priv(dpll, pin); 577 xa_for_each(&pin->ref_sync_pins, index, ref_sync_pin) { 578 if (!dpll_pin_available(ref_sync_pin)) 579 continue; 580 ref_sync_pin_priv = dpll_pin_on_dpll_priv(dpll, ref_sync_pin); 581 if (WARN_ON(!ops->ref_sync_get)) 582 return -EOPNOTSUPP; 583 ret = ops->ref_sync_get(pin, pin_priv, ref_sync_pin, 584 ref_sync_pin_priv, &state, extack); 585 if (ret) 586 return ret; 587 nest = nla_nest_start(msg, DPLL_A_PIN_REFERENCE_SYNC); 588 if (!nest) 589 return -EMSGSIZE; 590 if (nla_put_s32(msg, DPLL_A_PIN_ID, ref_sync_pin->id)) 591 goto nest_cancel; 592 if (nla_put_s32(msg, DPLL_A_PIN_STATE, state)) 593 goto nest_cancel; 594 nla_nest_end(msg, nest); 595 } 596 return 0; 597 598 nest_cancel: 599 nla_nest_cancel(msg, nest); 600 return -EMSGSIZE; 601 } 602 603 static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq) 604 { 605 int fs; 606 607 for (fs = 0; fs < pin->prop.freq_supported_num; fs++) 608 if (freq >= pin->prop.freq_supported[fs].min && 609 freq <= pin->prop.freq_supported[fs].max) 610 return true; 611 return false; 612 } 613 614 static int 615 dpll_msg_add_pin_parents(struct sk_buff *msg, struct dpll_pin *pin, 616 struct dpll_pin_ref *dpll_ref, 617 struct netlink_ext_ack *extack) 618 { 619 enum dpll_pin_state state; 620 struct dpll_pin_ref *ref; 621 struct dpll_pin *ppin; 622 struct nlattr *nest; 623 unsigned long index; 624 int ret; 625 626 xa_for_each(&pin->parent_refs, index, ref) { 627 const struct dpll_pin_ops *ops = dpll_pin_ops(ref); 628 void *parent_priv; 629 630 ppin = ref->pin; 631 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, ppin); 632 ret = ops->state_on_pin_get(pin, 633 dpll_pin_on_pin_priv(ppin, pin), 634 ppin, parent_priv, &state, extack); 635 if (ret) 636 return ret; 637 nest = nla_nest_start(msg, DPLL_A_PIN_PARENT_PIN); 638 if (!nest) 639 return -EMSGSIZE; 640 ret = dpll_msg_add_dev_parent_handle(msg, ppin->id); 641 if (ret) 642 goto nest_cancel; 643 if (nla_put_u32(msg, DPLL_A_PIN_STATE, state)) { 644 ret = -EMSGSIZE; 645 goto nest_cancel; 646 } 647 nla_nest_end(msg, nest); 648 } 649 650 return 0; 651 652 nest_cancel: 653 nla_nest_cancel(msg, nest); 654 return ret; 655 } 656 657 static int 658 dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin, 659 struct netlink_ext_ack *extack) 660 { 661 struct dpll_pin_ref *ref; 662 struct nlattr *attr; 663 unsigned long index; 664 int ret; 665 666 xa_for_each(&pin->dpll_refs, index, ref) { 667 attr = nla_nest_start(msg, DPLL_A_PIN_PARENT_DEVICE); 668 if (!attr) 669 return -EMSGSIZE; 670 ret = dpll_msg_add_dev_parent_handle(msg, ref->dpll->id); 671 if (ret) 672 goto nest_cancel; 673 ret = dpll_msg_add_pin_on_dpll_state(msg, pin, ref, extack); 674 if (ret) 675 goto nest_cancel; 676 ret = dpll_msg_add_pin_operstate(msg, pin, ref, extack); 677 if (ret) 678 goto nest_cancel; 679 ret = dpll_msg_add_pin_prio(msg, pin, ref, extack); 680 if (ret) 681 goto nest_cancel; 682 ret = dpll_msg_add_pin_direction(msg, pin, ref, extack); 683 if (ret) 684 goto nest_cancel; 685 ret = dpll_msg_add_phase_offset(msg, pin, ref, extack); 686 if (ret) 687 goto nest_cancel; 688 ret = dpll_msg_add_ffo(msg, pin, ref, 689 DPLL_FFO_PIN_DEVICE, extack); 690 if (ret) 691 goto nest_cancel; 692 nla_nest_end(msg, attr); 693 } 694 695 return 0; 696 697 nest_cancel: 698 nla_nest_end(msg, attr); 699 return ret; 700 } 701 702 static int 703 dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin, 704 struct netlink_ext_ack *extack) 705 { 706 const struct dpll_pin_properties *prop = &pin->prop; 707 struct dpll_pin_ref *ref; 708 int ret; 709 710 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 711 ASSERT_NOT_NULL(ref); 712 713 ret = dpll_msg_add_pin_handle(msg, pin); 714 if (ret) 715 return ret; 716 if (nla_put_string(msg, DPLL_A_PIN_MODULE_NAME, 717 module_name(pin->module))) 718 return -EMSGSIZE; 719 if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id), 720 &pin->clock_id, DPLL_A_PIN_PAD)) 721 return -EMSGSIZE; 722 if (prop->board_label && 723 nla_put_string(msg, DPLL_A_PIN_BOARD_LABEL, prop->board_label)) 724 return -EMSGSIZE; 725 if (prop->panel_label && 726 nla_put_string(msg, DPLL_A_PIN_PANEL_LABEL, prop->panel_label)) 727 return -EMSGSIZE; 728 if (prop->package_label && 729 nla_put_string(msg, DPLL_A_PIN_PACKAGE_LABEL, 730 prop->package_label)) 731 return -EMSGSIZE; 732 if (nla_put_u32(msg, DPLL_A_PIN_TYPE, prop->type)) 733 return -EMSGSIZE; 734 if (nla_put_u32(msg, DPLL_A_PIN_CAPABILITIES, prop->capabilities)) 735 return -EMSGSIZE; 736 ret = dpll_msg_add_pin_freq(msg, pin, ref, extack); 737 if (ret) 738 return ret; 739 if (prop->phase_gran && 740 nla_put_u32(msg, DPLL_A_PIN_PHASE_ADJUST_GRAN, 741 prop->phase_gran)) 742 return -EMSGSIZE; 743 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN, 744 prop->phase_range.min)) 745 return -EMSGSIZE; 746 if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MAX, 747 prop->phase_range.max)) 748 return -EMSGSIZE; 749 ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack); 750 if (ret) 751 return ret; 752 ret = dpll_msg_add_ffo(msg, pin, ref, 753 DPLL_FFO_PORT_RXTX_RATE, extack); 754 if (ret) 755 return ret; 756 ret = dpll_msg_add_measured_freq(msg, pin, ref, extack); 757 if (ret) 758 return ret; 759 ret = dpll_msg_add_pin_esync(msg, pin, ref, extack); 760 if (ret) 761 return ret; 762 if (!xa_empty(&pin->ref_sync_pins)) 763 ret = dpll_msg_add_pin_ref_sync(msg, pin, ref, extack); 764 if (ret) 765 return ret; 766 if (xa_empty(&pin->parent_refs)) 767 ret = dpll_msg_add_pin_dplls(msg, pin, extack); 768 else 769 ret = dpll_msg_add_pin_parents(msg, pin, ref, extack); 770 771 return ret; 772 } 773 774 static int 775 dpll_device_get_one(struct dpll_device *dpll, struct sk_buff *msg, 776 struct netlink_ext_ack *extack) 777 { 778 int ret; 779 780 ret = dpll_msg_add_dev_handle(msg, dpll); 781 if (ret) 782 return ret; 783 if (nla_put_string(msg, DPLL_A_MODULE_NAME, module_name(dpll->module))) 784 return -EMSGSIZE; 785 if (nla_put_64bit(msg, DPLL_A_CLOCK_ID, sizeof(dpll->clock_id), 786 &dpll->clock_id, DPLL_A_PAD)) 787 return -EMSGSIZE; 788 ret = dpll_msg_add_temp(msg, dpll, extack); 789 if (ret) 790 return ret; 791 ret = dpll_msg_add_lock_status(msg, dpll, extack); 792 if (ret) 793 return ret; 794 ret = dpll_msg_add_clock_quality_level(msg, dpll, extack); 795 if (ret) 796 return ret; 797 ret = dpll_msg_add_mode(msg, dpll, extack); 798 if (ret) 799 return ret; 800 ret = dpll_msg_add_mode_supported(msg, dpll, extack); 801 if (ret) 802 return ret; 803 if (nla_put_u32(msg, DPLL_A_TYPE, dpll->type)) 804 return -EMSGSIZE; 805 ret = dpll_msg_add_phase_offset_monitor(msg, dpll, extack); 806 if (ret) 807 return ret; 808 ret = dpll_msg_add_phase_offset_avg_factor(msg, dpll, extack); 809 if (ret) 810 return ret; 811 ret = dpll_msg_add_freq_monitor(msg, dpll, extack); 812 if (ret) 813 return ret; 814 815 return 0; 816 } 817 818 static int 819 dpll_device_event_send(enum dpll_cmd event, struct dpll_device *dpll) 820 { 821 struct sk_buff *msg; 822 int ret = -ENOMEM; 823 void *hdr; 824 825 if (WARN_ON(!xa_get_mark(&dpll_device_xa, dpll->id, DPLL_REGISTERED))) 826 return -ENODEV; 827 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 828 if (!msg) 829 return -ENOMEM; 830 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 831 if (!hdr) 832 goto err_free_msg; 833 ret = dpll_device_get_one(dpll, msg, NULL); 834 if (ret) 835 goto err_cancel_msg; 836 genlmsg_end(msg, hdr); 837 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 838 839 return 0; 840 841 err_cancel_msg: 842 genlmsg_cancel(msg, hdr); 843 err_free_msg: 844 nlmsg_free(msg); 845 846 return ret; 847 } 848 849 int dpll_device_create_ntf(struct dpll_device *dpll) 850 { 851 dpll_device_notify(dpll, DPLL_DEVICE_CREATED); 852 return dpll_device_event_send(DPLL_CMD_DEVICE_CREATE_NTF, dpll); 853 } 854 855 int dpll_device_delete_ntf(struct dpll_device *dpll) 856 { 857 dpll_device_notify(dpll, DPLL_DEVICE_DELETED); 858 return dpll_device_event_send(DPLL_CMD_DEVICE_DELETE_NTF, dpll); 859 } 860 861 static int 862 __dpll_device_change_ntf(struct dpll_device *dpll) 863 { 864 dpll_device_notify(dpll, DPLL_DEVICE_CHANGED); 865 return dpll_device_event_send(DPLL_CMD_DEVICE_CHANGE_NTF, dpll); 866 } 867 868 /** 869 * dpll_device_change_ntf - notify that the dpll device has been changed 870 * @dpll: registered dpll pointer 871 * 872 * Context: acquires and holds a dpll_lock. 873 * Return: 0 if succeeds, error code otherwise. 874 */ 875 int dpll_device_change_ntf(struct dpll_device *dpll) 876 { 877 int ret; 878 879 mutex_lock(&dpll_lock); 880 ret = __dpll_device_change_ntf(dpll); 881 mutex_unlock(&dpll_lock); 882 883 return ret; 884 } 885 EXPORT_SYMBOL_GPL(dpll_device_change_ntf); 886 887 static int 888 dpll_pin_event_send(enum dpll_cmd event, struct dpll_pin *pin) 889 { 890 struct sk_buff *msg; 891 int ret = -ENOMEM; 892 void *hdr; 893 894 if (!dpll_pin_available(pin)) 895 return -ENODEV; 896 897 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 898 if (!msg) 899 return -ENOMEM; 900 901 hdr = genlmsg_put(msg, 0, 0, &dpll_nl_family, 0, event); 902 if (!hdr) 903 goto err_free_msg; 904 ret = dpll_cmd_pin_get_one(msg, pin, NULL); 905 if (ret) 906 goto err_cancel_msg; 907 genlmsg_end(msg, hdr); 908 genlmsg_multicast(&dpll_nl_family, msg, 0, 0, GFP_KERNEL); 909 910 return 0; 911 912 err_cancel_msg: 913 genlmsg_cancel(msg, hdr); 914 err_free_msg: 915 nlmsg_free(msg); 916 917 return ret; 918 } 919 920 int dpll_pin_create_ntf(struct dpll_pin *pin) 921 { 922 dpll_pin_notify(pin, DPLL_PIN_CREATED); 923 return dpll_pin_event_send(DPLL_CMD_PIN_CREATE_NTF, pin); 924 } 925 926 int dpll_pin_delete_ntf(struct dpll_pin *pin) 927 { 928 dpll_pin_notify(pin, DPLL_PIN_DELETED); 929 return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin); 930 } 931 932 /** 933 * __dpll_pin_change_ntf - notify that the pin has been changed 934 * @pin: registered pin pointer 935 * 936 * Context: caller must hold dpll_lock. Suitable for use inside pin 937 * callbacks which are already invoked under dpll_lock. 938 * Return: 0 if succeeds, error code otherwise. 939 */ 940 int __dpll_pin_change_ntf(struct dpll_pin *pin) 941 { 942 lockdep_assert_held(&dpll_lock); 943 dpll_pin_notify(pin, DPLL_PIN_CHANGED); 944 return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin); 945 } 946 EXPORT_SYMBOL_GPL(__dpll_pin_change_ntf); 947 948 /** 949 * dpll_pin_change_ntf - notify that the pin has been changed 950 * @pin: registered pin pointer 951 * 952 * Context: acquires and holds a dpll_lock. 953 * Return: 0 if succeeds, error code otherwise. 954 */ 955 int dpll_pin_change_ntf(struct dpll_pin *pin) 956 { 957 int ret; 958 959 mutex_lock(&dpll_lock); 960 ret = __dpll_pin_change_ntf(pin); 961 mutex_unlock(&dpll_lock); 962 963 return ret; 964 } 965 EXPORT_SYMBOL_GPL(dpll_pin_change_ntf); 966 967 static int 968 dpll_mode_set(struct dpll_device *dpll, struct nlattr *a, 969 struct netlink_ext_ack *extack) 970 { 971 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 972 DECLARE_BITMAP(modes, DPLL_MODE_MAX + 1) = { 0 }; 973 enum dpll_mode mode = nla_get_u32(a), old_mode; 974 int ret; 975 976 if (!(ops->mode_set && ops->supported_modes_get)) { 977 NL_SET_ERR_MSG_ATTR(extack, a, 978 "dpll device does not support mode switch"); 979 return -EOPNOTSUPP; 980 } 981 982 ret = ops->mode_get(dpll, dpll_priv(dpll), &old_mode, extack); 983 if (ret) { 984 NL_SET_ERR_MSG(extack, "unable to get current mode"); 985 return ret; 986 } 987 988 if (mode == old_mode) 989 return 0; 990 991 ret = ops->supported_modes_get(dpll, dpll_priv(dpll), modes, extack); 992 if (ret) { 993 NL_SET_ERR_MSG(extack, "unable to get supported modes"); 994 return ret; 995 } 996 997 if (!test_bit(mode, modes)) { 998 NL_SET_ERR_MSG(extack, 999 "dpll device does not support requested mode"); 1000 return -EINVAL; 1001 } 1002 1003 return ops->mode_set(dpll, dpll_priv(dpll), mode, extack); 1004 } 1005 1006 static int 1007 dpll_phase_offset_monitor_set(struct dpll_device *dpll, struct nlattr *a, 1008 struct netlink_ext_ack *extack) 1009 { 1010 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1011 enum dpll_feature_state state = nla_get_u32(a), old_state; 1012 int ret; 1013 1014 if (!(ops->phase_offset_monitor_set && ops->phase_offset_monitor_get)) { 1015 NL_SET_ERR_MSG_ATTR(extack, a, "dpll device not capable of phase offset monitor"); 1016 return -EOPNOTSUPP; 1017 } 1018 ret = ops->phase_offset_monitor_get(dpll, dpll_priv(dpll), &old_state, 1019 extack); 1020 if (ret) { 1021 NL_SET_ERR_MSG(extack, "unable to get current state of phase offset monitor"); 1022 return ret; 1023 } 1024 if (state == old_state) 1025 return 0; 1026 1027 return ops->phase_offset_monitor_set(dpll, dpll_priv(dpll), state, 1028 extack); 1029 } 1030 1031 static int 1032 dpll_phase_offset_avg_factor_set(struct dpll_device *dpll, struct nlattr *a, 1033 struct netlink_ext_ack *extack) 1034 { 1035 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1036 u32 factor = nla_get_u32(a); 1037 1038 if (!ops->phase_offset_avg_factor_set) { 1039 NL_SET_ERR_MSG_ATTR(extack, a, 1040 "device not capable of changing phase offset average factor"); 1041 return -EOPNOTSUPP; 1042 } 1043 1044 return ops->phase_offset_avg_factor_set(dpll, dpll_priv(dpll), factor, 1045 extack); 1046 } 1047 1048 static int 1049 dpll_freq_monitor_set(struct dpll_device *dpll, struct nlattr *a, 1050 struct netlink_ext_ack *extack) 1051 { 1052 const struct dpll_device_ops *ops = dpll_device_ops(dpll); 1053 enum dpll_feature_state state = nla_get_u32(a), old_state; 1054 int ret; 1055 1056 if (!(ops->freq_monitor_set && ops->freq_monitor_get)) { 1057 NL_SET_ERR_MSG_ATTR(extack, a, 1058 "dpll device not capable of frequency monitor"); 1059 return -EOPNOTSUPP; 1060 } 1061 ret = ops->freq_monitor_get(dpll, dpll_priv(dpll), &old_state, 1062 extack); 1063 if (ret) { 1064 NL_SET_ERR_MSG(extack, 1065 "unable to get current state of frequency monitor"); 1066 return ret; 1067 } 1068 if (state == old_state) 1069 return 0; 1070 1071 return ops->freq_monitor_set(dpll, dpll_priv(dpll), state, extack); 1072 } 1073 1074 static int 1075 dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a, 1076 struct netlink_ext_ack *extack) 1077 { 1078 u64 freq = nla_get_u64(a), old_freq; 1079 struct dpll_pin_ref *ref, *failed; 1080 const struct dpll_pin_ops *ops; 1081 struct dpll_device *dpll; 1082 unsigned long i; 1083 int ret; 1084 1085 if (!dpll_pin_is_freq_supported(pin, freq)) { 1086 NL_SET_ERR_MSG_ATTR(extack, a, "frequency is not supported by the device"); 1087 return -EINVAL; 1088 } 1089 1090 xa_for_each(&pin->dpll_refs, i, ref) { 1091 ops = dpll_pin_ops(ref); 1092 if (!ops->frequency_set || !ops->frequency_get) { 1093 NL_SET_ERR_MSG(extack, "frequency set not supported by the device"); 1094 return -EOPNOTSUPP; 1095 } 1096 } 1097 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1098 ops = dpll_pin_ops(ref); 1099 dpll = ref->dpll; 1100 ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1101 dpll_priv(dpll), &old_freq, extack); 1102 if (ret) { 1103 NL_SET_ERR_MSG(extack, "unable to get old frequency value"); 1104 return ret; 1105 } 1106 if (freq == old_freq) 1107 return 0; 1108 1109 xa_for_each(&pin->dpll_refs, i, ref) { 1110 ops = dpll_pin_ops(ref); 1111 dpll = ref->dpll; 1112 ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1113 dpll, dpll_priv(dpll), freq, extack); 1114 if (ret) { 1115 failed = ref; 1116 NL_SET_ERR_MSG_FMT(extack, "frequency set failed for dpll_id:%u", 1117 dpll->id); 1118 goto rollback; 1119 } 1120 } 1121 __dpll_pin_change_ntf(pin); 1122 1123 return 0; 1124 1125 rollback: 1126 xa_for_each(&pin->dpll_refs, i, ref) { 1127 if (ref == failed) 1128 break; 1129 ops = dpll_pin_ops(ref); 1130 dpll = ref->dpll; 1131 if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1132 dpll, dpll_priv(dpll), old_freq, extack)) 1133 NL_SET_ERR_MSG(extack, "set frequency rollback failed"); 1134 } 1135 return ret; 1136 } 1137 1138 static int 1139 dpll_pin_esync_set(struct dpll_pin *pin, struct nlattr *a, 1140 struct netlink_ext_ack *extack) 1141 { 1142 struct dpll_pin_ref *ref, *failed; 1143 const struct dpll_pin_ops *ops; 1144 struct dpll_pin_esync esync; 1145 u64 freq = nla_get_u64(a); 1146 struct dpll_device *dpll; 1147 bool supported = false; 1148 unsigned long i; 1149 int ret; 1150 1151 xa_for_each(&pin->dpll_refs, i, ref) { 1152 ops = dpll_pin_ops(ref); 1153 if (!ops->esync_set || !ops->esync_get) { 1154 NL_SET_ERR_MSG(extack, 1155 "embedded sync feature is not supported by this device"); 1156 return -EOPNOTSUPP; 1157 } 1158 } 1159 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1160 ops = dpll_pin_ops(ref); 1161 dpll = ref->dpll; 1162 ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1163 dpll_priv(dpll), &esync, extack); 1164 if (ret) { 1165 NL_SET_ERR_MSG(extack, "unable to get current embedded sync frequency value"); 1166 return ret; 1167 } 1168 if (freq == esync.freq) 1169 return 0; 1170 for (i = 0; i < esync.range_num; i++) 1171 if (freq <= esync.range[i].max && freq >= esync.range[i].min) 1172 supported = true; 1173 if (!supported) { 1174 NL_SET_ERR_MSG_ATTR(extack, a, 1175 "requested embedded sync frequency value is not supported by this device"); 1176 return -EINVAL; 1177 } 1178 1179 xa_for_each(&pin->dpll_refs, i, ref) { 1180 void *pin_dpll_priv; 1181 1182 ops = dpll_pin_ops(ref); 1183 dpll = ref->dpll; 1184 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1185 ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1186 freq, extack); 1187 if (ret) { 1188 failed = ref; 1189 NL_SET_ERR_MSG_FMT(extack, 1190 "embedded sync frequency set failed for dpll_id: %u", 1191 dpll->id); 1192 goto rollback; 1193 } 1194 } 1195 __dpll_pin_change_ntf(pin); 1196 1197 return 0; 1198 1199 rollback: 1200 xa_for_each(&pin->dpll_refs, i, ref) { 1201 void *pin_dpll_priv; 1202 1203 if (ref == failed) 1204 break; 1205 ops = dpll_pin_ops(ref); 1206 dpll = ref->dpll; 1207 pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin); 1208 if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll), 1209 esync.freq, extack)) 1210 NL_SET_ERR_MSG(extack, "set embedded sync frequency rollback failed"); 1211 } 1212 return ret; 1213 } 1214 1215 static int 1216 dpll_pin_ref_sync_state_set(struct dpll_pin *pin, 1217 unsigned long ref_sync_pin_idx, 1218 const enum dpll_pin_state state, 1219 struct netlink_ext_ack *extack) 1220 1221 { 1222 struct dpll_pin_ref *ref, *failed; 1223 const struct dpll_pin_ops *ops; 1224 enum dpll_pin_state old_state; 1225 struct dpll_pin *ref_sync_pin; 1226 struct dpll_device *dpll; 1227 unsigned long i; 1228 int ret; 1229 1230 ref_sync_pin = xa_find(&pin->ref_sync_pins, &ref_sync_pin_idx, 1231 ULONG_MAX, XA_PRESENT); 1232 if (!ref_sync_pin) { 1233 NL_SET_ERR_MSG(extack, "reference sync pin not found"); 1234 return -EINVAL; 1235 } 1236 if (!dpll_pin_available(ref_sync_pin)) { 1237 NL_SET_ERR_MSG(extack, "reference sync pin not available"); 1238 return -EINVAL; 1239 } 1240 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1241 ASSERT_NOT_NULL(ref); 1242 ops = dpll_pin_ops(ref); 1243 if (!ops->ref_sync_set || !ops->ref_sync_get) { 1244 NL_SET_ERR_MSG(extack, "reference sync not supported by this pin"); 1245 return -EOPNOTSUPP; 1246 } 1247 dpll = ref->dpll; 1248 ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1249 ref_sync_pin, 1250 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1251 &old_state, extack); 1252 if (ret) { 1253 NL_SET_ERR_MSG(extack, "unable to get old reference sync state"); 1254 return ret; 1255 } 1256 if (state == old_state) 1257 return 0; 1258 xa_for_each(&pin->dpll_refs, i, ref) { 1259 ops = dpll_pin_ops(ref); 1260 dpll = ref->dpll; 1261 ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1262 ref_sync_pin, 1263 dpll_pin_on_dpll_priv(dpll, 1264 ref_sync_pin), 1265 state, extack); 1266 if (ret) { 1267 failed = ref; 1268 NL_SET_ERR_MSG_FMT(extack, "reference sync set failed for dpll_id:%u", 1269 dpll->id); 1270 goto rollback; 1271 } 1272 } 1273 __dpll_pin_change_ntf(pin); 1274 1275 return 0; 1276 1277 rollback: 1278 xa_for_each(&pin->dpll_refs, i, ref) { 1279 if (ref == failed) 1280 break; 1281 ops = dpll_pin_ops(ref); 1282 dpll = ref->dpll; 1283 if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1284 ref_sync_pin, 1285 dpll_pin_on_dpll_priv(dpll, ref_sync_pin), 1286 old_state, extack)) 1287 NL_SET_ERR_MSG(extack, "set reference sync rollback failed"); 1288 } 1289 return ret; 1290 } 1291 1292 static int 1293 dpll_pin_ref_sync_set(struct dpll_pin *pin, struct nlattr *nest, 1294 struct netlink_ext_ack *extack) 1295 { 1296 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1297 enum dpll_pin_state state; 1298 u32 sync_pin_id; 1299 1300 nla_parse_nested(tb, DPLL_A_PIN_MAX, nest, 1301 dpll_reference_sync_nl_policy, extack); 1302 if (!tb[DPLL_A_PIN_ID]) { 1303 NL_SET_ERR_MSG(extack, "sync pin id expected"); 1304 return -EINVAL; 1305 } 1306 sync_pin_id = nla_get_u32(tb[DPLL_A_PIN_ID]); 1307 1308 if (!tb[DPLL_A_PIN_STATE]) { 1309 NL_SET_ERR_MSG(extack, "sync pin state expected"); 1310 return -EINVAL; 1311 } 1312 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1313 1314 return dpll_pin_ref_sync_state_set(pin, sync_pin_id, state, extack); 1315 } 1316 1317 static int 1318 dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx, 1319 enum dpll_pin_state state, 1320 struct netlink_ext_ack *extack) 1321 { 1322 struct dpll_pin_ref *parent_ref; 1323 const struct dpll_pin_ops *ops; 1324 struct dpll_pin_ref *dpll_ref; 1325 void *pin_priv, *parent_priv; 1326 struct dpll_pin *parent; 1327 unsigned long i; 1328 int ret; 1329 1330 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1331 pin->prop.capabilities)) { 1332 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1333 return -EOPNOTSUPP; 1334 } 1335 parent = xa_load(&dpll_pin_xa, parent_idx); 1336 if (!parent) 1337 return -EINVAL; 1338 parent_ref = xa_load(&pin->parent_refs, parent->pin_idx); 1339 if (!parent_ref) 1340 return -EINVAL; 1341 xa_for_each(&parent->dpll_refs, i, dpll_ref) { 1342 ops = dpll_pin_ops(parent_ref); 1343 if (!ops->state_on_pin_set) 1344 return -EOPNOTSUPP; 1345 pin_priv = dpll_pin_on_pin_priv(parent, pin); 1346 parent_priv = dpll_pin_on_dpll_priv(dpll_ref->dpll, parent); 1347 ret = ops->state_on_pin_set(pin, pin_priv, parent, parent_priv, 1348 state, extack); 1349 if (ret) 1350 return ret; 1351 } 1352 __dpll_pin_change_ntf(pin); 1353 1354 return 0; 1355 } 1356 1357 static int 1358 dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin, 1359 enum dpll_pin_state state, 1360 struct netlink_ext_ack *extack) 1361 { 1362 const struct dpll_pin_ops *ops; 1363 struct dpll_pin_ref *ref; 1364 int ret; 1365 1366 if (!(DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE & 1367 pin->prop.capabilities)) { 1368 NL_SET_ERR_MSG(extack, "state changing is not allowed"); 1369 return -EOPNOTSUPP; 1370 } 1371 ref = xa_load(&pin->dpll_refs, dpll->id); 1372 ASSERT_NOT_NULL(ref); 1373 ops = dpll_pin_ops(ref); 1374 if (!ops->state_on_dpll_set) 1375 return -EOPNOTSUPP; 1376 ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1377 dpll, dpll_priv(dpll), state, extack); 1378 if (ret) 1379 return ret; 1380 __dpll_pin_change_ntf(pin); 1381 1382 return 0; 1383 } 1384 1385 static int 1386 dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin, 1387 u32 prio, struct netlink_ext_ack *extack) 1388 { 1389 const struct dpll_pin_ops *ops; 1390 struct dpll_pin_ref *ref; 1391 int ret; 1392 1393 if (!(DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE & 1394 pin->prop.capabilities)) { 1395 NL_SET_ERR_MSG(extack, "prio changing is not allowed"); 1396 return -EOPNOTSUPP; 1397 } 1398 ref = xa_load(&pin->dpll_refs, dpll->id); 1399 ASSERT_NOT_NULL(ref); 1400 ops = dpll_pin_ops(ref); 1401 if (!ops->prio_set) 1402 return -EOPNOTSUPP; 1403 ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll, 1404 dpll_priv(dpll), prio, extack); 1405 if (ret) 1406 return ret; 1407 __dpll_pin_change_ntf(pin); 1408 1409 return 0; 1410 } 1411 1412 static int 1413 dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll, 1414 enum dpll_pin_direction direction, 1415 struct netlink_ext_ack *extack) 1416 { 1417 const struct dpll_pin_ops *ops; 1418 struct dpll_pin_ref *ref; 1419 int ret; 1420 1421 if (!(DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE & 1422 pin->prop.capabilities)) { 1423 NL_SET_ERR_MSG(extack, "direction changing is not allowed"); 1424 return -EOPNOTSUPP; 1425 } 1426 ref = xa_load(&pin->dpll_refs, dpll->id); 1427 ASSERT_NOT_NULL(ref); 1428 ops = dpll_pin_ops(ref); 1429 if (!ops->direction_set) 1430 return -EOPNOTSUPP; 1431 ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1432 dpll, dpll_priv(dpll), direction, extack); 1433 if (ret) 1434 return ret; 1435 __dpll_pin_change_ntf(pin); 1436 1437 return 0; 1438 } 1439 1440 static int 1441 dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr, 1442 struct netlink_ext_ack *extack) 1443 { 1444 struct dpll_pin_ref *ref, *failed; 1445 const struct dpll_pin_ops *ops; 1446 s32 phase_adj, old_phase_adj; 1447 struct dpll_device *dpll; 1448 unsigned long i; 1449 int ret; 1450 1451 phase_adj = nla_get_s32(phase_adj_attr); 1452 if (phase_adj > pin->prop.phase_range.max || 1453 phase_adj < pin->prop.phase_range.min) { 1454 NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr, 1455 "phase adjust value of out range"); 1456 return -EINVAL; 1457 } 1458 if (pin->prop.phase_gran && phase_adj % (s32)pin->prop.phase_gran) { 1459 NL_SET_ERR_MSG_ATTR_FMT(extack, phase_adj_attr, 1460 "phase adjust value not multiple of %u", 1461 pin->prop.phase_gran); 1462 return -EINVAL; 1463 } 1464 1465 xa_for_each(&pin->dpll_refs, i, ref) { 1466 ops = dpll_pin_ops(ref); 1467 if (!ops->phase_adjust_set || !ops->phase_adjust_get) { 1468 NL_SET_ERR_MSG(extack, "phase adjust not supported"); 1469 return -EOPNOTSUPP; 1470 } 1471 } 1472 ref = dpll_xa_ref_dpll_first(&pin->dpll_refs); 1473 ops = dpll_pin_ops(ref); 1474 dpll = ref->dpll; 1475 ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin), 1476 dpll, dpll_priv(dpll), &old_phase_adj, 1477 extack); 1478 if (ret) { 1479 NL_SET_ERR_MSG(extack, "unable to get old phase adjust value"); 1480 return ret; 1481 } 1482 if (phase_adj == old_phase_adj) 1483 return 0; 1484 1485 xa_for_each(&pin->dpll_refs, i, ref) { 1486 ops = dpll_pin_ops(ref); 1487 dpll = ref->dpll; 1488 ret = ops->phase_adjust_set(pin, 1489 dpll_pin_on_dpll_priv(dpll, pin), 1490 dpll, dpll_priv(dpll), phase_adj, 1491 extack); 1492 if (ret) { 1493 failed = ref; 1494 NL_SET_ERR_MSG_FMT(extack, 1495 "phase adjust set failed for dpll_id:%u", 1496 dpll->id); 1497 goto rollback; 1498 } 1499 } 1500 __dpll_pin_change_ntf(pin); 1501 1502 return 0; 1503 1504 rollback: 1505 xa_for_each(&pin->dpll_refs, i, ref) { 1506 if (ref == failed) 1507 break; 1508 ops = dpll_pin_ops(ref); 1509 dpll = ref->dpll; 1510 if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin), 1511 dpll, dpll_priv(dpll), old_phase_adj, 1512 extack)) 1513 NL_SET_ERR_MSG(extack, "set phase adjust rollback failed"); 1514 } 1515 return ret; 1516 } 1517 1518 static int 1519 dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1520 struct netlink_ext_ack *extack) 1521 { 1522 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1523 enum dpll_pin_direction direction; 1524 enum dpll_pin_state state; 1525 struct dpll_pin_ref *ref; 1526 struct dpll_device *dpll; 1527 u32 pdpll_idx, prio; 1528 int ret; 1529 1530 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1531 dpll_pin_parent_device_nl_policy, extack); 1532 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1533 NL_SET_ERR_MSG(extack, "device parent id expected"); 1534 return -EINVAL; 1535 } 1536 pdpll_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1537 dpll = xa_load(&dpll_device_xa, pdpll_idx); 1538 if (!dpll) { 1539 NL_SET_ERR_MSG(extack, "parent device not found"); 1540 return -EINVAL; 1541 } 1542 ref = xa_load(&pin->dpll_refs, dpll->id); 1543 if (!ref) { 1544 NL_SET_ERR_MSG(extack, "pin not connected to given parent device"); 1545 return -EINVAL; 1546 } 1547 if (tb[DPLL_A_PIN_STATE]) { 1548 state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1549 ret = dpll_pin_state_set(dpll, pin, state, extack); 1550 if (ret) 1551 return ret; 1552 } 1553 if (tb[DPLL_A_PIN_PRIO]) { 1554 prio = nla_get_u32(tb[DPLL_A_PIN_PRIO]); 1555 ret = dpll_pin_prio_set(dpll, pin, prio, extack); 1556 if (ret) 1557 return ret; 1558 } 1559 if (tb[DPLL_A_PIN_DIRECTION]) { 1560 direction = nla_get_u32(tb[DPLL_A_PIN_DIRECTION]); 1561 ret = dpll_pin_direction_set(pin, dpll, direction, extack); 1562 if (ret) 1563 return ret; 1564 } 1565 return 0; 1566 } 1567 1568 static int 1569 dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest, 1570 struct netlink_ext_ack *extack) 1571 { 1572 struct nlattr *tb[DPLL_A_PIN_MAX + 1]; 1573 u32 ppin_idx; 1574 int ret; 1575 1576 nla_parse_nested(tb, DPLL_A_PIN_MAX, parent_nest, 1577 dpll_pin_parent_pin_nl_policy, extack); 1578 if (!tb[DPLL_A_PIN_PARENT_ID]) { 1579 NL_SET_ERR_MSG(extack, "device parent id expected"); 1580 return -EINVAL; 1581 } 1582 ppin_idx = nla_get_u32(tb[DPLL_A_PIN_PARENT_ID]); 1583 1584 if (tb[DPLL_A_PIN_STATE]) { 1585 enum dpll_pin_state state = nla_get_u32(tb[DPLL_A_PIN_STATE]); 1586 1587 ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack); 1588 if (ret) 1589 return ret; 1590 } 1591 1592 return 0; 1593 } 1594 1595 static int 1596 dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info) 1597 { 1598 struct nlattr *a; 1599 int rem, ret; 1600 1601 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1602 genlmsg_len(info->genlhdr), rem) { 1603 switch (nla_type(a)) { 1604 case DPLL_A_PIN_FREQUENCY: 1605 ret = dpll_pin_freq_set(pin, a, info->extack); 1606 if (ret) 1607 return ret; 1608 break; 1609 case DPLL_A_PIN_PHASE_ADJUST: 1610 ret = dpll_pin_phase_adj_set(pin, a, info->extack); 1611 if (ret) 1612 return ret; 1613 break; 1614 case DPLL_A_PIN_PARENT_DEVICE: 1615 ret = dpll_pin_parent_device_set(pin, a, info->extack); 1616 if (ret) 1617 return ret; 1618 break; 1619 case DPLL_A_PIN_PARENT_PIN: 1620 ret = dpll_pin_parent_pin_set(pin, a, info->extack); 1621 if (ret) 1622 return ret; 1623 break; 1624 case DPLL_A_PIN_ESYNC_FREQUENCY: 1625 ret = dpll_pin_esync_set(pin, a, info->extack); 1626 if (ret) 1627 return ret; 1628 break; 1629 case DPLL_A_PIN_REFERENCE_SYNC: 1630 ret = dpll_pin_ref_sync_set(pin, a, info->extack); 1631 if (ret) 1632 return ret; 1633 break; 1634 } 1635 } 1636 1637 return 0; 1638 } 1639 1640 static struct dpll_pin * 1641 dpll_pin_find(u64 clock_id, struct nlattr *mod_name_attr, 1642 enum dpll_pin_type type, struct nlattr *board_label, 1643 struct nlattr *panel_label, struct nlattr *package_label, 1644 struct netlink_ext_ack *extack) 1645 { 1646 bool board_match, panel_match, package_match; 1647 struct dpll_pin *pin_match = NULL, *pin; 1648 const struct dpll_pin_properties *prop; 1649 bool cid_match, mod_match, type_match; 1650 unsigned long i; 1651 1652 xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) { 1653 prop = &pin->prop; 1654 cid_match = clock_id ? pin->clock_id == clock_id : true; 1655 mod_match = mod_name_attr && module_name(pin->module) ? 1656 !nla_strcmp(mod_name_attr, 1657 module_name(pin->module)) : true; 1658 type_match = type ? prop->type == type : true; 1659 board_match = board_label ? (prop->board_label ? 1660 !nla_strcmp(board_label, prop->board_label) : false) : 1661 true; 1662 panel_match = panel_label ? (prop->panel_label ? 1663 !nla_strcmp(panel_label, prop->panel_label) : false) : 1664 true; 1665 package_match = package_label ? (prop->package_label ? 1666 !nla_strcmp(package_label, prop->package_label) : 1667 false) : true; 1668 if (cid_match && mod_match && type_match && board_match && 1669 panel_match && package_match) { 1670 if (pin_match) { 1671 NL_SET_ERR_MSG(extack, "multiple matches"); 1672 return ERR_PTR(-EINVAL); 1673 } 1674 pin_match = pin; 1675 } 1676 } 1677 if (!pin_match) { 1678 NL_SET_ERR_MSG(extack, "not found"); 1679 return ERR_PTR(-ENODEV); 1680 } 1681 return pin_match; 1682 } 1683 1684 static struct dpll_pin *dpll_pin_find_from_nlattr(struct genl_info *info) 1685 { 1686 struct nlattr *attr, *mod_name_attr = NULL, *board_label_attr = NULL, 1687 *panel_label_attr = NULL, *package_label_attr = NULL; 1688 enum dpll_pin_type type = 0; 1689 u64 clock_id = 0; 1690 int rem = 0; 1691 1692 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1693 genlmsg_len(info->genlhdr), rem) { 1694 switch (nla_type(attr)) { 1695 case DPLL_A_PIN_CLOCK_ID: 1696 if (clock_id) 1697 goto duplicated_attr; 1698 clock_id = nla_get_u64(attr); 1699 break; 1700 case DPLL_A_PIN_MODULE_NAME: 1701 if (mod_name_attr) 1702 goto duplicated_attr; 1703 mod_name_attr = attr; 1704 break; 1705 case DPLL_A_PIN_TYPE: 1706 if (type) 1707 goto duplicated_attr; 1708 type = nla_get_u32(attr); 1709 break; 1710 case DPLL_A_PIN_BOARD_LABEL: 1711 if (board_label_attr) 1712 goto duplicated_attr; 1713 board_label_attr = attr; 1714 break; 1715 case DPLL_A_PIN_PANEL_LABEL: 1716 if (panel_label_attr) 1717 goto duplicated_attr; 1718 panel_label_attr = attr; 1719 break; 1720 case DPLL_A_PIN_PACKAGE_LABEL: 1721 if (package_label_attr) 1722 goto duplicated_attr; 1723 package_label_attr = attr; 1724 break; 1725 default: 1726 break; 1727 } 1728 } 1729 if (!(clock_id || mod_name_attr || board_label_attr || 1730 panel_label_attr || package_label_attr)) { 1731 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1732 return ERR_PTR(-EINVAL); 1733 } 1734 return dpll_pin_find(clock_id, mod_name_attr, type, board_label_attr, 1735 panel_label_attr, package_label_attr, 1736 info->extack); 1737 duplicated_attr: 1738 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1739 return ERR_PTR(-EINVAL); 1740 } 1741 1742 int dpll_nl_pin_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1743 { 1744 struct dpll_pin *pin; 1745 struct sk_buff *msg; 1746 struct nlattr *hdr; 1747 int ret; 1748 1749 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1750 if (!msg) 1751 return -ENOMEM; 1752 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1753 DPLL_CMD_PIN_ID_GET); 1754 if (!hdr) { 1755 nlmsg_free(msg); 1756 return -EMSGSIZE; 1757 } 1758 pin = dpll_pin_find_from_nlattr(info); 1759 if (IS_ERR(pin)) { 1760 nlmsg_free(msg); 1761 return PTR_ERR(pin); 1762 } 1763 if (!dpll_pin_available(pin)) { 1764 nlmsg_free(msg); 1765 return -ENODEV; 1766 } 1767 ret = dpll_msg_add_pin_handle(msg, pin); 1768 if (ret) { 1769 nlmsg_free(msg); 1770 return ret; 1771 } 1772 genlmsg_end(msg, hdr); 1773 1774 return genlmsg_reply(msg, info); 1775 } 1776 1777 int dpll_nl_pin_get_doit(struct sk_buff *skb, struct genl_info *info) 1778 { 1779 struct dpll_pin *pin = info->user_ptr[0]; 1780 struct sk_buff *msg; 1781 struct nlattr *hdr; 1782 int ret; 1783 1784 if (!pin) 1785 return -ENODEV; 1786 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1787 if (!msg) 1788 return -ENOMEM; 1789 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1790 DPLL_CMD_PIN_GET); 1791 if (!hdr) { 1792 nlmsg_free(msg); 1793 return -EMSGSIZE; 1794 } 1795 ret = dpll_cmd_pin_get_one(msg, pin, info->extack); 1796 if (ret) { 1797 nlmsg_free(msg); 1798 return ret; 1799 } 1800 genlmsg_end(msg, hdr); 1801 1802 return genlmsg_reply(msg, info); 1803 } 1804 1805 int dpll_nl_pin_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 1806 { 1807 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 1808 struct dpll_pin *pin; 1809 struct nlattr *hdr; 1810 unsigned long i; 1811 int ret = 0; 1812 1813 mutex_lock(&dpll_lock); 1814 xa_for_each_marked_start(&dpll_pin_xa, i, pin, DPLL_REGISTERED, 1815 ctx->idx) { 1816 if (!dpll_pin_available(pin)) 1817 continue; 1818 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 1819 cb->nlh->nlmsg_seq, 1820 &dpll_nl_family, NLM_F_MULTI, 1821 DPLL_CMD_PIN_GET); 1822 if (!hdr) { 1823 ret = -EMSGSIZE; 1824 break; 1825 } 1826 ret = dpll_cmd_pin_get_one(skb, pin, cb->extack); 1827 if (ret) { 1828 genlmsg_cancel(skb, hdr); 1829 break; 1830 } 1831 genlmsg_end(skb, hdr); 1832 } 1833 mutex_unlock(&dpll_lock); 1834 1835 if (ret == -EMSGSIZE) { 1836 ctx->idx = i; 1837 return skb->len; 1838 } 1839 return ret; 1840 } 1841 1842 int dpll_nl_pin_set_doit(struct sk_buff *skb, struct genl_info *info) 1843 { 1844 struct dpll_pin *pin = info->user_ptr[0]; 1845 1846 return dpll_pin_set_from_nlattr(pin, info); 1847 } 1848 1849 static struct dpll_device * 1850 dpll_device_find(u64 clock_id, struct nlattr *mod_name_attr, 1851 enum dpll_type type, struct netlink_ext_ack *extack) 1852 { 1853 struct dpll_device *dpll_match = NULL, *dpll; 1854 bool cid_match, mod_match, type_match; 1855 unsigned long i; 1856 1857 xa_for_each_marked(&dpll_device_xa, i, dpll, DPLL_REGISTERED) { 1858 cid_match = clock_id ? dpll->clock_id == clock_id : true; 1859 mod_match = mod_name_attr ? (module_name(dpll->module) ? 1860 !nla_strcmp(mod_name_attr, 1861 module_name(dpll->module)) : false) : true; 1862 type_match = type ? dpll->type == type : true; 1863 if (cid_match && mod_match && type_match) { 1864 if (dpll_match) { 1865 NL_SET_ERR_MSG(extack, "multiple matches"); 1866 return ERR_PTR(-EINVAL); 1867 } 1868 dpll_match = dpll; 1869 } 1870 } 1871 if (!dpll_match) { 1872 NL_SET_ERR_MSG(extack, "not found"); 1873 return ERR_PTR(-ENODEV); 1874 } 1875 1876 return dpll_match; 1877 } 1878 1879 static struct dpll_device * 1880 dpll_device_find_from_nlattr(struct genl_info *info) 1881 { 1882 struct nlattr *attr, *mod_name_attr = NULL; 1883 enum dpll_type type = 0; 1884 u64 clock_id = 0; 1885 int rem = 0; 1886 1887 nla_for_each_attr(attr, genlmsg_data(info->genlhdr), 1888 genlmsg_len(info->genlhdr), rem) { 1889 switch (nla_type(attr)) { 1890 case DPLL_A_CLOCK_ID: 1891 if (clock_id) 1892 goto duplicated_attr; 1893 clock_id = nla_get_u64(attr); 1894 break; 1895 case DPLL_A_MODULE_NAME: 1896 if (mod_name_attr) 1897 goto duplicated_attr; 1898 mod_name_attr = attr; 1899 break; 1900 case DPLL_A_TYPE: 1901 if (type) 1902 goto duplicated_attr; 1903 type = nla_get_u32(attr); 1904 break; 1905 default: 1906 break; 1907 } 1908 } 1909 if (!clock_id && !mod_name_attr && !type) { 1910 NL_SET_ERR_MSG(info->extack, "missing attributes"); 1911 return ERR_PTR(-EINVAL); 1912 } 1913 return dpll_device_find(clock_id, mod_name_attr, type, info->extack); 1914 duplicated_attr: 1915 NL_SET_ERR_MSG(info->extack, "duplicated attribute"); 1916 return ERR_PTR(-EINVAL); 1917 } 1918 1919 int dpll_nl_device_id_get_doit(struct sk_buff *skb, struct genl_info *info) 1920 { 1921 struct dpll_device *dpll; 1922 struct sk_buff *msg; 1923 struct nlattr *hdr; 1924 int ret; 1925 1926 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1927 if (!msg) 1928 return -ENOMEM; 1929 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1930 DPLL_CMD_DEVICE_ID_GET); 1931 if (!hdr) { 1932 nlmsg_free(msg); 1933 return -EMSGSIZE; 1934 } 1935 1936 dpll = dpll_device_find_from_nlattr(info); 1937 if (IS_ERR(dpll)) { 1938 nlmsg_free(msg); 1939 return PTR_ERR(dpll); 1940 } 1941 ret = dpll_msg_add_dev_handle(msg, dpll); 1942 if (ret) { 1943 nlmsg_free(msg); 1944 return ret; 1945 } 1946 genlmsg_end(msg, hdr); 1947 1948 return genlmsg_reply(msg, info); 1949 } 1950 1951 int dpll_nl_device_get_doit(struct sk_buff *skb, struct genl_info *info) 1952 { 1953 struct dpll_device *dpll = info->user_ptr[0]; 1954 struct sk_buff *msg; 1955 struct nlattr *hdr; 1956 int ret; 1957 1958 msg = genlmsg_new(NLMSG_GOODSIZE, GFP_KERNEL); 1959 if (!msg) 1960 return -ENOMEM; 1961 hdr = genlmsg_put_reply(msg, info, &dpll_nl_family, 0, 1962 DPLL_CMD_DEVICE_GET); 1963 if (!hdr) { 1964 nlmsg_free(msg); 1965 return -EMSGSIZE; 1966 } 1967 1968 ret = dpll_device_get_one(dpll, msg, info->extack); 1969 if (ret) { 1970 nlmsg_free(msg); 1971 return ret; 1972 } 1973 genlmsg_end(msg, hdr); 1974 1975 return genlmsg_reply(msg, info); 1976 } 1977 1978 static int 1979 dpll_set_from_nlattr(struct dpll_device *dpll, struct genl_info *info) 1980 { 1981 struct nlattr *a; 1982 int rem, ret; 1983 1984 nla_for_each_attr(a, genlmsg_data(info->genlhdr), 1985 genlmsg_len(info->genlhdr), rem) { 1986 switch (nla_type(a)) { 1987 case DPLL_A_MODE: 1988 ret = dpll_mode_set(dpll, a, info->extack); 1989 if (ret) 1990 return ret; 1991 break; 1992 case DPLL_A_PHASE_OFFSET_MONITOR: 1993 ret = dpll_phase_offset_monitor_set(dpll, a, 1994 info->extack); 1995 if (ret) 1996 return ret; 1997 break; 1998 case DPLL_A_PHASE_OFFSET_AVG_FACTOR: 1999 ret = dpll_phase_offset_avg_factor_set(dpll, a, 2000 info->extack); 2001 if (ret) 2002 return ret; 2003 break; 2004 case DPLL_A_FREQUENCY_MONITOR: 2005 ret = dpll_freq_monitor_set(dpll, a, 2006 info->extack); 2007 if (ret) 2008 return ret; 2009 break; 2010 } 2011 } 2012 2013 return 0; 2014 } 2015 2016 int dpll_nl_device_set_doit(struct sk_buff *skb, struct genl_info *info) 2017 { 2018 struct dpll_device *dpll = info->user_ptr[0]; 2019 2020 return dpll_set_from_nlattr(dpll, info); 2021 } 2022 2023 int dpll_nl_device_get_dumpit(struct sk_buff *skb, struct netlink_callback *cb) 2024 { 2025 struct dpll_dump_ctx *ctx = dpll_dump_context(cb); 2026 struct dpll_device *dpll; 2027 struct nlattr *hdr; 2028 unsigned long i; 2029 int ret = 0; 2030 2031 mutex_lock(&dpll_lock); 2032 xa_for_each_marked_start(&dpll_device_xa, i, dpll, DPLL_REGISTERED, 2033 ctx->idx) { 2034 hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid, 2035 cb->nlh->nlmsg_seq, &dpll_nl_family, 2036 NLM_F_MULTI, DPLL_CMD_DEVICE_GET); 2037 if (!hdr) { 2038 ret = -EMSGSIZE; 2039 break; 2040 } 2041 ret = dpll_device_get_one(dpll, skb, cb->extack); 2042 if (ret) { 2043 genlmsg_cancel(skb, hdr); 2044 break; 2045 } 2046 genlmsg_end(skb, hdr); 2047 } 2048 mutex_unlock(&dpll_lock); 2049 2050 if (ret == -EMSGSIZE) { 2051 ctx->idx = i; 2052 return skb->len; 2053 } 2054 return ret; 2055 } 2056 2057 int dpll_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2058 struct genl_info *info) 2059 { 2060 u32 id; 2061 2062 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_ID)) 2063 return -EINVAL; 2064 2065 mutex_lock(&dpll_lock); 2066 id = nla_get_u32(info->attrs[DPLL_A_ID]); 2067 info->user_ptr[0] = dpll_device_get_by_id(id); 2068 if (!info->user_ptr[0]) { 2069 NL_SET_ERR_MSG(info->extack, "device not found"); 2070 goto unlock; 2071 } 2072 return 0; 2073 unlock: 2074 mutex_unlock(&dpll_lock); 2075 return -ENODEV; 2076 } 2077 2078 void dpll_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2079 struct genl_info *info) 2080 { 2081 mutex_unlock(&dpll_lock); 2082 } 2083 2084 int 2085 dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2086 struct genl_info *info) 2087 { 2088 mutex_lock(&dpll_lock); 2089 2090 return 0; 2091 } 2092 2093 void 2094 dpll_unlock_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2095 struct genl_info *info) 2096 { 2097 mutex_unlock(&dpll_lock); 2098 } 2099 2100 int dpll_pin_pre_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2101 struct genl_info *info) 2102 { 2103 int ret; 2104 2105 mutex_lock(&dpll_lock); 2106 if (GENL_REQ_ATTR_CHECK(info, DPLL_A_PIN_ID)) { 2107 ret = -EINVAL; 2108 goto unlock_dev; 2109 } 2110 info->user_ptr[0] = xa_load(&dpll_pin_xa, 2111 nla_get_u32(info->attrs[DPLL_A_PIN_ID])); 2112 if (!info->user_ptr[0] || 2113 !dpll_pin_available(info->user_ptr[0])) { 2114 NL_SET_ERR_MSG(info->extack, "pin not found"); 2115 ret = -ENODEV; 2116 goto unlock_dev; 2117 } 2118 2119 return 0; 2120 2121 unlock_dev: 2122 mutex_unlock(&dpll_lock); 2123 return ret; 2124 } 2125 2126 void dpll_pin_post_doit(const struct genl_split_ops *ops, struct sk_buff *skb, 2127 struct genl_info *info) 2128 { 2129 mutex_unlock(&dpll_lock); 2130 } 2131