1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx ZynqMP DPDMA Engine driver 4 * 5 * Copyright (C) 2015 - 2020 Xilinx, Inc. 6 * 7 * Author: Hyun Woo Kwon <hyun.kwon@xilinx.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/dma/xilinx_dpdma.h> 16 #include <linux/dmaengine.h> 17 #include <linux/dmapool.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_dma.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched.h> 24 #include <linux/slab.h> 25 #include <linux/spinlock.h> 26 #include <linux/wait.h> 27 28 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 29 30 #include "../dmaengine.h" 31 #include "../virt-dma.h" 32 33 /* DPDMA registers */ 34 #define XILINX_DPDMA_ERR_CTRL 0x000 35 #define XILINX_DPDMA_ISR 0x004 36 #define XILINX_DPDMA_IMR 0x008 37 #define XILINX_DPDMA_IEN 0x00c 38 #define XILINX_DPDMA_IDS 0x010 39 #define XILINX_DPDMA_INTR_DESC_DONE(n) BIT((n) + 0) 40 #define XILINX_DPDMA_INTR_DESC_DONE_MASK GENMASK(5, 0) 41 #define XILINX_DPDMA_INTR_NO_OSTAND(n) BIT((n) + 6) 42 #define XILINX_DPDMA_INTR_NO_OSTAND_MASK GENMASK(11, 6) 43 #define XILINX_DPDMA_INTR_AXI_ERR(n) BIT((n) + 12) 44 #define XILINX_DPDMA_INTR_AXI_ERR_MASK GENMASK(17, 12) 45 #define XILINX_DPDMA_INTR_DESC_ERR(n) BIT((n) + 16) 46 #define XILINX_DPDMA_INTR_DESC_ERR_MASK GENMASK(23, 18) 47 #define XILINX_DPDMA_INTR_WR_CMD_FIFO_FULL BIT(24) 48 #define XILINX_DPDMA_INTR_WR_DATA_FIFO_FULL BIT(25) 49 #define XILINX_DPDMA_INTR_AXI_4K_CROSS BIT(26) 50 #define XILINX_DPDMA_INTR_VSYNC BIT(27) 51 #define XILINX_DPDMA_INTR_CHAN_ERR_MASK 0x00041000 52 #define XILINX_DPDMA_INTR_CHAN_ERR 0x00fff000 53 #define XILINX_DPDMA_INTR_GLOBAL_ERR 0x07000000 54 #define XILINX_DPDMA_INTR_ERR_ALL 0x07fff000 55 #define XILINX_DPDMA_INTR_CHAN_MASK 0x00041041 56 #define XILINX_DPDMA_INTR_GLOBAL_MASK 0x0f000000 57 #define XILINX_DPDMA_INTR_ALL 0x0fffffff 58 #define XILINX_DPDMA_EISR 0x014 59 #define XILINX_DPDMA_EIMR 0x018 60 #define XILINX_DPDMA_EIEN 0x01c 61 #define XILINX_DPDMA_EIDS 0x020 62 #define XILINX_DPDMA_EINTR_INV_APB BIT(0) 63 #define XILINX_DPDMA_EINTR_RD_AXI_ERR(n) BIT((n) + 1) 64 #define XILINX_DPDMA_EINTR_RD_AXI_ERR_MASK GENMASK(6, 1) 65 #define XILINX_DPDMA_EINTR_PRE_ERR(n) BIT((n) + 7) 66 #define XILINX_DPDMA_EINTR_PRE_ERR_MASK GENMASK(12, 7) 67 #define XILINX_DPDMA_EINTR_CRC_ERR(n) BIT((n) + 13) 68 #define XILINX_DPDMA_EINTR_CRC_ERR_MASK GENMASK(18, 13) 69 #define XILINX_DPDMA_EINTR_WR_AXI_ERR(n) BIT((n) + 19) 70 #define XILINX_DPDMA_EINTR_WR_AXI_ERR_MASK GENMASK(24, 19) 71 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR(n) BIT((n) + 25) 72 #define XILINX_DPDMA_EINTR_DESC_DONE_ERR_MASK GENMASK(30, 25) 73 #define XILINX_DPDMA_EINTR_RD_CMD_FIFO_FULL BIT(32) 74 #define XILINX_DPDMA_EINTR_CHAN_ERR_MASK 0x02082082 75 #define XILINX_DPDMA_EINTR_CHAN_ERR 0x7ffffffe 76 #define XILINX_DPDMA_EINTR_GLOBAL_ERR 0x80000001 77 #define XILINX_DPDMA_EINTR_ALL 0xffffffff 78 #define XILINX_DPDMA_CNTL 0x100 79 #define XILINX_DPDMA_GBL 0x104 80 #define XILINX_DPDMA_GBL_TRIG_MASK(n) ((n) << 0) 81 #define XILINX_DPDMA_GBL_RETRIG_MASK(n) ((n) << 6) 82 #define XILINX_DPDMA_ALC0_CNTL 0x108 83 #define XILINX_DPDMA_ALC0_STATUS 0x10c 84 #define XILINX_DPDMA_ALC0_MAX 0x110 85 #define XILINX_DPDMA_ALC0_MIN 0x114 86 #define XILINX_DPDMA_ALC0_ACC 0x118 87 #define XILINX_DPDMA_ALC0_ACC_TRAN 0x11c 88 #define XILINX_DPDMA_ALC1_CNTL 0x120 89 #define XILINX_DPDMA_ALC1_STATUS 0x124 90 #define XILINX_DPDMA_ALC1_MAX 0x128 91 #define XILINX_DPDMA_ALC1_MIN 0x12c 92 #define XILINX_DPDMA_ALC1_ACC 0x130 93 #define XILINX_DPDMA_ALC1_ACC_TRAN 0x134 94 95 /* Channel register */ 96 #define XILINX_DPDMA_CH_BASE 0x200 97 #define XILINX_DPDMA_CH_OFFSET 0x100 98 #define XILINX_DPDMA_CH_DESC_START_ADDRE 0x000 99 #define XILINX_DPDMA_CH_DESC_START_ADDRE_MASK GENMASK(15, 0) 100 #define XILINX_DPDMA_CH_DESC_START_ADDR 0x004 101 #define XILINX_DPDMA_CH_DESC_NEXT_ADDRE 0x008 102 #define XILINX_DPDMA_CH_DESC_NEXT_ADDR 0x00c 103 #define XILINX_DPDMA_CH_PYLD_CUR_ADDRE 0x010 104 #define XILINX_DPDMA_CH_PYLD_CUR_ADDR 0x014 105 #define XILINX_DPDMA_CH_CNTL 0x018 106 #define XILINX_DPDMA_CH_CNTL_ENABLE BIT(0) 107 #define XILINX_DPDMA_CH_CNTL_PAUSE BIT(1) 108 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK GENMASK(5, 2) 109 #define XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK GENMASK(9, 6) 110 #define XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK GENMASK(13, 10) 111 #define XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS 11 112 #define XILINX_DPDMA_CH_STATUS 0x01c 113 #define XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK GENMASK(24, 21) 114 #define XILINX_DPDMA_CH_VDO 0x020 115 #define XILINX_DPDMA_CH_PYLD_SZ 0x024 116 #define XILINX_DPDMA_CH_DESC_ID 0x028 117 #define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15, 0) 118 119 /* DPDMA descriptor fields */ 120 #define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5 121 #define XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR BIT(8) 122 #define XILINX_DPDMA_DESC_CONTROL_DESC_UPDATE BIT(9) 123 #define XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE BIT(10) 124 #define XILINX_DPDMA_DESC_CONTROL_FRAG_MODE BIT(18) 125 #define XILINX_DPDMA_DESC_CONTROL_LAST BIT(19) 126 #define XILINX_DPDMA_DESC_CONTROL_ENABLE_CRC BIT(20) 127 #define XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME BIT(21) 128 #define XILINX_DPDMA_DESC_ID_MASK GENMASK(15, 0) 129 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK GENMASK(17, 0) 130 #define XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK GENMASK(31, 18) 131 #define XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK GENMASK(15, 0) 132 #define XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK GENMASK(31, 16) 133 134 #define XILINX_DPDMA_ALIGN_BYTES 256 135 #define XILINX_DPDMA_LINESIZE_ALIGN_BITS 128 136 137 #define XILINX_DPDMA_NUM_CHAN 6 138 139 struct xilinx_dpdma_chan; 140 141 /** 142 * struct xilinx_dpdma_hw_desc - DPDMA hardware descriptor 143 * @control: control configuration field 144 * @desc_id: descriptor ID 145 * @xfer_size: transfer size 146 * @hsize_stride: horizontal size and stride 147 * @timestamp_lsb: LSB of time stamp 148 * @timestamp_msb: MSB of time stamp 149 * @addr_ext: upper 16 bit of 48 bit address (next_desc and src_addr) 150 * @next_desc: next descriptor 32 bit address 151 * @src_addr: payload source address (1st page, 32 LSB) 152 * @addr_ext_23: payload source address (3nd and 3rd pages, 16 LSBs) 153 * @addr_ext_45: payload source address (4th and 5th pages, 16 LSBs) 154 * @src_addr2: payload source address (2nd page, 32 LSB) 155 * @src_addr3: payload source address (3rd page, 32 LSB) 156 * @src_addr4: payload source address (4th page, 32 LSB) 157 * @src_addr5: payload source address (5th page, 32 LSB) 158 * @crc: descriptor CRC 159 */ 160 struct xilinx_dpdma_hw_desc { 161 u32 control; 162 u32 desc_id; 163 u32 xfer_size; 164 u32 hsize_stride; 165 u32 timestamp_lsb; 166 u32 timestamp_msb; 167 u32 addr_ext; 168 u32 next_desc; 169 u32 src_addr; 170 u32 addr_ext_23; 171 u32 addr_ext_45; 172 u32 src_addr2; 173 u32 src_addr3; 174 u32 src_addr4; 175 u32 src_addr5; 176 u32 crc; 177 } __aligned(XILINX_DPDMA_ALIGN_BYTES); 178 179 /** 180 * struct xilinx_dpdma_sw_desc - DPDMA software descriptor 181 * @hw: DPDMA hardware descriptor 182 * @node: list node for software descriptors 183 * @dma_addr: DMA address of the software descriptor 184 */ 185 struct xilinx_dpdma_sw_desc { 186 struct xilinx_dpdma_hw_desc hw; 187 struct list_head node; 188 dma_addr_t dma_addr; 189 }; 190 191 /** 192 * struct xilinx_dpdma_tx_desc - DPDMA transaction descriptor 193 * @vdesc: virtual DMA descriptor 194 * @chan: DMA channel 195 * @descriptors: list of software descriptors 196 * @error: an error has been detected with this descriptor 197 */ 198 struct xilinx_dpdma_tx_desc { 199 struct virt_dma_desc vdesc; 200 struct xilinx_dpdma_chan *chan; 201 struct list_head descriptors; 202 bool error; 203 }; 204 205 #define to_dpdma_tx_desc(_desc) \ 206 container_of(_desc, struct xilinx_dpdma_tx_desc, vdesc) 207 208 /** 209 * struct xilinx_dpdma_chan - DPDMA channel 210 * @vchan: virtual DMA channel 211 * @reg: register base address 212 * @id: channel ID 213 * @wait_to_stop: queue to wait for outstanding transacitons before stopping 214 * @running: true if the channel is running 215 * @first_frame: flag for the first frame of stream 216 * @video_group: flag if multi-channel operation is needed for video channels 217 * @lock: lock to access struct xilinx_dpdma_chan. Must be taken before 218 * @vchan.lock, if both are to be held. 219 * @desc_pool: descriptor allocation pool 220 * @err_task: error IRQ bottom half handler 221 * @desc: References to descriptors being processed 222 * @desc.pending: Descriptor schedule to the hardware, pending execution 223 * @desc.active: Descriptor being executed by the hardware 224 * @xdev: DPDMA device 225 */ 226 struct xilinx_dpdma_chan { 227 struct virt_dma_chan vchan; 228 void __iomem *reg; 229 unsigned int id; 230 231 wait_queue_head_t wait_to_stop; 232 bool running; 233 bool first_frame; 234 bool video_group; 235 236 spinlock_t lock; /* lock to access struct xilinx_dpdma_chan */ 237 struct dma_pool *desc_pool; 238 struct tasklet_struct err_task; 239 240 struct { 241 struct xilinx_dpdma_tx_desc *pending; 242 struct xilinx_dpdma_tx_desc *active; 243 } desc; 244 245 struct xilinx_dpdma_device *xdev; 246 }; 247 248 #define to_xilinx_chan(_chan) \ 249 container_of(_chan, struct xilinx_dpdma_chan, vchan.chan) 250 251 /** 252 * struct xilinx_dpdma_device - DPDMA device 253 * @common: generic dma device structure 254 * @reg: register base address 255 * @dev: generic device structure 256 * @irq: the interrupt number 257 * @axi_clk: axi clock 258 * @chan: DPDMA channels 259 * @ext_addr: flag for 64 bit system (48 bit addressing) 260 */ 261 struct xilinx_dpdma_device { 262 struct dma_device common; 263 void __iomem *reg; 264 struct device *dev; 265 int irq; 266 267 struct clk *axi_clk; 268 struct xilinx_dpdma_chan *chan[XILINX_DPDMA_NUM_CHAN]; 269 270 bool ext_addr; 271 }; 272 273 /* ----------------------------------------------------------------------------- 274 * DebugFS 275 */ 276 #define XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE 32 277 #define XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR "65535" 278 279 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */ 280 enum xilinx_dpdma_testcases { 281 DPDMA_TC_INTR_DONE, 282 DPDMA_TC_NONE 283 }; 284 285 struct xilinx_dpdma_debugfs { 286 enum xilinx_dpdma_testcases testcase; 287 u16 xilinx_dpdma_irq_done_count; 288 unsigned int chan_id; 289 }; 290 291 static struct xilinx_dpdma_debugfs dpdma_debugfs; 292 struct xilinx_dpdma_debugfs_request { 293 const char *name; 294 enum xilinx_dpdma_testcases tc; 295 ssize_t (*read)(char *buf); 296 int (*write)(char *args); 297 }; 298 299 static void xilinx_dpdma_debugfs_desc_done_irq(struct xilinx_dpdma_chan *chan) 300 { 301 if (IS_ENABLED(CONFIG_DEBUG_FS) && chan->id == dpdma_debugfs.chan_id) 302 dpdma_debugfs.xilinx_dpdma_irq_done_count++; 303 } 304 305 static ssize_t xilinx_dpdma_debugfs_desc_done_irq_read(char *buf) 306 { 307 size_t out_str_len; 308 309 dpdma_debugfs.testcase = DPDMA_TC_NONE; 310 311 out_str_len = strlen(XILINX_DPDMA_DEBUGFS_UINT16_MAX_STR); 312 out_str_len = min_t(size_t, XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, 313 out_str_len + 1); 314 snprintf(buf, out_str_len, "%d", 315 dpdma_debugfs.xilinx_dpdma_irq_done_count); 316 317 return 0; 318 } 319 320 static int xilinx_dpdma_debugfs_desc_done_irq_write(char *args) 321 { 322 char *arg; 323 int ret; 324 u32 id; 325 326 arg = strsep(&args, " "); 327 if (!arg || strncasecmp(arg, "start", 5)) 328 return -EINVAL; 329 330 arg = strsep(&args, " "); 331 if (!arg) 332 return -EINVAL; 333 334 ret = kstrtou32(arg, 0, &id); 335 if (ret < 0) 336 return ret; 337 338 if (id < ZYNQMP_DPDMA_VIDEO0 || id > ZYNQMP_DPDMA_AUDIO1) 339 return -EINVAL; 340 341 dpdma_debugfs.testcase = DPDMA_TC_INTR_DONE; 342 dpdma_debugfs.xilinx_dpdma_irq_done_count = 0; 343 dpdma_debugfs.chan_id = id; 344 345 return 0; 346 } 347 348 /* Match xilinx_dpdma_testcases vs dpdma_debugfs_reqs[] entry */ 349 static struct xilinx_dpdma_debugfs_request dpdma_debugfs_reqs[] = { 350 { 351 .name = "DESCRIPTOR_DONE_INTR", 352 .tc = DPDMA_TC_INTR_DONE, 353 .read = xilinx_dpdma_debugfs_desc_done_irq_read, 354 .write = xilinx_dpdma_debugfs_desc_done_irq_write, 355 }, 356 }; 357 358 static ssize_t xilinx_dpdma_debugfs_read(struct file *f, char __user *buf, 359 size_t size, loff_t *pos) 360 { 361 enum xilinx_dpdma_testcases testcase; 362 char *kern_buff; 363 int ret = 0; 364 365 if (*pos != 0 || size <= 0) 366 return -EINVAL; 367 368 kern_buff = kzalloc(XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE, GFP_KERNEL); 369 if (!kern_buff) { 370 dpdma_debugfs.testcase = DPDMA_TC_NONE; 371 return -ENOMEM; 372 } 373 374 testcase = READ_ONCE(dpdma_debugfs.testcase); 375 if (testcase != DPDMA_TC_NONE) { 376 ret = dpdma_debugfs_reqs[testcase].read(kern_buff); 377 if (ret < 0) 378 goto done; 379 } else { 380 strscpy(kern_buff, "No testcase executed", 381 XILINX_DPDMA_DEBUGFS_READ_MAX_SIZE); 382 } 383 384 size = min(size, strlen(kern_buff)); 385 if (copy_to_user(buf, kern_buff, size)) 386 ret = -EFAULT; 387 388 done: 389 kfree(kern_buff); 390 if (ret) 391 return ret; 392 393 *pos = size + 1; 394 return size; 395 } 396 397 static ssize_t xilinx_dpdma_debugfs_write(struct file *f, 398 const char __user *buf, size_t size, 399 loff_t *pos) 400 { 401 char *kern_buff, *kern_buff_start; 402 char *testcase; 403 unsigned int i; 404 int ret; 405 406 if (*pos != 0 || size <= 0) 407 return -EINVAL; 408 409 /* Supporting single instance of test as of now. */ 410 if (dpdma_debugfs.testcase != DPDMA_TC_NONE) 411 return -EBUSY; 412 413 kern_buff = kzalloc(size, GFP_KERNEL); 414 if (!kern_buff) 415 return -ENOMEM; 416 kern_buff_start = kern_buff; 417 418 ret = strncpy_from_user(kern_buff, buf, size); 419 if (ret < 0) 420 goto done; 421 422 /* Read the testcase name from a user request. */ 423 testcase = strsep(&kern_buff, " "); 424 425 for (i = 0; i < ARRAY_SIZE(dpdma_debugfs_reqs); i++) { 426 if (!strcasecmp(testcase, dpdma_debugfs_reqs[i].name)) 427 break; 428 } 429 430 if (i == ARRAY_SIZE(dpdma_debugfs_reqs)) { 431 ret = -EINVAL; 432 goto done; 433 } 434 435 ret = dpdma_debugfs_reqs[i].write(kern_buff); 436 if (ret < 0) 437 goto done; 438 439 ret = size; 440 441 done: 442 kfree(kern_buff_start); 443 return ret; 444 } 445 446 static const struct file_operations fops_xilinx_dpdma_dbgfs = { 447 .owner = THIS_MODULE, 448 .read = xilinx_dpdma_debugfs_read, 449 .write = xilinx_dpdma_debugfs_write, 450 }; 451 452 static void xilinx_dpdma_debugfs_init(struct xilinx_dpdma_device *xdev) 453 { 454 struct dentry *dent; 455 456 dpdma_debugfs.testcase = DPDMA_TC_NONE; 457 458 dent = debugfs_create_file("testcase", 0444, xdev->common.dbg_dev_root, 459 NULL, &fops_xilinx_dpdma_dbgfs); 460 if (IS_ERR(dent)) 461 dev_err(xdev->dev, "Failed to create debugfs testcase file\n"); 462 } 463 464 /* ----------------------------------------------------------------------------- 465 * I/O Accessors 466 */ 467 468 static inline u32 dpdma_read(void __iomem *base, u32 offset) 469 { 470 return ioread32(base + offset); 471 } 472 473 static inline void dpdma_write(void __iomem *base, u32 offset, u32 val) 474 { 475 iowrite32(val, base + offset); 476 } 477 478 static inline void dpdma_clr(void __iomem *base, u32 offset, u32 clr) 479 { 480 dpdma_write(base, offset, dpdma_read(base, offset) & ~clr); 481 } 482 483 static inline void dpdma_set(void __iomem *base, u32 offset, u32 set) 484 { 485 dpdma_write(base, offset, dpdma_read(base, offset) | set); 486 } 487 488 /* ----------------------------------------------------------------------------- 489 * Descriptor Operations 490 */ 491 492 /** 493 * xilinx_dpdma_sw_desc_set_dma_addrs - Set DMA addresses in the descriptor 494 * @xdev: DPDMA device 495 * @sw_desc: The software descriptor in which to set DMA addresses 496 * @prev: The previous descriptor 497 * @dma_addr: array of dma addresses 498 * @num_src_addr: number of addresses in @dma_addr 499 * 500 * Set all the DMA addresses in the hardware descriptor corresponding to @dev 501 * from @dma_addr. If a previous descriptor is specified in @prev, its next 502 * descriptor DMA address is set to the DMA address of @sw_desc. @prev may be 503 * identical to @sw_desc for cyclic transfers. 504 */ 505 static void xilinx_dpdma_sw_desc_set_dma_addrs(struct xilinx_dpdma_device *xdev, 506 struct xilinx_dpdma_sw_desc *sw_desc, 507 struct xilinx_dpdma_sw_desc *prev, 508 dma_addr_t dma_addr[], 509 unsigned int num_src_addr) 510 { 511 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw; 512 unsigned int i; 513 514 hw_desc->src_addr = lower_32_bits(dma_addr[0]); 515 if (xdev->ext_addr) 516 hw_desc->addr_ext |= 517 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_SRC_ADDR_MASK, 518 upper_32_bits(dma_addr[0])); 519 520 for (i = 1; i < num_src_addr; i++) { 521 u32 *addr = &hw_desc->src_addr2; 522 523 addr[i - 1] = lower_32_bits(dma_addr[i]); 524 525 if (xdev->ext_addr) { 526 u32 *addr_ext = &hw_desc->addr_ext_23; 527 u32 addr_msb; 528 529 addr_msb = upper_32_bits(dma_addr[i]) & GENMASK(15, 0); 530 addr_msb <<= 16 * ((i - 1) % 2); 531 addr_ext[(i - 1) / 2] |= addr_msb; 532 } 533 } 534 535 if (!prev) 536 return; 537 538 prev->hw.next_desc = lower_32_bits(sw_desc->dma_addr); 539 if (xdev->ext_addr) 540 prev->hw.addr_ext |= 541 FIELD_PREP(XILINX_DPDMA_DESC_ADDR_EXT_NEXT_ADDR_MASK, 542 upper_32_bits(sw_desc->dma_addr)); 543 } 544 545 /** 546 * xilinx_dpdma_chan_alloc_sw_desc - Allocate a software descriptor 547 * @chan: DPDMA channel 548 * 549 * Allocate a software descriptor from the channel's descriptor pool. 550 * 551 * Return: a software descriptor or NULL. 552 */ 553 static struct xilinx_dpdma_sw_desc * 554 xilinx_dpdma_chan_alloc_sw_desc(struct xilinx_dpdma_chan *chan) 555 { 556 struct xilinx_dpdma_sw_desc *sw_desc; 557 dma_addr_t dma_addr; 558 559 sw_desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &dma_addr); 560 if (!sw_desc) 561 return NULL; 562 563 sw_desc->dma_addr = dma_addr; 564 565 return sw_desc; 566 } 567 568 /** 569 * xilinx_dpdma_chan_free_sw_desc - Free a software descriptor 570 * @chan: DPDMA channel 571 * @sw_desc: software descriptor to free 572 * 573 * Free a software descriptor from the channel's descriptor pool. 574 */ 575 static void 576 xilinx_dpdma_chan_free_sw_desc(struct xilinx_dpdma_chan *chan, 577 struct xilinx_dpdma_sw_desc *sw_desc) 578 { 579 dma_pool_free(chan->desc_pool, sw_desc, sw_desc->dma_addr); 580 } 581 582 /** 583 * xilinx_dpdma_chan_dump_tx_desc - Dump a tx descriptor 584 * @chan: DPDMA channel 585 * @tx_desc: tx descriptor to dump 586 * 587 * Dump contents of a tx descriptor 588 */ 589 static void xilinx_dpdma_chan_dump_tx_desc(struct xilinx_dpdma_chan *chan, 590 struct xilinx_dpdma_tx_desc *tx_desc) 591 { 592 struct xilinx_dpdma_sw_desc *sw_desc; 593 struct device *dev = chan->xdev->dev; 594 unsigned int i = 0; 595 596 dev_dbg(dev, "------- TX descriptor dump start -------\n"); 597 dev_dbg(dev, "------- channel ID = %d -------\n", chan->id); 598 599 list_for_each_entry(sw_desc, &tx_desc->descriptors, node) { 600 struct xilinx_dpdma_hw_desc *hw_desc = &sw_desc->hw; 601 602 dev_dbg(dev, "------- HW descriptor %d -------\n", i++); 603 dev_dbg(dev, "descriptor DMA addr: %pad\n", &sw_desc->dma_addr); 604 dev_dbg(dev, "control: 0x%08x\n", hw_desc->control); 605 dev_dbg(dev, "desc_id: 0x%08x\n", hw_desc->desc_id); 606 dev_dbg(dev, "xfer_size: 0x%08x\n", hw_desc->xfer_size); 607 dev_dbg(dev, "hsize_stride: 0x%08x\n", hw_desc->hsize_stride); 608 dev_dbg(dev, "timestamp_lsb: 0x%08x\n", hw_desc->timestamp_lsb); 609 dev_dbg(dev, "timestamp_msb: 0x%08x\n", hw_desc->timestamp_msb); 610 dev_dbg(dev, "addr_ext: 0x%08x\n", hw_desc->addr_ext); 611 dev_dbg(dev, "next_desc: 0x%08x\n", hw_desc->next_desc); 612 dev_dbg(dev, "src_addr: 0x%08x\n", hw_desc->src_addr); 613 dev_dbg(dev, "addr_ext_23: 0x%08x\n", hw_desc->addr_ext_23); 614 dev_dbg(dev, "addr_ext_45: 0x%08x\n", hw_desc->addr_ext_45); 615 dev_dbg(dev, "src_addr2: 0x%08x\n", hw_desc->src_addr2); 616 dev_dbg(dev, "src_addr3: 0x%08x\n", hw_desc->src_addr3); 617 dev_dbg(dev, "src_addr4: 0x%08x\n", hw_desc->src_addr4); 618 dev_dbg(dev, "src_addr5: 0x%08x\n", hw_desc->src_addr5); 619 dev_dbg(dev, "crc: 0x%08x\n", hw_desc->crc); 620 } 621 622 dev_dbg(dev, "------- TX descriptor dump end -------\n"); 623 } 624 625 /** 626 * xilinx_dpdma_chan_alloc_tx_desc - Allocate a transaction descriptor 627 * @chan: DPDMA channel 628 * 629 * Allocate a tx descriptor. 630 * 631 * Return: a tx descriptor or NULL. 632 */ 633 static struct xilinx_dpdma_tx_desc * 634 xilinx_dpdma_chan_alloc_tx_desc(struct xilinx_dpdma_chan *chan) 635 { 636 struct xilinx_dpdma_tx_desc *tx_desc; 637 638 tx_desc = kzalloc(sizeof(*tx_desc), GFP_NOWAIT); 639 if (!tx_desc) 640 return NULL; 641 642 INIT_LIST_HEAD(&tx_desc->descriptors); 643 tx_desc->chan = chan; 644 tx_desc->error = false; 645 646 return tx_desc; 647 } 648 649 /** 650 * xilinx_dpdma_chan_free_tx_desc - Free a virtual DMA descriptor 651 * @vdesc: virtual DMA descriptor 652 * 653 * Free the virtual DMA descriptor @vdesc including its software descriptors. 654 */ 655 static void xilinx_dpdma_chan_free_tx_desc(struct virt_dma_desc *vdesc) 656 { 657 struct xilinx_dpdma_sw_desc *sw_desc, *next; 658 struct xilinx_dpdma_tx_desc *desc; 659 660 if (!vdesc) 661 return; 662 663 desc = to_dpdma_tx_desc(vdesc); 664 665 list_for_each_entry_safe(sw_desc, next, &desc->descriptors, node) { 666 list_del(&sw_desc->node); 667 xilinx_dpdma_chan_free_sw_desc(desc->chan, sw_desc); 668 } 669 670 kfree(desc); 671 } 672 673 /** 674 * xilinx_dpdma_chan_prep_interleaved_dma - Prepare an interleaved dma 675 * descriptor 676 * @chan: DPDMA channel 677 * @xt: dma interleaved template 678 * 679 * Prepare a tx descriptor including internal software/hardware descriptors 680 * based on @xt. 681 * 682 * Return: A DPDMA TX descriptor on success, or NULL. 683 */ 684 static struct xilinx_dpdma_tx_desc * 685 xilinx_dpdma_chan_prep_interleaved_dma(struct xilinx_dpdma_chan *chan, 686 struct dma_interleaved_template *xt) 687 { 688 struct xilinx_dpdma_tx_desc *tx_desc; 689 struct xilinx_dpdma_sw_desc *sw_desc; 690 struct xilinx_dpdma_hw_desc *hw_desc; 691 size_t hsize = xt->sgl[0].size; 692 size_t stride = hsize + xt->sgl[0].icg; 693 694 if (!IS_ALIGNED(xt->src_start, XILINX_DPDMA_ALIGN_BYTES)) { 695 dev_err(chan->xdev->dev, 696 "chan%u: buffer should be aligned at %d B\n", 697 chan->id, XILINX_DPDMA_ALIGN_BYTES); 698 return NULL; 699 } 700 701 tx_desc = xilinx_dpdma_chan_alloc_tx_desc(chan); 702 if (!tx_desc) 703 return NULL; 704 705 sw_desc = xilinx_dpdma_chan_alloc_sw_desc(chan); 706 if (!sw_desc) { 707 xilinx_dpdma_chan_free_tx_desc(&tx_desc->vdesc); 708 return NULL; 709 } 710 711 xilinx_dpdma_sw_desc_set_dma_addrs(chan->xdev, sw_desc, sw_desc, 712 &xt->src_start, 1); 713 714 hw_desc = &sw_desc->hw; 715 hsize = ALIGN(hsize, XILINX_DPDMA_LINESIZE_ALIGN_BITS / 8); 716 hw_desc->xfer_size = hsize * xt->numf; 717 hw_desc->hsize_stride = 718 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_HSIZE_MASK, hsize) | 719 FIELD_PREP(XILINX_DPDMA_DESC_HSIZE_STRIDE_STRIDE_MASK, 720 stride / 16); 721 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_PREEMBLE; 722 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_COMPLETE_INTR; 723 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_IGNORE_DONE; 724 hw_desc->control |= XILINX_DPDMA_DESC_CONTROL_LAST_OF_FRAME; 725 726 list_add_tail(&sw_desc->node, &tx_desc->descriptors); 727 728 return tx_desc; 729 } 730 731 /* ----------------------------------------------------------------------------- 732 * DPDMA Channel Operations 733 */ 734 735 /** 736 * xilinx_dpdma_chan_enable - Enable the channel 737 * @chan: DPDMA channel 738 * 739 * Enable the channel and its interrupts. Set the QoS values for video class. 740 */ 741 static void xilinx_dpdma_chan_enable(struct xilinx_dpdma_chan *chan) 742 { 743 u32 reg; 744 745 reg = (XILINX_DPDMA_INTR_CHAN_MASK << chan->id) 746 | XILINX_DPDMA_INTR_GLOBAL_MASK; 747 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg); 748 reg = (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id) 749 | XILINX_DPDMA_INTR_GLOBAL_ERR; 750 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg); 751 752 reg = XILINX_DPDMA_CH_CNTL_ENABLE 753 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_WR_MASK, 754 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS) 755 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DSCR_RD_MASK, 756 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS) 757 | FIELD_PREP(XILINX_DPDMA_CH_CNTL_QOS_DATA_RD_MASK, 758 XILINX_DPDMA_CH_CNTL_QOS_VID_CLASS); 759 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, reg); 760 } 761 762 /** 763 * xilinx_dpdma_chan_disable - Disable the channel 764 * @chan: DPDMA channel 765 * 766 * Disable the channel and its interrupts. 767 */ 768 static void xilinx_dpdma_chan_disable(struct xilinx_dpdma_chan *chan) 769 { 770 u32 reg; 771 772 reg = XILINX_DPDMA_INTR_CHAN_MASK << chan->id; 773 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, reg); 774 reg = XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id; 775 dpdma_write(chan->xdev->reg, XILINX_DPDMA_EIEN, reg); 776 777 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE); 778 } 779 780 /** 781 * xilinx_dpdma_chan_pause - Pause the channel 782 * @chan: DPDMA channel 783 * 784 * Pause the channel. 785 */ 786 static void xilinx_dpdma_chan_pause(struct xilinx_dpdma_chan *chan) 787 { 788 dpdma_set(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE); 789 } 790 791 /** 792 * xilinx_dpdma_chan_unpause - Unpause the channel 793 * @chan: DPDMA channel 794 * 795 * Unpause the channel. 796 */ 797 static void xilinx_dpdma_chan_unpause(struct xilinx_dpdma_chan *chan) 798 { 799 dpdma_clr(chan->reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_PAUSE); 800 } 801 802 static u32 xilinx_dpdma_chan_video_group_ready(struct xilinx_dpdma_chan *chan) 803 { 804 struct xilinx_dpdma_device *xdev = chan->xdev; 805 u32 channels = 0; 806 unsigned int i; 807 808 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) { 809 if (xdev->chan[i]->video_group && !xdev->chan[i]->running) 810 return 0; 811 812 if (xdev->chan[i]->video_group) 813 channels |= BIT(i); 814 } 815 816 return channels; 817 } 818 819 /** 820 * xilinx_dpdma_chan_queue_transfer - Queue the next transfer 821 * @chan: DPDMA channel 822 * 823 * Queue the next descriptor, if any, to the hardware. If the channel is 824 * stopped, start it first. Otherwise retrigger it with the next descriptor. 825 */ 826 static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan) 827 { 828 struct xilinx_dpdma_device *xdev = chan->xdev; 829 struct xilinx_dpdma_sw_desc *sw_desc; 830 struct xilinx_dpdma_tx_desc *desc; 831 struct virt_dma_desc *vdesc; 832 u32 reg, channels; 833 bool first_frame; 834 835 lockdep_assert_held(&chan->lock); 836 837 if (chan->desc.pending) 838 return; 839 840 if (!chan->running) { 841 xilinx_dpdma_chan_unpause(chan); 842 xilinx_dpdma_chan_enable(chan); 843 chan->first_frame = true; 844 chan->running = true; 845 } 846 847 vdesc = vchan_next_desc(&chan->vchan); 848 if (!vdesc) 849 return; 850 851 desc = to_dpdma_tx_desc(vdesc); 852 chan->desc.pending = desc; 853 list_del(&desc->vdesc.node); 854 855 /* 856 * Assign the cookie to descriptors in this transaction. Only 16 bit 857 * will be used, but it should be enough. 858 */ 859 list_for_each_entry(sw_desc, &desc->descriptors, node) 860 sw_desc->hw.desc_id = desc->vdesc.tx.cookie 861 & XILINX_DPDMA_CH_DESC_ID_MASK; 862 863 sw_desc = list_first_entry(&desc->descriptors, 864 struct xilinx_dpdma_sw_desc, node); 865 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR, 866 lower_32_bits(sw_desc->dma_addr)); 867 if (xdev->ext_addr) 868 dpdma_write(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE, 869 FIELD_PREP(XILINX_DPDMA_CH_DESC_START_ADDRE_MASK, 870 upper_32_bits(sw_desc->dma_addr))); 871 872 first_frame = chan->first_frame; 873 chan->first_frame = false; 874 875 if (chan->video_group) { 876 channels = xilinx_dpdma_chan_video_group_ready(chan); 877 /* 878 * Trigger the transfer only when all channels in the group are 879 * ready. 880 */ 881 if (!channels) 882 return; 883 } else { 884 channels = BIT(chan->id); 885 } 886 887 if (first_frame) 888 reg = XILINX_DPDMA_GBL_TRIG_MASK(channels); 889 else 890 reg = XILINX_DPDMA_GBL_RETRIG_MASK(channels); 891 892 dpdma_write(xdev->reg, XILINX_DPDMA_GBL, reg); 893 } 894 895 /** 896 * xilinx_dpdma_chan_ostand - Number of outstanding transactions 897 * @chan: DPDMA channel 898 * 899 * Read and return the number of outstanding transactions from register. 900 * 901 * Return: Number of outstanding transactions from the status register. 902 */ 903 static u32 xilinx_dpdma_chan_ostand(struct xilinx_dpdma_chan *chan) 904 { 905 return FIELD_GET(XILINX_DPDMA_CH_STATUS_OTRAN_CNT_MASK, 906 dpdma_read(chan->reg, XILINX_DPDMA_CH_STATUS)); 907 } 908 909 /** 910 * xilinx_dpdma_chan_notify_no_ostand - Notify no outstanding transaction event 911 * @chan: DPDMA channel 912 * 913 * Notify waiters for no outstanding event, so waiters can stop the channel 914 * safely. This function is supposed to be called when 'no outstanding' 915 * interrupt is generated. The 'no outstanding' interrupt is disabled and 916 * should be re-enabled when this event is handled. If the channel status 917 * register still shows some number of outstanding transactions, the interrupt 918 * remains enabled. 919 * 920 * Return: 0 on success. On failure, -EWOULDBLOCK if there's still outstanding 921 * transaction(s). 922 */ 923 static int xilinx_dpdma_chan_notify_no_ostand(struct xilinx_dpdma_chan *chan) 924 { 925 u32 cnt; 926 927 cnt = xilinx_dpdma_chan_ostand(chan); 928 if (cnt) { 929 dev_dbg(chan->xdev->dev, 930 "chan%u: %d outstanding transactions\n", 931 chan->id, cnt); 932 return -EWOULDBLOCK; 933 } 934 935 /* Disable 'no outstanding' interrupt */ 936 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IDS, 937 XILINX_DPDMA_INTR_NO_OSTAND(chan->id)); 938 wake_up(&chan->wait_to_stop); 939 940 return 0; 941 } 942 943 /** 944 * xilinx_dpdma_chan_wait_no_ostand - Wait for the no outstanding irq 945 * @chan: DPDMA channel 946 * 947 * Wait for the no outstanding transaction interrupt. This functions can sleep 948 * for 50ms. 949 * 950 * Return: 0 on success. On failure, -ETIMEOUT for time out, or the error code 951 * from wait_event_interruptible_timeout(). 952 */ 953 static int xilinx_dpdma_chan_wait_no_ostand(struct xilinx_dpdma_chan *chan) 954 { 955 int ret; 956 957 /* Wait for a no outstanding transaction interrupt upto 50msec */ 958 ret = wait_event_interruptible_timeout(chan->wait_to_stop, 959 !xilinx_dpdma_chan_ostand(chan), 960 msecs_to_jiffies(50)); 961 if (ret > 0) { 962 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, 963 XILINX_DPDMA_INTR_NO_OSTAND(chan->id)); 964 return 0; 965 } 966 967 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n", 968 chan->id, xilinx_dpdma_chan_ostand(chan)); 969 970 if (ret == 0) 971 return -ETIMEDOUT; 972 973 return ret; 974 } 975 976 /** 977 * xilinx_dpdma_chan_poll_no_ostand - Poll the outstanding transaction status 978 * @chan: DPDMA channel 979 * 980 * Poll the outstanding transaction status, and return when there's no 981 * outstanding transaction. This functions can be used in the interrupt context 982 * or where the atomicity is required. Calling thread may wait more than 50ms. 983 * 984 * Return: 0 on success, or -ETIMEDOUT. 985 */ 986 static int xilinx_dpdma_chan_poll_no_ostand(struct xilinx_dpdma_chan *chan) 987 { 988 u32 cnt, loop = 50000; 989 990 /* Poll at least for 50ms (20 fps). */ 991 do { 992 cnt = xilinx_dpdma_chan_ostand(chan); 993 udelay(1); 994 } while (loop-- > 0 && cnt); 995 996 if (loop) { 997 dpdma_write(chan->xdev->reg, XILINX_DPDMA_IEN, 998 XILINX_DPDMA_INTR_NO_OSTAND(chan->id)); 999 return 0; 1000 } 1001 1002 dev_err(chan->xdev->dev, "chan%u: not ready to stop: %d trans\n", 1003 chan->id, xilinx_dpdma_chan_ostand(chan)); 1004 1005 return -ETIMEDOUT; 1006 } 1007 1008 /** 1009 * xilinx_dpdma_chan_stop - Stop the channel 1010 * @chan: DPDMA channel 1011 * 1012 * Stop a previously paused channel by first waiting for completion of all 1013 * outstanding transaction and then disabling the channel. 1014 * 1015 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop. 1016 */ 1017 static int xilinx_dpdma_chan_stop(struct xilinx_dpdma_chan *chan) 1018 { 1019 unsigned long flags; 1020 int ret; 1021 1022 ret = xilinx_dpdma_chan_wait_no_ostand(chan); 1023 if (ret) 1024 return ret; 1025 1026 spin_lock_irqsave(&chan->lock, flags); 1027 xilinx_dpdma_chan_disable(chan); 1028 chan->running = false; 1029 spin_unlock_irqrestore(&chan->lock, flags); 1030 1031 return 0; 1032 } 1033 1034 /** 1035 * xilinx_dpdma_chan_done_irq - Handle hardware descriptor completion 1036 * @chan: DPDMA channel 1037 * 1038 * Handle completion of the currently active descriptor (@chan->desc.active). As 1039 * we currently support cyclic transfers only, this just invokes the cyclic 1040 * callback. The descriptor will be completed at the VSYNC interrupt when a new 1041 * descriptor replaces it. 1042 */ 1043 static void xilinx_dpdma_chan_done_irq(struct xilinx_dpdma_chan *chan) 1044 { 1045 struct xilinx_dpdma_tx_desc *active; 1046 1047 spin_lock(&chan->lock); 1048 1049 xilinx_dpdma_debugfs_desc_done_irq(chan); 1050 1051 active = chan->desc.active; 1052 if (active) 1053 vchan_cyclic_callback(&active->vdesc); 1054 else 1055 dev_warn(chan->xdev->dev, 1056 "chan%u: DONE IRQ with no active descriptor!\n", 1057 chan->id); 1058 1059 spin_unlock(&chan->lock); 1060 } 1061 1062 /** 1063 * xilinx_dpdma_chan_vsync_irq - Handle hardware descriptor scheduling 1064 * @chan: DPDMA channel 1065 * 1066 * At VSYNC the active descriptor may have been replaced by the pending 1067 * descriptor. Detect this through the DESC_ID and perform appropriate 1068 * bookkeeping. 1069 */ 1070 static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan) 1071 { 1072 struct xilinx_dpdma_tx_desc *pending; 1073 struct xilinx_dpdma_sw_desc *sw_desc; 1074 u32 desc_id; 1075 1076 spin_lock(&chan->lock); 1077 1078 pending = chan->desc.pending; 1079 if (!chan->running || !pending) 1080 goto out; 1081 1082 desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID) 1083 & XILINX_DPDMA_CH_DESC_ID_MASK; 1084 1085 /* If the retrigger raced with vsync, retry at the next frame. */ 1086 sw_desc = list_first_entry(&pending->descriptors, 1087 struct xilinx_dpdma_sw_desc, node); 1088 if (sw_desc->hw.desc_id != desc_id) { 1089 dev_dbg(chan->xdev->dev, 1090 "chan%u: vsync race lost (%u != %u), retrying\n", 1091 chan->id, sw_desc->hw.desc_id, desc_id); 1092 goto out; 1093 } 1094 1095 /* 1096 * Complete the active descriptor, if any, promote the pending 1097 * descriptor to active, and queue the next transfer, if any. 1098 */ 1099 spin_lock(&chan->vchan.lock); 1100 if (chan->desc.active) 1101 vchan_cookie_complete(&chan->desc.active->vdesc); 1102 chan->desc.active = pending; 1103 chan->desc.pending = NULL; 1104 1105 xilinx_dpdma_chan_queue_transfer(chan); 1106 spin_unlock(&chan->vchan.lock); 1107 1108 out: 1109 spin_unlock(&chan->lock); 1110 } 1111 1112 /** 1113 * xilinx_dpdma_chan_err - Detect any channel error 1114 * @chan: DPDMA channel 1115 * @isr: masked Interrupt Status Register 1116 * @eisr: Error Interrupt Status Register 1117 * 1118 * Return: true if any channel error occurs, or false otherwise. 1119 */ 1120 static bool 1121 xilinx_dpdma_chan_err(struct xilinx_dpdma_chan *chan, u32 isr, u32 eisr) 1122 { 1123 if (!chan) 1124 return false; 1125 1126 if (chan->running && 1127 ((isr & (XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id)) || 1128 (eisr & (XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id)))) 1129 return true; 1130 1131 return false; 1132 } 1133 1134 /** 1135 * xilinx_dpdma_chan_handle_err - DPDMA channel error handling 1136 * @chan: DPDMA channel 1137 * 1138 * This function is called when any channel error or any global error occurs. 1139 * The function disables the paused channel by errors and determines 1140 * if the current active descriptor can be rescheduled depending on 1141 * the descriptor status. 1142 */ 1143 static void xilinx_dpdma_chan_handle_err(struct xilinx_dpdma_chan *chan) 1144 { 1145 struct xilinx_dpdma_device *xdev = chan->xdev; 1146 struct xilinx_dpdma_tx_desc *active; 1147 unsigned long flags; 1148 1149 spin_lock_irqsave(&chan->lock, flags); 1150 1151 dev_dbg(xdev->dev, "chan%u: cur desc addr = 0x%04x%08x\n", 1152 chan->id, 1153 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDRE), 1154 dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_START_ADDR)); 1155 dev_dbg(xdev->dev, "chan%u: cur payload addr = 0x%04x%08x\n", 1156 chan->id, 1157 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDRE), 1158 dpdma_read(chan->reg, XILINX_DPDMA_CH_PYLD_CUR_ADDR)); 1159 1160 xilinx_dpdma_chan_disable(chan); 1161 chan->running = false; 1162 1163 if (!chan->desc.active) 1164 goto out_unlock; 1165 1166 active = chan->desc.active; 1167 chan->desc.active = NULL; 1168 1169 xilinx_dpdma_chan_dump_tx_desc(chan, active); 1170 1171 if (active->error) 1172 dev_dbg(xdev->dev, "chan%u: repeated error on desc\n", 1173 chan->id); 1174 1175 /* Reschedule if there's no new descriptor */ 1176 if (!chan->desc.pending && 1177 list_empty(&chan->vchan.desc_issued)) { 1178 active->error = true; 1179 list_add_tail(&active->vdesc.node, 1180 &chan->vchan.desc_issued); 1181 } else { 1182 xilinx_dpdma_chan_free_tx_desc(&active->vdesc); 1183 } 1184 1185 out_unlock: 1186 spin_unlock_irqrestore(&chan->lock, flags); 1187 } 1188 1189 /* ----------------------------------------------------------------------------- 1190 * DMA Engine Operations 1191 */ 1192 1193 static struct dma_async_tx_descriptor * 1194 xilinx_dpdma_prep_interleaved_dma(struct dma_chan *dchan, 1195 struct dma_interleaved_template *xt, 1196 unsigned long flags) 1197 { 1198 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1199 struct xilinx_dpdma_tx_desc *desc; 1200 1201 if (xt->dir != DMA_MEM_TO_DEV) 1202 return NULL; 1203 1204 if (!xt->numf || !xt->sgl[0].size) 1205 return NULL; 1206 1207 if (!(flags & DMA_PREP_REPEAT) || !(flags & DMA_PREP_LOAD_EOT)) 1208 return NULL; 1209 1210 desc = xilinx_dpdma_chan_prep_interleaved_dma(chan, xt); 1211 if (!desc) 1212 return NULL; 1213 1214 vchan_tx_prep(&chan->vchan, &desc->vdesc, flags | DMA_CTRL_ACK); 1215 1216 return &desc->vdesc.tx; 1217 } 1218 1219 /** 1220 * xilinx_dpdma_alloc_chan_resources - Allocate resources for the channel 1221 * @dchan: DMA channel 1222 * 1223 * Allocate a descriptor pool for the channel. 1224 * 1225 * Return: 0 on success, or -ENOMEM if failed to allocate a pool. 1226 */ 1227 static int xilinx_dpdma_alloc_chan_resources(struct dma_chan *dchan) 1228 { 1229 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1230 size_t align = __alignof__(struct xilinx_dpdma_sw_desc); 1231 1232 chan->desc_pool = dma_pool_create(dev_name(chan->xdev->dev), 1233 chan->xdev->dev, 1234 sizeof(struct xilinx_dpdma_sw_desc), 1235 align, 0); 1236 if (!chan->desc_pool) { 1237 dev_err(chan->xdev->dev, 1238 "chan%u: failed to allocate a descriptor pool\n", 1239 chan->id); 1240 return -ENOMEM; 1241 } 1242 1243 return 0; 1244 } 1245 1246 /** 1247 * xilinx_dpdma_free_chan_resources - Free all resources for the channel 1248 * @dchan: DMA channel 1249 * 1250 * Free resources associated with the virtual DMA channel, and destroy the 1251 * descriptor pool. 1252 */ 1253 static void xilinx_dpdma_free_chan_resources(struct dma_chan *dchan) 1254 { 1255 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1256 1257 vchan_free_chan_resources(&chan->vchan); 1258 1259 dma_pool_destroy(chan->desc_pool); 1260 chan->desc_pool = NULL; 1261 } 1262 1263 static void xilinx_dpdma_issue_pending(struct dma_chan *dchan) 1264 { 1265 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1266 unsigned long flags; 1267 1268 spin_lock_irqsave(&chan->lock, flags); 1269 spin_lock(&chan->vchan.lock); 1270 if (vchan_issue_pending(&chan->vchan)) 1271 xilinx_dpdma_chan_queue_transfer(chan); 1272 spin_unlock(&chan->vchan.lock); 1273 spin_unlock_irqrestore(&chan->lock, flags); 1274 } 1275 1276 static int xilinx_dpdma_config(struct dma_chan *dchan, 1277 struct dma_slave_config *config) 1278 { 1279 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1280 struct xilinx_dpdma_peripheral_config *pconfig; 1281 unsigned long flags; 1282 1283 /* 1284 * The destination address doesn't need to be specified as the DPDMA is 1285 * hardwired to the destination (the DP controller). The transfer 1286 * width, burst size and port window size are thus meaningless, they're 1287 * fixed both on the DPDMA side and on the DP controller side. 1288 */ 1289 1290 /* 1291 * Use the peripheral_config to indicate that the channel is part 1292 * of a video group. This requires matching use of the custom 1293 * structure in each driver. 1294 */ 1295 pconfig = config->peripheral_config; 1296 if (WARN_ON(pconfig && config->peripheral_size != sizeof(*pconfig))) 1297 return -EINVAL; 1298 1299 spin_lock_irqsave(&chan->lock, flags); 1300 if (chan->id <= ZYNQMP_DPDMA_VIDEO2 && pconfig) 1301 chan->video_group = pconfig->video_group; 1302 spin_unlock_irqrestore(&chan->lock, flags); 1303 1304 return 0; 1305 } 1306 1307 static int xilinx_dpdma_pause(struct dma_chan *dchan) 1308 { 1309 xilinx_dpdma_chan_pause(to_xilinx_chan(dchan)); 1310 1311 return 0; 1312 } 1313 1314 static int xilinx_dpdma_resume(struct dma_chan *dchan) 1315 { 1316 xilinx_dpdma_chan_unpause(to_xilinx_chan(dchan)); 1317 1318 return 0; 1319 } 1320 1321 /** 1322 * xilinx_dpdma_terminate_all - Terminate the channel and descriptors 1323 * @dchan: DMA channel 1324 * 1325 * Pause the channel without waiting for ongoing transfers to complete. Waiting 1326 * for completion is performed by xilinx_dpdma_synchronize() that will disable 1327 * the channel to complete the stop. 1328 * 1329 * All the descriptors associated with the channel that are guaranteed not to 1330 * be touched by the hardware. The pending and active descriptor are not 1331 * touched, and will be freed either upon completion, or by 1332 * xilinx_dpdma_synchronize(). 1333 * 1334 * Return: 0 on success, or -ETIMEDOUT if the channel failed to stop. 1335 */ 1336 static int xilinx_dpdma_terminate_all(struct dma_chan *dchan) 1337 { 1338 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1339 struct xilinx_dpdma_device *xdev = chan->xdev; 1340 LIST_HEAD(descriptors); 1341 unsigned long flags; 1342 unsigned int i; 1343 1344 /* Pause the channel (including the whole video group if applicable). */ 1345 if (chan->video_group) { 1346 for (i = ZYNQMP_DPDMA_VIDEO0; i <= ZYNQMP_DPDMA_VIDEO2; i++) { 1347 if (xdev->chan[i]->video_group && 1348 xdev->chan[i]->running) { 1349 xilinx_dpdma_chan_pause(xdev->chan[i]); 1350 xdev->chan[i]->video_group = false; 1351 } 1352 } 1353 } else { 1354 xilinx_dpdma_chan_pause(chan); 1355 } 1356 1357 /* Gather all the descriptors we can free and free them. */ 1358 spin_lock_irqsave(&chan->vchan.lock, flags); 1359 vchan_get_all_descriptors(&chan->vchan, &descriptors); 1360 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1361 1362 vchan_dma_desc_free_list(&chan->vchan, &descriptors); 1363 1364 return 0; 1365 } 1366 1367 /** 1368 * xilinx_dpdma_synchronize - Synchronize callback execution 1369 * @dchan: DMA channel 1370 * 1371 * Synchronizing callback execution ensures that all previously issued 1372 * transfers have completed and all associated callbacks have been called and 1373 * have returned. 1374 * 1375 * This function waits for the DMA channel to stop. It assumes it has been 1376 * paused by a previous call to dmaengine_terminate_async(), and that no new 1377 * pending descriptors have been issued with dma_async_issue_pending(). The 1378 * behaviour is undefined otherwise. 1379 */ 1380 static void xilinx_dpdma_synchronize(struct dma_chan *dchan) 1381 { 1382 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1383 unsigned long flags; 1384 1385 xilinx_dpdma_chan_stop(chan); 1386 1387 spin_lock_irqsave(&chan->vchan.lock, flags); 1388 if (chan->desc.pending) { 1389 vchan_terminate_vdesc(&chan->desc.pending->vdesc); 1390 chan->desc.pending = NULL; 1391 } 1392 if (chan->desc.active) { 1393 vchan_terminate_vdesc(&chan->desc.active->vdesc); 1394 chan->desc.active = NULL; 1395 } 1396 spin_unlock_irqrestore(&chan->vchan.lock, flags); 1397 1398 vchan_synchronize(&chan->vchan); 1399 } 1400 1401 /* ----------------------------------------------------------------------------- 1402 * Interrupt and Tasklet Handling 1403 */ 1404 1405 /** 1406 * xilinx_dpdma_err - Detect any global error 1407 * @isr: Interrupt Status Register 1408 * @eisr: Error Interrupt Status Register 1409 * 1410 * Return: True if any global error occurs, or false otherwise. 1411 */ 1412 static bool xilinx_dpdma_err(u32 isr, u32 eisr) 1413 { 1414 if (isr & XILINX_DPDMA_INTR_GLOBAL_ERR || 1415 eisr & XILINX_DPDMA_EINTR_GLOBAL_ERR) 1416 return true; 1417 1418 return false; 1419 } 1420 1421 /** 1422 * xilinx_dpdma_handle_err_irq - Handle DPDMA error interrupt 1423 * @xdev: DPDMA device 1424 * @isr: masked Interrupt Status Register 1425 * @eisr: Error Interrupt Status Register 1426 * 1427 * Handle if any error occurs based on @isr and @eisr. This function disables 1428 * corresponding error interrupts, and those should be re-enabled once handling 1429 * is done. 1430 */ 1431 static void xilinx_dpdma_handle_err_irq(struct xilinx_dpdma_device *xdev, 1432 u32 isr, u32 eisr) 1433 { 1434 bool err = xilinx_dpdma_err(isr, eisr); 1435 unsigned int i; 1436 1437 dev_dbg_ratelimited(xdev->dev, 1438 "error irq: isr = 0x%08x, eisr = 0x%08x\n", 1439 isr, eisr); 1440 1441 /* Disable channel error interrupts until errors are handled. */ 1442 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, 1443 isr & ~XILINX_DPDMA_INTR_GLOBAL_ERR); 1444 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, 1445 eisr & ~XILINX_DPDMA_EINTR_GLOBAL_ERR); 1446 1447 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) 1448 if (err || xilinx_dpdma_chan_err(xdev->chan[i], isr, eisr)) 1449 tasklet_schedule(&xdev->chan[i]->err_task); 1450 } 1451 1452 /** 1453 * xilinx_dpdma_enable_irq - Enable interrupts 1454 * @xdev: DPDMA device 1455 * 1456 * Enable interrupts. 1457 */ 1458 static void xilinx_dpdma_enable_irq(struct xilinx_dpdma_device *xdev) 1459 { 1460 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, XILINX_DPDMA_INTR_ALL); 1461 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, XILINX_DPDMA_EINTR_ALL); 1462 } 1463 1464 /** 1465 * xilinx_dpdma_disable_irq - Disable interrupts 1466 * @xdev: DPDMA device 1467 * 1468 * Disable interrupts. 1469 */ 1470 static void xilinx_dpdma_disable_irq(struct xilinx_dpdma_device *xdev) 1471 { 1472 dpdma_write(xdev->reg, XILINX_DPDMA_IDS, XILINX_DPDMA_INTR_ALL); 1473 dpdma_write(xdev->reg, XILINX_DPDMA_EIDS, XILINX_DPDMA_EINTR_ALL); 1474 } 1475 1476 /** 1477 * xilinx_dpdma_chan_err_task - Per channel tasklet for error handling 1478 * @t: pointer to the tasklet associated with this handler 1479 * 1480 * Per channel error handling tasklet. This function waits for the outstanding 1481 * transaction to complete and triggers error handling. After error handling, 1482 * re-enable channel error interrupts, and restart the channel if needed. 1483 */ 1484 static void xilinx_dpdma_chan_err_task(struct tasklet_struct *t) 1485 { 1486 struct xilinx_dpdma_chan *chan = from_tasklet(chan, t, err_task); 1487 struct xilinx_dpdma_device *xdev = chan->xdev; 1488 unsigned long flags; 1489 1490 /* Proceed error handling even when polling fails. */ 1491 xilinx_dpdma_chan_poll_no_ostand(chan); 1492 1493 xilinx_dpdma_chan_handle_err(chan); 1494 1495 dpdma_write(xdev->reg, XILINX_DPDMA_IEN, 1496 XILINX_DPDMA_INTR_CHAN_ERR_MASK << chan->id); 1497 dpdma_write(xdev->reg, XILINX_DPDMA_EIEN, 1498 XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id); 1499 1500 spin_lock_irqsave(&chan->lock, flags); 1501 spin_lock(&chan->vchan.lock); 1502 xilinx_dpdma_chan_queue_transfer(chan); 1503 spin_unlock(&chan->vchan.lock); 1504 spin_unlock_irqrestore(&chan->lock, flags); 1505 } 1506 1507 static irqreturn_t xilinx_dpdma_irq_handler(int irq, void *data) 1508 { 1509 struct xilinx_dpdma_device *xdev = data; 1510 unsigned long mask; 1511 unsigned int i; 1512 u32 status; 1513 u32 error; 1514 1515 status = dpdma_read(xdev->reg, XILINX_DPDMA_ISR); 1516 error = dpdma_read(xdev->reg, XILINX_DPDMA_EISR); 1517 if (!status && !error) 1518 return IRQ_NONE; 1519 1520 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, status); 1521 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, error); 1522 1523 if (status & XILINX_DPDMA_INTR_VSYNC) { 1524 /* 1525 * There's a single VSYNC interrupt that needs to be processed 1526 * by each running channel to update the active descriptor. 1527 */ 1528 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) { 1529 struct xilinx_dpdma_chan *chan = xdev->chan[i]; 1530 1531 if (chan) 1532 xilinx_dpdma_chan_vsync_irq(chan); 1533 } 1534 } 1535 1536 mask = FIELD_GET(XILINX_DPDMA_INTR_DESC_DONE_MASK, status); 1537 if (mask) { 1538 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan)) 1539 xilinx_dpdma_chan_done_irq(xdev->chan[i]); 1540 } 1541 1542 mask = FIELD_GET(XILINX_DPDMA_INTR_NO_OSTAND_MASK, status); 1543 if (mask) { 1544 for_each_set_bit(i, &mask, ARRAY_SIZE(xdev->chan)) 1545 xilinx_dpdma_chan_notify_no_ostand(xdev->chan[i]); 1546 } 1547 1548 mask = status & XILINX_DPDMA_INTR_ERR_ALL; 1549 if (mask || error) 1550 xilinx_dpdma_handle_err_irq(xdev, mask, error); 1551 1552 return IRQ_HANDLED; 1553 } 1554 1555 /* ----------------------------------------------------------------------------- 1556 * Initialization & Cleanup 1557 */ 1558 1559 static int xilinx_dpdma_chan_init(struct xilinx_dpdma_device *xdev, 1560 unsigned int chan_id) 1561 { 1562 struct xilinx_dpdma_chan *chan; 1563 1564 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); 1565 if (!chan) 1566 return -ENOMEM; 1567 1568 chan->id = chan_id; 1569 chan->reg = xdev->reg + XILINX_DPDMA_CH_BASE 1570 + XILINX_DPDMA_CH_OFFSET * chan->id; 1571 chan->running = false; 1572 chan->xdev = xdev; 1573 1574 spin_lock_init(&chan->lock); 1575 init_waitqueue_head(&chan->wait_to_stop); 1576 1577 tasklet_setup(&chan->err_task, xilinx_dpdma_chan_err_task); 1578 1579 chan->vchan.desc_free = xilinx_dpdma_chan_free_tx_desc; 1580 vchan_init(&chan->vchan, &xdev->common); 1581 1582 xdev->chan[chan->id] = chan; 1583 1584 return 0; 1585 } 1586 1587 static void xilinx_dpdma_chan_remove(struct xilinx_dpdma_chan *chan) 1588 { 1589 if (!chan) 1590 return; 1591 1592 tasklet_kill(&chan->err_task); 1593 list_del(&chan->vchan.chan.device_node); 1594 } 1595 1596 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, 1597 struct of_dma *ofdma) 1598 { 1599 struct xilinx_dpdma_device *xdev = ofdma->of_dma_data; 1600 u32 chan_id = dma_spec->args[0]; 1601 1602 if (chan_id >= ARRAY_SIZE(xdev->chan)) 1603 return NULL; 1604 1605 if (!xdev->chan[chan_id]) 1606 return NULL; 1607 1608 return dma_get_slave_channel(&xdev->chan[chan_id]->vchan.chan); 1609 } 1610 1611 static void dpdma_hw_init(struct xilinx_dpdma_device *xdev) 1612 { 1613 unsigned int i; 1614 void __iomem *reg; 1615 1616 /* Disable all interrupts */ 1617 xilinx_dpdma_disable_irq(xdev); 1618 1619 /* Stop all channels */ 1620 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) { 1621 reg = xdev->reg + XILINX_DPDMA_CH_BASE 1622 + XILINX_DPDMA_CH_OFFSET * i; 1623 dpdma_clr(reg, XILINX_DPDMA_CH_CNTL, XILINX_DPDMA_CH_CNTL_ENABLE); 1624 } 1625 1626 /* Clear the interrupt status registers */ 1627 dpdma_write(xdev->reg, XILINX_DPDMA_ISR, XILINX_DPDMA_INTR_ALL); 1628 dpdma_write(xdev->reg, XILINX_DPDMA_EISR, XILINX_DPDMA_EINTR_ALL); 1629 } 1630 1631 static int xilinx_dpdma_probe(struct platform_device *pdev) 1632 { 1633 struct xilinx_dpdma_device *xdev; 1634 struct dma_device *ddev; 1635 unsigned int i; 1636 int ret; 1637 1638 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); 1639 if (!xdev) 1640 return -ENOMEM; 1641 1642 xdev->dev = &pdev->dev; 1643 xdev->ext_addr = sizeof(dma_addr_t) > 4; 1644 1645 INIT_LIST_HEAD(&xdev->common.channels); 1646 1647 platform_set_drvdata(pdev, xdev); 1648 1649 xdev->axi_clk = devm_clk_get(xdev->dev, "axi_clk"); 1650 if (IS_ERR(xdev->axi_clk)) 1651 return PTR_ERR(xdev->axi_clk); 1652 1653 xdev->reg = devm_platform_ioremap_resource(pdev, 0); 1654 if (IS_ERR(xdev->reg)) 1655 return PTR_ERR(xdev->reg); 1656 1657 dpdma_hw_init(xdev); 1658 1659 xdev->irq = platform_get_irq(pdev, 0); 1660 if (xdev->irq < 0) 1661 return xdev->irq; 1662 1663 ret = request_irq(xdev->irq, xilinx_dpdma_irq_handler, IRQF_SHARED, 1664 dev_name(xdev->dev), xdev); 1665 if (ret) { 1666 dev_err(xdev->dev, "failed to request IRQ\n"); 1667 return ret; 1668 } 1669 1670 ddev = &xdev->common; 1671 ddev->dev = &pdev->dev; 1672 1673 dma_cap_set(DMA_SLAVE, ddev->cap_mask); 1674 dma_cap_set(DMA_PRIVATE, ddev->cap_mask); 1675 dma_cap_set(DMA_INTERLEAVE, ddev->cap_mask); 1676 dma_cap_set(DMA_REPEAT, ddev->cap_mask); 1677 dma_cap_set(DMA_LOAD_EOT, ddev->cap_mask); 1678 ddev->copy_align = fls(XILINX_DPDMA_ALIGN_BYTES - 1); 1679 1680 ddev->device_alloc_chan_resources = xilinx_dpdma_alloc_chan_resources; 1681 ddev->device_free_chan_resources = xilinx_dpdma_free_chan_resources; 1682 ddev->device_prep_interleaved_dma = xilinx_dpdma_prep_interleaved_dma; 1683 /* TODO: Can we achieve better granularity ? */ 1684 ddev->device_tx_status = dma_cookie_status; 1685 ddev->device_issue_pending = xilinx_dpdma_issue_pending; 1686 ddev->device_config = xilinx_dpdma_config; 1687 ddev->device_pause = xilinx_dpdma_pause; 1688 ddev->device_resume = xilinx_dpdma_resume; 1689 ddev->device_terminate_all = xilinx_dpdma_terminate_all; 1690 ddev->device_synchronize = xilinx_dpdma_synchronize; 1691 ddev->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED); 1692 ddev->directions = BIT(DMA_MEM_TO_DEV); 1693 ddev->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 1694 1695 for (i = 0; i < ARRAY_SIZE(xdev->chan); ++i) { 1696 ret = xilinx_dpdma_chan_init(xdev, i); 1697 if (ret < 0) { 1698 dev_err(xdev->dev, "failed to initialize channel %u\n", 1699 i); 1700 goto error; 1701 } 1702 } 1703 1704 ret = clk_prepare_enable(xdev->axi_clk); 1705 if (ret) { 1706 dev_err(xdev->dev, "failed to enable the axi clock\n"); 1707 goto error; 1708 } 1709 1710 ret = dma_async_device_register(ddev); 1711 if (ret) { 1712 dev_err(xdev->dev, "failed to register the dma device\n"); 1713 goto error_dma_async; 1714 } 1715 1716 ret = of_dma_controller_register(xdev->dev->of_node, 1717 of_dma_xilinx_xlate, ddev); 1718 if (ret) { 1719 dev_err(xdev->dev, "failed to register DMA to DT DMA helper\n"); 1720 goto error_of_dma; 1721 } 1722 1723 xilinx_dpdma_enable_irq(xdev); 1724 1725 xilinx_dpdma_debugfs_init(xdev); 1726 1727 dev_info(&pdev->dev, "Xilinx DPDMA engine is probed\n"); 1728 1729 return 0; 1730 1731 error_of_dma: 1732 dma_async_device_unregister(ddev); 1733 error_dma_async: 1734 clk_disable_unprepare(xdev->axi_clk); 1735 error: 1736 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) 1737 xilinx_dpdma_chan_remove(xdev->chan[i]); 1738 1739 free_irq(xdev->irq, xdev); 1740 1741 return ret; 1742 } 1743 1744 static void xilinx_dpdma_remove(struct platform_device *pdev) 1745 { 1746 struct xilinx_dpdma_device *xdev = platform_get_drvdata(pdev); 1747 unsigned int i; 1748 1749 /* Start by disabling the IRQ to avoid races during cleanup. */ 1750 free_irq(xdev->irq, xdev); 1751 1752 xilinx_dpdma_disable_irq(xdev); 1753 of_dma_controller_free(pdev->dev.of_node); 1754 dma_async_device_unregister(&xdev->common); 1755 clk_disable_unprepare(xdev->axi_clk); 1756 1757 for (i = 0; i < ARRAY_SIZE(xdev->chan); i++) 1758 xilinx_dpdma_chan_remove(xdev->chan[i]); 1759 } 1760 1761 static const struct of_device_id xilinx_dpdma_of_match[] = { 1762 { .compatible = "xlnx,zynqmp-dpdma",}, 1763 { /* end of table */ }, 1764 }; 1765 MODULE_DEVICE_TABLE(of, xilinx_dpdma_of_match); 1766 1767 static struct platform_driver xilinx_dpdma_driver = { 1768 .probe = xilinx_dpdma_probe, 1769 .remove_new = xilinx_dpdma_remove, 1770 .driver = { 1771 .name = "xilinx-zynqmp-dpdma", 1772 .of_match_table = xilinx_dpdma_of_match, 1773 }, 1774 }; 1775 1776 module_platform_driver(xilinx_dpdma_driver); 1777 1778 MODULE_AUTHOR("Xilinx, Inc."); 1779 MODULE_DESCRIPTION("Xilinx ZynqMP DPDMA driver"); 1780 MODULE_LICENSE("GPL v2"); 1781