1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DMA driver for Xilinx Video DMA Engine 4 * 5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved. 6 * 7 * Based on the Freescale DMA driver. 8 * 9 * Description: 10 * The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP 11 * core that provides high-bandwidth direct memory access between memory 12 * and AXI4-Stream type video target peripherals. The core provides efficient 13 * two dimensional DMA operations with independent asynchronous read (S2MM) 14 * and write (MM2S) channel operation. It can be configured to have either 15 * one channel or two channels. If configured as two channels, one is to 16 * transmit to the video device (MM2S) and another is to receive from the 17 * video device (S2MM). Initialization, status, interrupt and management 18 * registers are accessed through an AXI4-Lite slave interface. 19 * 20 * The AXI Direct Memory Access (AXI DMA) core is a soft Xilinx IP core that 21 * provides high-bandwidth one dimensional direct memory access between memory 22 * and AXI4-Stream target peripherals. It supports one receive and one 23 * transmit channel, both of them optional at synthesis time. 24 * 25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory 26 * Access (DMA) between a memory-mapped source address and a memory-mapped 27 * destination address. 28 * 29 * The AXI Multichannel Direct Memory Access (AXI MCDMA) core is a soft 30 * Xilinx IP that provides high-bandwidth direct memory access between 31 * memory and AXI4-Stream target peripherals. It provides scatter gather 32 * (SG) interface with multiple channels independent configuration support. 33 * 34 */ 35 36 #include <linux/bitops.h> 37 #include <linux/dmapool.h> 38 #include <linux/dma/xilinx_dma.h> 39 #include <linux/init.h> 40 #include <linux/interrupt.h> 41 #include <linux/io.h> 42 #include <linux/iopoll.h> 43 #include <linux/module.h> 44 #include <linux/of.h> 45 #include <linux/of_dma.h> 46 #include <linux/of_irq.h> 47 #include <linux/platform_device.h> 48 #include <linux/slab.h> 49 #include <linux/string_choices.h> 50 #include <linux/clk.h> 51 #include <linux/io-64-nonatomic-lo-hi.h> 52 53 #include "../dmaengine.h" 54 55 /* Register/Descriptor Offsets */ 56 #define XILINX_DMA_MM2S_CTRL_OFFSET 0x0000 57 #define XILINX_DMA_S2MM_CTRL_OFFSET 0x0030 58 #define XILINX_VDMA_MM2S_DESC_OFFSET 0x0050 59 #define XILINX_VDMA_S2MM_DESC_OFFSET 0x00a0 60 61 /* Control Registers */ 62 #define XILINX_DMA_REG_DMACR 0x0000 63 #define XILINX_DMA_DMACR_DELAY_MAX 0xff 64 #define XILINX_DMA_DMACR_DELAY_SHIFT 24 65 #define XILINX_DMA_DMACR_FRAME_COUNT_MAX 0xff 66 #define XILINX_DMA_DMACR_FRAME_COUNT_SHIFT 16 67 #define XILINX_DMA_DMACR_ERR_IRQ BIT(14) 68 #define XILINX_DMA_DMACR_DLY_CNT_IRQ BIT(13) 69 #define XILINX_DMA_DMACR_FRM_CNT_IRQ BIT(12) 70 #define XILINX_DMA_DMACR_MASTER_SHIFT 8 71 #define XILINX_DMA_DMACR_FSYNCSRC_SHIFT 5 72 #define XILINX_DMA_DMACR_FRAMECNT_EN BIT(4) 73 #define XILINX_DMA_DMACR_GENLOCK_EN BIT(3) 74 #define XILINX_DMA_DMACR_RESET BIT(2) 75 #define XILINX_DMA_DMACR_CIRC_EN BIT(1) 76 #define XILINX_DMA_DMACR_RUNSTOP BIT(0) 77 #define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5) 78 #define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24) 79 #define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16) 80 #define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8) 81 82 #define XILINX_DMA_REG_DMASR 0x0004 83 #define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15) 84 #define XILINX_DMA_DMASR_ERR_IRQ BIT(14) 85 #define XILINX_DMA_DMASR_DLY_CNT_IRQ BIT(13) 86 #define XILINX_DMA_DMASR_FRM_CNT_IRQ BIT(12) 87 #define XILINX_DMA_DMASR_SOF_LATE_ERR BIT(11) 88 #define XILINX_DMA_DMASR_SG_DEC_ERR BIT(10) 89 #define XILINX_DMA_DMASR_SG_SLV_ERR BIT(9) 90 #define XILINX_DMA_DMASR_EOF_EARLY_ERR BIT(8) 91 #define XILINX_DMA_DMASR_SOF_EARLY_ERR BIT(7) 92 #define XILINX_DMA_DMASR_DMA_DEC_ERR BIT(6) 93 #define XILINX_DMA_DMASR_DMA_SLAVE_ERR BIT(5) 94 #define XILINX_DMA_DMASR_DMA_INT_ERR BIT(4) 95 #define XILINX_DMA_DMASR_SG_MASK BIT(3) 96 #define XILINX_DMA_DMASR_IDLE BIT(1) 97 #define XILINX_DMA_DMASR_HALTED BIT(0) 98 #define XILINX_DMA_DMASR_DELAY_MASK GENMASK(31, 24) 99 #define XILINX_DMA_DMASR_FRAME_COUNT_MASK GENMASK(23, 16) 100 101 #define XILINX_DMA_REG_CURDESC 0x0008 102 #define XILINX_DMA_REG_TAILDESC 0x0010 103 #define XILINX_DMA_REG_REG_INDEX 0x0014 104 #define XILINX_DMA_REG_FRMSTORE 0x0018 105 #define XILINX_DMA_REG_THRESHOLD 0x001c 106 #define XILINX_DMA_REG_FRMPTR_STS 0x0024 107 #define XILINX_DMA_REG_PARK_PTR 0x0028 108 #define XILINX_DMA_PARK_PTR_WR_REF_SHIFT 8 109 #define XILINX_DMA_PARK_PTR_WR_REF_MASK GENMASK(12, 8) 110 #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 111 #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0) 112 #define XILINX_DMA_REG_VDMA_VERSION 0x002c 113 114 /* Register Direct Mode Registers */ 115 #define XILINX_DMA_REG_VSIZE 0x0000 116 #define XILINX_DMA_VSIZE_MASK GENMASK(12, 0) 117 #define XILINX_DMA_REG_HSIZE 0x0004 118 #define XILINX_DMA_HSIZE_MASK GENMASK(15, 0) 119 120 #define XILINX_DMA_REG_FRMDLY_STRIDE 0x0008 121 #define XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT 24 122 #define XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT 0 123 124 #define XILINX_VDMA_REG_START_ADDRESS(n) (0x000c + 4 * (n)) 125 #define XILINX_VDMA_REG_START_ADDRESS_64(n) (0x000c + 8 * (n)) 126 127 #define XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP 0x00ec 128 #define XILINX_VDMA_ENABLE_VERTICAL_FLIP BIT(0) 129 130 /* HW specific definitions */ 131 #define XILINX_MCDMA_MAX_CHANS_PER_DEVICE 0x20 132 #define XILINX_DMA_MAX_CHANS_PER_DEVICE 0x2 133 #define XILINX_CDMA_MAX_CHANS_PER_DEVICE 0x1 134 #define XILINX_DMA_DFAULT_ADDRWIDTH 0x20 135 136 #define XILINX_DMA_DMAXR_ALL_IRQ_MASK \ 137 (XILINX_DMA_DMASR_FRM_CNT_IRQ | \ 138 XILINX_DMA_DMASR_DLY_CNT_IRQ | \ 139 XILINX_DMA_DMASR_ERR_IRQ) 140 141 #define XILINX_DMA_DMASR_ALL_ERR_MASK \ 142 (XILINX_DMA_DMASR_EOL_LATE_ERR | \ 143 XILINX_DMA_DMASR_SOF_LATE_ERR | \ 144 XILINX_DMA_DMASR_SG_DEC_ERR | \ 145 XILINX_DMA_DMASR_SG_SLV_ERR | \ 146 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 147 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 148 XILINX_DMA_DMASR_DMA_DEC_ERR | \ 149 XILINX_DMA_DMASR_DMA_SLAVE_ERR | \ 150 XILINX_DMA_DMASR_DMA_INT_ERR) 151 152 /* 153 * Recoverable errors are DMA Internal error, SOF Early, EOF Early 154 * and SOF Late. They are only recoverable when C_FLUSH_ON_FSYNC 155 * is enabled in the h/w system. 156 */ 157 #define XILINX_DMA_DMASR_ERR_RECOVER_MASK \ 158 (XILINX_DMA_DMASR_SOF_LATE_ERR | \ 159 XILINX_DMA_DMASR_EOF_EARLY_ERR | \ 160 XILINX_DMA_DMASR_SOF_EARLY_ERR | \ 161 XILINX_DMA_DMASR_DMA_INT_ERR) 162 163 /* Axi VDMA Flush on Fsync bits */ 164 #define XILINX_DMA_FLUSH_S2MM 3 165 #define XILINX_DMA_FLUSH_MM2S 2 166 #define XILINX_DMA_FLUSH_BOTH 1 167 168 /* Timeout for polling various registers */ 169 #define XILINX_DMA_POLL_TIMEOUT_US 1000000 170 /* Delay between polls (avoid a delay of 0 to prevent CPU stalls) */ 171 #define XILINX_DMA_POLL_DELAY_US 10 172 173 /* AXI DMA Specific Registers/Offsets */ 174 #define XILINX_DMA_REG_SRCDSTADDR 0x18 175 #define XILINX_DMA_REG_BTT 0x28 176 177 /* AXI DMA Specific Masks/Bit fields */ 178 #define XILINX_DMA_MAX_TRANS_LEN_MIN 8 179 #define XILINX_DMA_MAX_TRANS_LEN_MAX 23 180 #define XILINX_DMA_V2_MAX_TRANS_LEN_MAX 26 181 #define XILINX_DMA_CR_COALESCE_MAX GENMASK(23, 16) 182 #define XILINX_DMA_CR_DELAY_MAX GENMASK(31, 24) 183 #define XILINX_DMA_CR_CYCLIC_BD_EN_MASK BIT(4) 184 #define XILINX_DMA_CR_COALESCE_SHIFT 16 185 #define XILINX_DMA_CR_DELAY_SHIFT 24 186 #define XILINX_DMA_BD_SOP BIT(27) 187 #define XILINX_DMA_BD_EOP BIT(26) 188 #define XILINX_DMA_BD_COMP_MASK BIT(31) 189 #define XILINX_DMA_COALESCE_MAX 255 190 #define XILINX_DMA_NUM_DESCS 512 191 #define XILINX_DMA_NUM_APP_WORDS 5 192 193 /* AXI CDMA Specific Registers/Offsets */ 194 #define XILINX_CDMA_REG_SRCADDR 0x18 195 #define XILINX_CDMA_REG_DSTADDR 0x20 196 197 /* AXI CDMA Specific Masks */ 198 #define XILINX_CDMA_CR_SGMODE BIT(3) 199 200 #define xilinx_prep_dma_addr_t(addr) \ 201 ((dma_addr_t)((u64)addr##_##msb << 32 | (addr))) 202 203 /* AXI MCDMA Specific Registers/Offsets */ 204 #define XILINX_MCDMA_MM2S_CTRL_OFFSET 0x0000 205 #define XILINX_MCDMA_S2MM_CTRL_OFFSET 0x0500 206 #define XILINX_MCDMA_CHEN_OFFSET 0x0008 207 #define XILINX_MCDMA_CH_ERR_OFFSET 0x0010 208 #define XILINX_MCDMA_RXINT_SER_OFFSET 0x0020 209 #define XILINX_MCDMA_TXINT_SER_OFFSET 0x0028 210 #define XILINX_MCDMA_CHAN_CR_OFFSET(x) (0x40 + (x) * 0x40) 211 #define XILINX_MCDMA_CHAN_SR_OFFSET(x) (0x44 + (x) * 0x40) 212 #define XILINX_MCDMA_CHAN_CDESC_OFFSET(x) (0x48 + (x) * 0x40) 213 #define XILINX_MCDMA_CHAN_TDESC_OFFSET(x) (0x50 + (x) * 0x40) 214 215 /* AXI MCDMA Specific Masks/Shifts */ 216 #define XILINX_MCDMA_COALESCE_SHIFT 16 217 #define XILINX_MCDMA_COALESCE_MAX 24 218 #define XILINX_MCDMA_IRQ_ALL_MASK GENMASK(7, 5) 219 #define XILINX_MCDMA_COALESCE_MASK GENMASK(23, 16) 220 #define XILINX_MCDMA_CR_RUNSTOP_MASK BIT(0) 221 #define XILINX_MCDMA_IRQ_IOC_MASK BIT(5) 222 #define XILINX_MCDMA_IRQ_DELAY_MASK BIT(6) 223 #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) 224 #define XILINX_MCDMA_BD_EOP BIT(30) 225 #define XILINX_MCDMA_BD_SOP BIT(31) 226 227 /** 228 * struct xilinx_vdma_desc_hw - Hardware Descriptor 229 * @next_desc: Next Descriptor Pointer @0x00 230 * @pad1: Reserved @0x04 231 * @buf_addr: Buffer address @0x08 232 * @buf_addr_msb: MSB of Buffer address @0x0C 233 * @vsize: Vertical Size @0x10 234 * @hsize: Horizontal Size @0x14 235 * @stride: Number of bytes between the first 236 * pixels of each horizontal line @0x18 237 */ 238 struct xilinx_vdma_desc_hw { 239 u32 next_desc; 240 u32 pad1; 241 u32 buf_addr; 242 u32 buf_addr_msb; 243 u32 vsize; 244 u32 hsize; 245 u32 stride; 246 } __aligned(64); 247 248 /** 249 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA 250 * @next_desc: Next Descriptor Pointer @0x00 251 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 252 * @buf_addr: Buffer address @0x08 253 * @buf_addr_msb: MSB of Buffer address @0x0C 254 * @reserved1: Reserved @0x10 255 * @reserved2: Reserved @0x14 256 * @control: Control field @0x18 257 * @status: Status field @0x1C 258 * @app: APP Fields @0x20 - 0x30 259 */ 260 struct xilinx_axidma_desc_hw { 261 u32 next_desc; 262 u32 next_desc_msb; 263 u32 buf_addr; 264 u32 buf_addr_msb; 265 u32 reserved1; 266 u32 reserved2; 267 u32 control; 268 u32 status; 269 u32 app[XILINX_DMA_NUM_APP_WORDS]; 270 } __aligned(64); 271 272 /** 273 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA 274 * @next_desc: Next Descriptor Pointer @0x00 275 * @next_desc_msb: MSB of Next Descriptor Pointer @0x04 276 * @buf_addr: Buffer address @0x08 277 * @buf_addr_msb: MSB of Buffer address @0x0C 278 * @rsvd: Reserved field @0x10 279 * @control: Control Information field @0x14 280 * @status: Status field @0x18 281 * @sideband_status: Status of sideband signals @0x1C 282 * @app: APP Fields @0x20 - 0x30 283 */ 284 struct xilinx_aximcdma_desc_hw { 285 u32 next_desc; 286 u32 next_desc_msb; 287 u32 buf_addr; 288 u32 buf_addr_msb; 289 u32 rsvd; 290 u32 control; 291 u32 status; 292 u32 sideband_status; 293 u32 app[XILINX_DMA_NUM_APP_WORDS]; 294 } __aligned(64); 295 296 /** 297 * struct xilinx_cdma_desc_hw - Hardware Descriptor 298 * @next_desc: Next Descriptor Pointer @0x00 299 * @next_desc_msb: Next Descriptor Pointer MSB @0x04 300 * @src_addr: Source address @0x08 301 * @src_addr_msb: Source address MSB @0x0C 302 * @dest_addr: Destination address @0x10 303 * @dest_addr_msb: Destination address MSB @0x14 304 * @control: Control field @0x18 305 * @status: Status field @0x1C 306 */ 307 struct xilinx_cdma_desc_hw { 308 u32 next_desc; 309 u32 next_desc_msb; 310 u32 src_addr; 311 u32 src_addr_msb; 312 u32 dest_addr; 313 u32 dest_addr_msb; 314 u32 control; 315 u32 status; 316 } __aligned(64); 317 318 /** 319 * struct xilinx_vdma_tx_segment - Descriptor segment 320 * @hw: Hardware descriptor 321 * @node: Node in the descriptor segments list 322 * @phys: Physical address of segment 323 */ 324 struct xilinx_vdma_tx_segment { 325 struct xilinx_vdma_desc_hw hw; 326 struct list_head node; 327 dma_addr_t phys; 328 } __aligned(64); 329 330 /** 331 * struct xilinx_axidma_tx_segment - Descriptor segment 332 * @hw: Hardware descriptor 333 * @node: Node in the descriptor segments list 334 * @phys: Physical address of segment 335 */ 336 struct xilinx_axidma_tx_segment { 337 struct xilinx_axidma_desc_hw hw; 338 struct list_head node; 339 dma_addr_t phys; 340 } __aligned(64); 341 342 /** 343 * struct xilinx_aximcdma_tx_segment - Descriptor segment 344 * @hw: Hardware descriptor 345 * @node: Node in the descriptor segments list 346 * @phys: Physical address of segment 347 */ 348 struct xilinx_aximcdma_tx_segment { 349 struct xilinx_aximcdma_desc_hw hw; 350 struct list_head node; 351 dma_addr_t phys; 352 } __aligned(64); 353 354 /** 355 * struct xilinx_cdma_tx_segment - Descriptor segment 356 * @hw: Hardware descriptor 357 * @node: Node in the descriptor segments list 358 * @phys: Physical address of segment 359 */ 360 struct xilinx_cdma_tx_segment { 361 struct xilinx_cdma_desc_hw hw; 362 struct list_head node; 363 dma_addr_t phys; 364 } __aligned(64); 365 366 /** 367 * struct xilinx_dma_tx_descriptor - Per Transaction structure 368 * @async_tx: Async transaction descriptor 369 * @segments: TX segments list 370 * @node: Node in the channel descriptors list 371 * @cyclic: Check for cyclic transfers. 372 * @err: Whether the descriptor has an error. 373 * @residue: Residue of the completed descriptor 374 */ 375 struct xilinx_dma_tx_descriptor { 376 struct dma_async_tx_descriptor async_tx; 377 struct list_head segments; 378 struct list_head node; 379 bool cyclic; 380 bool err; 381 u32 residue; 382 }; 383 384 /** 385 * struct xilinx_dma_chan - Driver specific DMA channel structure 386 * @xdev: Driver specific device structure 387 * @ctrl_offset: Control registers offset 388 * @desc_offset: TX descriptor registers offset 389 * @lock: Descriptor operation lock 390 * @pending_list: Descriptors waiting 391 * @active_list: Descriptors ready to submit 392 * @done_list: Complete descriptors 393 * @free_seg_list: Free descriptors 394 * @common: DMA common channel 395 * @desc_pool: Descriptors pool 396 * @dev: The dma device 397 * @irq: Channel IRQ 398 * @id: Channel ID 399 * @direction: Transfer direction 400 * @num_frms: Number of frames 401 * @has_sg: Support scatter transfers 402 * @cyclic: Check for cyclic transfers. 403 * @genlock: Support genlock mode 404 * @err: Channel has errors 405 * @idle: Check for channel idle 406 * @terminating: Check for channel being synchronized by user 407 * @tasklet: Cleanup work after irq 408 * @config: Device configuration info 409 * @flush_on_fsync: Flush on Frame sync 410 * @desc_pendingcount: Descriptor pending count 411 * @ext_addr: Indicates 64 bit addressing is supported by dma channel 412 * @desc_submitcount: Descriptor h/w submitted count 413 * @seg_v: Statically allocated segments base 414 * @seg_mv: Statically allocated segments base for MCDMA 415 * @seg_p: Physical allocated segments base 416 * @cyclic_seg_v: Statically allocated segment base for cyclic transfers 417 * @cyclic_seg_p: Physical allocated segments base for cyclic dma 418 * @start_transfer: Differentiate b/w DMA IP's transfer 419 * @stop_transfer: Differentiate b/w DMA IP's quiesce 420 * @tdest: TDEST value for mcdma 421 * @has_vflip: S2MM vertical flip 422 * @irq_delay: Interrupt delay timeout 423 */ 424 struct xilinx_dma_chan { 425 struct xilinx_dma_device *xdev; 426 u32 ctrl_offset; 427 u32 desc_offset; 428 spinlock_t lock; 429 struct list_head pending_list; 430 struct list_head active_list; 431 struct list_head done_list; 432 struct list_head free_seg_list; 433 struct dma_chan common; 434 struct dma_pool *desc_pool; 435 struct device *dev; 436 int irq; 437 int id; 438 enum dma_transfer_direction direction; 439 int num_frms; 440 bool has_sg; 441 bool cyclic; 442 bool genlock; 443 bool err; 444 bool idle; 445 bool terminating; 446 struct tasklet_struct tasklet; 447 struct xilinx_vdma_config config; 448 bool flush_on_fsync; 449 u32 desc_pendingcount; 450 bool ext_addr; 451 u32 desc_submitcount; 452 struct xilinx_axidma_tx_segment *seg_v; 453 struct xilinx_aximcdma_tx_segment *seg_mv; 454 dma_addr_t seg_p; 455 struct xilinx_axidma_tx_segment *cyclic_seg_v; 456 dma_addr_t cyclic_seg_p; 457 void (*start_transfer)(struct xilinx_dma_chan *chan); 458 int (*stop_transfer)(struct xilinx_dma_chan *chan); 459 u16 tdest; 460 bool has_vflip; 461 u8 irq_delay; 462 }; 463 464 /** 465 * enum xdma_ip_type - DMA IP type. 466 * 467 * @XDMA_TYPE_AXIDMA: Axi dma ip. 468 * @XDMA_TYPE_CDMA: Axi cdma ip. 469 * @XDMA_TYPE_VDMA: Axi vdma ip. 470 * @XDMA_TYPE_AXIMCDMA: Axi MCDMA ip. 471 * 472 */ 473 enum xdma_ip_type { 474 XDMA_TYPE_AXIDMA = 0, 475 XDMA_TYPE_CDMA, 476 XDMA_TYPE_VDMA, 477 XDMA_TYPE_AXIMCDMA 478 }; 479 480 struct xilinx_dma_config { 481 enum xdma_ip_type dmatype; 482 int (*clk_init)(struct platform_device *pdev, struct clk **axi_clk, 483 struct clk **tx_clk, struct clk **txs_clk, 484 struct clk **rx_clk, struct clk **rxs_clk); 485 irqreturn_t (*irq_handler)(int irq, void *data); 486 const int max_channels; 487 }; 488 489 /** 490 * struct xilinx_dma_device - DMA device structure 491 * @regs: I/O mapped base address 492 * @dev: Device Structure 493 * @common: DMA device structure 494 * @chan: Driver specific DMA channel 495 * @flush_on_fsync: Flush on frame sync 496 * @ext_addr: Indicates 64 bit addressing is supported by dma device 497 * @pdev: Platform device structure pointer 498 * @dma_config: DMA config structure 499 * @axi_clk: DMA Axi4-lite interace clock 500 * @tx_clk: DMA mm2s clock 501 * @txs_clk: DMA mm2s stream clock 502 * @rx_clk: DMA s2mm clock 503 * @rxs_clk: DMA s2mm stream clock 504 * @s2mm_chan_id: DMA s2mm channel identifier 505 * @mm2s_chan_id: DMA mm2s channel identifier 506 * @max_buffer_len: Max buffer length 507 * @has_axistream_connected: AXI DMA connected to AXI Stream IP 508 */ 509 struct xilinx_dma_device { 510 void __iomem *regs; 511 struct device *dev; 512 struct dma_device common; 513 struct xilinx_dma_chan *chan[XILINX_MCDMA_MAX_CHANS_PER_DEVICE]; 514 u32 flush_on_fsync; 515 bool ext_addr; 516 struct platform_device *pdev; 517 const struct xilinx_dma_config *dma_config; 518 struct clk *axi_clk; 519 struct clk *tx_clk; 520 struct clk *txs_clk; 521 struct clk *rx_clk; 522 struct clk *rxs_clk; 523 u32 s2mm_chan_id; 524 u32 mm2s_chan_id; 525 u32 max_buffer_len; 526 bool has_axistream_connected; 527 }; 528 529 /* Macros */ 530 #define to_xilinx_chan(chan) \ 531 container_of(chan, struct xilinx_dma_chan, common) 532 #define to_dma_tx_descriptor(tx) \ 533 container_of(tx, struct xilinx_dma_tx_descriptor, async_tx) 534 #define xilinx_dma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \ 535 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \ 536 val, cond, delay_us, timeout_us) 537 538 /* IO accessors */ 539 static inline u32 dma_read(struct xilinx_dma_chan *chan, u32 reg) 540 { 541 return ioread32(chan->xdev->regs + reg); 542 } 543 544 static inline void dma_write(struct xilinx_dma_chan *chan, u32 reg, u32 value) 545 { 546 iowrite32(value, chan->xdev->regs + reg); 547 } 548 549 static inline void vdma_desc_write(struct xilinx_dma_chan *chan, u32 reg, 550 u32 value) 551 { 552 dma_write(chan, chan->desc_offset + reg, value); 553 } 554 555 static inline u32 dma_ctrl_read(struct xilinx_dma_chan *chan, u32 reg) 556 { 557 return dma_read(chan, chan->ctrl_offset + reg); 558 } 559 560 static inline void dma_ctrl_write(struct xilinx_dma_chan *chan, u32 reg, 561 u32 value) 562 { 563 dma_write(chan, chan->ctrl_offset + reg, value); 564 } 565 566 static inline void dma_ctrl_clr(struct xilinx_dma_chan *chan, u32 reg, 567 u32 clr) 568 { 569 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) & ~clr); 570 } 571 572 static inline void dma_ctrl_set(struct xilinx_dma_chan *chan, u32 reg, 573 u32 set) 574 { 575 dma_ctrl_write(chan, reg, dma_ctrl_read(chan, reg) | set); 576 } 577 578 /** 579 * vdma_desc_write_64 - 64-bit descriptor write 580 * @chan: Driver specific VDMA channel 581 * @reg: Register to write 582 * @value_lsb: lower address of the descriptor. 583 * @value_msb: upper address of the descriptor. 584 * 585 * Since vdma driver is trying to write to a register offset which is not a 586 * multiple of 64 bits(ex : 0x5c), we are writing as two separate 32 bits 587 * instead of a single 64 bit register write. 588 */ 589 static inline void vdma_desc_write_64(struct xilinx_dma_chan *chan, u32 reg, 590 u32 value_lsb, u32 value_msb) 591 { 592 /* Write the lsb 32 bits*/ 593 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); 594 595 /* Write the msb 32 bits */ 596 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); 597 } 598 599 static inline void dma_writeq(struct xilinx_dma_chan *chan, u32 reg, u64 value) 600 { 601 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); 602 } 603 604 static inline void xilinx_write(struct xilinx_dma_chan *chan, u32 reg, 605 dma_addr_t addr) 606 { 607 if (chan->ext_addr) 608 dma_writeq(chan, reg, addr); 609 else 610 dma_ctrl_write(chan, reg, addr); 611 } 612 613 static inline void xilinx_axidma_buf(struct xilinx_dma_chan *chan, 614 struct xilinx_axidma_desc_hw *hw, 615 dma_addr_t buf_addr, size_t sg_used, 616 size_t period_len) 617 { 618 if (chan->ext_addr) { 619 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len); 620 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used + 621 period_len); 622 } else { 623 hw->buf_addr = buf_addr + sg_used + period_len; 624 } 625 } 626 627 static inline void xilinx_aximcdma_buf(struct xilinx_dma_chan *chan, 628 struct xilinx_aximcdma_desc_hw *hw, 629 dma_addr_t buf_addr, size_t sg_used) 630 { 631 if (chan->ext_addr) { 632 hw->buf_addr = lower_32_bits(buf_addr + sg_used); 633 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used); 634 } else { 635 hw->buf_addr = buf_addr + sg_used; 636 } 637 } 638 639 /** 640 * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload length 641 * @tx: async transaction descriptor 642 * @payload_len: metadata payload length 643 * @max_len: metadata max length 644 * Return: The app field pointer. 645 */ 646 static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *tx, 647 size_t *payload_len, size_t *max_len) 648 { 649 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 650 struct xilinx_axidma_tx_segment *seg; 651 652 *max_len = *payload_len = sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; 653 seg = list_first_entry(&desc->segments, 654 struct xilinx_axidma_tx_segment, node); 655 return seg->hw.app; 656 } 657 658 static const struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops = { 659 .get_ptr = xilinx_dma_get_metadata_ptr, 660 }; 661 662 /* ----------------------------------------------------------------------------- 663 * Descriptors and segments alloc and free 664 */ 665 666 /** 667 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment 668 * @chan: Driver specific DMA channel 669 * 670 * Return: The allocated segment on success and NULL on failure. 671 */ 672 static struct xilinx_vdma_tx_segment * 673 xilinx_vdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 674 { 675 struct xilinx_vdma_tx_segment *segment; 676 dma_addr_t phys; 677 678 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 679 if (!segment) 680 return NULL; 681 682 segment->phys = phys; 683 684 return segment; 685 } 686 687 /** 688 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment 689 * @chan: Driver specific DMA channel 690 * 691 * Return: The allocated segment on success and NULL on failure. 692 */ 693 static struct xilinx_cdma_tx_segment * 694 xilinx_cdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 695 { 696 struct xilinx_cdma_tx_segment *segment; 697 dma_addr_t phys; 698 699 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); 700 if (!segment) 701 return NULL; 702 703 segment->phys = phys; 704 705 return segment; 706 } 707 708 /** 709 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment 710 * @chan: Driver specific DMA channel 711 * 712 * Return: The allocated segment on success and NULL on failure. 713 */ 714 static struct xilinx_axidma_tx_segment * 715 xilinx_axidma_alloc_tx_segment(struct xilinx_dma_chan *chan) 716 { 717 struct xilinx_axidma_tx_segment *segment = NULL; 718 unsigned long flags; 719 720 spin_lock_irqsave(&chan->lock, flags); 721 if (!list_empty(&chan->free_seg_list)) { 722 segment = list_first_entry(&chan->free_seg_list, 723 struct xilinx_axidma_tx_segment, 724 node); 725 list_del(&segment->node); 726 } 727 spin_unlock_irqrestore(&chan->lock, flags); 728 729 if (!segment) 730 dev_dbg(chan->dev, "Could not find free tx segment\n"); 731 732 return segment; 733 } 734 735 /** 736 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment 737 * @chan: Driver specific DMA channel 738 * 739 * Return: The allocated segment on success and NULL on failure. 740 */ 741 static struct xilinx_aximcdma_tx_segment * 742 xilinx_aximcdma_alloc_tx_segment(struct xilinx_dma_chan *chan) 743 { 744 struct xilinx_aximcdma_tx_segment *segment = NULL; 745 unsigned long flags; 746 747 spin_lock_irqsave(&chan->lock, flags); 748 if (!list_empty(&chan->free_seg_list)) { 749 segment = list_first_entry(&chan->free_seg_list, 750 struct xilinx_aximcdma_tx_segment, 751 node); 752 list_del(&segment->node); 753 } 754 spin_unlock_irqrestore(&chan->lock, flags); 755 756 return segment; 757 } 758 759 static void xilinx_dma_clean_hw_desc(struct xilinx_dma_chan *chan, 760 struct xilinx_axidma_tx_segment *segment) 761 { 762 dma_addr_t next; 763 u32 i; 764 765 /* 766 * Restore the buffer descriptor's next descriptor pointer to the value 767 * set up in xilinx_dma_alloc_chan_resources(). Otherwise using the DMA 768 * in cyclic mode leaves the next descriptor pointer altered and 769 * prevents subsequent non-cyclic transfers. 770 */ 771 i = segment - chan->seg_v; 772 next = chan->seg_p + 773 sizeof(*chan->seg_v) * ((i + 1) % XILINX_DMA_NUM_DESCS); 774 775 memset(&segment->hw, 0, sizeof(segment->hw)); 776 segment->hw.next_desc = lower_32_bits(next); 777 segment->hw.next_desc_msb = upper_32_bits(next); 778 } 779 780 static void xilinx_mcdma_clean_hw_desc(struct xilinx_aximcdma_desc_hw *hw) 781 { 782 u32 next_desc = hw->next_desc; 783 u32 next_desc_msb = hw->next_desc_msb; 784 785 memset(hw, 0, sizeof(struct xilinx_aximcdma_desc_hw)); 786 787 hw->next_desc = next_desc; 788 hw->next_desc_msb = next_desc_msb; 789 } 790 791 /** 792 * xilinx_dma_free_tx_segment - Free transaction segment 793 * @chan: Driver specific DMA channel 794 * @segment: DMA transaction segment 795 */ 796 static void xilinx_dma_free_tx_segment(struct xilinx_dma_chan *chan, 797 struct xilinx_axidma_tx_segment *segment) 798 { 799 xilinx_dma_clean_hw_desc(chan, segment); 800 801 list_add_tail(&segment->node, &chan->free_seg_list); 802 } 803 804 /** 805 * xilinx_mcdma_free_tx_segment - Free transaction segment 806 * @chan: Driver specific DMA channel 807 * @segment: DMA transaction segment 808 */ 809 static void xilinx_mcdma_free_tx_segment(struct xilinx_dma_chan *chan, 810 struct xilinx_aximcdma_tx_segment * 811 segment) 812 { 813 xilinx_mcdma_clean_hw_desc(&segment->hw); 814 815 list_add_tail(&segment->node, &chan->free_seg_list); 816 } 817 818 /** 819 * xilinx_cdma_free_tx_segment - Free transaction segment 820 * @chan: Driver specific DMA channel 821 * @segment: DMA transaction segment 822 */ 823 static void xilinx_cdma_free_tx_segment(struct xilinx_dma_chan *chan, 824 struct xilinx_cdma_tx_segment *segment) 825 { 826 dma_pool_free(chan->desc_pool, segment, segment->phys); 827 } 828 829 /** 830 * xilinx_vdma_free_tx_segment - Free transaction segment 831 * @chan: Driver specific DMA channel 832 * @segment: DMA transaction segment 833 */ 834 static void xilinx_vdma_free_tx_segment(struct xilinx_dma_chan *chan, 835 struct xilinx_vdma_tx_segment *segment) 836 { 837 dma_pool_free(chan->desc_pool, segment, segment->phys); 838 } 839 840 /** 841 * xilinx_dma_alloc_tx_descriptor - Allocate transaction descriptor 842 * @chan: Driver specific DMA channel 843 * 844 * Return: The allocated descriptor on success and NULL on failure. 845 */ 846 static struct xilinx_dma_tx_descriptor * 847 xilinx_dma_alloc_tx_descriptor(struct xilinx_dma_chan *chan) 848 { 849 struct xilinx_dma_tx_descriptor *desc; 850 851 desc = kzalloc_obj(*desc, GFP_NOWAIT); 852 if (!desc) 853 return NULL; 854 855 INIT_LIST_HEAD(&desc->segments); 856 857 return desc; 858 } 859 860 /** 861 * xilinx_dma_free_tx_descriptor - Free transaction descriptor 862 * @chan: Driver specific DMA channel 863 * @desc: DMA transaction descriptor 864 */ 865 static void 866 xilinx_dma_free_tx_descriptor(struct xilinx_dma_chan *chan, 867 struct xilinx_dma_tx_descriptor *desc) 868 { 869 struct xilinx_vdma_tx_segment *segment, *next; 870 struct xilinx_cdma_tx_segment *cdma_segment, *cdma_next; 871 struct xilinx_axidma_tx_segment *axidma_segment, *axidma_next; 872 struct xilinx_aximcdma_tx_segment *aximcdma_segment, *aximcdma_next; 873 874 if (!desc) 875 return; 876 877 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 878 list_for_each_entry_safe(segment, next, &desc->segments, node) { 879 list_del(&segment->node); 880 xilinx_vdma_free_tx_segment(chan, segment); 881 } 882 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 883 list_for_each_entry_safe(cdma_segment, cdma_next, 884 &desc->segments, node) { 885 list_del(&cdma_segment->node); 886 xilinx_cdma_free_tx_segment(chan, cdma_segment); 887 } 888 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 889 list_for_each_entry_safe(axidma_segment, axidma_next, 890 &desc->segments, node) { 891 list_del(&axidma_segment->node); 892 xilinx_dma_free_tx_segment(chan, axidma_segment); 893 } 894 } else { 895 list_for_each_entry_safe(aximcdma_segment, aximcdma_next, 896 &desc->segments, node) { 897 list_del(&aximcdma_segment->node); 898 xilinx_mcdma_free_tx_segment(chan, aximcdma_segment); 899 } 900 } 901 902 kfree(desc); 903 } 904 905 /* Required functions */ 906 907 /** 908 * xilinx_dma_free_desc_list - Free descriptors list 909 * @chan: Driver specific DMA channel 910 * @list: List to parse and delete the descriptor 911 */ 912 static void xilinx_dma_free_desc_list(struct xilinx_dma_chan *chan, 913 struct list_head *list) 914 { 915 struct xilinx_dma_tx_descriptor *desc, *next; 916 917 list_for_each_entry_safe(desc, next, list, node) { 918 list_del(&desc->node); 919 xilinx_dma_free_tx_descriptor(chan, desc); 920 } 921 } 922 923 /** 924 * xilinx_dma_free_descriptors - Free channel descriptors 925 * @chan: Driver specific DMA channel 926 */ 927 static void xilinx_dma_free_descriptors(struct xilinx_dma_chan *chan) 928 { 929 unsigned long flags; 930 931 spin_lock_irqsave(&chan->lock, flags); 932 933 xilinx_dma_free_desc_list(chan, &chan->done_list); 934 xilinx_dma_free_desc_list(chan, &chan->active_list); 935 xilinx_dma_free_desc_list(chan, &chan->pending_list); 936 937 spin_unlock_irqrestore(&chan->lock, flags); 938 } 939 940 /** 941 * xilinx_dma_free_chan_resources - Free channel resources 942 * @dchan: DMA channel 943 */ 944 static void xilinx_dma_free_chan_resources(struct dma_chan *dchan) 945 { 946 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 947 unsigned long flags; 948 949 dev_dbg(chan->dev, "Free all channel resources.\n"); 950 951 xilinx_dma_free_descriptors(chan); 952 953 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 954 spin_lock_irqsave(&chan->lock, flags); 955 INIT_LIST_HEAD(&chan->free_seg_list); 956 spin_unlock_irqrestore(&chan->lock, flags); 957 958 /* Free memory that is allocated for BD */ 959 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 960 XILINX_DMA_NUM_DESCS, chan->seg_v, 961 chan->seg_p); 962 963 /* Free Memory that is allocated for cyclic DMA Mode */ 964 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v), 965 chan->cyclic_seg_v, chan->cyclic_seg_p); 966 } 967 968 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 969 spin_lock_irqsave(&chan->lock, flags); 970 INIT_LIST_HEAD(&chan->free_seg_list); 971 spin_unlock_irqrestore(&chan->lock, flags); 972 973 /* Free memory that is allocated for BD */ 974 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * 975 XILINX_DMA_NUM_DESCS, chan->seg_mv, 976 chan->seg_p); 977 } 978 979 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && 980 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { 981 dma_pool_destroy(chan->desc_pool); 982 chan->desc_pool = NULL; 983 } 984 985 } 986 987 /** 988 * xilinx_dma_get_residue - Compute residue for a given descriptor 989 * @chan: Driver specific dma channel 990 * @desc: dma transaction descriptor 991 * 992 * Return: The number of residue bytes for the descriptor. 993 */ 994 static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, 995 struct xilinx_dma_tx_descriptor *desc) 996 { 997 struct xilinx_cdma_tx_segment *cdma_seg; 998 struct xilinx_axidma_tx_segment *axidma_seg; 999 struct xilinx_aximcdma_tx_segment *aximcdma_seg; 1000 struct xilinx_cdma_desc_hw *cdma_hw; 1001 struct xilinx_axidma_desc_hw *axidma_hw; 1002 struct xilinx_aximcdma_desc_hw *aximcdma_hw; 1003 struct list_head *entry; 1004 u32 residue = 0; 1005 1006 list_for_each(entry, &desc->segments) { 1007 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1008 cdma_seg = list_entry(entry, 1009 struct xilinx_cdma_tx_segment, 1010 node); 1011 cdma_hw = &cdma_seg->hw; 1012 residue += (cdma_hw->control & chan->xdev->max_buffer_len) - 1013 (cdma_hw->status & chan->xdev->max_buffer_len); 1014 } else if (chan->xdev->dma_config->dmatype == 1015 XDMA_TYPE_AXIDMA) { 1016 axidma_seg = list_entry(entry, 1017 struct xilinx_axidma_tx_segment, 1018 node); 1019 axidma_hw = &axidma_seg->hw; 1020 residue += (axidma_hw->control & chan->xdev->max_buffer_len) - 1021 (axidma_hw->status & chan->xdev->max_buffer_len); 1022 } else { 1023 aximcdma_seg = 1024 list_entry(entry, 1025 struct xilinx_aximcdma_tx_segment, 1026 node); 1027 aximcdma_hw = &aximcdma_seg->hw; 1028 residue += 1029 (aximcdma_hw->control & chan->xdev->max_buffer_len) - 1030 (aximcdma_hw->status & chan->xdev->max_buffer_len); 1031 } 1032 } 1033 1034 return residue; 1035 } 1036 1037 static u32 1038 xilinx_dma_get_residue_axidma_direct_s2mm(struct xilinx_dma_chan *chan, 1039 struct xilinx_dma_tx_descriptor *desc) 1040 { 1041 struct xilinx_axidma_tx_segment *seg; 1042 struct xilinx_axidma_desc_hw *hw; 1043 u32 finished_len; 1044 1045 finished_len = dma_ctrl_read(chan, XILINX_DMA_REG_BTT); 1046 1047 seg = list_first_entry(&desc->segments, struct xilinx_axidma_tx_segment, 1048 node); 1049 1050 hw = &seg->hw; 1051 1052 return hw->control - finished_len; 1053 } 1054 1055 /** 1056 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback 1057 * @chan: Driver specific dma channel 1058 * @desc: dma transaction descriptor 1059 * @flags: flags for spin lock 1060 */ 1061 static void xilinx_dma_chan_handle_cyclic(struct xilinx_dma_chan *chan, 1062 struct xilinx_dma_tx_descriptor *desc, 1063 unsigned long *flags) 1064 { 1065 struct dmaengine_desc_callback cb; 1066 1067 dmaengine_desc_get_callback(&desc->async_tx, &cb); 1068 if (dmaengine_desc_callback_valid(&cb)) { 1069 spin_unlock_irqrestore(&chan->lock, *flags); 1070 dmaengine_desc_callback_invoke(&cb, NULL); 1071 spin_lock_irqsave(&chan->lock, *flags); 1072 } 1073 } 1074 1075 /** 1076 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors 1077 * @chan: Driver specific DMA channel 1078 */ 1079 static void xilinx_dma_chan_desc_cleanup(struct xilinx_dma_chan *chan) 1080 { 1081 struct xilinx_dma_tx_descriptor *desc, *next; 1082 unsigned long flags; 1083 1084 spin_lock_irqsave(&chan->lock, flags); 1085 1086 list_for_each_entry_safe(desc, next, &chan->done_list, node) { 1087 struct dmaengine_result result; 1088 1089 if (desc->cyclic) { 1090 xilinx_dma_chan_handle_cyclic(chan, desc, &flags); 1091 break; 1092 } 1093 1094 /* Remove from the list of running transactions */ 1095 list_del(&desc->node); 1096 1097 if (unlikely(desc->err)) { 1098 if (chan->direction == DMA_DEV_TO_MEM) 1099 result.result = DMA_TRANS_READ_FAILED; 1100 else 1101 result.result = DMA_TRANS_WRITE_FAILED; 1102 } else { 1103 result.result = DMA_TRANS_NOERROR; 1104 } 1105 1106 result.residue = desc->residue; 1107 1108 /* Run the link descriptor callback function */ 1109 spin_unlock_irqrestore(&chan->lock, flags); 1110 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result); 1111 spin_lock_irqsave(&chan->lock, flags); 1112 1113 /* Run any dependencies, then free the descriptor */ 1114 dma_run_dependencies(&desc->async_tx); 1115 xilinx_dma_free_tx_descriptor(chan, desc); 1116 1117 /* 1118 * While we ran a callback the user called a terminate function, 1119 * which takes care of cleaning up any remaining descriptors 1120 */ 1121 if (chan->terminating) 1122 break; 1123 } 1124 1125 spin_unlock_irqrestore(&chan->lock, flags); 1126 } 1127 1128 /** 1129 * xilinx_dma_do_tasklet - Schedule completion tasklet 1130 * @t: Pointer to the Xilinx DMA channel structure 1131 */ 1132 static void xilinx_dma_do_tasklet(struct tasklet_struct *t) 1133 { 1134 struct xilinx_dma_chan *chan = from_tasklet(chan, t, tasklet); 1135 1136 xilinx_dma_chan_desc_cleanup(chan); 1137 } 1138 1139 /** 1140 * xilinx_dma_alloc_chan_resources - Allocate channel resources 1141 * @dchan: DMA channel 1142 * 1143 * Return: '0' on success and failure value on error 1144 */ 1145 static int xilinx_dma_alloc_chan_resources(struct dma_chan *dchan) 1146 { 1147 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1148 int i; 1149 1150 /* Has this channel already been allocated? */ 1151 if (chan->desc_pool) 1152 return 0; 1153 1154 /* 1155 * We need the descriptor to be aligned to 64bytes 1156 * for meeting Xilinx VDMA specification requirement. 1157 */ 1158 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1159 /* Allocate the buffer descriptors. */ 1160 chan->seg_v = dma_alloc_coherent(chan->dev, 1161 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, 1162 &chan->seg_p, GFP_KERNEL); 1163 if (!chan->seg_v) { 1164 dev_err(chan->dev, 1165 "unable to allocate channel %d descriptors\n", 1166 chan->id); 1167 return -ENOMEM; 1168 } 1169 /* 1170 * For cyclic DMA mode we need to program the tail Descriptor 1171 * register with a value which is not a part of the BD chain 1172 * so allocating a desc segment during channel allocation for 1173 * programming tail descriptor. 1174 */ 1175 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev, 1176 sizeof(*chan->cyclic_seg_v), 1177 &chan->cyclic_seg_p, 1178 GFP_KERNEL); 1179 if (!chan->cyclic_seg_v) { 1180 dev_err(chan->dev, 1181 "unable to allocate desc segment for cyclic DMA\n"); 1182 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * 1183 XILINX_DMA_NUM_DESCS, chan->seg_v, 1184 chan->seg_p); 1185 return -ENOMEM; 1186 } 1187 chan->cyclic_seg_v->phys = chan->cyclic_seg_p; 1188 1189 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1190 chan->seg_v[i].hw.next_desc = 1191 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1192 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1193 chan->seg_v[i].hw.next_desc_msb = 1194 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * 1195 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1196 chan->seg_v[i].phys = chan->seg_p + 1197 sizeof(*chan->seg_v) * i; 1198 list_add_tail(&chan->seg_v[i].node, 1199 &chan->free_seg_list); 1200 } 1201 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 1202 /* Allocate the buffer descriptors. */ 1203 chan->seg_mv = dma_alloc_coherent(chan->dev, 1204 sizeof(*chan->seg_mv) * 1205 XILINX_DMA_NUM_DESCS, 1206 &chan->seg_p, GFP_KERNEL); 1207 if (!chan->seg_mv) { 1208 dev_err(chan->dev, 1209 "unable to allocate channel %d descriptors\n", 1210 chan->id); 1211 return -ENOMEM; 1212 } 1213 for (i = 0; i < XILINX_DMA_NUM_DESCS; i++) { 1214 chan->seg_mv[i].hw.next_desc = 1215 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1216 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1217 chan->seg_mv[i].hw.next_desc_msb = 1218 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * 1219 ((i + 1) % XILINX_DMA_NUM_DESCS)); 1220 chan->seg_mv[i].phys = chan->seg_p + 1221 sizeof(*chan->seg_mv) * i; 1222 list_add_tail(&chan->seg_mv[i].node, 1223 &chan->free_seg_list); 1224 } 1225 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 1226 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", 1227 chan->dev, 1228 sizeof(struct xilinx_cdma_tx_segment), 1229 __alignof__(struct xilinx_cdma_tx_segment), 1230 0); 1231 } else { 1232 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", 1233 chan->dev, 1234 sizeof(struct xilinx_vdma_tx_segment), 1235 __alignof__(struct xilinx_vdma_tx_segment), 1236 0); 1237 } 1238 1239 if (!chan->desc_pool && 1240 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && 1241 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { 1242 dev_err(chan->dev, 1243 "unable to allocate channel %d descriptor pool\n", 1244 chan->id); 1245 return -ENOMEM; 1246 } 1247 1248 dma_cookie_init(dchan); 1249 1250 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 1251 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1252 XILINX_CDMA_CR_SGMODE); 1253 1254 return 0; 1255 } 1256 1257 /** 1258 * xilinx_dma_calc_copysize - Calculate the amount of data to copy 1259 * @chan: Driver specific DMA channel 1260 * @size: Total data that needs to be copied 1261 * @done: Amount of data that has been already copied 1262 * 1263 * Return: Amount of data that has to be copied 1264 */ 1265 static int xilinx_dma_calc_copysize(struct xilinx_dma_chan *chan, 1266 int size, int done) 1267 { 1268 size_t copy; 1269 1270 copy = min_t(size_t, size - done, 1271 chan->xdev->max_buffer_len); 1272 1273 if ((copy + done < size) && 1274 chan->xdev->common.copy_align) { 1275 /* 1276 * If this is not the last descriptor, make sure 1277 * the next one will be properly aligned 1278 */ 1279 copy = rounddown(copy, 1280 (1 << chan->xdev->common.copy_align)); 1281 } 1282 return copy; 1283 } 1284 1285 /** 1286 * xilinx_dma_tx_status - Get DMA transaction status 1287 * @dchan: DMA channel 1288 * @cookie: Transaction identifier 1289 * @txstate: Transaction state 1290 * 1291 * Return: DMA transaction status 1292 */ 1293 static enum dma_status xilinx_dma_tx_status(struct dma_chan *dchan, 1294 dma_cookie_t cookie, 1295 struct dma_tx_state *txstate) 1296 { 1297 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1298 struct xilinx_dma_tx_descriptor *desc; 1299 enum dma_status ret; 1300 unsigned long flags; 1301 u32 residue = 0; 1302 1303 ret = dma_cookie_status(dchan, cookie, txstate); 1304 if (ret == DMA_COMPLETE || !txstate) 1305 return ret; 1306 1307 spin_lock_irqsave(&chan->lock, flags); 1308 if (!list_empty(&chan->active_list)) { 1309 desc = list_last_entry(&chan->active_list, 1310 struct xilinx_dma_tx_descriptor, node); 1311 /* 1312 * VDMA and simple mode do not support residue reporting, so the 1313 * residue field will always be 0. 1314 */ 1315 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) 1316 residue = xilinx_dma_get_residue(chan, desc); 1317 } 1318 spin_unlock_irqrestore(&chan->lock, flags); 1319 1320 dma_set_residue(txstate, residue); 1321 1322 return ret; 1323 } 1324 1325 /** 1326 * xilinx_dma_stop_transfer - Halt DMA channel 1327 * @chan: Driver specific DMA channel 1328 * 1329 * Return: '0' on success and failure value on error 1330 */ 1331 static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan) 1332 { 1333 u32 val; 1334 1335 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1336 1337 /* Wait for the hardware to halt */ 1338 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1339 val & XILINX_DMA_DMASR_HALTED, 1340 XILINX_DMA_POLL_DELAY_US, 1341 XILINX_DMA_POLL_TIMEOUT_US); 1342 } 1343 1344 /** 1345 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete 1346 * @chan: Driver specific DMA channel 1347 * 1348 * Return: '0' on success and failure value on error 1349 */ 1350 static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan) 1351 { 1352 u32 val; 1353 1354 return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1355 val & XILINX_DMA_DMASR_IDLE, 1356 XILINX_DMA_POLL_DELAY_US, 1357 XILINX_DMA_POLL_TIMEOUT_US); 1358 } 1359 1360 /** 1361 * xilinx_dma_start - Start DMA channel 1362 * @chan: Driver specific DMA channel 1363 */ 1364 static void xilinx_dma_start(struct xilinx_dma_chan *chan) 1365 { 1366 int err; 1367 u32 val; 1368 1369 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RUNSTOP); 1370 1371 /* Wait for the hardware to start */ 1372 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val, 1373 !(val & XILINX_DMA_DMASR_HALTED), 1374 XILINX_DMA_POLL_DELAY_US, 1375 XILINX_DMA_POLL_TIMEOUT_US); 1376 1377 if (err) { 1378 dev_err(chan->dev, "Cannot start channel %p: %x\n", 1379 chan, dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1380 1381 chan->err = true; 1382 } 1383 } 1384 1385 /** 1386 * xilinx_vdma_start_transfer - Starts VDMA transfer 1387 * @chan: Driver specific channel struct pointer 1388 */ 1389 static void xilinx_vdma_start_transfer(struct xilinx_dma_chan *chan) 1390 { 1391 struct xilinx_vdma_config *config = &chan->config; 1392 struct xilinx_dma_tx_descriptor *desc; 1393 u32 reg, j; 1394 struct xilinx_vdma_tx_segment *segment, *last = NULL; 1395 int i = 0; 1396 1397 /* This function was invoked with lock held */ 1398 if (chan->err) 1399 return; 1400 1401 if (!chan->idle) 1402 return; 1403 1404 if (list_empty(&chan->pending_list)) 1405 return; 1406 1407 desc = list_first_entry(&chan->pending_list, 1408 struct xilinx_dma_tx_descriptor, node); 1409 1410 /* Configure the hardware using info in the config structure */ 1411 if (chan->has_vflip) { 1412 reg = dma_read(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP); 1413 reg &= ~XILINX_VDMA_ENABLE_VERTICAL_FLIP; 1414 reg |= config->vflip_en; 1415 dma_write(chan, XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP, 1416 reg); 1417 } 1418 1419 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1420 1421 if (config->frm_cnt_en) 1422 reg |= XILINX_DMA_DMACR_FRAMECNT_EN; 1423 else 1424 reg &= ~XILINX_DMA_DMACR_FRAMECNT_EN; 1425 1426 /* If not parking, enable circular mode */ 1427 if (config->park) 1428 reg &= ~XILINX_DMA_DMACR_CIRC_EN; 1429 else 1430 reg |= XILINX_DMA_DMACR_CIRC_EN; 1431 1432 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1433 1434 if (config->park) { 1435 j = chan->desc_submitcount; 1436 reg = dma_read(chan, XILINX_DMA_REG_PARK_PTR); 1437 if (chan->direction == DMA_MEM_TO_DEV) { 1438 reg &= ~XILINX_DMA_PARK_PTR_RD_REF_MASK; 1439 reg |= j << XILINX_DMA_PARK_PTR_RD_REF_SHIFT; 1440 } else { 1441 reg &= ~XILINX_DMA_PARK_PTR_WR_REF_MASK; 1442 reg |= j << XILINX_DMA_PARK_PTR_WR_REF_SHIFT; 1443 } 1444 dma_write(chan, XILINX_DMA_REG_PARK_PTR, reg); 1445 } 1446 1447 /* Start the hardware */ 1448 xilinx_dma_start(chan); 1449 1450 if (chan->err) 1451 return; 1452 1453 /* Start the transfer */ 1454 if (chan->desc_submitcount < chan->num_frms) 1455 i = chan->desc_submitcount; 1456 1457 list_for_each_entry(segment, &desc->segments, node) { 1458 if (chan->ext_addr) 1459 vdma_desc_write_64(chan, 1460 XILINX_VDMA_REG_START_ADDRESS_64(i++), 1461 segment->hw.buf_addr, 1462 segment->hw.buf_addr_msb); 1463 else 1464 vdma_desc_write(chan, 1465 XILINX_VDMA_REG_START_ADDRESS(i++), 1466 segment->hw.buf_addr); 1467 1468 last = segment; 1469 } 1470 1471 if (!last) 1472 return; 1473 1474 /* HW expects these parameters to be same for one transaction */ 1475 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); 1476 vdma_desc_write(chan, XILINX_DMA_REG_FRMDLY_STRIDE, 1477 last->hw.stride); 1478 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); 1479 1480 chan->desc_submitcount++; 1481 chan->desc_pendingcount--; 1482 list_move_tail(&desc->node, &chan->active_list); 1483 if (chan->desc_submitcount == chan->num_frms) 1484 chan->desc_submitcount = 0; 1485 1486 chan->idle = false; 1487 } 1488 1489 /** 1490 * xilinx_cdma_start_transfer - Starts cdma transfer 1491 * @chan: Driver specific channel struct pointer 1492 */ 1493 static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan) 1494 { 1495 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1496 struct xilinx_cdma_tx_segment *tail_segment; 1497 u32 ctrl_reg = dma_read(chan, XILINX_DMA_REG_DMACR); 1498 1499 if (chan->err) 1500 return; 1501 1502 if (!chan->idle) 1503 return; 1504 1505 if (list_empty(&chan->pending_list)) 1506 return; 1507 1508 head_desc = list_first_entry(&chan->pending_list, 1509 struct xilinx_dma_tx_descriptor, node); 1510 tail_desc = list_last_entry(&chan->pending_list, 1511 struct xilinx_dma_tx_descriptor, node); 1512 tail_segment = list_last_entry(&tail_desc->segments, 1513 struct xilinx_cdma_tx_segment, node); 1514 1515 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1516 ctrl_reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1517 ctrl_reg |= chan->desc_pendingcount << 1518 XILINX_DMA_CR_COALESCE_SHIFT; 1519 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, ctrl_reg); 1520 } 1521 1522 if (chan->has_sg) { 1523 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 1524 XILINX_CDMA_CR_SGMODE); 1525 1526 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1527 XILINX_CDMA_CR_SGMODE); 1528 1529 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1530 head_desc->async_tx.phys); 1531 1532 /* Update tail ptr register which will start the transfer */ 1533 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1534 tail_segment->phys); 1535 } else { 1536 /* In simple mode */ 1537 struct xilinx_cdma_tx_segment *segment; 1538 struct xilinx_cdma_desc_hw *hw; 1539 1540 segment = list_first_entry(&head_desc->segments, 1541 struct xilinx_cdma_tx_segment, 1542 node); 1543 1544 hw = &segment->hw; 1545 1546 xilinx_write(chan, XILINX_CDMA_REG_SRCADDR, 1547 xilinx_prep_dma_addr_t(hw->src_addr)); 1548 xilinx_write(chan, XILINX_CDMA_REG_DSTADDR, 1549 xilinx_prep_dma_addr_t(hw->dest_addr)); 1550 1551 /* Start the transfer */ 1552 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1553 hw->control & chan->xdev->max_buffer_len); 1554 } 1555 1556 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1557 chan->desc_pendingcount = 0; 1558 chan->idle = false; 1559 } 1560 1561 /** 1562 * xilinx_dma_start_transfer - Starts DMA transfer 1563 * @chan: Driver specific channel struct pointer 1564 */ 1565 static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan) 1566 { 1567 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1568 struct xilinx_axidma_tx_segment *tail_segment; 1569 u32 reg; 1570 1571 if (chan->err) 1572 return; 1573 1574 if (list_empty(&chan->pending_list)) { 1575 if (chan->cyclic) { 1576 struct xilinx_dma_tx_descriptor *desc; 1577 struct list_head *entry; 1578 1579 desc = list_last_entry(&chan->done_list, 1580 struct xilinx_dma_tx_descriptor, node); 1581 list_for_each(entry, &desc->segments) { 1582 struct xilinx_axidma_tx_segment *axidma_seg; 1583 struct xilinx_axidma_desc_hw *axidma_hw; 1584 axidma_seg = list_entry(entry, 1585 struct xilinx_axidma_tx_segment, 1586 node); 1587 axidma_hw = &axidma_seg->hw; 1588 axidma_hw->status = 0; 1589 } 1590 1591 list_splice_tail_init(&chan->done_list, &chan->active_list); 1592 chan->desc_pendingcount = 0; 1593 chan->idle = false; 1594 } 1595 return; 1596 } 1597 1598 /* 1599 * Direct (non-SG) mode has no descriptor queue: writing the BTT 1600 * register launches a transfer immediately, so a new transfer must 1601 * not be programmed while one is in flight. Keep such transfers 1602 * serialized. SG mode supports chaining onto a running transfer via 1603 * tail-pointer extension, so it is allowed to proceed when busy. 1604 */ 1605 if (!chan->has_sg && !chan->idle) 1606 return; 1607 1608 head_desc = list_first_entry(&chan->pending_list, 1609 struct xilinx_dma_tx_descriptor, node); 1610 tail_desc = list_last_entry(&chan->pending_list, 1611 struct xilinx_dma_tx_descriptor, node); 1612 tail_segment = list_last_entry(&tail_desc->segments, 1613 struct xilinx_axidma_tx_segment, node); 1614 1615 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 1616 1617 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { 1618 reg &= ~XILINX_DMA_CR_COALESCE_MAX; 1619 reg |= chan->desc_pendingcount << 1620 XILINX_DMA_CR_COALESCE_SHIFT; 1621 } 1622 1623 if (chan->has_sg && list_empty(&chan->active_list)) 1624 xilinx_write(chan, XILINX_DMA_REG_CURDESC, 1625 head_desc->async_tx.phys); 1626 reg &= ~XILINX_DMA_CR_DELAY_MAX; 1627 reg |= chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; 1628 reg |= XILINX_DMA_DMAXR_ALL_IRQ_MASK; 1629 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 1630 1631 if (chan->idle) 1632 xilinx_dma_start(chan); 1633 1634 if (chan->err) 1635 return; 1636 1637 /* Start the transfer */ 1638 if (chan->has_sg) { 1639 if (chan->cyclic) 1640 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1641 chan->cyclic_seg_v->phys); 1642 else 1643 xilinx_write(chan, XILINX_DMA_REG_TAILDESC, 1644 tail_segment->phys); 1645 } else { 1646 struct xilinx_axidma_tx_segment *segment; 1647 struct xilinx_axidma_desc_hw *hw; 1648 1649 segment = list_first_entry(&head_desc->segments, 1650 struct xilinx_axidma_tx_segment, 1651 node); 1652 hw = &segment->hw; 1653 1654 xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, 1655 xilinx_prep_dma_addr_t(hw->buf_addr)); 1656 1657 /* Start the transfer */ 1658 dma_ctrl_write(chan, XILINX_DMA_REG_BTT, 1659 hw->control & chan->xdev->max_buffer_len); 1660 } 1661 1662 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1663 chan->desc_pendingcount = 0; 1664 chan->idle = false; 1665 } 1666 1667 /** 1668 * xilinx_mcdma_start_transfer - Starts MCDMA transfer 1669 * @chan: Driver specific channel struct pointer 1670 */ 1671 static void xilinx_mcdma_start_transfer(struct xilinx_dma_chan *chan) 1672 { 1673 struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; 1674 struct xilinx_aximcdma_tx_segment *tail_segment; 1675 u32 reg; 1676 1677 /* 1678 * lock has been held by calling functions, so we don't need it 1679 * to take it here again. 1680 */ 1681 1682 if (chan->err) 1683 return; 1684 1685 if (list_empty(&chan->pending_list)) 1686 return; 1687 1688 head_desc = list_first_entry(&chan->pending_list, 1689 struct xilinx_dma_tx_descriptor, node); 1690 tail_desc = list_last_entry(&chan->pending_list, 1691 struct xilinx_dma_tx_descriptor, node); 1692 tail_segment = list_last_entry(&tail_desc->segments, 1693 struct xilinx_aximcdma_tx_segment, node); 1694 1695 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1696 1697 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { 1698 reg &= ~XILINX_MCDMA_COALESCE_MASK; 1699 reg |= chan->desc_pendingcount << 1700 XILINX_MCDMA_COALESCE_SHIFT; 1701 } 1702 1703 reg |= XILINX_MCDMA_IRQ_ALL_MASK; 1704 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1705 1706 /* Program current descriptor */ 1707 if (chan->has_sg && list_empty(&chan->active_list)) 1708 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), 1709 head_desc->async_tx.phys); 1710 1711 /* Program channel enable register */ 1712 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHEN_OFFSET); 1713 reg |= BIT(chan->tdest); 1714 dma_ctrl_write(chan, XILINX_MCDMA_CHEN_OFFSET, reg); 1715 1716 /* Start the fetch of BDs for the channel */ 1717 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); 1718 reg |= XILINX_MCDMA_CR_RUNSTOP_MASK; 1719 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); 1720 1721 if (chan->idle) 1722 xilinx_dma_start(chan); 1723 1724 if (chan->err) 1725 return; 1726 1727 /* Start the transfer */ 1728 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), 1729 tail_segment->phys); 1730 1731 list_splice_tail_init(&chan->pending_list, &chan->active_list); 1732 chan->desc_pendingcount = 0; 1733 chan->idle = false; 1734 } 1735 1736 /** 1737 * xilinx_dma_issue_pending - Issue pending transactions 1738 * @dchan: DMA channel 1739 */ 1740 static void xilinx_dma_issue_pending(struct dma_chan *dchan) 1741 { 1742 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 1743 unsigned long flags; 1744 1745 spin_lock_irqsave(&chan->lock, flags); 1746 chan->start_transfer(chan); 1747 spin_unlock_irqrestore(&chan->lock, flags); 1748 } 1749 1750 /** 1751 * xilinx_dma_device_config - Configure the DMA channel 1752 * @dchan: DMA channel 1753 * @config: channel configuration 1754 * 1755 * Return: 0 always. 1756 */ 1757 static int xilinx_dma_device_config(struct dma_chan *dchan, 1758 struct dma_slave_config *config) 1759 { 1760 return 0; 1761 } 1762 1763 /** 1764 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete 1765 * @chan : xilinx DMA channel 1766 * 1767 * CONTEXT: hardirq 1768 */ 1769 static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) 1770 { 1771 struct xilinx_dma_tx_descriptor *desc, *next; 1772 1773 /* This function was invoked with lock held */ 1774 if (list_empty(&chan->active_list)) 1775 return; 1776 1777 list_for_each_entry_safe(desc, next, &chan->active_list, node) { 1778 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 1779 struct xilinx_axidma_tx_segment *seg; 1780 1781 seg = list_last_entry(&desc->segments, 1782 struct xilinx_axidma_tx_segment, node); 1783 if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) 1784 break; 1785 } 1786 if (chan->has_sg && chan->xdev->dma_config->dmatype != 1787 XDMA_TYPE_VDMA) 1788 desc->residue = xilinx_dma_get_residue(chan, desc); 1789 else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA && 1790 chan->direction == DMA_DEV_TO_MEM && !chan->has_sg) 1791 desc->residue = xilinx_dma_get_residue_axidma_direct_s2mm(chan, desc); 1792 else 1793 desc->residue = 0; 1794 desc->err = chan->err; 1795 1796 list_del(&desc->node); 1797 if (!desc->cyclic) 1798 dma_cookie_complete(&desc->async_tx); 1799 list_add_tail(&desc->node, &chan->done_list); 1800 } 1801 } 1802 1803 /** 1804 * xilinx_dma_reset - Reset DMA channel 1805 * @chan: Driver specific DMA channel 1806 * 1807 * Return: '0' on success and failure value on error 1808 */ 1809 static int xilinx_dma_reset(struct xilinx_dma_chan *chan) 1810 { 1811 int err; 1812 u32 tmp; 1813 1814 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, XILINX_DMA_DMACR_RESET); 1815 1816 /* Wait for the hardware to finish reset */ 1817 err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp, 1818 !(tmp & XILINX_DMA_DMACR_RESET), 1819 XILINX_DMA_POLL_DELAY_US, 1820 XILINX_DMA_POLL_TIMEOUT_US); 1821 1822 if (err) { 1823 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", 1824 dma_ctrl_read(chan, XILINX_DMA_REG_DMACR), 1825 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR)); 1826 return -ETIMEDOUT; 1827 } 1828 1829 chan->err = false; 1830 chan->idle = true; 1831 chan->desc_pendingcount = 0; 1832 chan->desc_submitcount = 0; 1833 1834 return err; 1835 } 1836 1837 /** 1838 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts 1839 * @chan: Driver specific DMA channel 1840 * 1841 * Return: '0' on success and failure value on error 1842 */ 1843 static int xilinx_dma_chan_reset(struct xilinx_dma_chan *chan) 1844 { 1845 int err; 1846 1847 /* Reset VDMA */ 1848 err = xilinx_dma_reset(chan); 1849 if (err) 1850 return err; 1851 1852 /* Enable interrupts */ 1853 dma_ctrl_set(chan, XILINX_DMA_REG_DMACR, 1854 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1855 1856 return 0; 1857 } 1858 1859 /** 1860 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler 1861 * @irq: IRQ number 1862 * @data: Pointer to the Xilinx MCDMA channel structure 1863 * 1864 * Return: IRQ_HANDLED/IRQ_NONE 1865 */ 1866 static irqreturn_t xilinx_mcdma_irq_handler(int irq, void *data) 1867 { 1868 struct xilinx_dma_chan *chan = data; 1869 u32 status, ser_offset, chan_sermask, chan_offset = 0, chan_id; 1870 1871 if (chan->direction == DMA_DEV_TO_MEM) 1872 ser_offset = XILINX_MCDMA_RXINT_SER_OFFSET; 1873 else 1874 ser_offset = XILINX_MCDMA_TXINT_SER_OFFSET; 1875 1876 /* Read the channel id raising the interrupt*/ 1877 chan_sermask = dma_ctrl_read(chan, ser_offset); 1878 chan_id = ffs(chan_sermask); 1879 1880 if (!chan_id) 1881 return IRQ_NONE; 1882 1883 if (chan->direction == DMA_DEV_TO_MEM) 1884 chan_offset = chan->xdev->dma_config->max_channels / 2; 1885 1886 chan_offset = chan_offset + (chan_id - 1); 1887 chan = chan->xdev->chan[chan_offset]; 1888 /* Read the status and ack the interrupts. */ 1889 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); 1890 if (!(status & XILINX_MCDMA_IRQ_ALL_MASK)) 1891 return IRQ_NONE; 1892 1893 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), 1894 status & XILINX_MCDMA_IRQ_ALL_MASK); 1895 1896 if (status & XILINX_MCDMA_IRQ_ERR_MASK) { 1897 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", 1898 chan, 1899 dma_ctrl_read(chan, XILINX_MCDMA_CH_ERR_OFFSET), 1900 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET 1901 (chan->tdest)), 1902 dma_ctrl_read(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET 1903 (chan->tdest))); 1904 chan->err = true; 1905 } 1906 1907 if (status & XILINX_MCDMA_IRQ_DELAY_MASK) { 1908 /* 1909 * Device takes too long to do the transfer when user requires 1910 * responsiveness. 1911 */ 1912 dev_dbg(chan->dev, "Inter-packet latency too long\n"); 1913 } 1914 1915 if (status & XILINX_MCDMA_IRQ_IOC_MASK) { 1916 spin_lock(&chan->lock); 1917 xilinx_dma_complete_descriptor(chan); 1918 if (list_empty(&chan->active_list)) { 1919 chan->idle = true; 1920 chan->start_transfer(chan); 1921 } 1922 spin_unlock(&chan->lock); 1923 } 1924 1925 tasklet_hi_schedule(&chan->tasklet); 1926 return IRQ_HANDLED; 1927 } 1928 1929 /** 1930 * xilinx_dma_irq_handler - DMA Interrupt handler 1931 * @irq: IRQ number 1932 * @data: Pointer to the Xilinx DMA channel structure 1933 * 1934 * Return: IRQ_HANDLED/IRQ_NONE 1935 */ 1936 static irqreturn_t xilinx_dma_irq_handler(int irq, void *data) 1937 { 1938 struct xilinx_dma_chan *chan = data; 1939 u32 status; 1940 1941 /* Read the status and ack the interrupts. */ 1942 status = dma_ctrl_read(chan, XILINX_DMA_REG_DMASR); 1943 if (!(status & XILINX_DMA_DMAXR_ALL_IRQ_MASK)) 1944 return IRQ_NONE; 1945 1946 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 1947 status & XILINX_DMA_DMAXR_ALL_IRQ_MASK); 1948 1949 if (status & XILINX_DMA_DMASR_ERR_IRQ) { 1950 /* 1951 * An error occurred. If C_FLUSH_ON_FSYNC is enabled and the 1952 * error is recoverable, ignore it. Otherwise flag the error. 1953 * 1954 * Only recoverable errors can be cleared in the DMASR register, 1955 * make sure not to write to other error bits to 1. 1956 */ 1957 u32 errors = status & XILINX_DMA_DMASR_ALL_ERR_MASK; 1958 1959 dma_ctrl_write(chan, XILINX_DMA_REG_DMASR, 1960 errors & XILINX_DMA_DMASR_ERR_RECOVER_MASK); 1961 1962 if (!chan->flush_on_fsync || 1963 (errors & ~XILINX_DMA_DMASR_ERR_RECOVER_MASK)) { 1964 dev_err(chan->dev, 1965 "Channel %p has errors %x, cdr %x tdr %x\n", 1966 chan, errors, 1967 dma_ctrl_read(chan, XILINX_DMA_REG_CURDESC), 1968 dma_ctrl_read(chan, XILINX_DMA_REG_TAILDESC)); 1969 chan->err = true; 1970 } 1971 } 1972 1973 if (status & (XILINX_DMA_DMASR_FRM_CNT_IRQ | 1974 XILINX_DMA_DMASR_DLY_CNT_IRQ)) { 1975 spin_lock(&chan->lock); 1976 xilinx_dma_complete_descriptor(chan); 1977 if (list_empty(&chan->active_list)) { 1978 chan->idle = true; 1979 chan->start_transfer(chan); 1980 } 1981 spin_unlock(&chan->lock); 1982 } 1983 1984 tasklet_schedule(&chan->tasklet); 1985 return IRQ_HANDLED; 1986 } 1987 1988 /** 1989 * append_desc_queue - Queuing descriptor 1990 * @chan: Driver specific dma channel 1991 * @desc: dma transaction descriptor 1992 */ 1993 static void append_desc_queue(struct xilinx_dma_chan *chan, 1994 struct xilinx_dma_tx_descriptor *desc) 1995 { 1996 struct xilinx_vdma_tx_segment *tail_segment; 1997 struct xilinx_dma_tx_descriptor *tail_desc; 1998 struct xilinx_axidma_tx_segment *axidma_tail_segment; 1999 struct xilinx_aximcdma_tx_segment *aximcdma_tail_segment; 2000 struct xilinx_cdma_tx_segment *cdma_tail_segment; 2001 2002 if (list_empty(&chan->pending_list)) 2003 goto append; 2004 2005 /* 2006 * Add the hardware descriptor to the chain of hardware descriptors 2007 * that already exists in memory. 2008 */ 2009 tail_desc = list_last_entry(&chan->pending_list, 2010 struct xilinx_dma_tx_descriptor, node); 2011 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 2012 tail_segment = list_last_entry(&tail_desc->segments, 2013 struct xilinx_vdma_tx_segment, 2014 node); 2015 tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2016 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 2017 cdma_tail_segment = list_last_entry(&tail_desc->segments, 2018 struct xilinx_cdma_tx_segment, 2019 node); 2020 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2021 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 2022 axidma_tail_segment = list_last_entry(&tail_desc->segments, 2023 struct xilinx_axidma_tx_segment, 2024 node); 2025 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2026 } else { 2027 aximcdma_tail_segment = 2028 list_last_entry(&tail_desc->segments, 2029 struct xilinx_aximcdma_tx_segment, 2030 node); 2031 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; 2032 } 2033 2034 /* 2035 * Add the software descriptor and all children to the list 2036 * of pending transactions 2037 */ 2038 append: 2039 list_add_tail(&desc->node, &chan->pending_list); 2040 chan->desc_pendingcount++; 2041 2042 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) 2043 && unlikely(chan->desc_pendingcount > chan->num_frms)) { 2044 dev_dbg(chan->dev, "desc pendingcount is too high\n"); 2045 chan->desc_pendingcount = chan->num_frms; 2046 } 2047 } 2048 2049 /** 2050 * xilinx_dma_tx_submit - Submit DMA transaction 2051 * @tx: Async transaction descriptor 2052 * 2053 * Return: cookie value on success and failure value on error 2054 */ 2055 static dma_cookie_t xilinx_dma_tx_submit(struct dma_async_tx_descriptor *tx) 2056 { 2057 struct xilinx_dma_tx_descriptor *desc = to_dma_tx_descriptor(tx); 2058 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); 2059 dma_cookie_t cookie; 2060 unsigned long flags; 2061 int err; 2062 2063 if (chan->cyclic) { 2064 xilinx_dma_free_tx_descriptor(chan, desc); 2065 return -EBUSY; 2066 } 2067 2068 if (chan->err) { 2069 /* 2070 * If reset fails, need to hard reset the system. 2071 * Channel is no longer functional 2072 */ 2073 err = xilinx_dma_chan_reset(chan); 2074 if (err < 0) 2075 return err; 2076 } 2077 2078 spin_lock_irqsave(&chan->lock, flags); 2079 2080 cookie = dma_cookie_assign(tx); 2081 2082 /* Put this transaction onto the tail of the pending queue */ 2083 append_desc_queue(chan, desc); 2084 2085 if (desc->cyclic) 2086 chan->cyclic = true; 2087 2088 chan->terminating = false; 2089 2090 spin_unlock_irqrestore(&chan->lock, flags); 2091 2092 return cookie; 2093 } 2094 2095 /** 2096 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a 2097 * DMA_SLAVE transaction 2098 * @dchan: DMA channel 2099 * @xt: Interleaved template pointer 2100 * @flags: transfer ack flags 2101 * 2102 * Return: Async transaction descriptor on success and NULL on failure 2103 */ 2104 static struct dma_async_tx_descriptor * 2105 xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan, 2106 struct dma_interleaved_template *xt, 2107 unsigned long flags) 2108 { 2109 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2110 struct xilinx_dma_tx_descriptor *desc; 2111 struct xilinx_vdma_tx_segment *segment; 2112 struct xilinx_vdma_desc_hw *hw; 2113 2114 if (!is_slave_direction(xt->dir)) 2115 return NULL; 2116 2117 if (!xt->numf || !xt->sgl[0].size) 2118 return NULL; 2119 2120 if (xt->numf & ~XILINX_DMA_VSIZE_MASK || 2121 xt->sgl[0].size & ~XILINX_DMA_HSIZE_MASK) 2122 return NULL; 2123 2124 if (xt->frame_size != 1) 2125 return NULL; 2126 2127 /* Allocate a transaction descriptor. */ 2128 desc = xilinx_dma_alloc_tx_descriptor(chan); 2129 if (!desc) 2130 return NULL; 2131 2132 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2133 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2134 async_tx_ack(&desc->async_tx); 2135 2136 /* Allocate the link descriptor from DMA pool */ 2137 segment = xilinx_vdma_alloc_tx_segment(chan); 2138 if (!segment) 2139 goto error; 2140 2141 /* Fill in the hardware descriptor */ 2142 hw = &segment->hw; 2143 hw->vsize = xt->numf; 2144 hw->hsize = xt->sgl[0].size; 2145 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << 2146 XILINX_DMA_FRMDLY_STRIDE_STRIDE_SHIFT; 2147 hw->stride |= chan->config.frm_dly << 2148 XILINX_DMA_FRMDLY_STRIDE_FRMDLY_SHIFT; 2149 2150 if (xt->dir != DMA_MEM_TO_DEV) { 2151 if (chan->ext_addr) { 2152 hw->buf_addr = lower_32_bits(xt->dst_start); 2153 hw->buf_addr_msb = upper_32_bits(xt->dst_start); 2154 } else { 2155 hw->buf_addr = xt->dst_start; 2156 } 2157 } else { 2158 if (chan->ext_addr) { 2159 hw->buf_addr = lower_32_bits(xt->src_start); 2160 hw->buf_addr_msb = upper_32_bits(xt->src_start); 2161 } else { 2162 hw->buf_addr = xt->src_start; 2163 } 2164 } 2165 2166 /* Insert the segment into the descriptor segments list. */ 2167 list_add_tail(&segment->node, &desc->segments); 2168 2169 /* Link the last hardware descriptor with the first. */ 2170 segment = list_first_entry(&desc->segments, 2171 struct xilinx_vdma_tx_segment, node); 2172 desc->async_tx.phys = segment->phys; 2173 2174 return &desc->async_tx; 2175 2176 error: 2177 xilinx_dma_free_tx_descriptor(chan, desc); 2178 return NULL; 2179 } 2180 2181 /** 2182 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction 2183 * @dchan: DMA channel 2184 * @dma_dst: destination address 2185 * @dma_src: source address 2186 * @len: transfer length 2187 * @flags: transfer ack flags 2188 * 2189 * Return: Async transaction descriptor on success and NULL on failure 2190 */ 2191 static struct dma_async_tx_descriptor * 2192 xilinx_cdma_prep_memcpy(struct dma_chan *dchan, dma_addr_t dma_dst, 2193 dma_addr_t dma_src, size_t len, unsigned long flags) 2194 { 2195 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2196 struct xilinx_dma_tx_descriptor *desc; 2197 struct xilinx_cdma_tx_segment *segment; 2198 struct xilinx_cdma_desc_hw *hw; 2199 2200 if (!len || len > chan->xdev->max_buffer_len) 2201 return NULL; 2202 2203 desc = xilinx_dma_alloc_tx_descriptor(chan); 2204 if (!desc) 2205 return NULL; 2206 2207 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2208 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2209 2210 /* Allocate the link descriptor from DMA pool */ 2211 segment = xilinx_cdma_alloc_tx_segment(chan); 2212 if (!segment) 2213 goto error; 2214 2215 hw = &segment->hw; 2216 hw->control = len; 2217 hw->src_addr = dma_src; 2218 hw->dest_addr = dma_dst; 2219 if (chan->ext_addr) { 2220 hw->src_addr_msb = upper_32_bits(dma_src); 2221 hw->dest_addr_msb = upper_32_bits(dma_dst); 2222 } 2223 2224 /* Insert the segment into the descriptor segments list. */ 2225 list_add_tail(&segment->node, &desc->segments); 2226 2227 desc->async_tx.phys = segment->phys; 2228 hw->next_desc = segment->phys; 2229 2230 return &desc->async_tx; 2231 2232 error: 2233 xilinx_dma_free_tx_descriptor(chan, desc); 2234 return NULL; 2235 } 2236 2237 /** 2238 * xilinx_dma_prep_peripheral_dma_vec - prepare descriptors for a DMA_SLAVE 2239 * transaction from DMA vectors 2240 * @dchan: DMA channel 2241 * @vecs: Array of DMA vectors that should be transferred 2242 * @nb: number of entries in @vecs 2243 * @direction: DMA direction 2244 * @flags: transfer ack flags 2245 * 2246 * Return: Async transaction descriptor on success and NULL on failure 2247 */ 2248 static struct dma_async_tx_descriptor *xilinx_dma_prep_peripheral_dma_vec( 2249 struct dma_chan *dchan, const struct dma_vec *vecs, size_t nb, 2250 enum dma_transfer_direction direction, unsigned long flags) 2251 { 2252 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2253 struct xilinx_dma_tx_descriptor *desc; 2254 struct xilinx_axidma_tx_segment *segment, *head, *prev = NULL; 2255 size_t copy; 2256 size_t sg_used; 2257 unsigned int i; 2258 2259 if (!is_slave_direction(direction) || direction != chan->direction) 2260 return NULL; 2261 2262 desc = xilinx_dma_alloc_tx_descriptor(chan); 2263 if (!desc) 2264 return NULL; 2265 2266 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2267 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2268 2269 /* Build transactions using information from DMA vectors */ 2270 for (i = 0; i < nb; i++) { 2271 sg_used = 0; 2272 2273 /* Loop until the entire dma_vec entry is used */ 2274 while (sg_used < vecs[i].len) { 2275 struct xilinx_axidma_desc_hw *hw; 2276 2277 /* Get a free segment */ 2278 segment = xilinx_axidma_alloc_tx_segment(chan); 2279 if (!segment) 2280 goto error; 2281 2282 /* 2283 * Calculate the maximum number of bytes to transfer, 2284 * making sure it is less than the hw limit 2285 */ 2286 copy = xilinx_dma_calc_copysize(chan, vecs[i].len, 2287 sg_used); 2288 hw = &segment->hw; 2289 2290 /* Fill in the descriptor */ 2291 xilinx_axidma_buf(chan, hw, vecs[i].addr, sg_used, 0); 2292 hw->control = copy; 2293 2294 if (prev) 2295 prev->hw.next_desc = segment->phys; 2296 2297 prev = segment; 2298 sg_used += copy; 2299 2300 /* 2301 * Insert the segment into the descriptor segments 2302 * list. 2303 */ 2304 list_add_tail(&segment->node, &desc->segments); 2305 } 2306 } 2307 2308 head = list_first_entry(&desc->segments, struct xilinx_axidma_tx_segment, node); 2309 desc->async_tx.phys = head->phys; 2310 2311 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2312 if (chan->direction == DMA_MEM_TO_DEV) { 2313 segment->hw.control |= XILINX_DMA_BD_SOP; 2314 segment = list_last_entry(&desc->segments, 2315 struct xilinx_axidma_tx_segment, 2316 node); 2317 segment->hw.control |= XILINX_DMA_BD_EOP; 2318 } 2319 2320 if (chan->xdev->has_axistream_connected) 2321 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; 2322 2323 return &desc->async_tx; 2324 2325 error: 2326 xilinx_dma_free_tx_descriptor(chan, desc); 2327 return NULL; 2328 } 2329 2330 /** 2331 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2332 * @dchan: DMA channel 2333 * @sgl: scatterlist to transfer to/from 2334 * @sg_len: number of entries in @scatterlist 2335 * @direction: DMA direction 2336 * @flags: transfer ack flags 2337 * @context: APP words of the descriptor 2338 * 2339 * Return: Async transaction descriptor on success and NULL on failure 2340 */ 2341 static struct dma_async_tx_descriptor *xilinx_dma_prep_slave_sg( 2342 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 2343 enum dma_transfer_direction direction, unsigned long flags, 2344 void *context) 2345 { 2346 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2347 struct xilinx_dma_tx_descriptor *desc; 2348 struct xilinx_axidma_tx_segment *segment = NULL; 2349 u32 *app_w = (u32 *)context; 2350 struct scatterlist *sg; 2351 size_t copy; 2352 size_t sg_used; 2353 unsigned int i; 2354 2355 if (!is_slave_direction(direction)) 2356 return NULL; 2357 2358 /* Allocate a transaction descriptor. */ 2359 desc = xilinx_dma_alloc_tx_descriptor(chan); 2360 if (!desc) 2361 return NULL; 2362 2363 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2364 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2365 2366 /* Build transactions using information in the scatter gather list */ 2367 for_each_sg(sgl, sg, sg_len, i) { 2368 sg_used = 0; 2369 2370 /* Loop until the entire scatterlist entry is used */ 2371 while (sg_used < sg_dma_len(sg)) { 2372 struct xilinx_axidma_desc_hw *hw; 2373 2374 /* Get a free segment */ 2375 segment = xilinx_axidma_alloc_tx_segment(chan); 2376 if (!segment) 2377 goto error; 2378 2379 /* 2380 * Calculate the maximum number of bytes to transfer, 2381 * making sure it is less than the hw limit 2382 */ 2383 copy = xilinx_dma_calc_copysize(chan, sg_dma_len(sg), 2384 sg_used); 2385 hw = &segment->hw; 2386 2387 /* Fill in the descriptor */ 2388 xilinx_axidma_buf(chan, hw, sg_dma_address(sg), 2389 sg_used, 0); 2390 2391 hw->control = copy; 2392 2393 if (chan->direction == DMA_MEM_TO_DEV) { 2394 if (app_w) 2395 memcpy(hw->app, app_w, sizeof(u32) * 2396 XILINX_DMA_NUM_APP_WORDS); 2397 } 2398 2399 sg_used += copy; 2400 2401 /* 2402 * Insert the segment into the descriptor segments 2403 * list. 2404 */ 2405 list_add_tail(&segment->node, &desc->segments); 2406 } 2407 } 2408 2409 segment = list_first_entry(&desc->segments, 2410 struct xilinx_axidma_tx_segment, node); 2411 desc->async_tx.phys = segment->phys; 2412 2413 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2414 if (chan->direction == DMA_MEM_TO_DEV) { 2415 segment->hw.control |= XILINX_DMA_BD_SOP; 2416 segment = list_last_entry(&desc->segments, 2417 struct xilinx_axidma_tx_segment, 2418 node); 2419 segment->hw.control |= XILINX_DMA_BD_EOP; 2420 } 2421 2422 if (chan->xdev->has_axistream_connected) 2423 desc->async_tx.metadata_ops = &xilinx_dma_metadata_ops; 2424 2425 return &desc->async_tx; 2426 2427 error: 2428 xilinx_dma_free_tx_descriptor(chan, desc); 2429 return NULL; 2430 } 2431 2432 /** 2433 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction 2434 * @dchan: DMA channel 2435 * @buf_addr: Physical address of the buffer 2436 * @buf_len: Total length of the cyclic buffers 2437 * @period_len: length of individual cyclic buffer 2438 * @direction: DMA direction 2439 * @flags: transfer ack flags 2440 * 2441 * Return: Async transaction descriptor on success and NULL on failure 2442 */ 2443 static struct dma_async_tx_descriptor *xilinx_dma_prep_dma_cyclic( 2444 struct dma_chan *dchan, dma_addr_t buf_addr, size_t buf_len, 2445 size_t period_len, enum dma_transfer_direction direction, 2446 unsigned long flags) 2447 { 2448 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2449 struct xilinx_dma_tx_descriptor *desc; 2450 struct xilinx_axidma_tx_segment *segment, *head_segment, *prev = NULL; 2451 size_t copy, sg_used; 2452 unsigned int num_periods; 2453 int i; 2454 u32 reg; 2455 2456 if (!period_len) 2457 return NULL; 2458 2459 num_periods = buf_len / period_len; 2460 2461 if (!num_periods) 2462 return NULL; 2463 2464 if (!is_slave_direction(direction)) 2465 return NULL; 2466 2467 /* Allocate a transaction descriptor. */ 2468 desc = xilinx_dma_alloc_tx_descriptor(chan); 2469 if (!desc) 2470 return NULL; 2471 2472 chan->direction = direction; 2473 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2474 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2475 2476 for (i = 0; i < num_periods; ++i) { 2477 sg_used = 0; 2478 2479 while (sg_used < period_len) { 2480 struct xilinx_axidma_desc_hw *hw; 2481 2482 /* Get a free segment */ 2483 segment = xilinx_axidma_alloc_tx_segment(chan); 2484 if (!segment) 2485 goto error; 2486 2487 /* 2488 * Calculate the maximum number of bytes to transfer, 2489 * making sure it is less than the hw limit 2490 */ 2491 copy = xilinx_dma_calc_copysize(chan, period_len, 2492 sg_used); 2493 hw = &segment->hw; 2494 xilinx_axidma_buf(chan, hw, buf_addr, sg_used, 2495 period_len * i); 2496 hw->control = copy; 2497 2498 if (prev) 2499 prev->hw.next_desc = segment->phys; 2500 2501 prev = segment; 2502 sg_used += copy; 2503 2504 /* 2505 * Insert the segment into the descriptor segments 2506 * list. 2507 */ 2508 list_add_tail(&segment->node, &desc->segments); 2509 } 2510 } 2511 2512 head_segment = list_first_entry(&desc->segments, 2513 struct xilinx_axidma_tx_segment, node); 2514 desc->async_tx.phys = head_segment->phys; 2515 2516 desc->cyclic = true; 2517 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2518 reg |= XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2519 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2520 2521 segment = list_last_entry(&desc->segments, 2522 struct xilinx_axidma_tx_segment, 2523 node); 2524 segment->hw.next_desc = (u32) head_segment->phys; 2525 2526 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2527 if (direction == DMA_MEM_TO_DEV) { 2528 head_segment->hw.control |= XILINX_DMA_BD_SOP; 2529 segment->hw.control |= XILINX_DMA_BD_EOP; 2530 } 2531 2532 return &desc->async_tx; 2533 2534 error: 2535 xilinx_dma_free_tx_descriptor(chan, desc); 2536 return NULL; 2537 } 2538 2539 /** 2540 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 2541 * @dchan: DMA channel 2542 * @sgl: scatterlist to transfer to/from 2543 * @sg_len: number of entries in @scatterlist 2544 * @direction: DMA direction 2545 * @flags: transfer ack flags 2546 * @context: APP words of the descriptor 2547 * 2548 * Return: Async transaction descriptor on success and NULL on failure 2549 */ 2550 static struct dma_async_tx_descriptor * 2551 xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 2552 unsigned int sg_len, 2553 enum dma_transfer_direction direction, 2554 unsigned long flags, void *context) 2555 { 2556 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2557 struct xilinx_dma_tx_descriptor *desc; 2558 struct xilinx_aximcdma_tx_segment *segment = NULL; 2559 u32 *app_w = (u32 *)context; 2560 struct scatterlist *sg; 2561 size_t copy; 2562 size_t sg_used; 2563 unsigned int i; 2564 2565 if (!is_slave_direction(direction)) 2566 return NULL; 2567 2568 /* Allocate a transaction descriptor. */ 2569 desc = xilinx_dma_alloc_tx_descriptor(chan); 2570 if (!desc) 2571 return NULL; 2572 2573 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 2574 desc->async_tx.tx_submit = xilinx_dma_tx_submit; 2575 2576 /* Build transactions using information in the scatter gather list */ 2577 for_each_sg(sgl, sg, sg_len, i) { 2578 sg_used = 0; 2579 2580 /* Loop until the entire scatterlist entry is used */ 2581 while (sg_used < sg_dma_len(sg)) { 2582 struct xilinx_aximcdma_desc_hw *hw; 2583 2584 /* Get a free segment */ 2585 segment = xilinx_aximcdma_alloc_tx_segment(chan); 2586 if (!segment) 2587 goto error; 2588 2589 /* 2590 * Calculate the maximum number of bytes to transfer, 2591 * making sure it is less than the hw limit 2592 */ 2593 copy = min_t(size_t, sg_dma_len(sg) - sg_used, 2594 chan->xdev->max_buffer_len); 2595 hw = &segment->hw; 2596 2597 /* Fill in the descriptor */ 2598 xilinx_aximcdma_buf(chan, hw, sg_dma_address(sg), 2599 sg_used); 2600 hw->control = copy; 2601 2602 if (chan->direction == DMA_MEM_TO_DEV && app_w) { 2603 memcpy(hw->app, app_w, sizeof(u32) * 2604 XILINX_DMA_NUM_APP_WORDS); 2605 } 2606 2607 sg_used += copy; 2608 /* 2609 * Insert the segment into the descriptor segments 2610 * list. 2611 */ 2612 list_add_tail(&segment->node, &desc->segments); 2613 } 2614 } 2615 2616 segment = list_first_entry(&desc->segments, 2617 struct xilinx_aximcdma_tx_segment, node); 2618 desc->async_tx.phys = segment->phys; 2619 2620 /* For the last DMA_MEM_TO_DEV transfer, set EOP */ 2621 if (chan->direction == DMA_MEM_TO_DEV) { 2622 segment->hw.control |= XILINX_MCDMA_BD_SOP; 2623 segment = list_last_entry(&desc->segments, 2624 struct xilinx_aximcdma_tx_segment, 2625 node); 2626 segment->hw.control |= XILINX_MCDMA_BD_EOP; 2627 } 2628 2629 return &desc->async_tx; 2630 2631 error: 2632 xilinx_dma_free_tx_descriptor(chan, desc); 2633 2634 return NULL; 2635 } 2636 2637 /** 2638 * xilinx_dma_terminate_all - Halt the channel and free descriptors 2639 * @dchan: Driver specific DMA Channel pointer 2640 * 2641 * Return: '0' always. 2642 */ 2643 static int xilinx_dma_terminate_all(struct dma_chan *dchan) 2644 { 2645 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2646 u32 reg; 2647 int err; 2648 2649 if (!chan->cyclic) { 2650 err = chan->stop_transfer(chan); 2651 if (err) { 2652 dev_err(chan->dev, "Cannot stop channel %p: %x\n", 2653 chan, dma_ctrl_read(chan, 2654 XILINX_DMA_REG_DMASR)); 2655 chan->err = true; 2656 } 2657 } 2658 2659 xilinx_dma_chan_reset(chan); 2660 /* Remove and free all of the descriptors in the lists */ 2661 chan->terminating = true; 2662 xilinx_dma_free_descriptors(chan); 2663 chan->idle = true; 2664 2665 if (chan->cyclic) { 2666 reg = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2667 reg &= ~XILINX_DMA_CR_CYCLIC_BD_EN_MASK; 2668 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); 2669 chan->cyclic = false; 2670 } 2671 2672 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) 2673 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2674 XILINX_CDMA_CR_SGMODE); 2675 2676 return 0; 2677 } 2678 2679 static void xilinx_dma_synchronize(struct dma_chan *dchan) 2680 { 2681 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2682 2683 tasklet_kill(&chan->tasklet); 2684 } 2685 2686 /** 2687 * xilinx_vdma_channel_set_config - Configure VDMA channel 2688 * Run-time configuration for Axi VDMA, supports: 2689 * . halt the channel 2690 * . configure interrupt coalescing and inter-packet delay threshold 2691 * . start/stop parking 2692 * . enable genlock 2693 * 2694 * @dchan: DMA channel 2695 * @cfg: VDMA device configuration pointer 2696 * 2697 * Return: '0' on success and failure value on error 2698 */ 2699 int xilinx_vdma_channel_set_config(struct dma_chan *dchan, 2700 struct xilinx_vdma_config *cfg) 2701 { 2702 struct xilinx_dma_chan *chan = to_xilinx_chan(dchan); 2703 u32 dmacr; 2704 2705 if (cfg->reset) 2706 return xilinx_dma_chan_reset(chan); 2707 2708 dmacr = dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); 2709 2710 chan->config.frm_dly = cfg->frm_dly; 2711 chan->config.park = cfg->park; 2712 2713 /* genlock settings */ 2714 chan->config.gen_lock = cfg->gen_lock; 2715 chan->config.master = cfg->master; 2716 2717 dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN; 2718 if (cfg->gen_lock && chan->genlock) { 2719 dmacr |= XILINX_DMA_DMACR_GENLOCK_EN; 2720 dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK; 2721 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; 2722 } 2723 2724 chan->config.frm_cnt_en = cfg->frm_cnt_en; 2725 chan->config.vflip_en = cfg->vflip_en; 2726 2727 if (cfg->park) 2728 chan->config.park_frm = cfg->park_frm; 2729 else 2730 chan->config.park_frm = -1; 2731 2732 chan->config.coalesc = cfg->coalesc; 2733 chan->config.delay = cfg->delay; 2734 2735 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { 2736 dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK; 2737 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; 2738 chan->config.coalesc = cfg->coalesc; 2739 } 2740 2741 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { 2742 dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK; 2743 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; 2744 chan->config.delay = cfg->delay; 2745 } 2746 2747 /* FSync Source selection */ 2748 dmacr &= ~XILINX_DMA_DMACR_FSYNCSRC_MASK; 2749 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; 2750 2751 dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, dmacr); 2752 2753 return 0; 2754 } 2755 EXPORT_SYMBOL(xilinx_vdma_channel_set_config); 2756 2757 /* ----------------------------------------------------------------------------- 2758 * Probe and remove 2759 */ 2760 2761 /** 2762 * xilinx_dma_chan_remove - Per Channel remove function 2763 * @chan: Driver specific DMA channel 2764 */ 2765 static void xilinx_dma_chan_remove(struct xilinx_dma_chan *chan) 2766 { 2767 /* Disable all interrupts */ 2768 dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR, 2769 XILINX_DMA_DMAXR_ALL_IRQ_MASK); 2770 2771 if (chan->irq > 0) 2772 free_irq(chan->irq, chan); 2773 2774 tasklet_kill(&chan->tasklet); 2775 2776 list_del(&chan->common.device_node); 2777 } 2778 2779 static int axidma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2780 struct clk **tx_clk, struct clk **rx_clk, 2781 struct clk **sg_clk, struct clk **tmp_clk) 2782 { 2783 int err; 2784 2785 *tmp_clk = NULL; 2786 2787 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2788 if (IS_ERR(*axi_clk)) 2789 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2790 2791 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2792 if (IS_ERR(*tx_clk)) 2793 *tx_clk = NULL; 2794 2795 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2796 if (IS_ERR(*rx_clk)) 2797 *rx_clk = NULL; 2798 2799 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk"); 2800 if (IS_ERR(*sg_clk)) 2801 *sg_clk = NULL; 2802 2803 err = clk_prepare_enable(*axi_clk); 2804 if (err) { 2805 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2806 return err; 2807 } 2808 2809 err = clk_prepare_enable(*tx_clk); 2810 if (err) { 2811 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2812 goto err_disable_axiclk; 2813 } 2814 2815 err = clk_prepare_enable(*rx_clk); 2816 if (err) { 2817 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2818 goto err_disable_txclk; 2819 } 2820 2821 err = clk_prepare_enable(*sg_clk); 2822 if (err) { 2823 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err); 2824 goto err_disable_rxclk; 2825 } 2826 2827 return 0; 2828 2829 err_disable_rxclk: 2830 clk_disable_unprepare(*rx_clk); 2831 err_disable_txclk: 2832 clk_disable_unprepare(*tx_clk); 2833 err_disable_axiclk: 2834 clk_disable_unprepare(*axi_clk); 2835 2836 return err; 2837 } 2838 2839 static int axicdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2840 struct clk **dev_clk, struct clk **tmp_clk, 2841 struct clk **tmp1_clk, struct clk **tmp2_clk) 2842 { 2843 int err; 2844 2845 *tmp_clk = NULL; 2846 *tmp1_clk = NULL; 2847 *tmp2_clk = NULL; 2848 2849 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2850 if (IS_ERR(*axi_clk)) 2851 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2852 2853 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); 2854 if (IS_ERR(*dev_clk)) 2855 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n"); 2856 2857 err = clk_prepare_enable(*axi_clk); 2858 if (err) { 2859 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); 2860 return err; 2861 } 2862 2863 err = clk_prepare_enable(*dev_clk); 2864 if (err) { 2865 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err); 2866 goto err_disable_axiclk; 2867 } 2868 2869 return 0; 2870 2871 err_disable_axiclk: 2872 clk_disable_unprepare(*axi_clk); 2873 2874 return err; 2875 } 2876 2877 static int axivdma_clk_init(struct platform_device *pdev, struct clk **axi_clk, 2878 struct clk **tx_clk, struct clk **txs_clk, 2879 struct clk **rx_clk, struct clk **rxs_clk) 2880 { 2881 int err; 2882 2883 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); 2884 if (IS_ERR(*axi_clk)) 2885 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); 2886 2887 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); 2888 if (IS_ERR(*tx_clk)) 2889 *tx_clk = NULL; 2890 2891 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk"); 2892 if (IS_ERR(*txs_clk)) 2893 *txs_clk = NULL; 2894 2895 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); 2896 if (IS_ERR(*rx_clk)) 2897 *rx_clk = NULL; 2898 2899 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk"); 2900 if (IS_ERR(*rxs_clk)) 2901 *rxs_clk = NULL; 2902 2903 err = clk_prepare_enable(*axi_clk); 2904 if (err) { 2905 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", 2906 err); 2907 return err; 2908 } 2909 2910 err = clk_prepare_enable(*tx_clk); 2911 if (err) { 2912 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); 2913 goto err_disable_axiclk; 2914 } 2915 2916 err = clk_prepare_enable(*txs_clk); 2917 if (err) { 2918 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err); 2919 goto err_disable_txclk; 2920 } 2921 2922 err = clk_prepare_enable(*rx_clk); 2923 if (err) { 2924 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); 2925 goto err_disable_txsclk; 2926 } 2927 2928 err = clk_prepare_enable(*rxs_clk); 2929 if (err) { 2930 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err); 2931 goto err_disable_rxclk; 2932 } 2933 2934 return 0; 2935 2936 err_disable_rxclk: 2937 clk_disable_unprepare(*rx_clk); 2938 err_disable_txsclk: 2939 clk_disable_unprepare(*txs_clk); 2940 err_disable_txclk: 2941 clk_disable_unprepare(*tx_clk); 2942 err_disable_axiclk: 2943 clk_disable_unprepare(*axi_clk); 2944 2945 return err; 2946 } 2947 2948 static void xdma_disable_allclks(struct xilinx_dma_device *xdev) 2949 { 2950 clk_disable_unprepare(xdev->rxs_clk); 2951 clk_disable_unprepare(xdev->rx_clk); 2952 clk_disable_unprepare(xdev->txs_clk); 2953 clk_disable_unprepare(xdev->tx_clk); 2954 clk_disable_unprepare(xdev->axi_clk); 2955 } 2956 2957 /** 2958 * xilinx_dma_chan_probe - Per Channel Probing 2959 * It get channel features from the device tree entry and 2960 * initialize special channel handling routines 2961 * 2962 * @xdev: Driver specific device structure 2963 * @node: Device node 2964 * 2965 * Return: '0' on success and failure value on error 2966 */ 2967 static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev, 2968 struct device_node *node) 2969 { 2970 struct xilinx_dma_chan *chan; 2971 bool has_dre = false; 2972 u32 value, width; 2973 int err; 2974 2975 /* Allocate and initialize the channel structure */ 2976 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); 2977 if (!chan) 2978 return -ENOMEM; 2979 2980 chan->dev = xdev->dev; 2981 chan->xdev = xdev; 2982 chan->desc_pendingcount = 0x0; 2983 chan->ext_addr = xdev->ext_addr; 2984 /* This variable ensures that descriptors are not 2985 * Submitted when dma engine is in progress. This variable is 2986 * Added to avoid polling for a bit in the status register to 2987 * Know dma state in the driver hot path. 2988 */ 2989 chan->idle = true; 2990 2991 spin_lock_init(&chan->lock); 2992 INIT_LIST_HEAD(&chan->pending_list); 2993 INIT_LIST_HEAD(&chan->done_list); 2994 INIT_LIST_HEAD(&chan->active_list); 2995 INIT_LIST_HEAD(&chan->free_seg_list); 2996 2997 /* Retrieve the channel properties from the device tree */ 2998 has_dre = of_property_read_bool(node, "xlnx,include-dre"); 2999 3000 of_property_read_u8(node, "xlnx,irq-delay", &chan->irq_delay); 3001 3002 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); 3003 3004 err = of_property_read_u32(node, "xlnx,datawidth", &value); 3005 if (err) { 3006 dev_err(xdev->dev, "missing xlnx,datawidth property\n"); 3007 return err; 3008 } 3009 width = value >> 3; /* Convert bits to bytes */ 3010 3011 /* If data width is greater than 8 bytes, DRE is not in hw */ 3012 if (width > 8) 3013 has_dre = false; 3014 3015 if (!has_dre) 3016 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1); 3017 3018 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") || 3019 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") || 3020 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) { 3021 chan->direction = DMA_MEM_TO_DEV; 3022 chan->id = xdev->mm2s_chan_id++; 3023 chan->tdest = chan->id; 3024 3025 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; 3026 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3027 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; 3028 chan->config.park = 1; 3029 3030 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 3031 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) 3032 chan->flush_on_fsync = true; 3033 } 3034 } else if (of_device_is_compatible(node, 3035 "xlnx,axi-vdma-s2mm-channel") || 3036 of_device_is_compatible(node, 3037 "xlnx,axi-dma-s2mm-channel")) { 3038 chan->direction = DMA_DEV_TO_MEM; 3039 chan->id = xdev->s2mm_chan_id++; 3040 chan->tdest = chan->id - xdev->dma_config->max_channels / 2; 3041 chan->has_vflip = of_property_read_bool(node, 3042 "xlnx,enable-vert-flip"); 3043 if (chan->has_vflip) { 3044 chan->config.vflip_en = dma_read(chan, 3045 XILINX_VDMA_REG_ENABLE_VERTICAL_FLIP) & 3046 XILINX_VDMA_ENABLE_VERTICAL_FLIP; 3047 } 3048 3049 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 3050 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; 3051 else 3052 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; 3053 3054 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3055 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; 3056 chan->config.park = 1; 3057 3058 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || 3059 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) 3060 chan->flush_on_fsync = true; 3061 } 3062 } else { 3063 dev_err(xdev->dev, "Invalid channel compatible node\n"); 3064 return -EINVAL; 3065 } 3066 3067 xdev->common.directions |= BIT(chan->direction); 3068 3069 /* Request the interrupt */ 3070 chan->irq = of_irq_get(node, chan->tdest); 3071 if (chan->irq < 0) 3072 return dev_err_probe(xdev->dev, chan->irq, "failed to get irq\n"); 3073 err = request_irq(chan->irq, xdev->dma_config->irq_handler, 3074 IRQF_SHARED, "xilinx-dma-controller", chan); 3075 if (err) { 3076 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); 3077 return err; 3078 } 3079 3080 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3081 chan->start_transfer = xilinx_dma_start_transfer; 3082 chan->stop_transfer = xilinx_dma_stop_transfer; 3083 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3084 chan->start_transfer = xilinx_mcdma_start_transfer; 3085 chan->stop_transfer = xilinx_dma_stop_transfer; 3086 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 3087 chan->start_transfer = xilinx_cdma_start_transfer; 3088 chan->stop_transfer = xilinx_cdma_stop_transfer; 3089 } else { 3090 chan->start_transfer = xilinx_vdma_start_transfer; 3091 chan->stop_transfer = xilinx_dma_stop_transfer; 3092 } 3093 3094 /* check if SG is enabled (only for AXIDMA, AXIMCDMA, and CDMA) */ 3095 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { 3096 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA || 3097 dma_ctrl_read(chan, XILINX_DMA_REG_DMASR) & 3098 XILINX_DMA_DMASR_SG_MASK) 3099 chan->has_sg = true; 3100 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, 3101 str_enabled_disabled(chan->has_sg)); 3102 } 3103 3104 /* Initialize the tasklet */ 3105 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet); 3106 3107 /* 3108 * Initialize the DMA channel and add it to the DMA engine channels 3109 * list. 3110 */ 3111 chan->common.device = &xdev->common; 3112 3113 list_add_tail(&chan->common.device_node, &xdev->common.channels); 3114 xdev->chan[chan->id] = chan; 3115 3116 /* Reset the channel */ 3117 err = xilinx_dma_chan_reset(chan); 3118 if (err < 0) { 3119 dev_err(xdev->dev, "Reset channel failed\n"); 3120 return err; 3121 } 3122 3123 return 0; 3124 } 3125 3126 /** 3127 * xilinx_dma_child_probe - Per child node probe 3128 * It get number of dma-channels per child node from 3129 * device-tree and initializes all the channels. 3130 * 3131 * @xdev: Driver specific device structure 3132 * @node: Device node 3133 * 3134 * Return: '0' on success and failure value on error. 3135 */ 3136 static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, 3137 struct device_node *node) 3138 { 3139 int ret, i; 3140 u32 nr_channels = 1; 3141 3142 ret = of_property_read_u32(node, "dma-channels", &nr_channels); 3143 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0) 3144 dev_warn(xdev->dev, "missing dma-channels property\n"); 3145 3146 for (i = 0; i < nr_channels; i++) { 3147 ret = xilinx_dma_chan_probe(xdev, node); 3148 if (ret) 3149 return ret; 3150 } 3151 3152 return 0; 3153 } 3154 3155 /** 3156 * of_dma_xilinx_xlate - Translation function 3157 * @dma_spec: Pointer to DMA specifier as found in the device tree 3158 * @ofdma: Pointer to DMA controller data 3159 * 3160 * Return: DMA channel pointer on success and NULL on error 3161 */ 3162 static struct dma_chan *of_dma_xilinx_xlate(struct of_phandle_args *dma_spec, 3163 struct of_dma *ofdma) 3164 { 3165 struct xilinx_dma_device *xdev = ofdma->of_dma_data; 3166 int chan_id = dma_spec->args[0]; 3167 3168 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) 3169 return NULL; 3170 3171 return dma_get_slave_channel(&xdev->chan[chan_id]->common); 3172 } 3173 3174 static const struct xilinx_dma_config axidma_config = { 3175 .dmatype = XDMA_TYPE_AXIDMA, 3176 .clk_init = axidma_clk_init, 3177 .irq_handler = xilinx_dma_irq_handler, 3178 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3179 }; 3180 3181 static const struct xilinx_dma_config aximcdma_config = { 3182 .dmatype = XDMA_TYPE_AXIMCDMA, 3183 .clk_init = axidma_clk_init, 3184 .irq_handler = xilinx_mcdma_irq_handler, 3185 .max_channels = XILINX_MCDMA_MAX_CHANS_PER_DEVICE, 3186 }; 3187 static const struct xilinx_dma_config axicdma_config = { 3188 .dmatype = XDMA_TYPE_CDMA, 3189 .clk_init = axicdma_clk_init, 3190 .irq_handler = xilinx_dma_irq_handler, 3191 .max_channels = XILINX_CDMA_MAX_CHANS_PER_DEVICE, 3192 }; 3193 3194 static const struct xilinx_dma_config axivdma_config = { 3195 .dmatype = XDMA_TYPE_VDMA, 3196 .clk_init = axivdma_clk_init, 3197 .irq_handler = xilinx_dma_irq_handler, 3198 .max_channels = XILINX_DMA_MAX_CHANS_PER_DEVICE, 3199 }; 3200 3201 static const struct of_device_id xilinx_dma_of_ids[] = { 3202 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config }, 3203 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config }, 3204 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config }, 3205 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config }, 3206 {} 3207 }; 3208 MODULE_DEVICE_TABLE(of, xilinx_dma_of_ids); 3209 3210 /** 3211 * xilinx_dma_probe - Driver probe function 3212 * @pdev: Pointer to the platform_device structure 3213 * 3214 * Return: '0' on success and failure value on error 3215 */ 3216 static int xilinx_dma_probe(struct platform_device *pdev) 3217 { 3218 int (*clk_init)(struct platform_device *, struct clk **, struct clk **, 3219 struct clk **, struct clk **, struct clk **) 3220 = axivdma_clk_init; 3221 struct device_node *node = pdev->dev.of_node; 3222 struct xilinx_dma_device *xdev; 3223 struct device_node *np = pdev->dev.of_node; 3224 u32 num_frames, addr_width = XILINX_DMA_DFAULT_ADDRWIDTH, len_width; 3225 int i, err; 3226 3227 /* Allocate and initialize the DMA engine structure */ 3228 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); 3229 if (!xdev) 3230 return -ENOMEM; 3231 3232 xdev->dev = &pdev->dev; 3233 if (np) { 3234 const struct of_device_id *match; 3235 3236 match = of_match_node(xilinx_dma_of_ids, np); 3237 if (match && match->data) { 3238 xdev->dma_config = match->data; 3239 clk_init = xdev->dma_config->clk_init; 3240 } 3241 } 3242 3243 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, 3244 &xdev->rx_clk, &xdev->rxs_clk); 3245 if (err) 3246 return err; 3247 3248 /* Request and map I/O memory */ 3249 xdev->regs = devm_platform_ioremap_resource(pdev, 0); 3250 if (IS_ERR(xdev->regs)) { 3251 err = PTR_ERR(xdev->regs); 3252 goto disable_clks; 3253 } 3254 /* Retrieve the DMA engine properties from the device tree */ 3255 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); 3256 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; 3257 3258 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || 3259 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3260 if (!of_property_read_u32(node, "xlnx,sg-length-width", 3261 &len_width)) { 3262 if (len_width < XILINX_DMA_MAX_TRANS_LEN_MIN || 3263 len_width > XILINX_DMA_V2_MAX_TRANS_LEN_MAX) { 3264 dev_warn(xdev->dev, 3265 "invalid xlnx,sg-length-width property value. Using default width\n"); 3266 } else { 3267 if (len_width > XILINX_DMA_MAX_TRANS_LEN_MAX) 3268 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); 3269 xdev->max_buffer_len = 3270 GENMASK(len_width - 1, 0); 3271 } 3272 } 3273 } 3274 3275 dma_set_max_seg_size(xdev->dev, xdev->max_buffer_len); 3276 3277 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3278 xdev->has_axistream_connected = 3279 of_property_read_bool(node, "xlnx,axistream-connected"); 3280 } 3281 3282 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3283 err = of_property_read_u32(node, "xlnx,num-fstores", 3284 &num_frames); 3285 if (err < 0) { 3286 dev_err(xdev->dev, 3287 "missing xlnx,num-fstores property\n"); 3288 goto disable_clks; 3289 } 3290 3291 err = of_property_read_u32(node, "xlnx,flush-fsync", 3292 &xdev->flush_on_fsync); 3293 if (err < 0) 3294 dev_warn(xdev->dev, 3295 "missing xlnx,flush-fsync property\n"); 3296 } 3297 3298 err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width); 3299 if (err < 0) 3300 dev_warn(xdev->dev, 3301 "missing xlnx,addrwidth property, using default value %d\n", 3302 XILINX_DMA_DFAULT_ADDRWIDTH); 3303 3304 if (addr_width > 32) 3305 xdev->ext_addr = true; 3306 else 3307 xdev->ext_addr = false; 3308 3309 /* Set metadata mode */ 3310 if (xdev->has_axistream_connected) 3311 xdev->common.desc_metadata_modes = DESC_METADATA_ENGINE; 3312 3313 /* Set the dma mask bits */ 3314 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); 3315 if (err < 0) { 3316 dev_err(xdev->dev, "DMA mask error %d\n", err); 3317 goto disable_clks; 3318 } 3319 3320 /* Initialize the DMA engine */ 3321 xdev->common.dev = &pdev->dev; 3322 3323 INIT_LIST_HEAD(&xdev->common.channels); 3324 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { 3325 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); 3326 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); 3327 } 3328 3329 xdev->common.device_alloc_chan_resources = 3330 xilinx_dma_alloc_chan_resources; 3331 xdev->common.device_free_chan_resources = 3332 xilinx_dma_free_chan_resources; 3333 xdev->common.device_terminate_all = xilinx_dma_terminate_all; 3334 xdev->common.device_synchronize = xilinx_dma_synchronize; 3335 xdev->common.device_tx_status = xilinx_dma_tx_status; 3336 xdev->common.device_issue_pending = xilinx_dma_issue_pending; 3337 xdev->common.device_config = xilinx_dma_device_config; 3338 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { 3339 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask); 3340 xdev->common.device_prep_peripheral_dma_vec = xilinx_dma_prep_peripheral_dma_vec; 3341 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; 3342 xdev->common.device_prep_dma_cyclic = 3343 xilinx_dma_prep_dma_cyclic; 3344 /* Residue calculation is supported by only AXI DMA and CDMA */ 3345 xdev->common.residue_granularity = 3346 DMA_RESIDUE_GRANULARITY_SEGMENT; 3347 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { 3348 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); 3349 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; 3350 /* Residue calculation is supported by only AXI DMA and CDMA */ 3351 xdev->common.residue_granularity = 3352 DMA_RESIDUE_GRANULARITY_SEGMENT; 3353 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { 3354 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg; 3355 } else { 3356 xdev->common.device_prep_interleaved_dma = 3357 xilinx_vdma_dma_prep_interleaved; 3358 } 3359 3360 platform_set_drvdata(pdev, xdev); 3361 3362 /* Initialize the channels */ 3363 for_each_child_of_node_scoped(node, child) { 3364 err = xilinx_dma_child_probe(xdev, child); 3365 if (err < 0) 3366 goto error; 3367 } 3368 3369 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { 3370 for (i = 0; i < xdev->dma_config->max_channels; i++) 3371 if (xdev->chan[i]) 3372 xdev->chan[i]->num_frms = num_frames; 3373 } 3374 3375 /* Register the DMA engine with the core */ 3376 err = dma_async_device_register(&xdev->common); 3377 if (err) { 3378 dev_err(xdev->dev, "failed to register the dma device\n"); 3379 goto error; 3380 } 3381 3382 err = of_dma_controller_register(node, of_dma_xilinx_xlate, 3383 xdev); 3384 if (err < 0) { 3385 dev_err(&pdev->dev, "Unable to register DMA to DT\n"); 3386 dma_async_device_unregister(&xdev->common); 3387 goto error; 3388 } 3389 3390 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) 3391 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n"); 3392 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) 3393 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n"); 3394 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) 3395 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n"); 3396 else 3397 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n"); 3398 3399 return 0; 3400 3401 error: 3402 for (i = 0; i < xdev->dma_config->max_channels; i++) 3403 if (xdev->chan[i]) 3404 xilinx_dma_chan_remove(xdev->chan[i]); 3405 disable_clks: 3406 xdma_disable_allclks(xdev); 3407 3408 return err; 3409 } 3410 3411 /** 3412 * xilinx_dma_remove - Driver remove function 3413 * @pdev: Pointer to the platform_device structure 3414 */ 3415 static void xilinx_dma_remove(struct platform_device *pdev) 3416 { 3417 struct xilinx_dma_device *xdev = platform_get_drvdata(pdev); 3418 int i; 3419 3420 of_dma_controller_free(pdev->dev.of_node); 3421 3422 dma_async_device_unregister(&xdev->common); 3423 3424 for (i = 0; i < xdev->dma_config->max_channels; i++) 3425 if (xdev->chan[i]) 3426 xilinx_dma_chan_remove(xdev->chan[i]); 3427 3428 xdma_disable_allclks(xdev); 3429 } 3430 3431 static struct platform_driver xilinx_vdma_driver = { 3432 .driver = { 3433 .name = "xilinx-vdma", 3434 .of_match_table = xilinx_dma_of_ids, 3435 }, 3436 .probe = xilinx_dma_probe, 3437 .remove = xilinx_dma_remove, 3438 }; 3439 3440 module_platform_driver(xilinx_vdma_driver); 3441 3442 MODULE_AUTHOR("Xilinx, Inc."); 3443 MODULE_DESCRIPTION("Xilinx VDMA driver"); 3444 MODULE_LICENSE("GPL v2"); 3445