xref: /linux/drivers/dma/xilinx/xdma-regs.h (revision 4232da23d75d173195c6766729e51947b64f83cd)
117ce2522SLizhi Hou /* SPDX-License-Identifier: GPL-2.0-or-later */
217ce2522SLizhi Hou /*
317ce2522SLizhi Hou  * Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved.
417ce2522SLizhi Hou  * Copyright (C) 2022, Advanced Micro Devices, Inc.
517ce2522SLizhi Hou  */
617ce2522SLizhi Hou 
717ce2522SLizhi Hou #ifndef __DMA_XDMA_REGS_H
817ce2522SLizhi Hou #define __DMA_XDMA_REGS_H
917ce2522SLizhi Hou 
1017ce2522SLizhi Hou /* The length of register space exposed to host */
1117ce2522SLizhi Hou #define XDMA_REG_SPACE_LEN	65536
1217ce2522SLizhi Hou 
1317ce2522SLizhi Hou /*
1417ce2522SLizhi Hou  * maximum number of DMA channels for each direction:
1517ce2522SLizhi Hou  * Host to Card (H2C) or Card to Host (C2H)
1617ce2522SLizhi Hou  */
1717ce2522SLizhi Hou #define XDMA_MAX_CHANNELS	4
1817ce2522SLizhi Hou 
1917ce2522SLizhi Hou /*
2017ce2522SLizhi Hou  * macros to define the number of descriptor blocks can be used in one
2117ce2522SLizhi Hou  * DMA transfer request.
2217ce2522SLizhi Hou  * the DMA engine uses a linked list of descriptor blocks that specify the
2317ce2522SLizhi Hou  * source, destination, and length of the DMA transfers.
2417ce2522SLizhi Hou  */
2517ce2522SLizhi Hou #define XDMA_DESC_BLOCK_NUM		BIT(7)
2617ce2522SLizhi Hou #define XDMA_DESC_BLOCK_MASK		(XDMA_DESC_BLOCK_NUM - 1)
2717ce2522SLizhi Hou 
2817ce2522SLizhi Hou /* descriptor definitions */
2917ce2522SLizhi Hou #define XDMA_DESC_ADJACENT		32
3017ce2522SLizhi Hou #define XDMA_DESC_ADJACENT_MASK		(XDMA_DESC_ADJACENT - 1)
3117ce2522SLizhi Hou #define XDMA_DESC_ADJACENT_BITS		GENMASK(13, 8)
3217ce2522SLizhi Hou #define XDMA_DESC_MAGIC			0xad4bUL
3317ce2522SLizhi Hou #define XDMA_DESC_MAGIC_BITS		GENMASK(31, 16)
3417ce2522SLizhi Hou #define XDMA_DESC_FLAGS_BITS		GENMASK(7, 0)
3517ce2522SLizhi Hou #define XDMA_DESC_STOPPED		BIT(0)
3617ce2522SLizhi Hou #define XDMA_DESC_COMPLETED		BIT(1)
3717ce2522SLizhi Hou #define XDMA_DESC_BLEN_BITS		28
3817ce2522SLizhi Hou #define XDMA_DESC_BLEN_MAX		(BIT(XDMA_DESC_BLEN_BITS) - PAGE_SIZE)
3917ce2522SLizhi Hou 
4017ce2522SLizhi Hou /* macros to construct the descriptor control word */
4117ce2522SLizhi Hou #define XDMA_DESC_CONTROL(adjacent, flag)				\
4217ce2522SLizhi Hou 	(FIELD_PREP(XDMA_DESC_MAGIC_BITS, XDMA_DESC_MAGIC) |		\
4317ce2522SLizhi Hou 	 FIELD_PREP(XDMA_DESC_ADJACENT_BITS, (adjacent) - 1) |		\
4417ce2522SLizhi Hou 	 FIELD_PREP(XDMA_DESC_FLAGS_BITS, (flag)))
4517ce2522SLizhi Hou #define XDMA_DESC_CONTROL_LAST						\
4617ce2522SLizhi Hou 	XDMA_DESC_CONTROL(1, XDMA_DESC_STOPPED | XDMA_DESC_COMPLETED)
47cd8c732cSMiquel Raynal #define XDMA_DESC_CONTROL_CYCLIC					\
48cd8c732cSMiquel Raynal 	XDMA_DESC_CONTROL(1, XDMA_DESC_COMPLETED)
4917ce2522SLizhi Hou 
5017ce2522SLizhi Hou /*
5117ce2522SLizhi Hou  * Descriptor for a single contiguous memory block transfer.
5217ce2522SLizhi Hou  *
5317ce2522SLizhi Hou  * Multiple descriptors are linked by means of the next pointer. An additional
5417ce2522SLizhi Hou  * extra adjacent number gives the amount of extra contiguous descriptors.
5517ce2522SLizhi Hou  *
5617ce2522SLizhi Hou  * The descriptors are in root complex memory, and the bytes in the 32-bit
5717ce2522SLizhi Hou  * words must be in little-endian byte ordering.
5817ce2522SLizhi Hou  */
5917ce2522SLizhi Hou struct xdma_hw_desc {
6017ce2522SLizhi Hou 	__le32		control;
6117ce2522SLizhi Hou 	__le32		bytes;
6217ce2522SLizhi Hou 	__le64		src_addr;
6317ce2522SLizhi Hou 	__le64		dst_addr;
6417ce2522SLizhi Hou 	__le64		next_desc;
6517ce2522SLizhi Hou };
6617ce2522SLizhi Hou 
6717ce2522SLizhi Hou #define XDMA_DESC_SIZE			sizeof(struct xdma_hw_desc)
6817ce2522SLizhi Hou #define XDMA_DESC_BLOCK_SIZE		(XDMA_DESC_SIZE * XDMA_DESC_ADJACENT)
69e5bc76b0SJan Kuliga #define XDMA_DESC_BLOCK_ALIGN		32
70e5bc76b0SJan Kuliga #define XDMA_DESC_BLOCK_BOUNDARY	4096
7117ce2522SLizhi Hou 
7217ce2522SLizhi Hou /*
7317ce2522SLizhi Hou  * Channel registers
7417ce2522SLizhi Hou  */
7517ce2522SLizhi Hou #define XDMA_CHAN_IDENTIFIER		0x0
7617ce2522SLizhi Hou #define XDMA_CHAN_CONTROL		0x4
7717ce2522SLizhi Hou #define XDMA_CHAN_CONTROL_W1S		0x8
7817ce2522SLizhi Hou #define XDMA_CHAN_CONTROL_W1C		0xc
7917ce2522SLizhi Hou #define XDMA_CHAN_STATUS		0x40
807a9c7f46SJan Kuliga #define XDMA_CHAN_STATUS_RC		0x44
8117ce2522SLizhi Hou #define XDMA_CHAN_COMPLETED_DESC	0x48
8217ce2522SLizhi Hou #define XDMA_CHAN_ALIGNMENTS		0x4c
8317ce2522SLizhi Hou #define XDMA_CHAN_INTR_ENABLE		0x90
8417ce2522SLizhi Hou #define XDMA_CHAN_INTR_ENABLE_W1S	0x94
8517ce2522SLizhi Hou #define XDMA_CHAN_INTR_ENABLE_W1C	0x9c
8617ce2522SLizhi Hou 
8717ce2522SLizhi Hou #define XDMA_CHAN_STRIDE	0x100
8817ce2522SLizhi Hou #define XDMA_CHAN_H2C_OFFSET	0x0
8917ce2522SLizhi Hou #define XDMA_CHAN_C2H_OFFSET	0x1000
9017ce2522SLizhi Hou #define XDMA_CHAN_H2C_TARGET	0x0
9117ce2522SLizhi Hou #define XDMA_CHAN_C2H_TARGET	0x1
9217ce2522SLizhi Hou 
9317ce2522SLizhi Hou /* macro to check if channel is available */
9417ce2522SLizhi Hou #define XDMA_CHAN_MAGIC		0x1fc0
9517ce2522SLizhi Hou #define XDMA_CHAN_CHECK_TARGET(id, target)		\
9617ce2522SLizhi Hou 	(((u32)(id) >> 16) == XDMA_CHAN_MAGIC + (target))
9717ce2522SLizhi Hou 
9817ce2522SLizhi Hou /* bits of the channel control register */
9917ce2522SLizhi Hou #define CHAN_CTRL_RUN_STOP			BIT(0)
10017ce2522SLizhi Hou #define CHAN_CTRL_IE_DESC_STOPPED		BIT(1)
10117ce2522SLizhi Hou #define CHAN_CTRL_IE_DESC_COMPLETED		BIT(2)
10217ce2522SLizhi Hou #define CHAN_CTRL_IE_DESC_ALIGN_MISMATCH	BIT(3)
10317ce2522SLizhi Hou #define CHAN_CTRL_IE_MAGIC_STOPPED		BIT(4)
10417ce2522SLizhi Hou #define CHAN_CTRL_IE_IDLE_STOPPED		BIT(6)
10517ce2522SLizhi Hou #define CHAN_CTRL_IE_READ_ERROR			GENMASK(13, 9)
1067a9c7f46SJan Kuliga #define CHAN_CTRL_IE_WRITE_ERROR		GENMASK(18, 14)
10717ce2522SLizhi Hou #define CHAN_CTRL_IE_DESC_ERROR			GENMASK(23, 19)
10817ce2522SLizhi Hou #define CHAN_CTRL_NON_INCR_ADDR			BIT(25)
10917ce2522SLizhi Hou #define CHAN_CTRL_POLL_MODE_WB			BIT(26)
11017ce2522SLizhi Hou 
11117ce2522SLizhi Hou #define CHAN_CTRL_START	(CHAN_CTRL_RUN_STOP |				\
11217ce2522SLizhi Hou 			 CHAN_CTRL_IE_DESC_STOPPED |			\
11317ce2522SLizhi Hou 			 CHAN_CTRL_IE_DESC_COMPLETED |			\
11417ce2522SLizhi Hou 			 CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |		\
11517ce2522SLizhi Hou 			 CHAN_CTRL_IE_MAGIC_STOPPED |			\
11617ce2522SLizhi Hou 			 CHAN_CTRL_IE_READ_ERROR |			\
1177a9c7f46SJan Kuliga 			 CHAN_CTRL_IE_WRITE_ERROR |			\
1187a9c7f46SJan Kuliga 			 CHAN_CTRL_IE_DESC_ERROR)
1197a9c7f46SJan Kuliga 
120*6a40fb82SLouis Chauvet /* bits of the channel status register */
121*6a40fb82SLouis Chauvet #define XDMA_CHAN_STATUS_BUSY			BIT(0)
122*6a40fb82SLouis Chauvet 
1237a9c7f46SJan Kuliga #define XDMA_CHAN_STATUS_MASK CHAN_CTRL_START
1247a9c7f46SJan Kuliga 
1257a9c7f46SJan Kuliga #define XDMA_CHAN_ERROR_MASK (CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |	\
1267a9c7f46SJan Kuliga 			      CHAN_CTRL_IE_MAGIC_STOPPED |		\
1277a9c7f46SJan Kuliga 			      CHAN_CTRL_IE_READ_ERROR |			\
1287a9c7f46SJan Kuliga 			      CHAN_CTRL_IE_WRITE_ERROR |		\
12917ce2522SLizhi Hou 			      CHAN_CTRL_IE_DESC_ERROR)
13017ce2522SLizhi Hou 
13117ce2522SLizhi Hou /* bits of the channel interrupt enable mask */
13217ce2522SLizhi Hou #define CHAN_IM_DESC_ERROR			BIT(19)
13317ce2522SLizhi Hou #define CHAN_IM_READ_ERROR			BIT(9)
13417ce2522SLizhi Hou #define CHAN_IM_IDLE_STOPPED			BIT(6)
13517ce2522SLizhi Hou #define CHAN_IM_MAGIC_STOPPED			BIT(4)
13617ce2522SLizhi Hou #define CHAN_IM_DESC_COMPLETED			BIT(2)
13717ce2522SLizhi Hou #define CHAN_IM_DESC_STOPPED			BIT(1)
13817ce2522SLizhi Hou 
13917ce2522SLizhi Hou #define CHAN_IM_ALL	(CHAN_IM_DESC_ERROR | CHAN_IM_READ_ERROR |	\
14017ce2522SLizhi Hou 			 CHAN_IM_IDLE_STOPPED | CHAN_IM_MAGIC_STOPPED | \
14117ce2522SLizhi Hou 			 CHAN_IM_DESC_COMPLETED | CHAN_IM_DESC_STOPPED)
14217ce2522SLizhi Hou 
14317ce2522SLizhi Hou /*
14417ce2522SLizhi Hou  * Channel SGDMA registers
14517ce2522SLizhi Hou  */
14617ce2522SLizhi Hou #define XDMA_SGDMA_IDENTIFIER	0x4000
14717ce2522SLizhi Hou #define XDMA_SGDMA_DESC_LO	0x4080
14817ce2522SLizhi Hou #define XDMA_SGDMA_DESC_HI	0x4084
14917ce2522SLizhi Hou #define XDMA_SGDMA_DESC_ADJ	0x4088
15017ce2522SLizhi Hou #define XDMA_SGDMA_DESC_CREDIT	0x408c
15117ce2522SLizhi Hou 
15217ce2522SLizhi Hou /*
15317ce2522SLizhi Hou  * interrupt registers
15417ce2522SLizhi Hou  */
15517ce2522SLizhi Hou #define XDMA_IRQ_IDENTIFIER		0x2000
15617ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_EN		0x2004
15717ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_EN_W1S	0x2008
15817ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_EN_W1C	0x200c
15917ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_EN		0x2010
16017ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_EN_W1S	0x2014
16117ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_EN_W1C	0x2018
16217ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_REQ		0x2040
16317ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_REQ		0x2044
16417ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_PEND		0x2048
16517ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_PEND		0x204c
16617ce2522SLizhi Hou #define XDMA_IRQ_USER_VEC_NUM		0x2080
16717ce2522SLizhi Hou #define XDMA_IRQ_CHAN_VEC_NUM		0x20a0
16817ce2522SLizhi Hou 
16917ce2522SLizhi Hou #define XDMA_IRQ_VEC_SHIFT		8
17017ce2522SLizhi Hou 
17117ce2522SLizhi Hou #endif /* __DMA_XDMA_REGS_H */
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