1*17ce2522SLizhi Hou /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*17ce2522SLizhi Hou /* 3*17ce2522SLizhi Hou * Copyright (C) 2017-2020 Xilinx, Inc. All rights reserved. 4*17ce2522SLizhi Hou * Copyright (C) 2022, Advanced Micro Devices, Inc. 5*17ce2522SLizhi Hou */ 6*17ce2522SLizhi Hou 7*17ce2522SLizhi Hou #ifndef __DMA_XDMA_REGS_H 8*17ce2522SLizhi Hou #define __DMA_XDMA_REGS_H 9*17ce2522SLizhi Hou 10*17ce2522SLizhi Hou /* The length of register space exposed to host */ 11*17ce2522SLizhi Hou #define XDMA_REG_SPACE_LEN 65536 12*17ce2522SLizhi Hou 13*17ce2522SLizhi Hou /* 14*17ce2522SLizhi Hou * maximum number of DMA channels for each direction: 15*17ce2522SLizhi Hou * Host to Card (H2C) or Card to Host (C2H) 16*17ce2522SLizhi Hou */ 17*17ce2522SLizhi Hou #define XDMA_MAX_CHANNELS 4 18*17ce2522SLizhi Hou 19*17ce2522SLizhi Hou /* 20*17ce2522SLizhi Hou * macros to define the number of descriptor blocks can be used in one 21*17ce2522SLizhi Hou * DMA transfer request. 22*17ce2522SLizhi Hou * the DMA engine uses a linked list of descriptor blocks that specify the 23*17ce2522SLizhi Hou * source, destination, and length of the DMA transfers. 24*17ce2522SLizhi Hou */ 25*17ce2522SLizhi Hou #define XDMA_DESC_BLOCK_NUM BIT(7) 26*17ce2522SLizhi Hou #define XDMA_DESC_BLOCK_MASK (XDMA_DESC_BLOCK_NUM - 1) 27*17ce2522SLizhi Hou 28*17ce2522SLizhi Hou /* descriptor definitions */ 29*17ce2522SLizhi Hou #define XDMA_DESC_ADJACENT 32 30*17ce2522SLizhi Hou #define XDMA_DESC_ADJACENT_MASK (XDMA_DESC_ADJACENT - 1) 31*17ce2522SLizhi Hou #define XDMA_DESC_ADJACENT_BITS GENMASK(13, 8) 32*17ce2522SLizhi Hou #define XDMA_DESC_MAGIC 0xad4bUL 33*17ce2522SLizhi Hou #define XDMA_DESC_MAGIC_BITS GENMASK(31, 16) 34*17ce2522SLizhi Hou #define XDMA_DESC_FLAGS_BITS GENMASK(7, 0) 35*17ce2522SLizhi Hou #define XDMA_DESC_STOPPED BIT(0) 36*17ce2522SLizhi Hou #define XDMA_DESC_COMPLETED BIT(1) 37*17ce2522SLizhi Hou #define XDMA_DESC_BLEN_BITS 28 38*17ce2522SLizhi Hou #define XDMA_DESC_BLEN_MAX (BIT(XDMA_DESC_BLEN_BITS) - PAGE_SIZE) 39*17ce2522SLizhi Hou 40*17ce2522SLizhi Hou /* macros to construct the descriptor control word */ 41*17ce2522SLizhi Hou #define XDMA_DESC_CONTROL(adjacent, flag) \ 42*17ce2522SLizhi Hou (FIELD_PREP(XDMA_DESC_MAGIC_BITS, XDMA_DESC_MAGIC) | \ 43*17ce2522SLizhi Hou FIELD_PREP(XDMA_DESC_ADJACENT_BITS, (adjacent) - 1) | \ 44*17ce2522SLizhi Hou FIELD_PREP(XDMA_DESC_FLAGS_BITS, (flag))) 45*17ce2522SLizhi Hou #define XDMA_DESC_CONTROL_LAST \ 46*17ce2522SLizhi Hou XDMA_DESC_CONTROL(1, XDMA_DESC_STOPPED | XDMA_DESC_COMPLETED) 47*17ce2522SLizhi Hou 48*17ce2522SLizhi Hou /* 49*17ce2522SLizhi Hou * Descriptor for a single contiguous memory block transfer. 50*17ce2522SLizhi Hou * 51*17ce2522SLizhi Hou * Multiple descriptors are linked by means of the next pointer. An additional 52*17ce2522SLizhi Hou * extra adjacent number gives the amount of extra contiguous descriptors. 53*17ce2522SLizhi Hou * 54*17ce2522SLizhi Hou * The descriptors are in root complex memory, and the bytes in the 32-bit 55*17ce2522SLizhi Hou * words must be in little-endian byte ordering. 56*17ce2522SLizhi Hou */ 57*17ce2522SLizhi Hou struct xdma_hw_desc { 58*17ce2522SLizhi Hou __le32 control; 59*17ce2522SLizhi Hou __le32 bytes; 60*17ce2522SLizhi Hou __le64 src_addr; 61*17ce2522SLizhi Hou __le64 dst_addr; 62*17ce2522SLizhi Hou __le64 next_desc; 63*17ce2522SLizhi Hou }; 64*17ce2522SLizhi Hou 65*17ce2522SLizhi Hou #define XDMA_DESC_SIZE sizeof(struct xdma_hw_desc) 66*17ce2522SLizhi Hou #define XDMA_DESC_BLOCK_SIZE (XDMA_DESC_SIZE * XDMA_DESC_ADJACENT) 67*17ce2522SLizhi Hou #define XDMA_DESC_BLOCK_ALIGN 4096 68*17ce2522SLizhi Hou 69*17ce2522SLizhi Hou /* 70*17ce2522SLizhi Hou * Channel registers 71*17ce2522SLizhi Hou */ 72*17ce2522SLizhi Hou #define XDMA_CHAN_IDENTIFIER 0x0 73*17ce2522SLizhi Hou #define XDMA_CHAN_CONTROL 0x4 74*17ce2522SLizhi Hou #define XDMA_CHAN_CONTROL_W1S 0x8 75*17ce2522SLizhi Hou #define XDMA_CHAN_CONTROL_W1C 0xc 76*17ce2522SLizhi Hou #define XDMA_CHAN_STATUS 0x40 77*17ce2522SLizhi Hou #define XDMA_CHAN_COMPLETED_DESC 0x48 78*17ce2522SLizhi Hou #define XDMA_CHAN_ALIGNMENTS 0x4c 79*17ce2522SLizhi Hou #define XDMA_CHAN_INTR_ENABLE 0x90 80*17ce2522SLizhi Hou #define XDMA_CHAN_INTR_ENABLE_W1S 0x94 81*17ce2522SLizhi Hou #define XDMA_CHAN_INTR_ENABLE_W1C 0x9c 82*17ce2522SLizhi Hou 83*17ce2522SLizhi Hou #define XDMA_CHAN_STRIDE 0x100 84*17ce2522SLizhi Hou #define XDMA_CHAN_H2C_OFFSET 0x0 85*17ce2522SLizhi Hou #define XDMA_CHAN_C2H_OFFSET 0x1000 86*17ce2522SLizhi Hou #define XDMA_CHAN_H2C_TARGET 0x0 87*17ce2522SLizhi Hou #define XDMA_CHAN_C2H_TARGET 0x1 88*17ce2522SLizhi Hou 89*17ce2522SLizhi Hou /* macro to check if channel is available */ 90*17ce2522SLizhi Hou #define XDMA_CHAN_MAGIC 0x1fc0 91*17ce2522SLizhi Hou #define XDMA_CHAN_CHECK_TARGET(id, target) \ 92*17ce2522SLizhi Hou (((u32)(id) >> 16) == XDMA_CHAN_MAGIC + (target)) 93*17ce2522SLizhi Hou 94*17ce2522SLizhi Hou /* bits of the channel control register */ 95*17ce2522SLizhi Hou #define CHAN_CTRL_RUN_STOP BIT(0) 96*17ce2522SLizhi Hou #define CHAN_CTRL_IE_DESC_STOPPED BIT(1) 97*17ce2522SLizhi Hou #define CHAN_CTRL_IE_DESC_COMPLETED BIT(2) 98*17ce2522SLizhi Hou #define CHAN_CTRL_IE_DESC_ALIGN_MISMATCH BIT(3) 99*17ce2522SLizhi Hou #define CHAN_CTRL_IE_MAGIC_STOPPED BIT(4) 100*17ce2522SLizhi Hou #define CHAN_CTRL_IE_IDLE_STOPPED BIT(6) 101*17ce2522SLizhi Hou #define CHAN_CTRL_IE_READ_ERROR GENMASK(13, 9) 102*17ce2522SLizhi Hou #define CHAN_CTRL_IE_DESC_ERROR GENMASK(23, 19) 103*17ce2522SLizhi Hou #define CHAN_CTRL_NON_INCR_ADDR BIT(25) 104*17ce2522SLizhi Hou #define CHAN_CTRL_POLL_MODE_WB BIT(26) 105*17ce2522SLizhi Hou 106*17ce2522SLizhi Hou #define CHAN_CTRL_START (CHAN_CTRL_RUN_STOP | \ 107*17ce2522SLizhi Hou CHAN_CTRL_IE_DESC_STOPPED | \ 108*17ce2522SLizhi Hou CHAN_CTRL_IE_DESC_COMPLETED | \ 109*17ce2522SLizhi Hou CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \ 110*17ce2522SLizhi Hou CHAN_CTRL_IE_MAGIC_STOPPED | \ 111*17ce2522SLizhi Hou CHAN_CTRL_IE_READ_ERROR | \ 112*17ce2522SLizhi Hou CHAN_CTRL_IE_DESC_ERROR) 113*17ce2522SLizhi Hou 114*17ce2522SLizhi Hou /* bits of the channel interrupt enable mask */ 115*17ce2522SLizhi Hou #define CHAN_IM_DESC_ERROR BIT(19) 116*17ce2522SLizhi Hou #define CHAN_IM_READ_ERROR BIT(9) 117*17ce2522SLizhi Hou #define CHAN_IM_IDLE_STOPPED BIT(6) 118*17ce2522SLizhi Hou #define CHAN_IM_MAGIC_STOPPED BIT(4) 119*17ce2522SLizhi Hou #define CHAN_IM_DESC_COMPLETED BIT(2) 120*17ce2522SLizhi Hou #define CHAN_IM_DESC_STOPPED BIT(1) 121*17ce2522SLizhi Hou 122*17ce2522SLizhi Hou #define CHAN_IM_ALL (CHAN_IM_DESC_ERROR | CHAN_IM_READ_ERROR | \ 123*17ce2522SLizhi Hou CHAN_IM_IDLE_STOPPED | CHAN_IM_MAGIC_STOPPED | \ 124*17ce2522SLizhi Hou CHAN_IM_DESC_COMPLETED | CHAN_IM_DESC_STOPPED) 125*17ce2522SLizhi Hou 126*17ce2522SLizhi Hou /* 127*17ce2522SLizhi Hou * Channel SGDMA registers 128*17ce2522SLizhi Hou */ 129*17ce2522SLizhi Hou #define XDMA_SGDMA_IDENTIFIER 0x4000 130*17ce2522SLizhi Hou #define XDMA_SGDMA_DESC_LO 0x4080 131*17ce2522SLizhi Hou #define XDMA_SGDMA_DESC_HI 0x4084 132*17ce2522SLizhi Hou #define XDMA_SGDMA_DESC_ADJ 0x4088 133*17ce2522SLizhi Hou #define XDMA_SGDMA_DESC_CREDIT 0x408c 134*17ce2522SLizhi Hou 135*17ce2522SLizhi Hou /* bits of the SG DMA control register */ 136*17ce2522SLizhi Hou #define XDMA_CTRL_RUN_STOP BIT(0) 137*17ce2522SLizhi Hou #define XDMA_CTRL_IE_DESC_STOPPED BIT(1) 138*17ce2522SLizhi Hou #define XDMA_CTRL_IE_DESC_COMPLETED BIT(2) 139*17ce2522SLizhi Hou #define XDMA_CTRL_IE_DESC_ALIGN_MISMATCH BIT(3) 140*17ce2522SLizhi Hou #define XDMA_CTRL_IE_MAGIC_STOPPED BIT(4) 141*17ce2522SLizhi Hou #define XDMA_CTRL_IE_IDLE_STOPPED BIT(6) 142*17ce2522SLizhi Hou #define XDMA_CTRL_IE_READ_ERROR GENMASK(13, 9) 143*17ce2522SLizhi Hou #define XDMA_CTRL_IE_DESC_ERROR GENMASK(23, 19) 144*17ce2522SLizhi Hou #define XDMA_CTRL_NON_INCR_ADDR BIT(25) 145*17ce2522SLizhi Hou #define XDMA_CTRL_POLL_MODE_WB BIT(26) 146*17ce2522SLizhi Hou 147*17ce2522SLizhi Hou /* 148*17ce2522SLizhi Hou * interrupt registers 149*17ce2522SLizhi Hou */ 150*17ce2522SLizhi Hou #define XDMA_IRQ_IDENTIFIER 0x2000 151*17ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_EN 0x2004 152*17ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_EN_W1S 0x2008 153*17ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_EN_W1C 0x200c 154*17ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_EN 0x2010 155*17ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_EN_W1S 0x2014 156*17ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_EN_W1C 0x2018 157*17ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_REQ 0x2040 158*17ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_REQ 0x2044 159*17ce2522SLizhi Hou #define XDMA_IRQ_USER_INT_PEND 0x2048 160*17ce2522SLizhi Hou #define XDMA_IRQ_CHAN_INT_PEND 0x204c 161*17ce2522SLizhi Hou #define XDMA_IRQ_USER_VEC_NUM 0x2080 162*17ce2522SLizhi Hou #define XDMA_IRQ_CHAN_VEC_NUM 0x20a0 163*17ce2522SLizhi Hou 164*17ce2522SLizhi Hou #define XDMA_IRQ_VEC_SHIFT 8 165*17ce2522SLizhi Hou 166*17ce2522SLizhi Hou #endif /* __DMA_XDMA_REGS_H */ 167