1 /* 2 * Applied Micro X-Gene SoC DMA engine Driver 3 * 4 * Copyright (c) 2015, Applied Micro Circuits Corporation 5 * Authors: Rameshwar Prasad Sahu <rsahu@apm.com> 6 * Loc Ho <lho@apm.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program. If not, see <http://www.gnu.org/licenses/>. 20 * 21 * NOTE: PM support is currently not available. 22 */ 23 24 #include <linux/acpi.h> 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/dmapool.h> 30 #include <linux/interrupt.h> 31 #include <linux/io.h> 32 #include <linux/irq.h> 33 #include <linux/module.h> 34 #include <linux/of_device.h> 35 36 #include "dmaengine.h" 37 38 /* X-Gene DMA ring csr registers and bit definations */ 39 #define XGENE_DMA_RING_CONFIG 0x04 40 #define XGENE_DMA_RING_ENABLE BIT(31) 41 #define XGENE_DMA_RING_ID 0x08 42 #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31)) 43 #define XGENE_DMA_RING_ID_BUF 0x0C 44 #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21)) 45 #define XGENE_DMA_RING_THRESLD0_SET1 0x30 46 #define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64 47 #define XGENE_DMA_RING_THRESLD1_SET1 0x34 48 #define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8 49 #define XGENE_DMA_RING_HYSTERESIS 0x68 50 #define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF 51 #define XGENE_DMA_RING_STATE 0x6C 52 #define XGENE_DMA_RING_STATE_WR_BASE 0x70 53 #define XGENE_DMA_RING_NE_INT_MODE 0x017C 54 #define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \ 55 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v))) 56 #define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \ 57 ((m) &= (~BIT(31 - (v)))) 58 #define XGENE_DMA_RING_CLKEN 0xC208 59 #define XGENE_DMA_RING_SRST 0xC200 60 #define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070 61 #define XGENE_DMA_RING_BLK_MEM_RDY 0xD074 62 #define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF 63 #define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num)) 64 #define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v)) 65 #define XGENE_DMA_RING_CMD_OFFSET 0x2C 66 #define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6) 67 #define XGENE_DMA_RING_COHERENT_SET(m) \ 68 (((u32 *)(m))[2] |= BIT(4)) 69 #define XGENE_DMA_RING_ADDRL_SET(m, v) \ 70 (((u32 *)(m))[2] |= (((v) >> 8) << 5)) 71 #define XGENE_DMA_RING_ADDRH_SET(m, v) \ 72 (((u32 *)(m))[3] |= ((v) >> 35)) 73 #define XGENE_DMA_RING_ACCEPTLERR_SET(m) \ 74 (((u32 *)(m))[3] |= BIT(19)) 75 #define XGENE_DMA_RING_SIZE_SET(m, v) \ 76 (((u32 *)(m))[3] |= ((v) << 23)) 77 #define XGENE_DMA_RING_RECOMBBUF_SET(m) \ 78 (((u32 *)(m))[3] |= BIT(27)) 79 #define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \ 80 (((u32 *)(m))[3] |= (0x7 << 28)) 81 #define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \ 82 (((u32 *)(m))[4] |= 0x3) 83 #define XGENE_DMA_RING_SELTHRSH_SET(m) \ 84 (((u32 *)(m))[4] |= BIT(3)) 85 #define XGENE_DMA_RING_TYPE_SET(m, v) \ 86 (((u32 *)(m))[4] |= ((v) << 19)) 87 88 /* X-Gene DMA device csr registers and bit definitions */ 89 #define XGENE_DMA_IPBRR 0x0 90 #define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF) 91 #define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3) 92 #define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3) 93 #define XGENE_DMA_GCR 0x10 94 #define XGENE_DMA_CH_SETUP(v) \ 95 ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF) 96 #define XGENE_DMA_ENABLE(v) ((v) |= BIT(31)) 97 #define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31)) 98 #define XGENE_DMA_RAID6_CONT 0x14 99 #define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24) 100 #define XGENE_DMA_INT 0x70 101 #define XGENE_DMA_INT_MASK 0x74 102 #define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF 103 #define XGENE_DMA_INT_ALL_UNMASK 0x0 104 #define XGENE_DMA_INT_MASK_SHIFT 0x14 105 #define XGENE_DMA_RING_INT0_MASK 0x90A0 106 #define XGENE_DMA_RING_INT1_MASK 0x90A8 107 #define XGENE_DMA_RING_INT2_MASK 0x90B0 108 #define XGENE_DMA_RING_INT3_MASK 0x90B8 109 #define XGENE_DMA_RING_INT4_MASK 0x90C0 110 #define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0 111 #define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF 112 #define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070 113 #define XGENE_DMA_BLK_MEM_RDY 0xD074 114 #define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF 115 #define XGENE_DMA_RING_CMD_SM_OFFSET 0x8000 116 117 /* X-Gene SoC EFUSE csr register and bit defination */ 118 #define XGENE_SOC_JTAG1_SHADOW 0x18 119 #define XGENE_DMA_PQ_DISABLE_MASK BIT(13) 120 121 /* X-Gene DMA Descriptor format */ 122 #define XGENE_DMA_DESC_NV_BIT BIT_ULL(50) 123 #define XGENE_DMA_DESC_IN_BIT BIT_ULL(55) 124 #define XGENE_DMA_DESC_C_BIT BIT_ULL(63) 125 #define XGENE_DMA_DESC_DR_BIT BIT_ULL(61) 126 #define XGENE_DMA_DESC_ELERR_POS 46 127 #define XGENE_DMA_DESC_RTYPE_POS 56 128 #define XGENE_DMA_DESC_LERR_POS 60 129 #define XGENE_DMA_DESC_BUFLEN_POS 48 130 #define XGENE_DMA_DESC_HOENQ_NUM_POS 48 131 #define XGENE_DMA_DESC_ELERR_RD(m) \ 132 (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3) 133 #define XGENE_DMA_DESC_LERR_RD(m) \ 134 (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7) 135 #define XGENE_DMA_DESC_STATUS(elerr, lerr) \ 136 (((elerr) << 4) | (lerr)) 137 138 /* X-Gene DMA descriptor empty s/w signature */ 139 #define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL 140 141 /* X-Gene DMA configurable parameters defines */ 142 #define XGENE_DMA_RING_NUM 512 143 #define XGENE_DMA_BUFNUM 0x0 144 #define XGENE_DMA_CPU_BUFNUM 0x18 145 #define XGENE_DMA_RING_OWNER_DMA 0x03 146 #define XGENE_DMA_RING_OWNER_CPU 0x0F 147 #define XGENE_DMA_RING_TYPE_REGULAR 0x01 148 #define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */ 149 #define XGENE_DMA_RING_NUM_CONFIG 5 150 #define XGENE_DMA_MAX_CHANNEL 4 151 #define XGENE_DMA_XOR_CHANNEL 0 152 #define XGENE_DMA_PQ_CHANNEL 1 153 #define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */ 154 #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */ 155 #define XGENE_DMA_MAX_XOR_SRC 5 156 #define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0 157 #define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL 158 159 /* X-Gene DMA descriptor error codes */ 160 #define ERR_DESC_AXI 0x01 161 #define ERR_BAD_DESC 0x02 162 #define ERR_READ_DATA_AXI 0x03 163 #define ERR_WRITE_DATA_AXI 0x04 164 #define ERR_FBP_TIMEOUT 0x05 165 #define ERR_ECC 0x06 166 #define ERR_DIFF_SIZE 0x08 167 #define ERR_SCT_GAT_LEN 0x09 168 #define ERR_CRC_ERR 0x11 169 #define ERR_CHKSUM 0x12 170 #define ERR_DIF 0x13 171 172 /* X-Gene DMA error interrupt codes */ 173 #define ERR_DIF_SIZE_INT 0x0 174 #define ERR_GS_ERR_INT 0x1 175 #define ERR_FPB_TIMEO_INT 0x2 176 #define ERR_WFIFO_OVF_INT 0x3 177 #define ERR_RFIFO_OVF_INT 0x4 178 #define ERR_WR_TIMEO_INT 0x5 179 #define ERR_RD_TIMEO_INT 0x6 180 #define ERR_WR_ERR_INT 0x7 181 #define ERR_RD_ERR_INT 0x8 182 #define ERR_BAD_DESC_INT 0x9 183 #define ERR_DESC_DST_INT 0xA 184 #define ERR_DESC_SRC_INT 0xB 185 186 /* X-Gene DMA flyby operation code */ 187 #define FLYBY_2SRC_XOR 0x80 188 #define FLYBY_3SRC_XOR 0x90 189 #define FLYBY_4SRC_XOR 0xA0 190 #define FLYBY_5SRC_XOR 0xB0 191 192 /* X-Gene DMA SW descriptor flags */ 193 #define XGENE_DMA_FLAG_64B_DESC BIT(0) 194 195 /* Define to dump X-Gene DMA descriptor */ 196 #define XGENE_DMA_DESC_DUMP(desc, m) \ 197 print_hex_dump(KERN_ERR, (m), \ 198 DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0) 199 200 #define to_dma_desc_sw(tx) \ 201 container_of(tx, struct xgene_dma_desc_sw, tx) 202 #define to_dma_chan(dchan) \ 203 container_of(dchan, struct xgene_dma_chan, dma_chan) 204 205 #define chan_dbg(chan, fmt, arg...) \ 206 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) 207 #define chan_err(chan, fmt, arg...) \ 208 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) 209 210 struct xgene_dma_desc_hw { 211 __le64 m0; 212 __le64 m1; 213 __le64 m2; 214 __le64 m3; 215 }; 216 217 enum xgene_dma_ring_cfgsize { 218 XGENE_DMA_RING_CFG_SIZE_512B, 219 XGENE_DMA_RING_CFG_SIZE_2KB, 220 XGENE_DMA_RING_CFG_SIZE_16KB, 221 XGENE_DMA_RING_CFG_SIZE_64KB, 222 XGENE_DMA_RING_CFG_SIZE_512KB, 223 XGENE_DMA_RING_CFG_SIZE_INVALID 224 }; 225 226 struct xgene_dma_ring { 227 struct xgene_dma *pdma; 228 u8 buf_num; 229 u16 id; 230 u16 num; 231 u16 head; 232 u16 owner; 233 u16 slots; 234 u16 dst_ring_num; 235 u32 size; 236 void __iomem *cmd; 237 void __iomem *cmd_base; 238 dma_addr_t desc_paddr; 239 u32 state[XGENE_DMA_RING_NUM_CONFIG]; 240 enum xgene_dma_ring_cfgsize cfgsize; 241 union { 242 void *desc_vaddr; 243 struct xgene_dma_desc_hw *desc_hw; 244 }; 245 }; 246 247 struct xgene_dma_desc_sw { 248 struct xgene_dma_desc_hw desc1; 249 struct xgene_dma_desc_hw desc2; 250 u32 flags; 251 struct list_head node; 252 struct list_head tx_list; 253 struct dma_async_tx_descriptor tx; 254 }; 255 256 /** 257 * struct xgene_dma_chan - internal representation of an X-Gene DMA channel 258 * @dma_chan: dmaengine channel object member 259 * @pdma: X-Gene DMA device structure reference 260 * @dev: struct device reference for dma mapping api 261 * @id: raw id of this channel 262 * @rx_irq: channel IRQ 263 * @name: name of X-Gene DMA channel 264 * @lock: serializes enqueue/dequeue operations to the descriptor pool 265 * @pending: number of transaction request pushed to DMA controller for 266 * execution, but still waiting for completion, 267 * @max_outstanding: max number of outstanding request we can push to channel 268 * @ld_pending: descriptors which are queued to run, but have not yet been 269 * submitted to the hardware for execution 270 * @ld_running: descriptors which are currently being executing by the hardware 271 * @ld_completed: descriptors which have finished execution by the hardware. 272 * These descriptors have already had their cleanup actions run. They 273 * are waiting for the ACK bit to be set by the async tx API. 274 * @desc_pool: descriptor pool for DMA operations 275 * @tasklet: bottom half where all completed descriptors cleans 276 * @tx_ring: transmit ring descriptor that we use to prepare actual 277 * descriptors for further executions 278 * @rx_ring: receive ring descriptor that we use to get completed DMA 279 * descriptors during cleanup time 280 */ 281 struct xgene_dma_chan { 282 struct dma_chan dma_chan; 283 struct xgene_dma *pdma; 284 struct device *dev; 285 int id; 286 int rx_irq; 287 char name[10]; 288 spinlock_t lock; 289 int pending; 290 int max_outstanding; 291 struct list_head ld_pending; 292 struct list_head ld_running; 293 struct list_head ld_completed; 294 struct dma_pool *desc_pool; 295 struct tasklet_struct tasklet; 296 struct xgene_dma_ring tx_ring; 297 struct xgene_dma_ring rx_ring; 298 }; 299 300 /** 301 * struct xgene_dma - internal representation of an X-Gene DMA device 302 * @err_irq: DMA error irq number 303 * @ring_num: start id number for DMA ring 304 * @csr_dma: base for DMA register access 305 * @csr_ring: base for DMA ring register access 306 * @csr_ring_cmd: base for DMA ring command register access 307 * @csr_efuse: base for efuse register access 308 * @dma_dev: embedded struct dma_device 309 * @chan: reference to X-Gene DMA channels 310 */ 311 struct xgene_dma { 312 struct device *dev; 313 struct clk *clk; 314 int err_irq; 315 int ring_num; 316 void __iomem *csr_dma; 317 void __iomem *csr_ring; 318 void __iomem *csr_ring_cmd; 319 void __iomem *csr_efuse; 320 struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL]; 321 struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL]; 322 }; 323 324 static const char * const xgene_dma_desc_err[] = { 325 [ERR_DESC_AXI] = "AXI error when reading src/dst link list", 326 [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc", 327 [ERR_READ_DATA_AXI] = "AXI error when reading data", 328 [ERR_WRITE_DATA_AXI] = "AXI error when writing data", 329 [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch", 330 [ERR_ECC] = "ECC double bit error", 331 [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result", 332 [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same", 333 [ERR_CRC_ERR] = "CRC error", 334 [ERR_CHKSUM] = "Checksum error", 335 [ERR_DIF] = "DIF error", 336 }; 337 338 static const char * const xgene_dma_err[] = { 339 [ERR_DIF_SIZE_INT] = "DIF size error", 340 [ERR_GS_ERR_INT] = "Gather scatter not same size error", 341 [ERR_FPB_TIMEO_INT] = "Free pool time out error", 342 [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error", 343 [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error", 344 [ERR_WR_TIMEO_INT] = "Write time out error", 345 [ERR_RD_TIMEO_INT] = "Read time out error", 346 [ERR_WR_ERR_INT] = "HBF bus write error", 347 [ERR_RD_ERR_INT] = "HBF bus read error", 348 [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error", 349 [ERR_DESC_DST_INT] = "HFB reading dst link address error", 350 [ERR_DESC_SRC_INT] = "HFB reading src link address error", 351 }; 352 353 static bool is_pq_enabled(struct xgene_dma *pdma) 354 { 355 u32 val; 356 357 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW); 358 return !(val & XGENE_DMA_PQ_DISABLE_MASK); 359 } 360 361 static u64 xgene_dma_encode_len(size_t len) 362 { 363 return (len < XGENE_DMA_MAX_BYTE_CNT) ? 364 ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) : 365 XGENE_DMA_16K_BUFFER_LEN_CODE; 366 } 367 368 static u8 xgene_dma_encode_xor_flyby(u32 src_cnt) 369 { 370 static u8 flyby_type[] = { 371 FLYBY_2SRC_XOR, /* Dummy */ 372 FLYBY_2SRC_XOR, /* Dummy */ 373 FLYBY_2SRC_XOR, 374 FLYBY_3SRC_XOR, 375 FLYBY_4SRC_XOR, 376 FLYBY_5SRC_XOR 377 }; 378 379 return flyby_type[src_cnt]; 380 } 381 382 static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len, 383 dma_addr_t *paddr) 384 { 385 size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ? 386 *len : XGENE_DMA_MAX_BYTE_CNT; 387 388 *ext8 |= cpu_to_le64(*paddr); 389 *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes)); 390 *len -= nbytes; 391 *paddr += nbytes; 392 } 393 394 static void xgene_dma_invalidate_buffer(__le64 *ext8) 395 { 396 *ext8 |= cpu_to_le64(XGENE_DMA_INVALID_LEN_CODE); 397 } 398 399 static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx) 400 { 401 switch (idx) { 402 case 0: 403 return &desc->m1; 404 case 1: 405 return &desc->m0; 406 case 2: 407 return &desc->m3; 408 case 3: 409 return &desc->m2; 410 default: 411 pr_err("Invalid dma descriptor index\n"); 412 } 413 414 return NULL; 415 } 416 417 static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc, 418 u16 dst_ring_num) 419 { 420 desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT); 421 desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA << 422 XGENE_DMA_DESC_RTYPE_POS); 423 desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT); 424 desc->m3 |= cpu_to_le64((u64)dst_ring_num << 425 XGENE_DMA_DESC_HOENQ_NUM_POS); 426 } 427 428 static void xgene_dma_prep_cpy_desc(struct xgene_dma_chan *chan, 429 struct xgene_dma_desc_sw *desc_sw, 430 dma_addr_t dst, dma_addr_t src, 431 size_t len) 432 { 433 struct xgene_dma_desc_hw *desc1, *desc2; 434 int i; 435 436 /* Get 1st descriptor */ 437 desc1 = &desc_sw->desc1; 438 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num); 439 440 /* Set destination address */ 441 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT); 442 desc1->m3 |= cpu_to_le64(dst); 443 444 /* Set 1st source address */ 445 xgene_dma_set_src_buffer(&desc1->m1, &len, &src); 446 447 if (!len) 448 return; 449 450 /* 451 * We need to split this source buffer, 452 * and need to use 2nd descriptor 453 */ 454 desc2 = &desc_sw->desc2; 455 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT); 456 457 /* Set 2nd to 5th source address */ 458 for (i = 0; i < 4 && len; i++) 459 xgene_dma_set_src_buffer(xgene_dma_lookup_ext8(desc2, i), 460 &len, &src); 461 462 /* Invalidate unused source address field */ 463 for (; i < 4; i++) 464 xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i)); 465 466 /* Updated flag that we have prepared 64B descriptor */ 467 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC; 468 } 469 470 static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan, 471 struct xgene_dma_desc_sw *desc_sw, 472 dma_addr_t *dst, dma_addr_t *src, 473 u32 src_cnt, size_t *nbytes, 474 const u8 *scf) 475 { 476 struct xgene_dma_desc_hw *desc1, *desc2; 477 size_t len = *nbytes; 478 int i; 479 480 desc1 = &desc_sw->desc1; 481 desc2 = &desc_sw->desc2; 482 483 /* Initialize DMA descriptor */ 484 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num); 485 486 /* Set destination address */ 487 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT); 488 desc1->m3 |= cpu_to_le64(*dst); 489 490 /* We have multiple source addresses, so need to set NV bit*/ 491 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT); 492 493 /* Set flyby opcode */ 494 desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt)); 495 496 /* Set 1st to 5th source addresses */ 497 for (i = 0; i < src_cnt; i++) { 498 len = *nbytes; 499 xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 : 500 xgene_dma_lookup_ext8(desc2, i - 1), 501 &len, &src[i]); 502 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8))); 503 } 504 505 /* Update meta data */ 506 *nbytes = len; 507 *dst += XGENE_DMA_MAX_BYTE_CNT; 508 509 /* We need always 64B descriptor to perform xor or pq operations */ 510 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC; 511 } 512 513 static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx) 514 { 515 struct xgene_dma_desc_sw *desc; 516 struct xgene_dma_chan *chan; 517 dma_cookie_t cookie; 518 519 if (unlikely(!tx)) 520 return -EINVAL; 521 522 chan = to_dma_chan(tx->chan); 523 desc = to_dma_desc_sw(tx); 524 525 spin_lock_bh(&chan->lock); 526 527 cookie = dma_cookie_assign(tx); 528 529 /* Add this transaction list onto the tail of the pending queue */ 530 list_splice_tail_init(&desc->tx_list, &chan->ld_pending); 531 532 spin_unlock_bh(&chan->lock); 533 534 return cookie; 535 } 536 537 static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan, 538 struct xgene_dma_desc_sw *desc) 539 { 540 list_del(&desc->node); 541 chan_dbg(chan, "LD %p free\n", desc); 542 dma_pool_free(chan->desc_pool, desc, desc->tx.phys); 543 } 544 545 static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor( 546 struct xgene_dma_chan *chan) 547 { 548 struct xgene_dma_desc_sw *desc; 549 dma_addr_t phys; 550 551 desc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys); 552 if (!desc) { 553 chan_err(chan, "Failed to allocate LDs\n"); 554 return NULL; 555 } 556 557 INIT_LIST_HEAD(&desc->tx_list); 558 desc->tx.phys = phys; 559 desc->tx.tx_submit = xgene_dma_tx_submit; 560 dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan); 561 562 chan_dbg(chan, "LD %p allocated\n", desc); 563 564 return desc; 565 } 566 567 /** 568 * xgene_dma_clean_completed_descriptor - free all descriptors which 569 * has been completed and acked 570 * @chan: X-Gene DMA channel 571 * 572 * This function is used on all completed and acked descriptors. 573 */ 574 static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan) 575 { 576 struct xgene_dma_desc_sw *desc, *_desc; 577 578 /* Run the callback for each descriptor, in order */ 579 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) { 580 if (async_tx_test_ack(&desc->tx)) 581 xgene_dma_clean_descriptor(chan, desc); 582 } 583 } 584 585 /** 586 * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor 587 * @chan: X-Gene DMA channel 588 * @desc: descriptor to cleanup and free 589 * 590 * This function is used on a descriptor which has been executed by the DMA 591 * controller. It will run any callbacks, submit any dependencies. 592 */ 593 static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan, 594 struct xgene_dma_desc_sw *desc) 595 { 596 struct dma_async_tx_descriptor *tx = &desc->tx; 597 598 /* 599 * If this is not the last transaction in the group, 600 * then no need to complete cookie and run any callback as 601 * this is not the tx_descriptor which had been sent to caller 602 * of this DMA request 603 */ 604 605 if (tx->cookie == 0) 606 return; 607 608 dma_cookie_complete(tx); 609 dma_descriptor_unmap(tx); 610 611 /* Run the link descriptor callback function */ 612 dmaengine_desc_get_callback_invoke(tx, NULL); 613 614 /* Run any dependencies */ 615 dma_run_dependencies(tx); 616 } 617 618 /** 619 * xgene_dma_clean_running_descriptor - move the completed descriptor from 620 * ld_running to ld_completed 621 * @chan: X-Gene DMA channel 622 * @desc: the descriptor which is completed 623 * 624 * Free the descriptor directly if acked by async_tx api, 625 * else move it to queue ld_completed. 626 */ 627 static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan, 628 struct xgene_dma_desc_sw *desc) 629 { 630 /* Remove from the list of running transactions */ 631 list_del(&desc->node); 632 633 /* 634 * the client is allowed to attach dependent operations 635 * until 'ack' is set 636 */ 637 if (!async_tx_test_ack(&desc->tx)) { 638 /* 639 * Move this descriptor to the list of descriptors which is 640 * completed, but still awaiting the 'ack' bit to be set. 641 */ 642 list_add_tail(&desc->node, &chan->ld_completed); 643 return; 644 } 645 646 chan_dbg(chan, "LD %p free\n", desc); 647 dma_pool_free(chan->desc_pool, desc, desc->tx.phys); 648 } 649 650 static void xgene_chan_xfer_request(struct xgene_dma_chan *chan, 651 struct xgene_dma_desc_sw *desc_sw) 652 { 653 struct xgene_dma_ring *ring = &chan->tx_ring; 654 struct xgene_dma_desc_hw *desc_hw; 655 656 /* Get hw descriptor from DMA tx ring */ 657 desc_hw = &ring->desc_hw[ring->head]; 658 659 /* 660 * Increment the head count to point next 661 * descriptor for next time 662 */ 663 if (++ring->head == ring->slots) 664 ring->head = 0; 665 666 /* Copy prepared sw descriptor data to hw descriptor */ 667 memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw)); 668 669 /* 670 * Check if we have prepared 64B descriptor, 671 * in this case we need one more hw descriptor 672 */ 673 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) { 674 desc_hw = &ring->desc_hw[ring->head]; 675 676 if (++ring->head == ring->slots) 677 ring->head = 0; 678 679 memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw)); 680 } 681 682 /* Increment the pending transaction count */ 683 chan->pending += ((desc_sw->flags & 684 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1); 685 686 /* Notify the hw that we have descriptor ready for execution */ 687 iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ? 688 2 : 1, ring->cmd); 689 } 690 691 /** 692 * xgene_chan_xfer_ld_pending - push any pending transactions to hw 693 * @chan : X-Gene DMA channel 694 * 695 * LOCKING: must hold chan->lock 696 */ 697 static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan) 698 { 699 struct xgene_dma_desc_sw *desc_sw, *_desc_sw; 700 701 /* 702 * If the list of pending descriptors is empty, then we 703 * don't need to do any work at all 704 */ 705 if (list_empty(&chan->ld_pending)) { 706 chan_dbg(chan, "No pending LDs\n"); 707 return; 708 } 709 710 /* 711 * Move elements from the queue of pending transactions onto the list 712 * of running transactions and push it to hw for further executions 713 */ 714 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) { 715 /* 716 * Check if have pushed max number of transactions to hw 717 * as capable, so let's stop here and will push remaining 718 * elements from pening ld queue after completing some 719 * descriptors that we have already pushed 720 */ 721 if (chan->pending >= chan->max_outstanding) 722 return; 723 724 xgene_chan_xfer_request(chan, desc_sw); 725 726 /* 727 * Delete this element from ld pending queue and append it to 728 * ld running queue 729 */ 730 list_move_tail(&desc_sw->node, &chan->ld_running); 731 } 732 } 733 734 /** 735 * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed 736 * and move them to ld_completed to free until flag 'ack' is set 737 * @chan: X-Gene DMA channel 738 * 739 * This function is used on descriptors which have been executed by the DMA 740 * controller. It will run any callbacks, submit any dependencies, then 741 * free these descriptors if flag 'ack' is set. 742 */ 743 static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan) 744 { 745 struct xgene_dma_ring *ring = &chan->rx_ring; 746 struct xgene_dma_desc_sw *desc_sw, *_desc_sw; 747 struct xgene_dma_desc_hw *desc_hw; 748 struct list_head ld_completed; 749 u8 status; 750 751 INIT_LIST_HEAD(&ld_completed); 752 753 spin_lock_bh(&chan->lock); 754 755 /* Clean already completed and acked descriptors */ 756 xgene_dma_clean_completed_descriptor(chan); 757 758 /* Move all completed descriptors to ld completed queue, in order */ 759 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) { 760 /* Get subsequent hw descriptor from DMA rx ring */ 761 desc_hw = &ring->desc_hw[ring->head]; 762 763 /* Check if this descriptor has been completed */ 764 if (unlikely(le64_to_cpu(desc_hw->m0) == 765 XGENE_DMA_DESC_EMPTY_SIGNATURE)) 766 break; 767 768 if (++ring->head == ring->slots) 769 ring->head = 0; 770 771 /* Check if we have any error with DMA transactions */ 772 status = XGENE_DMA_DESC_STATUS( 773 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu( 774 desc_hw->m0)), 775 XGENE_DMA_DESC_LERR_RD(le64_to_cpu( 776 desc_hw->m0))); 777 if (status) { 778 /* Print the DMA error type */ 779 chan_err(chan, "%s\n", xgene_dma_desc_err[status]); 780 781 /* 782 * We have DMA transactions error here. Dump DMA Tx 783 * and Rx descriptors for this request */ 784 XGENE_DMA_DESC_DUMP(&desc_sw->desc1, 785 "X-Gene DMA TX DESC1: "); 786 787 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) 788 XGENE_DMA_DESC_DUMP(&desc_sw->desc2, 789 "X-Gene DMA TX DESC2: "); 790 791 XGENE_DMA_DESC_DUMP(desc_hw, 792 "X-Gene DMA RX ERR DESC: "); 793 } 794 795 /* Notify the hw about this completed descriptor */ 796 iowrite32(-1, ring->cmd); 797 798 /* Mark this hw descriptor as processed */ 799 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE); 800 801 /* 802 * Decrement the pending transaction count 803 * as we have processed one 804 */ 805 chan->pending -= ((desc_sw->flags & 806 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1); 807 808 /* 809 * Delete this node from ld running queue and append it to 810 * ld completed queue for further processing 811 */ 812 list_move_tail(&desc_sw->node, &ld_completed); 813 } 814 815 /* 816 * Start any pending transactions automatically 817 * In the ideal case, we keep the DMA controller busy while we go 818 * ahead and free the descriptors below. 819 */ 820 xgene_chan_xfer_ld_pending(chan); 821 822 spin_unlock_bh(&chan->lock); 823 824 /* Run the callback for each descriptor, in order */ 825 list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) { 826 xgene_dma_run_tx_complete_actions(chan, desc_sw); 827 xgene_dma_clean_running_descriptor(chan, desc_sw); 828 } 829 } 830 831 static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan) 832 { 833 struct xgene_dma_chan *chan = to_dma_chan(dchan); 834 835 /* Has this channel already been allocated? */ 836 if (chan->desc_pool) 837 return 1; 838 839 chan->desc_pool = dma_pool_create(chan->name, chan->dev, 840 sizeof(struct xgene_dma_desc_sw), 841 0, 0); 842 if (!chan->desc_pool) { 843 chan_err(chan, "Failed to allocate descriptor pool\n"); 844 return -ENOMEM; 845 } 846 847 chan_dbg(chan, "Allocate descripto pool\n"); 848 849 return 1; 850 } 851 852 /** 853 * xgene_dma_free_desc_list - Free all descriptors in a queue 854 * @chan: X-Gene DMA channel 855 * @list: the list to free 856 * 857 * LOCKING: must hold chan->lock 858 */ 859 static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan, 860 struct list_head *list) 861 { 862 struct xgene_dma_desc_sw *desc, *_desc; 863 864 list_for_each_entry_safe(desc, _desc, list, node) 865 xgene_dma_clean_descriptor(chan, desc); 866 } 867 868 static void xgene_dma_free_chan_resources(struct dma_chan *dchan) 869 { 870 struct xgene_dma_chan *chan = to_dma_chan(dchan); 871 872 chan_dbg(chan, "Free all resources\n"); 873 874 if (!chan->desc_pool) 875 return; 876 877 /* Process all running descriptor */ 878 xgene_dma_cleanup_descriptors(chan); 879 880 spin_lock_bh(&chan->lock); 881 882 /* Clean all link descriptor queues */ 883 xgene_dma_free_desc_list(chan, &chan->ld_pending); 884 xgene_dma_free_desc_list(chan, &chan->ld_running); 885 xgene_dma_free_desc_list(chan, &chan->ld_completed); 886 887 spin_unlock_bh(&chan->lock); 888 889 /* Delete this channel DMA pool */ 890 dma_pool_destroy(chan->desc_pool); 891 chan->desc_pool = NULL; 892 } 893 894 static struct dma_async_tx_descriptor *xgene_dma_prep_sg( 895 struct dma_chan *dchan, struct scatterlist *dst_sg, 896 u32 dst_nents, struct scatterlist *src_sg, 897 u32 src_nents, unsigned long flags) 898 { 899 struct xgene_dma_desc_sw *first = NULL, *new = NULL; 900 struct xgene_dma_chan *chan; 901 size_t dst_avail, src_avail; 902 dma_addr_t dst, src; 903 size_t len; 904 905 if (unlikely(!dchan)) 906 return NULL; 907 908 if (unlikely(!dst_nents || !src_nents)) 909 return NULL; 910 911 if (unlikely(!dst_sg || !src_sg)) 912 return NULL; 913 914 chan = to_dma_chan(dchan); 915 916 /* Get prepared for the loop */ 917 dst_avail = sg_dma_len(dst_sg); 918 src_avail = sg_dma_len(src_sg); 919 dst_nents--; 920 src_nents--; 921 922 /* Run until we are out of scatterlist entries */ 923 while (true) { 924 /* Create the largest transaction possible */ 925 len = min_t(size_t, src_avail, dst_avail); 926 len = min_t(size_t, len, XGENE_DMA_MAX_64B_DESC_BYTE_CNT); 927 if (len == 0) 928 goto fetch; 929 930 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; 931 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; 932 933 /* Allocate the link descriptor from DMA pool */ 934 new = xgene_dma_alloc_descriptor(chan); 935 if (!new) 936 goto fail; 937 938 /* Prepare DMA descriptor */ 939 xgene_dma_prep_cpy_desc(chan, new, dst, src, len); 940 941 if (!first) 942 first = new; 943 944 new->tx.cookie = 0; 945 async_tx_ack(&new->tx); 946 947 /* update metadata */ 948 dst_avail -= len; 949 src_avail -= len; 950 951 /* Insert the link descriptor to the LD ring */ 952 list_add_tail(&new->node, &first->tx_list); 953 954 fetch: 955 /* fetch the next dst scatterlist entry */ 956 if (dst_avail == 0) { 957 /* no more entries: we're done */ 958 if (dst_nents == 0) 959 break; 960 961 /* fetch the next entry: if there are no more: done */ 962 dst_sg = sg_next(dst_sg); 963 if (!dst_sg) 964 break; 965 966 dst_nents--; 967 dst_avail = sg_dma_len(dst_sg); 968 } 969 970 /* fetch the next src scatterlist entry */ 971 if (src_avail == 0) { 972 /* no more entries: we're done */ 973 if (src_nents == 0) 974 break; 975 976 /* fetch the next entry: if there are no more: done */ 977 src_sg = sg_next(src_sg); 978 if (!src_sg) 979 break; 980 981 src_nents--; 982 src_avail = sg_dma_len(src_sg); 983 } 984 } 985 986 if (!new) 987 return NULL; 988 989 new->tx.flags = flags; /* client is in control of this ack */ 990 new->tx.cookie = -EBUSY; 991 list_splice(&first->tx_list, &new->tx_list); 992 993 return &new->tx; 994 fail: 995 if (!first) 996 return NULL; 997 998 xgene_dma_free_desc_list(chan, &first->tx_list); 999 return NULL; 1000 } 1001 1002 static struct dma_async_tx_descriptor *xgene_dma_prep_xor( 1003 struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src, 1004 u32 src_cnt, size_t len, unsigned long flags) 1005 { 1006 struct xgene_dma_desc_sw *first = NULL, *new; 1007 struct xgene_dma_chan *chan; 1008 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = { 1009 0x01, 0x01, 0x01, 0x01, 0x01}; 1010 1011 if (unlikely(!dchan || !len)) 1012 return NULL; 1013 1014 chan = to_dma_chan(dchan); 1015 1016 do { 1017 /* Allocate the link descriptor from DMA pool */ 1018 new = xgene_dma_alloc_descriptor(chan); 1019 if (!new) 1020 goto fail; 1021 1022 /* Prepare xor DMA descriptor */ 1023 xgene_dma_prep_xor_desc(chan, new, &dst, src, 1024 src_cnt, &len, multi); 1025 1026 if (!first) 1027 first = new; 1028 1029 new->tx.cookie = 0; 1030 async_tx_ack(&new->tx); 1031 1032 /* Insert the link descriptor to the LD ring */ 1033 list_add_tail(&new->node, &first->tx_list); 1034 } while (len); 1035 1036 new->tx.flags = flags; /* client is in control of this ack */ 1037 new->tx.cookie = -EBUSY; 1038 list_splice(&first->tx_list, &new->tx_list); 1039 1040 return &new->tx; 1041 1042 fail: 1043 if (!first) 1044 return NULL; 1045 1046 xgene_dma_free_desc_list(chan, &first->tx_list); 1047 return NULL; 1048 } 1049 1050 static struct dma_async_tx_descriptor *xgene_dma_prep_pq( 1051 struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src, 1052 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags) 1053 { 1054 struct xgene_dma_desc_sw *first = NULL, *new; 1055 struct xgene_dma_chan *chan; 1056 size_t _len = len; 1057 dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC]; 1058 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01}; 1059 1060 if (unlikely(!dchan || !len)) 1061 return NULL; 1062 1063 chan = to_dma_chan(dchan); 1064 1065 /* 1066 * Save source addresses on local variable, may be we have to 1067 * prepare two descriptor to generate P and Q if both enabled 1068 * in the flags by client 1069 */ 1070 memcpy(_src, src, sizeof(*src) * src_cnt); 1071 1072 if (flags & DMA_PREP_PQ_DISABLE_P) 1073 len = 0; 1074 1075 if (flags & DMA_PREP_PQ_DISABLE_Q) 1076 _len = 0; 1077 1078 do { 1079 /* Allocate the link descriptor from DMA pool */ 1080 new = xgene_dma_alloc_descriptor(chan); 1081 if (!new) 1082 goto fail; 1083 1084 if (!first) 1085 first = new; 1086 1087 new->tx.cookie = 0; 1088 async_tx_ack(&new->tx); 1089 1090 /* Insert the link descriptor to the LD ring */ 1091 list_add_tail(&new->node, &first->tx_list); 1092 1093 /* 1094 * Prepare DMA descriptor to generate P, 1095 * if DMA_PREP_PQ_DISABLE_P flag is not set 1096 */ 1097 if (len) { 1098 xgene_dma_prep_xor_desc(chan, new, &dst[0], src, 1099 src_cnt, &len, multi); 1100 continue; 1101 } 1102 1103 /* 1104 * Prepare DMA descriptor to generate Q, 1105 * if DMA_PREP_PQ_DISABLE_Q flag is not set 1106 */ 1107 if (_len) { 1108 xgene_dma_prep_xor_desc(chan, new, &dst[1], _src, 1109 src_cnt, &_len, scf); 1110 } 1111 } while (len || _len); 1112 1113 new->tx.flags = flags; /* client is in control of this ack */ 1114 new->tx.cookie = -EBUSY; 1115 list_splice(&first->tx_list, &new->tx_list); 1116 1117 return &new->tx; 1118 1119 fail: 1120 if (!first) 1121 return NULL; 1122 1123 xgene_dma_free_desc_list(chan, &first->tx_list); 1124 return NULL; 1125 } 1126 1127 static void xgene_dma_issue_pending(struct dma_chan *dchan) 1128 { 1129 struct xgene_dma_chan *chan = to_dma_chan(dchan); 1130 1131 spin_lock_bh(&chan->lock); 1132 xgene_chan_xfer_ld_pending(chan); 1133 spin_unlock_bh(&chan->lock); 1134 } 1135 1136 static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan, 1137 dma_cookie_t cookie, 1138 struct dma_tx_state *txstate) 1139 { 1140 return dma_cookie_status(dchan, cookie, txstate); 1141 } 1142 1143 static void xgene_dma_tasklet_cb(unsigned long data) 1144 { 1145 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data; 1146 1147 /* Run all cleanup for descriptors which have been completed */ 1148 xgene_dma_cleanup_descriptors(chan); 1149 1150 /* Re-enable DMA channel IRQ */ 1151 enable_irq(chan->rx_irq); 1152 } 1153 1154 static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id) 1155 { 1156 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id; 1157 1158 BUG_ON(!chan); 1159 1160 /* 1161 * Disable DMA channel IRQ until we process completed 1162 * descriptors 1163 */ 1164 disable_irq_nosync(chan->rx_irq); 1165 1166 /* 1167 * Schedule the tasklet to handle all cleanup of the current 1168 * transaction. It will start a new transaction if there is 1169 * one pending. 1170 */ 1171 tasklet_schedule(&chan->tasklet); 1172 1173 return IRQ_HANDLED; 1174 } 1175 1176 static irqreturn_t xgene_dma_err_isr(int irq, void *id) 1177 { 1178 struct xgene_dma *pdma = (struct xgene_dma *)id; 1179 unsigned long int_mask; 1180 u32 val, i; 1181 1182 val = ioread32(pdma->csr_dma + XGENE_DMA_INT); 1183 1184 /* Clear DMA interrupts */ 1185 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT); 1186 1187 /* Print DMA error info */ 1188 int_mask = val >> XGENE_DMA_INT_MASK_SHIFT; 1189 for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err)) 1190 dev_err(pdma->dev, 1191 "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]); 1192 1193 return IRQ_HANDLED; 1194 } 1195 1196 static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring) 1197 { 1198 int i; 1199 1200 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE); 1201 1202 for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++) 1203 iowrite32(ring->state[i], ring->pdma->csr_ring + 1204 XGENE_DMA_RING_STATE_WR_BASE + (i * 4)); 1205 } 1206 1207 static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring) 1208 { 1209 memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG); 1210 xgene_dma_wr_ring_state(ring); 1211 } 1212 1213 static void xgene_dma_setup_ring(struct xgene_dma_ring *ring) 1214 { 1215 void *ring_cfg = ring->state; 1216 u64 addr = ring->desc_paddr; 1217 u32 i, val; 1218 1219 ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE; 1220 1221 /* Clear DMA ring state */ 1222 xgene_dma_clr_ring_state(ring); 1223 1224 /* Set DMA ring type */ 1225 XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR); 1226 1227 if (ring->owner == XGENE_DMA_RING_OWNER_DMA) { 1228 /* Set recombination buffer and timeout */ 1229 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg); 1230 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg); 1231 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg); 1232 } 1233 1234 /* Initialize DMA ring state */ 1235 XGENE_DMA_RING_SELTHRSH_SET(ring_cfg); 1236 XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg); 1237 XGENE_DMA_RING_COHERENT_SET(ring_cfg); 1238 XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr); 1239 XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr); 1240 XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize); 1241 1242 /* Write DMA ring configurations */ 1243 xgene_dma_wr_ring_state(ring); 1244 1245 /* Set DMA ring id */ 1246 iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id), 1247 ring->pdma->csr_ring + XGENE_DMA_RING_ID); 1248 1249 /* Set DMA ring buffer */ 1250 iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num), 1251 ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF); 1252 1253 if (ring->owner != XGENE_DMA_RING_OWNER_CPU) 1254 return; 1255 1256 /* Set empty signature to DMA Rx ring descriptors */ 1257 for (i = 0; i < ring->slots; i++) { 1258 struct xgene_dma_desc_hw *desc; 1259 1260 desc = &ring->desc_hw[i]; 1261 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE); 1262 } 1263 1264 /* Enable DMA Rx ring interrupt */ 1265 val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE); 1266 XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num); 1267 iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE); 1268 } 1269 1270 static void xgene_dma_clear_ring(struct xgene_dma_ring *ring) 1271 { 1272 u32 ring_id, val; 1273 1274 if (ring->owner == XGENE_DMA_RING_OWNER_CPU) { 1275 /* Disable DMA Rx ring interrupt */ 1276 val = ioread32(ring->pdma->csr_ring + 1277 XGENE_DMA_RING_NE_INT_MODE); 1278 XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num); 1279 iowrite32(val, ring->pdma->csr_ring + 1280 XGENE_DMA_RING_NE_INT_MODE); 1281 } 1282 1283 /* Clear DMA ring state */ 1284 ring_id = XGENE_DMA_RING_ID_SETUP(ring->id); 1285 iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID); 1286 1287 iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF); 1288 xgene_dma_clr_ring_state(ring); 1289 } 1290 1291 static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring) 1292 { 1293 ring->cmd_base = ring->pdma->csr_ring_cmd + 1294 XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num - 1295 XGENE_DMA_RING_NUM)); 1296 1297 ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET; 1298 } 1299 1300 static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan, 1301 enum xgene_dma_ring_cfgsize cfgsize) 1302 { 1303 int size; 1304 1305 switch (cfgsize) { 1306 case XGENE_DMA_RING_CFG_SIZE_512B: 1307 size = 0x200; 1308 break; 1309 case XGENE_DMA_RING_CFG_SIZE_2KB: 1310 size = 0x800; 1311 break; 1312 case XGENE_DMA_RING_CFG_SIZE_16KB: 1313 size = 0x4000; 1314 break; 1315 case XGENE_DMA_RING_CFG_SIZE_64KB: 1316 size = 0x10000; 1317 break; 1318 case XGENE_DMA_RING_CFG_SIZE_512KB: 1319 size = 0x80000; 1320 break; 1321 default: 1322 chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize); 1323 return -EINVAL; 1324 } 1325 1326 return size; 1327 } 1328 1329 static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring) 1330 { 1331 /* Clear DMA ring configurations */ 1332 xgene_dma_clear_ring(ring); 1333 1334 /* De-allocate DMA ring descriptor */ 1335 if (ring->desc_vaddr) { 1336 dma_free_coherent(ring->pdma->dev, ring->size, 1337 ring->desc_vaddr, ring->desc_paddr); 1338 ring->desc_vaddr = NULL; 1339 } 1340 } 1341 1342 static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan) 1343 { 1344 xgene_dma_delete_ring_one(&chan->rx_ring); 1345 xgene_dma_delete_ring_one(&chan->tx_ring); 1346 } 1347 1348 static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan, 1349 struct xgene_dma_ring *ring, 1350 enum xgene_dma_ring_cfgsize cfgsize) 1351 { 1352 int ret; 1353 1354 /* Setup DMA ring descriptor variables */ 1355 ring->pdma = chan->pdma; 1356 ring->cfgsize = cfgsize; 1357 ring->num = chan->pdma->ring_num++; 1358 ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num); 1359 1360 ret = xgene_dma_get_ring_size(chan, cfgsize); 1361 if (ret <= 0) 1362 return ret; 1363 ring->size = ret; 1364 1365 /* Allocate memory for DMA ring descriptor */ 1366 ring->desc_vaddr = dma_zalloc_coherent(chan->dev, ring->size, 1367 &ring->desc_paddr, GFP_KERNEL); 1368 if (!ring->desc_vaddr) { 1369 chan_err(chan, "Failed to allocate ring desc\n"); 1370 return -ENOMEM; 1371 } 1372 1373 /* Configure and enable DMA ring */ 1374 xgene_dma_set_ring_cmd(ring); 1375 xgene_dma_setup_ring(ring); 1376 1377 return 0; 1378 } 1379 1380 static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan) 1381 { 1382 struct xgene_dma_ring *rx_ring = &chan->rx_ring; 1383 struct xgene_dma_ring *tx_ring = &chan->tx_ring; 1384 int ret; 1385 1386 /* Create DMA Rx ring descriptor */ 1387 rx_ring->owner = XGENE_DMA_RING_OWNER_CPU; 1388 rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id; 1389 1390 ret = xgene_dma_create_ring_one(chan, rx_ring, 1391 XGENE_DMA_RING_CFG_SIZE_64KB); 1392 if (ret) 1393 return ret; 1394 1395 chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n", 1396 rx_ring->id, rx_ring->num, rx_ring->desc_vaddr); 1397 1398 /* Create DMA Tx ring descriptor */ 1399 tx_ring->owner = XGENE_DMA_RING_OWNER_DMA; 1400 tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id; 1401 1402 ret = xgene_dma_create_ring_one(chan, tx_ring, 1403 XGENE_DMA_RING_CFG_SIZE_64KB); 1404 if (ret) { 1405 xgene_dma_delete_ring_one(rx_ring); 1406 return ret; 1407 } 1408 1409 tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num); 1410 1411 chan_dbg(chan, 1412 "Tx ring id 0x%X num %d desc 0x%p\n", 1413 tx_ring->id, tx_ring->num, tx_ring->desc_vaddr); 1414 1415 /* Set the max outstanding request possible to this channel */ 1416 chan->max_outstanding = tx_ring->slots; 1417 1418 return ret; 1419 } 1420 1421 static int xgene_dma_init_rings(struct xgene_dma *pdma) 1422 { 1423 int ret, i, j; 1424 1425 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1426 ret = xgene_dma_create_chan_rings(&pdma->chan[i]); 1427 if (ret) { 1428 for (j = 0; j < i; j++) 1429 xgene_dma_delete_chan_rings(&pdma->chan[j]); 1430 return ret; 1431 } 1432 } 1433 1434 return ret; 1435 } 1436 1437 static void xgene_dma_enable(struct xgene_dma *pdma) 1438 { 1439 u32 val; 1440 1441 /* Configure and enable DMA engine */ 1442 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR); 1443 XGENE_DMA_CH_SETUP(val); 1444 XGENE_DMA_ENABLE(val); 1445 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR); 1446 } 1447 1448 static void xgene_dma_disable(struct xgene_dma *pdma) 1449 { 1450 u32 val; 1451 1452 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR); 1453 XGENE_DMA_DISABLE(val); 1454 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR); 1455 } 1456 1457 static void xgene_dma_mask_interrupts(struct xgene_dma *pdma) 1458 { 1459 /* 1460 * Mask DMA ring overflow, underflow and 1461 * AXI write/read error interrupts 1462 */ 1463 iowrite32(XGENE_DMA_INT_ALL_MASK, 1464 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK); 1465 iowrite32(XGENE_DMA_INT_ALL_MASK, 1466 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK); 1467 iowrite32(XGENE_DMA_INT_ALL_MASK, 1468 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK); 1469 iowrite32(XGENE_DMA_INT_ALL_MASK, 1470 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK); 1471 iowrite32(XGENE_DMA_INT_ALL_MASK, 1472 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK); 1473 1474 /* Mask DMA error interrupts */ 1475 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK); 1476 } 1477 1478 static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma) 1479 { 1480 /* 1481 * Unmask DMA ring overflow, underflow and 1482 * AXI write/read error interrupts 1483 */ 1484 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1485 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK); 1486 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1487 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK); 1488 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1489 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK); 1490 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1491 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK); 1492 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1493 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK); 1494 1495 /* Unmask DMA error interrupts */ 1496 iowrite32(XGENE_DMA_INT_ALL_UNMASK, 1497 pdma->csr_dma + XGENE_DMA_INT_MASK); 1498 } 1499 1500 static void xgene_dma_init_hw(struct xgene_dma *pdma) 1501 { 1502 u32 val; 1503 1504 /* Associate DMA ring to corresponding ring HW */ 1505 iowrite32(XGENE_DMA_ASSOC_RING_MNGR1, 1506 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC); 1507 1508 /* Configure RAID6 polynomial control setting */ 1509 if (is_pq_enabled(pdma)) 1510 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D), 1511 pdma->csr_dma + XGENE_DMA_RAID6_CONT); 1512 else 1513 dev_info(pdma->dev, "PQ is disabled in HW\n"); 1514 1515 xgene_dma_enable(pdma); 1516 xgene_dma_unmask_interrupts(pdma); 1517 1518 /* Get DMA id and version info */ 1519 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR); 1520 1521 /* DMA device info */ 1522 dev_info(pdma->dev, 1523 "X-Gene DMA v%d.%02d.%02d driver registered %d channels", 1524 XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val), 1525 XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL); 1526 } 1527 1528 static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma) 1529 { 1530 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) && 1531 (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST))) 1532 return 0; 1533 1534 iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN); 1535 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST); 1536 1537 /* Bring up memory */ 1538 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN); 1539 1540 /* Force a barrier */ 1541 ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN); 1542 1543 /* reset may take up to 1ms */ 1544 usleep_range(1000, 1100); 1545 1546 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY) 1547 != XGENE_DMA_RING_BLK_MEM_RDY_VAL) { 1548 dev_err(pdma->dev, 1549 "Failed to release ring mngr memory from shutdown\n"); 1550 return -ENODEV; 1551 } 1552 1553 /* program threshold set 1 and all hysteresis */ 1554 iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL, 1555 pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1); 1556 iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL, 1557 pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1); 1558 iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL, 1559 pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS); 1560 1561 /* Enable QPcore and assign error queue */ 1562 iowrite32(XGENE_DMA_RING_ENABLE, 1563 pdma->csr_ring + XGENE_DMA_RING_CONFIG); 1564 1565 return 0; 1566 } 1567 1568 static int xgene_dma_init_mem(struct xgene_dma *pdma) 1569 { 1570 int ret; 1571 1572 ret = xgene_dma_init_ring_mngr(pdma); 1573 if (ret) 1574 return ret; 1575 1576 /* Bring up memory */ 1577 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN); 1578 1579 /* Force a barrier */ 1580 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN); 1581 1582 /* reset may take up to 1ms */ 1583 usleep_range(1000, 1100); 1584 1585 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY) 1586 != XGENE_DMA_BLK_MEM_RDY_VAL) { 1587 dev_err(pdma->dev, 1588 "Failed to release DMA memory from shutdown\n"); 1589 return -ENODEV; 1590 } 1591 1592 return 0; 1593 } 1594 1595 static int xgene_dma_request_irqs(struct xgene_dma *pdma) 1596 { 1597 struct xgene_dma_chan *chan; 1598 int ret, i, j; 1599 1600 /* Register DMA error irq */ 1601 ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr, 1602 0, "dma_error", pdma); 1603 if (ret) { 1604 dev_err(pdma->dev, 1605 "Failed to register error IRQ %d\n", pdma->err_irq); 1606 return ret; 1607 } 1608 1609 /* Register DMA channel rx irq */ 1610 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1611 chan = &pdma->chan[i]; 1612 irq_set_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY); 1613 ret = devm_request_irq(chan->dev, chan->rx_irq, 1614 xgene_dma_chan_ring_isr, 1615 0, chan->name, chan); 1616 if (ret) { 1617 chan_err(chan, "Failed to register Rx IRQ %d\n", 1618 chan->rx_irq); 1619 devm_free_irq(pdma->dev, pdma->err_irq, pdma); 1620 1621 for (j = 0; j < i; j++) { 1622 chan = &pdma->chan[i]; 1623 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY); 1624 devm_free_irq(chan->dev, chan->rx_irq, chan); 1625 } 1626 1627 return ret; 1628 } 1629 } 1630 1631 return 0; 1632 } 1633 1634 static void xgene_dma_free_irqs(struct xgene_dma *pdma) 1635 { 1636 struct xgene_dma_chan *chan; 1637 int i; 1638 1639 /* Free DMA device error irq */ 1640 devm_free_irq(pdma->dev, pdma->err_irq, pdma); 1641 1642 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1643 chan = &pdma->chan[i]; 1644 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY); 1645 devm_free_irq(chan->dev, chan->rx_irq, chan); 1646 } 1647 } 1648 1649 static void xgene_dma_set_caps(struct xgene_dma_chan *chan, 1650 struct dma_device *dma_dev) 1651 { 1652 /* Initialize DMA device capability mask */ 1653 dma_cap_zero(dma_dev->cap_mask); 1654 1655 /* Set DMA device capability */ 1656 dma_cap_set(DMA_SG, dma_dev->cap_mask); 1657 1658 /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR 1659 * and channel 1 supports XOR, PQ both. First thing here is we have 1660 * mechanism in hw to enable/disable PQ/XOR supports on channel 1, 1661 * we can make sure this by reading SoC Efuse register. 1662 * Second thing, we have hw errata that if we run channel 0 and 1663 * channel 1 simultaneously with executing XOR and PQ request, 1664 * suddenly DMA engine hangs, So here we enable XOR on channel 0 only 1665 * if XOR and PQ supports on channel 1 is disabled. 1666 */ 1667 if ((chan->id == XGENE_DMA_PQ_CHANNEL) && 1668 is_pq_enabled(chan->pdma)) { 1669 dma_cap_set(DMA_PQ, dma_dev->cap_mask); 1670 dma_cap_set(DMA_XOR, dma_dev->cap_mask); 1671 } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) && 1672 !is_pq_enabled(chan->pdma)) { 1673 dma_cap_set(DMA_XOR, dma_dev->cap_mask); 1674 } 1675 1676 /* Set base and prep routines */ 1677 dma_dev->dev = chan->dev; 1678 dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources; 1679 dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources; 1680 dma_dev->device_issue_pending = xgene_dma_issue_pending; 1681 dma_dev->device_tx_status = xgene_dma_tx_status; 1682 dma_dev->device_prep_dma_sg = xgene_dma_prep_sg; 1683 1684 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { 1685 dma_dev->device_prep_dma_xor = xgene_dma_prep_xor; 1686 dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC; 1687 dma_dev->xor_align = DMAENGINE_ALIGN_64_BYTES; 1688 } 1689 1690 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { 1691 dma_dev->device_prep_dma_pq = xgene_dma_prep_pq; 1692 dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC; 1693 dma_dev->pq_align = DMAENGINE_ALIGN_64_BYTES; 1694 } 1695 } 1696 1697 static int xgene_dma_async_register(struct xgene_dma *pdma, int id) 1698 { 1699 struct xgene_dma_chan *chan = &pdma->chan[id]; 1700 struct dma_device *dma_dev = &pdma->dma_dev[id]; 1701 int ret; 1702 1703 chan->dma_chan.device = dma_dev; 1704 1705 spin_lock_init(&chan->lock); 1706 INIT_LIST_HEAD(&chan->ld_pending); 1707 INIT_LIST_HEAD(&chan->ld_running); 1708 INIT_LIST_HEAD(&chan->ld_completed); 1709 tasklet_init(&chan->tasklet, xgene_dma_tasklet_cb, 1710 (unsigned long)chan); 1711 1712 chan->pending = 0; 1713 chan->desc_pool = NULL; 1714 dma_cookie_init(&chan->dma_chan); 1715 1716 /* Setup dma device capabilities and prep routines */ 1717 xgene_dma_set_caps(chan, dma_dev); 1718 1719 /* Initialize DMA device list head */ 1720 INIT_LIST_HEAD(&dma_dev->channels); 1721 list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels); 1722 1723 /* Register with Linux async DMA framework*/ 1724 ret = dma_async_device_register(dma_dev); 1725 if (ret) { 1726 chan_err(chan, "Failed to register async device %d", ret); 1727 tasklet_kill(&chan->tasklet); 1728 1729 return ret; 1730 } 1731 1732 /* DMA capability info */ 1733 dev_info(pdma->dev, 1734 "%s: CAPABILITY ( %s%s%s)\n", dma_chan_name(&chan->dma_chan), 1735 dma_has_cap(DMA_SG, dma_dev->cap_mask) ? "SGCPY " : "", 1736 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "", 1737 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : ""); 1738 1739 return 0; 1740 } 1741 1742 static int xgene_dma_init_async(struct xgene_dma *pdma) 1743 { 1744 int ret, i, j; 1745 1746 for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) { 1747 ret = xgene_dma_async_register(pdma, i); 1748 if (ret) { 1749 for (j = 0; j < i; j++) { 1750 dma_async_device_unregister(&pdma->dma_dev[j]); 1751 tasklet_kill(&pdma->chan[j].tasklet); 1752 } 1753 1754 return ret; 1755 } 1756 } 1757 1758 return ret; 1759 } 1760 1761 static void xgene_dma_async_unregister(struct xgene_dma *pdma) 1762 { 1763 int i; 1764 1765 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) 1766 dma_async_device_unregister(&pdma->dma_dev[i]); 1767 } 1768 1769 static void xgene_dma_init_channels(struct xgene_dma *pdma) 1770 { 1771 struct xgene_dma_chan *chan; 1772 int i; 1773 1774 pdma->ring_num = XGENE_DMA_RING_NUM; 1775 1776 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1777 chan = &pdma->chan[i]; 1778 chan->dev = pdma->dev; 1779 chan->pdma = pdma; 1780 chan->id = i; 1781 snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id); 1782 } 1783 } 1784 1785 static int xgene_dma_get_resources(struct platform_device *pdev, 1786 struct xgene_dma *pdma) 1787 { 1788 struct resource *res; 1789 int irq, i; 1790 1791 /* Get DMA csr region */ 1792 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1793 if (!res) { 1794 dev_err(&pdev->dev, "Failed to get csr region\n"); 1795 return -ENXIO; 1796 } 1797 1798 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start, 1799 resource_size(res)); 1800 if (!pdma->csr_dma) { 1801 dev_err(&pdev->dev, "Failed to ioremap csr region"); 1802 return -ENOMEM; 1803 } 1804 1805 /* Get DMA ring csr region */ 1806 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1807 if (!res) { 1808 dev_err(&pdev->dev, "Failed to get ring csr region\n"); 1809 return -ENXIO; 1810 } 1811 1812 pdma->csr_ring = devm_ioremap(&pdev->dev, res->start, 1813 resource_size(res)); 1814 if (!pdma->csr_ring) { 1815 dev_err(&pdev->dev, "Failed to ioremap ring csr region"); 1816 return -ENOMEM; 1817 } 1818 1819 /* Get DMA ring cmd csr region */ 1820 res = platform_get_resource(pdev, IORESOURCE_MEM, 2); 1821 if (!res) { 1822 dev_err(&pdev->dev, "Failed to get ring cmd csr region\n"); 1823 return -ENXIO; 1824 } 1825 1826 pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start, 1827 resource_size(res)); 1828 if (!pdma->csr_ring_cmd) { 1829 dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region"); 1830 return -ENOMEM; 1831 } 1832 1833 pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET; 1834 1835 /* Get efuse csr region */ 1836 res = platform_get_resource(pdev, IORESOURCE_MEM, 3); 1837 if (!res) { 1838 dev_err(&pdev->dev, "Failed to get efuse csr region\n"); 1839 return -ENXIO; 1840 } 1841 1842 pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start, 1843 resource_size(res)); 1844 if (!pdma->csr_efuse) { 1845 dev_err(&pdev->dev, "Failed to ioremap efuse csr region"); 1846 return -ENOMEM; 1847 } 1848 1849 /* Get DMA error interrupt */ 1850 irq = platform_get_irq(pdev, 0); 1851 if (irq <= 0) { 1852 dev_err(&pdev->dev, "Failed to get Error IRQ\n"); 1853 return -ENXIO; 1854 } 1855 1856 pdma->err_irq = irq; 1857 1858 /* Get DMA Rx ring descriptor interrupts for all DMA channels */ 1859 for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) { 1860 irq = platform_get_irq(pdev, i); 1861 if (irq <= 0) { 1862 dev_err(&pdev->dev, "Failed to get Rx IRQ\n"); 1863 return -ENXIO; 1864 } 1865 1866 pdma->chan[i - 1].rx_irq = irq; 1867 } 1868 1869 return 0; 1870 } 1871 1872 static int xgene_dma_probe(struct platform_device *pdev) 1873 { 1874 struct xgene_dma *pdma; 1875 int ret, i; 1876 1877 pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL); 1878 if (!pdma) 1879 return -ENOMEM; 1880 1881 pdma->dev = &pdev->dev; 1882 platform_set_drvdata(pdev, pdma); 1883 1884 ret = xgene_dma_get_resources(pdev, pdma); 1885 if (ret) 1886 return ret; 1887 1888 pdma->clk = devm_clk_get(&pdev->dev, NULL); 1889 if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) { 1890 dev_err(&pdev->dev, "Failed to get clk\n"); 1891 return PTR_ERR(pdma->clk); 1892 } 1893 1894 /* Enable clk before accessing registers */ 1895 if (!IS_ERR(pdma->clk)) { 1896 ret = clk_prepare_enable(pdma->clk); 1897 if (ret) { 1898 dev_err(&pdev->dev, "Failed to enable clk %d\n", ret); 1899 return ret; 1900 } 1901 } 1902 1903 /* Remove DMA RAM out of shutdown */ 1904 ret = xgene_dma_init_mem(pdma); 1905 if (ret) 1906 goto err_clk_enable; 1907 1908 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42)); 1909 if (ret) { 1910 dev_err(&pdev->dev, "No usable DMA configuration\n"); 1911 goto err_dma_mask; 1912 } 1913 1914 /* Initialize DMA channels software state */ 1915 xgene_dma_init_channels(pdma); 1916 1917 /* Configue DMA rings */ 1918 ret = xgene_dma_init_rings(pdma); 1919 if (ret) 1920 goto err_clk_enable; 1921 1922 ret = xgene_dma_request_irqs(pdma); 1923 if (ret) 1924 goto err_request_irq; 1925 1926 /* Configure and enable DMA engine */ 1927 xgene_dma_init_hw(pdma); 1928 1929 /* Register DMA device with linux async framework */ 1930 ret = xgene_dma_init_async(pdma); 1931 if (ret) 1932 goto err_async_init; 1933 1934 return 0; 1935 1936 err_async_init: 1937 xgene_dma_free_irqs(pdma); 1938 1939 err_request_irq: 1940 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) 1941 xgene_dma_delete_chan_rings(&pdma->chan[i]); 1942 1943 err_dma_mask: 1944 err_clk_enable: 1945 if (!IS_ERR(pdma->clk)) 1946 clk_disable_unprepare(pdma->clk); 1947 1948 return ret; 1949 } 1950 1951 static int xgene_dma_remove(struct platform_device *pdev) 1952 { 1953 struct xgene_dma *pdma = platform_get_drvdata(pdev); 1954 struct xgene_dma_chan *chan; 1955 int i; 1956 1957 xgene_dma_async_unregister(pdma); 1958 1959 /* Mask interrupts and disable DMA engine */ 1960 xgene_dma_mask_interrupts(pdma); 1961 xgene_dma_disable(pdma); 1962 xgene_dma_free_irqs(pdma); 1963 1964 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) { 1965 chan = &pdma->chan[i]; 1966 tasklet_kill(&chan->tasklet); 1967 xgene_dma_delete_chan_rings(chan); 1968 } 1969 1970 if (!IS_ERR(pdma->clk)) 1971 clk_disable_unprepare(pdma->clk); 1972 1973 return 0; 1974 } 1975 1976 #ifdef CONFIG_ACPI 1977 static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = { 1978 {"APMC0D43", 0}, 1979 {}, 1980 }; 1981 MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr); 1982 #endif 1983 1984 static const struct of_device_id xgene_dma_of_match_ptr[] = { 1985 {.compatible = "apm,xgene-storm-dma",}, 1986 {}, 1987 }; 1988 MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr); 1989 1990 static struct platform_driver xgene_dma_driver = { 1991 .probe = xgene_dma_probe, 1992 .remove = xgene_dma_remove, 1993 .driver = { 1994 .name = "X-Gene-DMA", 1995 .of_match_table = xgene_dma_of_match_ptr, 1996 .acpi_match_table = ACPI_PTR(xgene_dma_acpi_match_ptr), 1997 }, 1998 }; 1999 2000 module_platform_driver(xgene_dma_driver); 2001 2002 MODULE_DESCRIPTION("APM X-Gene SoC DMA driver"); 2003 MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>"); 2004 MODULE_AUTHOR("Loc Ho <lho@apm.com>"); 2005 MODULE_LICENSE("GPL"); 2006 MODULE_VERSION("1.0"); 2007