1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * K3 NAVSS DMA glue interface 4 * 5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com 6 * 7 */ 8 9 #include <linux/atomic.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/io.h> 13 #include <linux/init.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/soc/ti/k3-ringacc.h> 17 #include <linux/dma/ti-cppi5.h> 18 #include <linux/dma/k3-udma-glue.h> 19 20 #include "k3-udma.h" 21 #include "k3-psil-priv.h" 22 23 struct k3_udma_glue_common { 24 struct device *dev; 25 struct udma_dev *udmax; 26 const struct udma_tisci_rm *tisci_rm; 27 struct k3_ringacc *ringacc; 28 u32 src_thread; 29 u32 dst_thread; 30 31 u32 hdesc_size; 32 bool epib; 33 u32 psdata_size; 34 u32 swdata_size; 35 u32 atype; 36 }; 37 38 struct k3_udma_glue_tx_channel { 39 struct k3_udma_glue_common common; 40 41 struct udma_tchan *udma_tchanx; 42 int udma_tchan_id; 43 44 struct k3_ring *ringtx; 45 struct k3_ring *ringtxcq; 46 47 bool psil_paired; 48 49 int virq; 50 51 atomic_t free_pkts; 52 bool tx_pause_on_err; 53 bool tx_filt_einfo; 54 bool tx_filt_pswords; 55 bool tx_supr_tdpkt; 56 }; 57 58 struct k3_udma_glue_rx_flow { 59 struct udma_rflow *udma_rflow; 60 int udma_rflow_id; 61 struct k3_ring *ringrx; 62 struct k3_ring *ringrxfdq; 63 64 int virq; 65 }; 66 67 struct k3_udma_glue_rx_channel { 68 struct k3_udma_glue_common common; 69 70 struct udma_rchan *udma_rchanx; 71 int udma_rchan_id; 72 bool remote; 73 74 bool psil_paired; 75 76 u32 swdata_size; 77 int flow_id_base; 78 79 struct k3_udma_glue_rx_flow *flows; 80 u32 flow_num; 81 u32 flows_ready; 82 }; 83 84 #define K3_UDMAX_TDOWN_TIMEOUT_US 1000 85 86 static int of_k3_udma_glue_parse(struct device_node *udmax_np, 87 struct k3_udma_glue_common *common) 88 { 89 common->ringacc = of_k3_ringacc_get_by_phandle(udmax_np, 90 "ti,ringacc"); 91 if (IS_ERR(common->ringacc)) 92 return PTR_ERR(common->ringacc); 93 94 common->udmax = of_xudma_dev_get(udmax_np, NULL); 95 if (IS_ERR(common->udmax)) 96 return PTR_ERR(common->udmax); 97 98 common->tisci_rm = xudma_dev_get_tisci_rm(common->udmax); 99 100 return 0; 101 } 102 103 static int of_k3_udma_glue_parse_chn(struct device_node *chn_np, 104 const char *name, struct k3_udma_glue_common *common, 105 bool tx_chn) 106 { 107 struct psil_endpoint_config *ep_config; 108 struct of_phandle_args dma_spec; 109 u32 thread_id; 110 int ret = 0; 111 int index; 112 113 if (unlikely(!name)) 114 return -EINVAL; 115 116 index = of_property_match_string(chn_np, "dma-names", name); 117 if (index < 0) 118 return index; 119 120 if (of_parse_phandle_with_args(chn_np, "dmas", "#dma-cells", index, 121 &dma_spec)) 122 return -ENOENT; 123 124 thread_id = dma_spec.args[0]; 125 if (dma_spec.args_count == 2) { 126 if (dma_spec.args[1] > 2) { 127 dev_err(common->dev, "Invalid channel atype: %u\n", 128 dma_spec.args[1]); 129 ret = -EINVAL; 130 goto out_put_spec; 131 } 132 common->atype = dma_spec.args[1]; 133 } 134 135 if (tx_chn && !(thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)) { 136 ret = -EINVAL; 137 goto out_put_spec; 138 } 139 140 if (!tx_chn && (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)) { 141 ret = -EINVAL; 142 goto out_put_spec; 143 } 144 145 /* get psil endpoint config */ 146 ep_config = psil_get_ep_config(thread_id); 147 if (IS_ERR(ep_config)) { 148 dev_err(common->dev, 149 "No configuration for psi-l thread 0x%04x\n", 150 thread_id); 151 ret = PTR_ERR(ep_config); 152 goto out_put_spec; 153 } 154 155 common->epib = ep_config->needs_epib; 156 common->psdata_size = ep_config->psd_size; 157 158 if (tx_chn) 159 common->dst_thread = thread_id; 160 else 161 common->src_thread = thread_id; 162 163 ret = of_k3_udma_glue_parse(dma_spec.np, common); 164 165 out_put_spec: 166 of_node_put(dma_spec.np); 167 return ret; 168 }; 169 170 static void k3_udma_glue_dump_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) 171 { 172 struct device *dev = tx_chn->common.dev; 173 174 dev_dbg(dev, "dump_tx_chn:\n" 175 "udma_tchan_id: %d\n" 176 "src_thread: %08x\n" 177 "dst_thread: %08x\n", 178 tx_chn->udma_tchan_id, 179 tx_chn->common.src_thread, 180 tx_chn->common.dst_thread); 181 } 182 183 static void k3_udma_glue_dump_tx_rt_chn(struct k3_udma_glue_tx_channel *chn, 184 char *mark) 185 { 186 struct device *dev = chn->common.dev; 187 188 dev_dbg(dev, "=== dump ===> %s\n", mark); 189 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_CTL_REG, 190 xudma_tchanrt_read(chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG)); 191 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_PEER_RT_EN_REG, 192 xudma_tchanrt_read(chn->udma_tchanx, 193 UDMA_CHAN_RT_PEER_RT_EN_REG)); 194 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_PCNT_REG, 195 xudma_tchanrt_read(chn->udma_tchanx, UDMA_CHAN_RT_PCNT_REG)); 196 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_BCNT_REG, 197 xudma_tchanrt_read(chn->udma_tchanx, UDMA_CHAN_RT_BCNT_REG)); 198 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_SBCNT_REG, 199 xudma_tchanrt_read(chn->udma_tchanx, UDMA_CHAN_RT_SBCNT_REG)); 200 } 201 202 static int k3_udma_glue_cfg_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) 203 { 204 const struct udma_tisci_rm *tisci_rm = tx_chn->common.tisci_rm; 205 struct ti_sci_msg_rm_udmap_tx_ch_cfg req; 206 207 memset(&req, 0, sizeof(req)); 208 209 req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | 210 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | 211 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | 212 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | 213 TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | 214 TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | 215 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | 216 TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID; 217 req.nav_id = tisci_rm->tisci_dev_id; 218 req.index = tx_chn->udma_tchan_id; 219 if (tx_chn->tx_pause_on_err) 220 req.tx_pause_on_err = 1; 221 if (tx_chn->tx_filt_einfo) 222 req.tx_filt_einfo = 1; 223 if (tx_chn->tx_filt_pswords) 224 req.tx_filt_pswords = 1; 225 req.tx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR; 226 if (tx_chn->tx_supr_tdpkt) 227 req.tx_supr_tdpkt = 1; 228 req.tx_fetch_size = tx_chn->common.hdesc_size >> 2; 229 req.txcq_qnum = k3_ringacc_get_ring_id(tx_chn->ringtxcq); 230 req.tx_atype = tx_chn->common.atype; 231 232 return tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req); 233 } 234 235 struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev, 236 const char *name, struct k3_udma_glue_tx_channel_cfg *cfg) 237 { 238 struct k3_udma_glue_tx_channel *tx_chn; 239 int ret; 240 241 tx_chn = devm_kzalloc(dev, sizeof(*tx_chn), GFP_KERNEL); 242 if (!tx_chn) 243 return ERR_PTR(-ENOMEM); 244 245 tx_chn->common.dev = dev; 246 tx_chn->common.swdata_size = cfg->swdata_size; 247 tx_chn->tx_pause_on_err = cfg->tx_pause_on_err; 248 tx_chn->tx_filt_einfo = cfg->tx_filt_einfo; 249 tx_chn->tx_filt_pswords = cfg->tx_filt_pswords; 250 tx_chn->tx_supr_tdpkt = cfg->tx_supr_tdpkt; 251 252 /* parse of udmap channel */ 253 ret = of_k3_udma_glue_parse_chn(dev->of_node, name, 254 &tx_chn->common, true); 255 if (ret) 256 goto err; 257 258 tx_chn->common.hdesc_size = cppi5_hdesc_calc_size(tx_chn->common.epib, 259 tx_chn->common.psdata_size, 260 tx_chn->common.swdata_size); 261 262 /* request and cfg UDMAP TX channel */ 263 tx_chn->udma_tchanx = xudma_tchan_get(tx_chn->common.udmax, -1); 264 if (IS_ERR(tx_chn->udma_tchanx)) { 265 ret = PTR_ERR(tx_chn->udma_tchanx); 266 dev_err(dev, "UDMAX tchanx get err %d\n", ret); 267 goto err; 268 } 269 tx_chn->udma_tchan_id = xudma_tchan_get_id(tx_chn->udma_tchanx); 270 271 atomic_set(&tx_chn->free_pkts, cfg->txcq_cfg.size); 272 273 /* request and cfg rings */ 274 tx_chn->ringtx = k3_ringacc_request_ring(tx_chn->common.ringacc, 275 tx_chn->udma_tchan_id, 0); 276 if (!tx_chn->ringtx) { 277 ret = -ENODEV; 278 dev_err(dev, "Failed to get TX ring %u\n", 279 tx_chn->udma_tchan_id); 280 goto err; 281 } 282 283 tx_chn->ringtxcq = k3_ringacc_request_ring(tx_chn->common.ringacc, 284 -1, 0); 285 if (!tx_chn->ringtxcq) { 286 ret = -ENODEV; 287 dev_err(dev, "Failed to get TXCQ ring\n"); 288 goto err; 289 } 290 291 ret = k3_ringacc_ring_cfg(tx_chn->ringtx, &cfg->tx_cfg); 292 if (ret) { 293 dev_err(dev, "Failed to cfg ringtx %d\n", ret); 294 goto err; 295 } 296 297 ret = k3_ringacc_ring_cfg(tx_chn->ringtxcq, &cfg->txcq_cfg); 298 if (ret) { 299 dev_err(dev, "Failed to cfg ringtx %d\n", ret); 300 goto err; 301 } 302 303 /* request and cfg psi-l */ 304 tx_chn->common.src_thread = 305 xudma_dev_get_psil_base(tx_chn->common.udmax) + 306 tx_chn->udma_tchan_id; 307 308 ret = k3_udma_glue_cfg_tx_chn(tx_chn); 309 if (ret) { 310 dev_err(dev, "Failed to cfg tchan %d\n", ret); 311 goto err; 312 } 313 314 ret = xudma_navss_psil_pair(tx_chn->common.udmax, 315 tx_chn->common.src_thread, 316 tx_chn->common.dst_thread); 317 if (ret) { 318 dev_err(dev, "PSI-L request err %d\n", ret); 319 goto err; 320 } 321 322 tx_chn->psil_paired = true; 323 324 /* reset TX RT registers */ 325 k3_udma_glue_disable_tx_chn(tx_chn); 326 327 k3_udma_glue_dump_tx_chn(tx_chn); 328 329 return tx_chn; 330 331 err: 332 k3_udma_glue_release_tx_chn(tx_chn); 333 return ERR_PTR(ret); 334 } 335 EXPORT_SYMBOL_GPL(k3_udma_glue_request_tx_chn); 336 337 void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) 338 { 339 if (tx_chn->psil_paired) { 340 xudma_navss_psil_unpair(tx_chn->common.udmax, 341 tx_chn->common.src_thread, 342 tx_chn->common.dst_thread); 343 tx_chn->psil_paired = false; 344 } 345 346 if (!IS_ERR_OR_NULL(tx_chn->udma_tchanx)) 347 xudma_tchan_put(tx_chn->common.udmax, 348 tx_chn->udma_tchanx); 349 350 if (tx_chn->ringtxcq) 351 k3_ringacc_ring_free(tx_chn->ringtxcq); 352 353 if (tx_chn->ringtx) 354 k3_ringacc_ring_free(tx_chn->ringtx); 355 } 356 EXPORT_SYMBOL_GPL(k3_udma_glue_release_tx_chn); 357 358 int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, 359 struct cppi5_host_desc_t *desc_tx, 360 dma_addr_t desc_dma) 361 { 362 u32 ringtxcq_id; 363 364 if (!atomic_add_unless(&tx_chn->free_pkts, -1, 0)) 365 return -ENOMEM; 366 367 ringtxcq_id = k3_ringacc_get_ring_id(tx_chn->ringtxcq); 368 cppi5_desc_set_retpolicy(&desc_tx->hdr, 0, ringtxcq_id); 369 370 return k3_ringacc_ring_push(tx_chn->ringtx, &desc_dma); 371 } 372 EXPORT_SYMBOL_GPL(k3_udma_glue_push_tx_chn); 373 374 int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, 375 dma_addr_t *desc_dma) 376 { 377 int ret; 378 379 ret = k3_ringacc_ring_pop(tx_chn->ringtxcq, desc_dma); 380 if (!ret) 381 atomic_inc(&tx_chn->free_pkts); 382 383 return ret; 384 } 385 EXPORT_SYMBOL_GPL(k3_udma_glue_pop_tx_chn); 386 387 int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) 388 { 389 u32 txrt_ctl; 390 391 txrt_ctl = UDMA_PEER_RT_EN_ENABLE; 392 xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, 393 txrt_ctl); 394 395 txrt_ctl = xudma_tchanrt_read(tx_chn->udma_tchanx, 396 UDMA_CHAN_RT_CTL_REG); 397 txrt_ctl |= UDMA_CHAN_RT_CTL_EN; 398 xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, 399 txrt_ctl); 400 401 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn en"); 402 return 0; 403 } 404 EXPORT_SYMBOL_GPL(k3_udma_glue_enable_tx_chn); 405 406 void k3_udma_glue_disable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn) 407 { 408 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn dis1"); 409 410 xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, 0); 411 412 xudma_tchanrt_write(tx_chn->udma_tchanx, 413 UDMA_CHAN_RT_PEER_RT_EN_REG, 0); 414 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn dis2"); 415 } 416 EXPORT_SYMBOL_GPL(k3_udma_glue_disable_tx_chn); 417 418 void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, 419 bool sync) 420 { 421 int i = 0; 422 u32 val; 423 424 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown1"); 425 426 xudma_tchanrt_write(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG, 427 UDMA_CHAN_RT_CTL_EN | UDMA_CHAN_RT_CTL_TDOWN); 428 429 val = xudma_tchanrt_read(tx_chn->udma_tchanx, UDMA_CHAN_RT_CTL_REG); 430 431 while (sync && (val & UDMA_CHAN_RT_CTL_EN)) { 432 val = xudma_tchanrt_read(tx_chn->udma_tchanx, 433 UDMA_CHAN_RT_CTL_REG); 434 udelay(1); 435 if (i > K3_UDMAX_TDOWN_TIMEOUT_US) { 436 dev_err(tx_chn->common.dev, "TX tdown timeout\n"); 437 break; 438 } 439 i++; 440 } 441 442 val = xudma_tchanrt_read(tx_chn->udma_tchanx, 443 UDMA_CHAN_RT_PEER_RT_EN_REG); 444 if (sync && (val & UDMA_PEER_RT_EN_ENABLE)) 445 dev_err(tx_chn->common.dev, "TX tdown peer not stopped\n"); 446 k3_udma_glue_dump_tx_rt_chn(tx_chn, "txchn tdown2"); 447 } 448 EXPORT_SYMBOL_GPL(k3_udma_glue_tdown_tx_chn); 449 450 void k3_udma_glue_reset_tx_chn(struct k3_udma_glue_tx_channel *tx_chn, 451 void *data, 452 void (*cleanup)(void *data, dma_addr_t desc_dma)) 453 { 454 dma_addr_t desc_dma; 455 int occ_tx, i, ret; 456 457 /* reset TXCQ as it is not input for udma - expected to be empty */ 458 if (tx_chn->ringtxcq) 459 k3_ringacc_ring_reset(tx_chn->ringtxcq); 460 461 /* 462 * TXQ reset need to be special way as it is input for udma and its 463 * state cached by udma, so: 464 * 1) save TXQ occ 465 * 2) clean up TXQ and call callback .cleanup() for each desc 466 * 3) reset TXQ in a special way 467 */ 468 occ_tx = k3_ringacc_ring_get_occ(tx_chn->ringtx); 469 dev_dbg(tx_chn->common.dev, "TX reset occ_tx %u\n", occ_tx); 470 471 for (i = 0; i < occ_tx; i++) { 472 ret = k3_ringacc_ring_pop(tx_chn->ringtx, &desc_dma); 473 if (ret) { 474 dev_err(tx_chn->common.dev, "TX reset pop %d\n", ret); 475 break; 476 } 477 cleanup(data, desc_dma); 478 } 479 480 k3_ringacc_ring_reset_dma(tx_chn->ringtx, occ_tx); 481 } 482 EXPORT_SYMBOL_GPL(k3_udma_glue_reset_tx_chn); 483 484 u32 k3_udma_glue_tx_get_hdesc_size(struct k3_udma_glue_tx_channel *tx_chn) 485 { 486 return tx_chn->common.hdesc_size; 487 } 488 EXPORT_SYMBOL_GPL(k3_udma_glue_tx_get_hdesc_size); 489 490 u32 k3_udma_glue_tx_get_txcq_id(struct k3_udma_glue_tx_channel *tx_chn) 491 { 492 return k3_ringacc_get_ring_id(tx_chn->ringtxcq); 493 } 494 EXPORT_SYMBOL_GPL(k3_udma_glue_tx_get_txcq_id); 495 496 int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn) 497 { 498 tx_chn->virq = k3_ringacc_get_ring_irq_num(tx_chn->ringtxcq); 499 500 return tx_chn->virq; 501 } 502 EXPORT_SYMBOL_GPL(k3_udma_glue_tx_get_irq); 503 504 static int k3_udma_glue_cfg_rx_chn(struct k3_udma_glue_rx_channel *rx_chn) 505 { 506 const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm; 507 struct ti_sci_msg_rm_udmap_rx_ch_cfg req; 508 int ret; 509 510 memset(&req, 0, sizeof(req)); 511 512 req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | 513 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | 514 TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | 515 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | 516 TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | 517 TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID; 518 519 req.nav_id = tisci_rm->tisci_dev_id; 520 req.index = rx_chn->udma_rchan_id; 521 req.rx_fetch_size = rx_chn->common.hdesc_size >> 2; 522 /* 523 * TODO: we can't support rxcq_qnum/RCHAN[a]_RCQ cfg with current sysfw 524 * and udmax impl, so just configure it to invalid value. 525 * req.rxcq_qnum = k3_ringacc_get_ring_id(rx_chn->flows[0].ringrx); 526 */ 527 req.rxcq_qnum = 0xFFFF; 528 if (rx_chn->flow_num && rx_chn->flow_id_base != rx_chn->udma_rchan_id) { 529 /* Default flow + extra ones */ 530 req.flowid_start = rx_chn->flow_id_base; 531 req.flowid_cnt = rx_chn->flow_num; 532 } 533 req.rx_chan_type = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR; 534 req.rx_atype = rx_chn->common.atype; 535 536 ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req); 537 if (ret) 538 dev_err(rx_chn->common.dev, "rchan%d cfg failed %d\n", 539 rx_chn->udma_rchan_id, ret); 540 541 return ret; 542 } 543 544 static void k3_udma_glue_release_rx_flow(struct k3_udma_glue_rx_channel *rx_chn, 545 u32 flow_num) 546 { 547 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num]; 548 549 if (IS_ERR_OR_NULL(flow->udma_rflow)) 550 return; 551 552 if (flow->ringrxfdq) 553 k3_ringacc_ring_free(flow->ringrxfdq); 554 555 if (flow->ringrx) 556 k3_ringacc_ring_free(flow->ringrx); 557 558 xudma_rflow_put(rx_chn->common.udmax, flow->udma_rflow); 559 flow->udma_rflow = NULL; 560 rx_chn->flows_ready--; 561 } 562 563 static int k3_udma_glue_cfg_rx_flow(struct k3_udma_glue_rx_channel *rx_chn, 564 u32 flow_idx, 565 struct k3_udma_glue_rx_flow_cfg *flow_cfg) 566 { 567 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_idx]; 568 const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm; 569 struct device *dev = rx_chn->common.dev; 570 struct ti_sci_msg_rm_udmap_flow_cfg req; 571 int rx_ring_id; 572 int rx_ringfdq_id; 573 int ret = 0; 574 575 flow->udma_rflow = xudma_rflow_get(rx_chn->common.udmax, 576 flow->udma_rflow_id); 577 if (IS_ERR(flow->udma_rflow)) { 578 ret = PTR_ERR(flow->udma_rflow); 579 dev_err(dev, "UDMAX rflow get err %d\n", ret); 580 return ret; 581 } 582 583 if (flow->udma_rflow_id != xudma_rflow_get_id(flow->udma_rflow)) { 584 ret = -ENODEV; 585 goto err_rflow_put; 586 } 587 588 /* request and cfg rings */ 589 flow->ringrx = k3_ringacc_request_ring(rx_chn->common.ringacc, 590 flow_cfg->ring_rxq_id, 0); 591 if (!flow->ringrx) { 592 ret = -ENODEV; 593 dev_err(dev, "Failed to get RX ring\n"); 594 goto err_rflow_put; 595 } 596 597 flow->ringrxfdq = k3_ringacc_request_ring(rx_chn->common.ringacc, 598 flow_cfg->ring_rxfdq0_id, 0); 599 if (!flow->ringrxfdq) { 600 ret = -ENODEV; 601 dev_err(dev, "Failed to get RXFDQ ring\n"); 602 goto err_ringrx_free; 603 } 604 605 ret = k3_ringacc_ring_cfg(flow->ringrx, &flow_cfg->rx_cfg); 606 if (ret) { 607 dev_err(dev, "Failed to cfg ringrx %d\n", ret); 608 goto err_ringrxfdq_free; 609 } 610 611 ret = k3_ringacc_ring_cfg(flow->ringrxfdq, &flow_cfg->rxfdq_cfg); 612 if (ret) { 613 dev_err(dev, "Failed to cfg ringrxfdq %d\n", ret); 614 goto err_ringrxfdq_free; 615 } 616 617 if (rx_chn->remote) { 618 rx_ring_id = TI_SCI_RESOURCE_NULL; 619 rx_ringfdq_id = TI_SCI_RESOURCE_NULL; 620 } else { 621 rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx); 622 rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq); 623 } 624 625 memset(&req, 0, sizeof(req)); 626 627 req.valid_params = 628 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID | 629 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID | 630 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID | 631 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID | 632 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID | 633 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID | 634 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID | 635 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID | 636 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID | 637 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID | 638 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID | 639 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID | 640 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID; 641 req.nav_id = tisci_rm->tisci_dev_id; 642 req.flow_index = flow->udma_rflow_id; 643 if (rx_chn->common.epib) 644 req.rx_einfo_present = 1; 645 if (rx_chn->common.psdata_size) 646 req.rx_psinfo_present = 1; 647 if (flow_cfg->rx_error_handling) 648 req.rx_error_handling = 1; 649 req.rx_desc_type = 0; 650 req.rx_dest_qnum = rx_ring_id; 651 req.rx_src_tag_hi_sel = 0; 652 req.rx_src_tag_lo_sel = flow_cfg->src_tag_lo_sel; 653 req.rx_dest_tag_hi_sel = 0; 654 req.rx_dest_tag_lo_sel = 0; 655 req.rx_fdq0_sz0_qnum = rx_ringfdq_id; 656 req.rx_fdq1_qnum = rx_ringfdq_id; 657 req.rx_fdq2_qnum = rx_ringfdq_id; 658 req.rx_fdq3_qnum = rx_ringfdq_id; 659 660 ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req); 661 if (ret) { 662 dev_err(dev, "flow%d config failed: %d\n", flow->udma_rflow_id, 663 ret); 664 goto err_ringrxfdq_free; 665 } 666 667 rx_chn->flows_ready++; 668 dev_dbg(dev, "flow%d config done. ready:%d\n", 669 flow->udma_rflow_id, rx_chn->flows_ready); 670 671 return 0; 672 673 err_ringrxfdq_free: 674 k3_ringacc_ring_free(flow->ringrxfdq); 675 676 err_ringrx_free: 677 k3_ringacc_ring_free(flow->ringrx); 678 679 err_rflow_put: 680 xudma_rflow_put(rx_chn->common.udmax, flow->udma_rflow); 681 flow->udma_rflow = NULL; 682 683 return ret; 684 } 685 686 static void k3_udma_glue_dump_rx_chn(struct k3_udma_glue_rx_channel *chn) 687 { 688 struct device *dev = chn->common.dev; 689 690 dev_dbg(dev, "dump_rx_chn:\n" 691 "udma_rchan_id: %d\n" 692 "src_thread: %08x\n" 693 "dst_thread: %08x\n" 694 "epib: %d\n" 695 "hdesc_size: %u\n" 696 "psdata_size: %u\n" 697 "swdata_size: %u\n" 698 "flow_id_base: %d\n" 699 "flow_num: %d\n", 700 chn->udma_rchan_id, 701 chn->common.src_thread, 702 chn->common.dst_thread, 703 chn->common.epib, 704 chn->common.hdesc_size, 705 chn->common.psdata_size, 706 chn->common.swdata_size, 707 chn->flow_id_base, 708 chn->flow_num); 709 } 710 711 static void k3_udma_glue_dump_rx_rt_chn(struct k3_udma_glue_rx_channel *chn, 712 char *mark) 713 { 714 struct device *dev = chn->common.dev; 715 716 dev_dbg(dev, "=== dump ===> %s\n", mark); 717 718 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_CTL_REG, 719 xudma_rchanrt_read(chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG)); 720 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_PEER_RT_EN_REG, 721 xudma_rchanrt_read(chn->udma_rchanx, 722 UDMA_CHAN_RT_PEER_RT_EN_REG)); 723 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_PCNT_REG, 724 xudma_rchanrt_read(chn->udma_rchanx, UDMA_CHAN_RT_PCNT_REG)); 725 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_BCNT_REG, 726 xudma_rchanrt_read(chn->udma_rchanx, UDMA_CHAN_RT_BCNT_REG)); 727 dev_dbg(dev, "0x%08X: %08X\n", UDMA_CHAN_RT_SBCNT_REG, 728 xudma_rchanrt_read(chn->udma_rchanx, UDMA_CHAN_RT_SBCNT_REG)); 729 } 730 731 static int 732 k3_udma_glue_allocate_rx_flows(struct k3_udma_glue_rx_channel *rx_chn, 733 struct k3_udma_glue_rx_channel_cfg *cfg) 734 { 735 int ret; 736 737 /* default rflow */ 738 if (cfg->flow_id_use_rxchan_id) 739 return 0; 740 741 /* not a GP rflows */ 742 if (rx_chn->flow_id_base != -1 && 743 !xudma_rflow_is_gp(rx_chn->common.udmax, rx_chn->flow_id_base)) 744 return 0; 745 746 /* Allocate range of GP rflows */ 747 ret = xudma_alloc_gp_rflow_range(rx_chn->common.udmax, 748 rx_chn->flow_id_base, 749 rx_chn->flow_num); 750 if (ret < 0) { 751 dev_err(rx_chn->common.dev, "UDMAX reserve_rflow %d cnt:%d err: %d\n", 752 rx_chn->flow_id_base, rx_chn->flow_num, ret); 753 return ret; 754 } 755 rx_chn->flow_id_base = ret; 756 757 return 0; 758 } 759 760 static struct k3_udma_glue_rx_channel * 761 k3_udma_glue_request_rx_chn_priv(struct device *dev, const char *name, 762 struct k3_udma_glue_rx_channel_cfg *cfg) 763 { 764 struct k3_udma_glue_rx_channel *rx_chn; 765 int ret, i; 766 767 if (cfg->flow_id_num <= 0) 768 return ERR_PTR(-EINVAL); 769 770 if (cfg->flow_id_num != 1 && 771 (cfg->def_flow_cfg || cfg->flow_id_use_rxchan_id)) 772 return ERR_PTR(-EINVAL); 773 774 rx_chn = devm_kzalloc(dev, sizeof(*rx_chn), GFP_KERNEL); 775 if (!rx_chn) 776 return ERR_PTR(-ENOMEM); 777 778 rx_chn->common.dev = dev; 779 rx_chn->common.swdata_size = cfg->swdata_size; 780 rx_chn->remote = false; 781 782 /* parse of udmap channel */ 783 ret = of_k3_udma_glue_parse_chn(dev->of_node, name, 784 &rx_chn->common, false); 785 if (ret) 786 goto err; 787 788 rx_chn->common.hdesc_size = cppi5_hdesc_calc_size(rx_chn->common.epib, 789 rx_chn->common.psdata_size, 790 rx_chn->common.swdata_size); 791 792 /* request and cfg UDMAP RX channel */ 793 rx_chn->udma_rchanx = xudma_rchan_get(rx_chn->common.udmax, -1); 794 if (IS_ERR(rx_chn->udma_rchanx)) { 795 ret = PTR_ERR(rx_chn->udma_rchanx); 796 dev_err(dev, "UDMAX rchanx get err %d\n", ret); 797 goto err; 798 } 799 rx_chn->udma_rchan_id = xudma_rchan_get_id(rx_chn->udma_rchanx); 800 801 rx_chn->flow_num = cfg->flow_id_num; 802 rx_chn->flow_id_base = cfg->flow_id_base; 803 804 /* Use RX channel id as flow id: target dev can't generate flow_id */ 805 if (cfg->flow_id_use_rxchan_id) 806 rx_chn->flow_id_base = rx_chn->udma_rchan_id; 807 808 rx_chn->flows = devm_kcalloc(dev, rx_chn->flow_num, 809 sizeof(*rx_chn->flows), GFP_KERNEL); 810 if (!rx_chn->flows) { 811 ret = -ENOMEM; 812 goto err; 813 } 814 815 ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg); 816 if (ret) 817 goto err; 818 819 for (i = 0; i < rx_chn->flow_num; i++) 820 rx_chn->flows[i].udma_rflow_id = rx_chn->flow_id_base + i; 821 822 /* request and cfg psi-l */ 823 rx_chn->common.dst_thread = 824 xudma_dev_get_psil_base(rx_chn->common.udmax) + 825 rx_chn->udma_rchan_id; 826 827 ret = k3_udma_glue_cfg_rx_chn(rx_chn); 828 if (ret) { 829 dev_err(dev, "Failed to cfg rchan %d\n", ret); 830 goto err; 831 } 832 833 /* init default RX flow only if flow_num = 1 */ 834 if (cfg->def_flow_cfg) { 835 ret = k3_udma_glue_cfg_rx_flow(rx_chn, 0, cfg->def_flow_cfg); 836 if (ret) 837 goto err; 838 } 839 840 ret = xudma_navss_psil_pair(rx_chn->common.udmax, 841 rx_chn->common.src_thread, 842 rx_chn->common.dst_thread); 843 if (ret) { 844 dev_err(dev, "PSI-L request err %d\n", ret); 845 goto err; 846 } 847 848 rx_chn->psil_paired = true; 849 850 /* reset RX RT registers */ 851 k3_udma_glue_disable_rx_chn(rx_chn); 852 853 k3_udma_glue_dump_rx_chn(rx_chn); 854 855 return rx_chn; 856 857 err: 858 k3_udma_glue_release_rx_chn(rx_chn); 859 return ERR_PTR(ret); 860 } 861 862 static struct k3_udma_glue_rx_channel * 863 k3_udma_glue_request_remote_rx_chn(struct device *dev, const char *name, 864 struct k3_udma_glue_rx_channel_cfg *cfg) 865 { 866 struct k3_udma_glue_rx_channel *rx_chn; 867 int ret, i; 868 869 if (cfg->flow_id_num <= 0 || 870 cfg->flow_id_use_rxchan_id || 871 cfg->def_flow_cfg || 872 cfg->flow_id_base < 0) 873 return ERR_PTR(-EINVAL); 874 875 /* 876 * Remote RX channel is under control of Remote CPU core, so 877 * Linux can only request and manipulate by dedicated RX flows 878 */ 879 880 rx_chn = devm_kzalloc(dev, sizeof(*rx_chn), GFP_KERNEL); 881 if (!rx_chn) 882 return ERR_PTR(-ENOMEM); 883 884 rx_chn->common.dev = dev; 885 rx_chn->common.swdata_size = cfg->swdata_size; 886 rx_chn->remote = true; 887 rx_chn->udma_rchan_id = -1; 888 rx_chn->flow_num = cfg->flow_id_num; 889 rx_chn->flow_id_base = cfg->flow_id_base; 890 rx_chn->psil_paired = false; 891 892 /* parse of udmap channel */ 893 ret = of_k3_udma_glue_parse_chn(dev->of_node, name, 894 &rx_chn->common, false); 895 if (ret) 896 goto err; 897 898 rx_chn->common.hdesc_size = cppi5_hdesc_calc_size(rx_chn->common.epib, 899 rx_chn->common.psdata_size, 900 rx_chn->common.swdata_size); 901 902 rx_chn->flows = devm_kcalloc(dev, rx_chn->flow_num, 903 sizeof(*rx_chn->flows), GFP_KERNEL); 904 if (!rx_chn->flows) { 905 ret = -ENOMEM; 906 goto err; 907 } 908 909 ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg); 910 if (ret) 911 goto err; 912 913 for (i = 0; i < rx_chn->flow_num; i++) 914 rx_chn->flows[i].udma_rflow_id = rx_chn->flow_id_base + i; 915 916 k3_udma_glue_dump_rx_chn(rx_chn); 917 918 return rx_chn; 919 920 err: 921 k3_udma_glue_release_rx_chn(rx_chn); 922 return ERR_PTR(ret); 923 } 924 925 struct k3_udma_glue_rx_channel * 926 k3_udma_glue_request_rx_chn(struct device *dev, const char *name, 927 struct k3_udma_glue_rx_channel_cfg *cfg) 928 { 929 if (cfg->remote) 930 return k3_udma_glue_request_remote_rx_chn(dev, name, cfg); 931 else 932 return k3_udma_glue_request_rx_chn_priv(dev, name, cfg); 933 } 934 EXPORT_SYMBOL_GPL(k3_udma_glue_request_rx_chn); 935 936 void k3_udma_glue_release_rx_chn(struct k3_udma_glue_rx_channel *rx_chn) 937 { 938 int i; 939 940 if (IS_ERR_OR_NULL(rx_chn->common.udmax)) 941 return; 942 943 if (rx_chn->psil_paired) { 944 xudma_navss_psil_unpair(rx_chn->common.udmax, 945 rx_chn->common.src_thread, 946 rx_chn->common.dst_thread); 947 rx_chn->psil_paired = false; 948 } 949 950 for (i = 0; i < rx_chn->flow_num; i++) 951 k3_udma_glue_release_rx_flow(rx_chn, i); 952 953 if (xudma_rflow_is_gp(rx_chn->common.udmax, rx_chn->flow_id_base)) 954 xudma_free_gp_rflow_range(rx_chn->common.udmax, 955 rx_chn->flow_id_base, 956 rx_chn->flow_num); 957 958 if (!IS_ERR_OR_NULL(rx_chn->udma_rchanx)) 959 xudma_rchan_put(rx_chn->common.udmax, 960 rx_chn->udma_rchanx); 961 } 962 EXPORT_SYMBOL_GPL(k3_udma_glue_release_rx_chn); 963 964 int k3_udma_glue_rx_flow_init(struct k3_udma_glue_rx_channel *rx_chn, 965 u32 flow_idx, 966 struct k3_udma_glue_rx_flow_cfg *flow_cfg) 967 { 968 if (flow_idx >= rx_chn->flow_num) 969 return -EINVAL; 970 971 return k3_udma_glue_cfg_rx_flow(rx_chn, flow_idx, flow_cfg); 972 } 973 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_init); 974 975 u32 k3_udma_glue_rx_flow_get_fdq_id(struct k3_udma_glue_rx_channel *rx_chn, 976 u32 flow_idx) 977 { 978 struct k3_udma_glue_rx_flow *flow; 979 980 if (flow_idx >= rx_chn->flow_num) 981 return -EINVAL; 982 983 flow = &rx_chn->flows[flow_idx]; 984 985 return k3_ringacc_get_ring_id(flow->ringrxfdq); 986 } 987 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_get_fdq_id); 988 989 u32 k3_udma_glue_rx_get_flow_id_base(struct k3_udma_glue_rx_channel *rx_chn) 990 { 991 return rx_chn->flow_id_base; 992 } 993 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_get_flow_id_base); 994 995 int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn, 996 u32 flow_idx) 997 { 998 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_idx]; 999 const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm; 1000 struct device *dev = rx_chn->common.dev; 1001 struct ti_sci_msg_rm_udmap_flow_cfg req; 1002 int rx_ring_id; 1003 int rx_ringfdq_id; 1004 int ret = 0; 1005 1006 if (!rx_chn->remote) 1007 return -EINVAL; 1008 1009 rx_ring_id = k3_ringacc_get_ring_id(flow->ringrx); 1010 rx_ringfdq_id = k3_ringacc_get_ring_id(flow->ringrxfdq); 1011 1012 memset(&req, 0, sizeof(req)); 1013 1014 req.valid_params = 1015 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID | 1016 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID | 1017 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID | 1018 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID | 1019 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID; 1020 req.nav_id = tisci_rm->tisci_dev_id; 1021 req.flow_index = flow->udma_rflow_id; 1022 req.rx_dest_qnum = rx_ring_id; 1023 req.rx_fdq0_sz0_qnum = rx_ringfdq_id; 1024 req.rx_fdq1_qnum = rx_ringfdq_id; 1025 req.rx_fdq2_qnum = rx_ringfdq_id; 1026 req.rx_fdq3_qnum = rx_ringfdq_id; 1027 1028 ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req); 1029 if (ret) { 1030 dev_err(dev, "flow%d enable failed: %d\n", flow->udma_rflow_id, 1031 ret); 1032 } 1033 1034 return ret; 1035 } 1036 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_enable); 1037 1038 int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn, 1039 u32 flow_idx) 1040 { 1041 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_idx]; 1042 const struct udma_tisci_rm *tisci_rm = rx_chn->common.tisci_rm; 1043 struct device *dev = rx_chn->common.dev; 1044 struct ti_sci_msg_rm_udmap_flow_cfg req; 1045 int ret = 0; 1046 1047 if (!rx_chn->remote) 1048 return -EINVAL; 1049 1050 memset(&req, 0, sizeof(req)); 1051 req.valid_params = 1052 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID | 1053 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID | 1054 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID | 1055 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID | 1056 TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID; 1057 req.nav_id = tisci_rm->tisci_dev_id; 1058 req.flow_index = flow->udma_rflow_id; 1059 req.rx_dest_qnum = TI_SCI_RESOURCE_NULL; 1060 req.rx_fdq0_sz0_qnum = TI_SCI_RESOURCE_NULL; 1061 req.rx_fdq1_qnum = TI_SCI_RESOURCE_NULL; 1062 req.rx_fdq2_qnum = TI_SCI_RESOURCE_NULL; 1063 req.rx_fdq3_qnum = TI_SCI_RESOURCE_NULL; 1064 1065 ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci, &req); 1066 if (ret) { 1067 dev_err(dev, "flow%d disable failed: %d\n", flow->udma_rflow_id, 1068 ret); 1069 } 1070 1071 return ret; 1072 } 1073 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_flow_disable); 1074 1075 int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn) 1076 { 1077 u32 rxrt_ctl; 1078 1079 if (rx_chn->remote) 1080 return -EINVAL; 1081 1082 if (rx_chn->flows_ready < rx_chn->flow_num) 1083 return -EINVAL; 1084 1085 rxrt_ctl = xudma_rchanrt_read(rx_chn->udma_rchanx, 1086 UDMA_CHAN_RT_CTL_REG); 1087 rxrt_ctl |= UDMA_CHAN_RT_CTL_EN; 1088 xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, 1089 rxrt_ctl); 1090 1091 xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, 1092 UDMA_PEER_RT_EN_ENABLE); 1093 1094 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt en"); 1095 return 0; 1096 } 1097 EXPORT_SYMBOL_GPL(k3_udma_glue_enable_rx_chn); 1098 1099 void k3_udma_glue_disable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn) 1100 { 1101 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt dis1"); 1102 1103 xudma_rchanrt_write(rx_chn->udma_rchanx, 1104 UDMA_CHAN_RT_PEER_RT_EN_REG, 0); 1105 xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG, 0); 1106 1107 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt dis2"); 1108 } 1109 EXPORT_SYMBOL_GPL(k3_udma_glue_disable_rx_chn); 1110 1111 void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, 1112 bool sync) 1113 { 1114 int i = 0; 1115 u32 val; 1116 1117 if (rx_chn->remote) 1118 return; 1119 1120 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown1"); 1121 1122 xudma_rchanrt_write(rx_chn->udma_rchanx, UDMA_CHAN_RT_PEER_RT_EN_REG, 1123 UDMA_PEER_RT_EN_ENABLE | UDMA_PEER_RT_EN_TEARDOWN); 1124 1125 val = xudma_rchanrt_read(rx_chn->udma_rchanx, UDMA_CHAN_RT_CTL_REG); 1126 1127 while (sync && (val & UDMA_CHAN_RT_CTL_EN)) { 1128 val = xudma_rchanrt_read(rx_chn->udma_rchanx, 1129 UDMA_CHAN_RT_CTL_REG); 1130 udelay(1); 1131 if (i > K3_UDMAX_TDOWN_TIMEOUT_US) { 1132 dev_err(rx_chn->common.dev, "RX tdown timeout\n"); 1133 break; 1134 } 1135 i++; 1136 } 1137 1138 val = xudma_rchanrt_read(rx_chn->udma_rchanx, 1139 UDMA_CHAN_RT_PEER_RT_EN_REG); 1140 if (sync && (val & UDMA_PEER_RT_EN_ENABLE)) 1141 dev_err(rx_chn->common.dev, "TX tdown peer not stopped\n"); 1142 k3_udma_glue_dump_rx_rt_chn(rx_chn, "rxrt tdown2"); 1143 } 1144 EXPORT_SYMBOL_GPL(k3_udma_glue_tdown_rx_chn); 1145 1146 void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, 1147 u32 flow_num, void *data, 1148 void (*cleanup)(void *data, dma_addr_t desc_dma), bool skip_fdq) 1149 { 1150 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num]; 1151 struct device *dev = rx_chn->common.dev; 1152 dma_addr_t desc_dma; 1153 int occ_rx, i, ret; 1154 1155 /* reset RXCQ as it is not input for udma - expected to be empty */ 1156 occ_rx = k3_ringacc_ring_get_occ(flow->ringrx); 1157 dev_dbg(dev, "RX reset flow %u occ_rx %u\n", flow_num, occ_rx); 1158 if (flow->ringrx) 1159 k3_ringacc_ring_reset(flow->ringrx); 1160 1161 /* Skip RX FDQ in case one FDQ is used for the set of flows */ 1162 if (skip_fdq) 1163 return; 1164 1165 /* 1166 * RX FDQ reset need to be special way as it is input for udma and its 1167 * state cached by udma, so: 1168 * 1) save RX FDQ occ 1169 * 2) clean up RX FDQ and call callback .cleanup() for each desc 1170 * 3) reset RX FDQ in a special way 1171 */ 1172 occ_rx = k3_ringacc_ring_get_occ(flow->ringrxfdq); 1173 dev_dbg(dev, "RX reset flow %u occ_rx_fdq %u\n", flow_num, occ_rx); 1174 1175 for (i = 0; i < occ_rx; i++) { 1176 ret = k3_ringacc_ring_pop(flow->ringrxfdq, &desc_dma); 1177 if (ret) { 1178 dev_err(dev, "RX reset pop %d\n", ret); 1179 break; 1180 } 1181 cleanup(data, desc_dma); 1182 } 1183 1184 k3_ringacc_ring_reset_dma(flow->ringrxfdq, occ_rx); 1185 } 1186 EXPORT_SYMBOL_GPL(k3_udma_glue_reset_rx_chn); 1187 1188 int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, 1189 u32 flow_num, struct cppi5_host_desc_t *desc_rx, 1190 dma_addr_t desc_dma) 1191 { 1192 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num]; 1193 1194 return k3_ringacc_ring_push(flow->ringrxfdq, &desc_dma); 1195 } 1196 EXPORT_SYMBOL_GPL(k3_udma_glue_push_rx_chn); 1197 1198 int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_channel *rx_chn, 1199 u32 flow_num, dma_addr_t *desc_dma) 1200 { 1201 struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num]; 1202 1203 return k3_ringacc_ring_pop(flow->ringrx, desc_dma); 1204 } 1205 EXPORT_SYMBOL_GPL(k3_udma_glue_pop_rx_chn); 1206 1207 int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn, 1208 u32 flow_num) 1209 { 1210 struct k3_udma_glue_rx_flow *flow; 1211 1212 flow = &rx_chn->flows[flow_num]; 1213 1214 flow->virq = k3_ringacc_get_ring_irq_num(flow->ringrx); 1215 1216 return flow->virq; 1217 } 1218 EXPORT_SYMBOL_GPL(k3_udma_glue_rx_get_irq); 1219