1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com 4 */ 5 6 #include <linux/kernel.h> 7 8 #include "k3-psil-priv.h" 9 10 #define PSIL_PDMA_XY_TR(x) \ 11 { \ 12 .thread_id = x, \ 13 .ep_config = { \ 14 .ep_type = PSIL_EP_PDMA_XY, \ 15 }, \ 16 } 17 18 #define PSIL_PDMA_XY_PKT(x) \ 19 { \ 20 .thread_id = x, \ 21 .ep_config = { \ 22 .ep_type = PSIL_EP_PDMA_XY, \ 23 .pkt_mode = 1, \ 24 }, \ 25 } 26 27 #define PSIL_PDMA_MCASP(x) \ 28 { \ 29 .thread_id = x, \ 30 .ep_config = { \ 31 .ep_type = PSIL_EP_PDMA_XY, \ 32 .pdma_acc32 = 1, \ 33 .pdma_burst = 1, \ 34 }, \ 35 } 36 37 #define PSIL_ETHERNET(x) \ 38 { \ 39 .thread_id = x, \ 40 .ep_config = { \ 41 .ep_type = PSIL_EP_NATIVE, \ 42 .pkt_mode = 1, \ 43 .needs_epib = 1, \ 44 .psd_size = 16, \ 45 }, \ 46 } 47 48 #define PSIL_SA2UL(x, tx) \ 49 { \ 50 .thread_id = x, \ 51 .ep_config = { \ 52 .ep_type = PSIL_EP_NATIVE, \ 53 .pkt_mode = 1, \ 54 .needs_epib = 1, \ 55 .psd_size = 64, \ 56 .notdpkt = tx, \ 57 }, \ 58 } 59 60 #define PSIL_CSI2RX(x) \ 61 { \ 62 .thread_id = x, \ 63 .ep_config = { \ 64 .ep_type = PSIL_EP_NATIVE, \ 65 }, \ 66 } 67 68 /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ 69 static struct psil_ep j721s2_src_ep_map[] = { 70 /* PDMA_MCASP - McASP0-4 */ 71 PSIL_PDMA_MCASP(0x4400), 72 PSIL_PDMA_MCASP(0x4401), 73 PSIL_PDMA_MCASP(0x4402), 74 PSIL_PDMA_MCASP(0x4403), 75 PSIL_PDMA_MCASP(0x4404), 76 /* PDMA_SPI_G0 - SPI0-3 */ 77 PSIL_PDMA_XY_PKT(0x4600), 78 PSIL_PDMA_XY_PKT(0x4601), 79 PSIL_PDMA_XY_PKT(0x4602), 80 PSIL_PDMA_XY_PKT(0x4603), 81 PSIL_PDMA_XY_PKT(0x4604), 82 PSIL_PDMA_XY_PKT(0x4605), 83 PSIL_PDMA_XY_PKT(0x4606), 84 PSIL_PDMA_XY_PKT(0x4607), 85 PSIL_PDMA_XY_PKT(0x4608), 86 PSIL_PDMA_XY_PKT(0x4609), 87 PSIL_PDMA_XY_PKT(0x460a), 88 PSIL_PDMA_XY_PKT(0x460b), 89 PSIL_PDMA_XY_PKT(0x460c), 90 PSIL_PDMA_XY_PKT(0x460d), 91 PSIL_PDMA_XY_PKT(0x460e), 92 PSIL_PDMA_XY_PKT(0x460f), 93 /* PDMA_SPI_G1 - SPI4-7 */ 94 PSIL_PDMA_XY_PKT(0x4610), 95 PSIL_PDMA_XY_PKT(0x4611), 96 PSIL_PDMA_XY_PKT(0x4612), 97 PSIL_PDMA_XY_PKT(0x4613), 98 PSIL_PDMA_XY_PKT(0x4614), 99 PSIL_PDMA_XY_PKT(0x4615), 100 PSIL_PDMA_XY_PKT(0x4616), 101 PSIL_PDMA_XY_PKT(0x4617), 102 PSIL_PDMA_XY_PKT(0x4618), 103 PSIL_PDMA_XY_PKT(0x4619), 104 PSIL_PDMA_XY_PKT(0x461a), 105 PSIL_PDMA_XY_PKT(0x461b), 106 PSIL_PDMA_XY_PKT(0x461c), 107 PSIL_PDMA_XY_PKT(0x461d), 108 PSIL_PDMA_XY_PKT(0x461e), 109 PSIL_PDMA_XY_PKT(0x461f), 110 /* MAIN_CPSW2G */ 111 PSIL_ETHERNET(0x4640), 112 /* PDMA_USART_G0 - UART0-1 */ 113 PSIL_PDMA_XY_PKT(0x4700), 114 PSIL_PDMA_XY_PKT(0x4701), 115 /* PDMA_USART_G1 - UART2-3 */ 116 PSIL_PDMA_XY_PKT(0x4702), 117 PSIL_PDMA_XY_PKT(0x4703), 118 /* PDMA_USART_G2 - UART4-9 */ 119 PSIL_PDMA_XY_PKT(0x4704), 120 PSIL_PDMA_XY_PKT(0x4705), 121 PSIL_PDMA_XY_PKT(0x4706), 122 PSIL_PDMA_XY_PKT(0x4707), 123 PSIL_PDMA_XY_PKT(0x4708), 124 PSIL_PDMA_XY_PKT(0x4709), 125 /* CSI2RX */ 126 PSIL_CSI2RX(0x4940), 127 PSIL_CSI2RX(0x4941), 128 PSIL_CSI2RX(0x4942), 129 PSIL_CSI2RX(0x4943), 130 PSIL_CSI2RX(0x4944), 131 PSIL_CSI2RX(0x4945), 132 PSIL_CSI2RX(0x4946), 133 PSIL_CSI2RX(0x4947), 134 PSIL_CSI2RX(0x4948), 135 PSIL_CSI2RX(0x4949), 136 PSIL_CSI2RX(0x494a), 137 PSIL_CSI2RX(0x494b), 138 PSIL_CSI2RX(0x494c), 139 PSIL_CSI2RX(0x494d), 140 PSIL_CSI2RX(0x494e), 141 PSIL_CSI2RX(0x494f), 142 PSIL_CSI2RX(0x4950), 143 PSIL_CSI2RX(0x4951), 144 PSIL_CSI2RX(0x4952), 145 PSIL_CSI2RX(0x4953), 146 PSIL_CSI2RX(0x4954), 147 PSIL_CSI2RX(0x4955), 148 PSIL_CSI2RX(0x4956), 149 PSIL_CSI2RX(0x4957), 150 PSIL_CSI2RX(0x4958), 151 PSIL_CSI2RX(0x4959), 152 PSIL_CSI2RX(0x495a), 153 PSIL_CSI2RX(0x495b), 154 PSIL_CSI2RX(0x495c), 155 PSIL_CSI2RX(0x495d), 156 PSIL_CSI2RX(0x495e), 157 PSIL_CSI2RX(0x495f), 158 PSIL_CSI2RX(0x4960), 159 PSIL_CSI2RX(0x4961), 160 PSIL_CSI2RX(0x4962), 161 PSIL_CSI2RX(0x4963), 162 PSIL_CSI2RX(0x4964), 163 PSIL_CSI2RX(0x4965), 164 PSIL_CSI2RX(0x4966), 165 PSIL_CSI2RX(0x4967), 166 PSIL_CSI2RX(0x4968), 167 PSIL_CSI2RX(0x4969), 168 PSIL_CSI2RX(0x496a), 169 PSIL_CSI2RX(0x496b), 170 PSIL_CSI2RX(0x496c), 171 PSIL_CSI2RX(0x496d), 172 PSIL_CSI2RX(0x496e), 173 PSIL_CSI2RX(0x496f), 174 PSIL_CSI2RX(0x4970), 175 PSIL_CSI2RX(0x4971), 176 PSIL_CSI2RX(0x4972), 177 PSIL_CSI2RX(0x4973), 178 PSIL_CSI2RX(0x4974), 179 PSIL_CSI2RX(0x4975), 180 PSIL_CSI2RX(0x4976), 181 PSIL_CSI2RX(0x4977), 182 PSIL_CSI2RX(0x4978), 183 PSIL_CSI2RX(0x4979), 184 PSIL_CSI2RX(0x497a), 185 PSIL_CSI2RX(0x497b), 186 PSIL_CSI2RX(0x497c), 187 PSIL_CSI2RX(0x497d), 188 PSIL_CSI2RX(0x497e), 189 PSIL_CSI2RX(0x497f), 190 /* MAIN SA2UL */ 191 PSIL_SA2UL(0x4a40, 0), 192 PSIL_SA2UL(0x4a41, 0), 193 PSIL_SA2UL(0x4a42, 0), 194 PSIL_SA2UL(0x4a43, 0), 195 /* CPSW0 */ 196 PSIL_ETHERNET(0x7000), 197 /* MCU_PDMA0 (MCU_PDMA_MISC_G0) - SPI0 */ 198 PSIL_PDMA_XY_PKT(0x7100), 199 PSIL_PDMA_XY_PKT(0x7101), 200 PSIL_PDMA_XY_PKT(0x7102), 201 PSIL_PDMA_XY_PKT(0x7103), 202 /* MCU_PDMA1 (MCU_PDMA_MISC_G1) - SPI1-2 */ 203 PSIL_PDMA_XY_PKT(0x7200), 204 PSIL_PDMA_XY_PKT(0x7201), 205 PSIL_PDMA_XY_PKT(0x7202), 206 PSIL_PDMA_XY_PKT(0x7203), 207 PSIL_PDMA_XY_PKT(0x7204), 208 PSIL_PDMA_XY_PKT(0x7205), 209 PSIL_PDMA_XY_PKT(0x7206), 210 PSIL_PDMA_XY_PKT(0x7207), 211 /* MCU_PDMA2 (MCU_PDMA_MISC_G2) - UART0 */ 212 PSIL_PDMA_XY_PKT(0x7300), 213 /* MCU_PDMA_ADC - ADC0-1 */ 214 PSIL_PDMA_XY_TR(0x7400), 215 PSIL_PDMA_XY_TR(0x7401), 216 PSIL_PDMA_XY_TR(0x7402), 217 PSIL_PDMA_XY_TR(0x7403), 218 /* SA2UL */ 219 PSIL_SA2UL(0x7500, 0), 220 PSIL_SA2UL(0x7501, 0), 221 PSIL_SA2UL(0x7502, 0), 222 PSIL_SA2UL(0x7503, 0), 223 }; 224 225 /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ 226 static struct psil_ep j721s2_dst_ep_map[] = { 227 /* MAIN SA2UL */ 228 PSIL_SA2UL(0xca40, 1), 229 PSIL_SA2UL(0xca41, 1), 230 /* CPSW0 */ 231 PSIL_ETHERNET(0xf000), 232 PSIL_ETHERNET(0xf001), 233 PSIL_ETHERNET(0xf002), 234 PSIL_ETHERNET(0xf003), 235 PSIL_ETHERNET(0xf004), 236 PSIL_ETHERNET(0xf005), 237 PSIL_ETHERNET(0xf006), 238 PSIL_ETHERNET(0xf007), 239 /* MAIN_CPSW2G */ 240 PSIL_ETHERNET(0xc640), 241 PSIL_ETHERNET(0xc641), 242 PSIL_ETHERNET(0xc642), 243 PSIL_ETHERNET(0xc643), 244 PSIL_ETHERNET(0xc644), 245 PSIL_ETHERNET(0xc645), 246 PSIL_ETHERNET(0xc646), 247 PSIL_ETHERNET(0xc647), 248 /* SA2UL */ 249 PSIL_SA2UL(0xf500, 1), 250 PSIL_SA2UL(0xf501, 1), 251 }; 252 253 struct psil_ep_map j721s2_ep_map = { 254 .name = "j721s2", 255 .src = j721s2_src_ep_map, 256 .src_count = ARRAY_SIZE(j721s2_src_ep_map), 257 .dst = j721s2_dst_ep_map, 258 .dst_count = ARRAY_SIZE(j721s2_dst_ep_map), 259 }; 260