1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2013-2014 Allwinner Tech Co., Ltd 4 * Author: Sugar <shuge@allwinnertech.com> 5 * 6 * Copyright (C) 2014 Maxime Ripard 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dmapool.h> 15 #include <linux/interrupt.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_dma.h> 19 #include <linux/platform_device.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/string_choices.h> 23 #include <linux/types.h> 24 25 #include "virt-dma.h" 26 27 /* 28 * Common registers 29 */ 30 #define DMA_IRQ_EN(x) ((x) * 0x04) 31 #define DMA_IRQ_HALF BIT(0) 32 #define DMA_IRQ_PKG BIT(1) 33 #define DMA_IRQ_QUEUE BIT(2) 34 35 #define DMA_IRQ_CHAN_NR 8 36 #define DMA_IRQ_CHAN_WIDTH 4 37 38 39 #define DMA_IRQ_STAT(x) ((x) * 0x04 + 0x10) 40 41 #define DMA_STAT 0x30 42 43 /* Offset between DMA_IRQ_EN and DMA_IRQ_STAT limits number of channels */ 44 #define DMA_MAX_CHANNELS (DMA_IRQ_CHAN_NR * 0x10 / 4) 45 46 /* 47 * sun8i specific registers 48 */ 49 #define SUN8I_DMA_GATE 0x20 50 #define SUN8I_DMA_GATE_ENABLE 0x4 51 52 #define SUNXI_H3_SECURE_REG 0x20 53 #define SUNXI_H3_DMA_GATE 0x28 54 #define SUNXI_H3_DMA_GATE_ENABLE 0x4 55 /* 56 * Channels specific registers 57 */ 58 #define DMA_CHAN_ENABLE 0x00 59 #define DMA_CHAN_ENABLE_START BIT(0) 60 #define DMA_CHAN_ENABLE_STOP 0 61 62 #define DMA_CHAN_PAUSE 0x04 63 #define DMA_CHAN_PAUSE_PAUSE BIT(1) 64 #define DMA_CHAN_PAUSE_RESUME 0 65 66 #define DMA_CHAN_LLI_ADDR 0x08 67 68 #define DMA_CHAN_CUR_CFG 0x0c 69 #define DMA_CHAN_MAX_DRQ_A31 0x1f 70 #define DMA_CHAN_MAX_DRQ_H6 0x3f 71 #define DMA_CHAN_CFG_SRC_DRQ_A31(x) ((x) & DMA_CHAN_MAX_DRQ_A31) 72 #define DMA_CHAN_CFG_SRC_DRQ_H6(x) ((x) & DMA_CHAN_MAX_DRQ_H6) 73 #define DMA_CHAN_CFG_SRC_MODE_A31(x) (((x) & 0x1) << 5) 74 #define DMA_CHAN_CFG_SRC_MODE_H6(x) (((x) & 0x1) << 8) 75 #define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) 76 #define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) 77 #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) 78 79 #define DMA_CHAN_CFG_DST_DRQ_A31(x) (DMA_CHAN_CFG_SRC_DRQ_A31(x) << 16) 80 #define DMA_CHAN_CFG_DST_DRQ_H6(x) (DMA_CHAN_CFG_SRC_DRQ_H6(x) << 16) 81 #define DMA_CHAN_CFG_DST_MODE_A31(x) (DMA_CHAN_CFG_SRC_MODE_A31(x) << 16) 82 #define DMA_CHAN_CFG_DST_MODE_H6(x) (DMA_CHAN_CFG_SRC_MODE_H6(x) << 16) 83 #define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << 16) 84 #define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) << 16) 85 #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) 86 87 #define DMA_CHAN_CUR_SRC 0x10 88 89 #define DMA_CHAN_CUR_DST 0x14 90 91 #define DMA_CHAN_CUR_CNT 0x18 92 93 #define DMA_CHAN_CUR_PARA 0x1c 94 95 /* 96 * LLI address mangling 97 * 98 * The LLI link physical address is also mangled, but we avoid dealing 99 * with that by allocating LLIs from the DMA32 zone. 100 */ 101 #define SRC_HIGH_ADDR(x) (((x) & 0x3U) << 16) 102 #define DST_HIGH_ADDR(x) (((x) & 0x3U) << 18) 103 104 /* 105 * Various hardware related defines 106 */ 107 #define LLI_LAST_ITEM 0xfffff800 108 #define NORMAL_WAIT 8 109 #define DRQ_SDRAM 1 110 #define LINEAR_MODE 0 111 #define IO_MODE 1 112 113 /* forward declaration */ 114 struct sun6i_dma_dev; 115 116 /* 117 * Hardware channels / ports representation 118 * 119 * The hardware is used in several SoCs, with differing numbers 120 * of channels and endpoints. This structure ties those numbers 121 * to a certain compatible string. 122 */ 123 struct sun6i_dma_config { 124 u32 nr_max_channels; 125 u32 nr_max_requests; 126 u32 nr_max_vchans; 127 /* 128 * In the datasheets/user manuals of newer Allwinner SoCs, a special 129 * bit (bit 2 at register 0x20) is present. 130 * It's named "DMA MCLK interface circuit auto gating bit" in the 131 * documents, and the footnote of this register says that this bit 132 * should be set up when initializing the DMA controller. 133 * Allwinner A23/A33 user manuals do not have this bit documented, 134 * however these SoCs really have and need this bit, as seen in the 135 * BSP kernel source code. 136 */ 137 void (*clock_autogate_enable)(struct sun6i_dma_dev *); 138 void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst); 139 void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq); 140 void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode); 141 u32 src_burst_lengths; 142 u32 dst_burst_lengths; 143 u32 src_addr_widths; 144 u32 dst_addr_widths; 145 bool has_high_addr; 146 bool has_mbus_clk; 147 }; 148 149 /* 150 * Hardware representation of the LLI 151 * 152 * The hardware will be fed the physical address of this structure, 153 * and read its content in order to start the transfer. 154 */ 155 struct sun6i_dma_lli { 156 u32 cfg; 157 u32 src; 158 u32 dst; 159 u32 len; 160 u32 para; 161 u32 p_lli_next; 162 163 /* 164 * This field is not used by the DMA controller, but will be 165 * used by the CPU to go through the list (mostly for dumping 166 * or freeing it). 167 */ 168 struct sun6i_dma_lli *v_lli_next; 169 }; 170 171 172 struct sun6i_desc { 173 struct virt_dma_desc vd; 174 dma_addr_t p_lli; 175 struct sun6i_dma_lli *v_lli; 176 }; 177 178 struct sun6i_pchan { 179 u32 idx; 180 void __iomem *base; 181 struct sun6i_vchan *vchan; 182 struct sun6i_desc *desc; 183 struct sun6i_desc *done; 184 }; 185 186 struct sun6i_vchan { 187 struct virt_dma_chan vc; 188 struct list_head node; 189 struct dma_slave_config cfg; 190 struct sun6i_pchan *phy; 191 u8 port; 192 u8 irq_type; 193 bool cyclic; 194 }; 195 196 struct sun6i_dma_dev { 197 struct dma_device slave; 198 void __iomem *base; 199 struct clk *clk; 200 struct clk *clk_mbus; 201 int irq; 202 spinlock_t lock; 203 struct reset_control *rstc; 204 struct tasklet_struct task; 205 atomic_t tasklet_shutdown; 206 struct list_head pending; 207 struct dma_pool *pool; 208 struct sun6i_pchan *pchans; 209 struct sun6i_vchan *vchans; 210 const struct sun6i_dma_config *cfg; 211 u32 num_pchans; 212 u32 num_vchans; 213 u32 max_request; 214 }; 215 216 static struct device *chan2dev(struct dma_chan *chan) 217 { 218 return &chan->dev->device; 219 } 220 221 static inline struct sun6i_dma_dev *to_sun6i_dma_dev(struct dma_device *d) 222 { 223 return container_of(d, struct sun6i_dma_dev, slave); 224 } 225 226 static inline struct sun6i_vchan *to_sun6i_vchan(struct dma_chan *chan) 227 { 228 return container_of(chan, struct sun6i_vchan, vc.chan); 229 } 230 231 static inline struct sun6i_desc * 232 to_sun6i_desc(struct dma_async_tx_descriptor *tx) 233 { 234 return container_of(tx, struct sun6i_desc, vd.tx); 235 } 236 237 static inline void sun6i_dma_dump_com_regs(struct sun6i_dma_dev *sdev) 238 { 239 dev_dbg(sdev->slave.dev, "Common register:\n" 240 "\tmask0(%04x): 0x%08x\n" 241 "\tmask1(%04x): 0x%08x\n" 242 "\tpend0(%04x): 0x%08x\n" 243 "\tpend1(%04x): 0x%08x\n" 244 "\tstats(%04x): 0x%08x\n", 245 DMA_IRQ_EN(0), readl(sdev->base + DMA_IRQ_EN(0)), 246 DMA_IRQ_EN(1), readl(sdev->base + DMA_IRQ_EN(1)), 247 DMA_IRQ_STAT(0), readl(sdev->base + DMA_IRQ_STAT(0)), 248 DMA_IRQ_STAT(1), readl(sdev->base + DMA_IRQ_STAT(1)), 249 DMA_STAT, readl(sdev->base + DMA_STAT)); 250 } 251 252 static inline void sun6i_dma_dump_chan_regs(struct sun6i_dma_dev *sdev, 253 struct sun6i_pchan *pchan) 254 { 255 dev_dbg(sdev->slave.dev, "Chan %d reg:\n" 256 "\t___en(%04x): \t0x%08x\n" 257 "\tpause(%04x): \t0x%08x\n" 258 "\tstart(%04x): \t0x%08x\n" 259 "\t__cfg(%04x): \t0x%08x\n" 260 "\t__src(%04x): \t0x%08x\n" 261 "\t__dst(%04x): \t0x%08x\n" 262 "\tcount(%04x): \t0x%08x\n" 263 "\t_para(%04x): \t0x%08x\n\n", 264 pchan->idx, 265 DMA_CHAN_ENABLE, 266 readl(pchan->base + DMA_CHAN_ENABLE), 267 DMA_CHAN_PAUSE, 268 readl(pchan->base + DMA_CHAN_PAUSE), 269 DMA_CHAN_LLI_ADDR, 270 readl(pchan->base + DMA_CHAN_LLI_ADDR), 271 DMA_CHAN_CUR_CFG, 272 readl(pchan->base + DMA_CHAN_CUR_CFG), 273 DMA_CHAN_CUR_SRC, 274 readl(pchan->base + DMA_CHAN_CUR_SRC), 275 DMA_CHAN_CUR_DST, 276 readl(pchan->base + DMA_CHAN_CUR_DST), 277 DMA_CHAN_CUR_CNT, 278 readl(pchan->base + DMA_CHAN_CUR_CNT), 279 DMA_CHAN_CUR_PARA, 280 readl(pchan->base + DMA_CHAN_CUR_PARA)); 281 } 282 283 static inline s8 convert_burst(u32 maxburst) 284 { 285 switch (maxburst) { 286 case 1: 287 return 0; 288 case 4: 289 return 1; 290 case 8: 291 return 2; 292 case 16: 293 return 3; 294 default: 295 return -EINVAL; 296 } 297 } 298 299 static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width) 300 { 301 return ilog2(addr_width); 302 } 303 304 static void sun6i_enable_clock_autogate_a23(struct sun6i_dma_dev *sdev) 305 { 306 writel(SUN8I_DMA_GATE_ENABLE, sdev->base + SUN8I_DMA_GATE); 307 } 308 309 static void sun6i_enable_clock_autogate_h3(struct sun6i_dma_dev *sdev) 310 { 311 writel(SUNXI_H3_DMA_GATE_ENABLE, sdev->base + SUNXI_H3_DMA_GATE); 312 } 313 314 static void sun6i_set_burst_length_a31(u32 *p_cfg, s8 src_burst, s8 dst_burst) 315 { 316 *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) | 317 DMA_CHAN_CFG_DST_BURST_A31(dst_burst); 318 } 319 320 static void sun6i_set_burst_length_h3(u32 *p_cfg, s8 src_burst, s8 dst_burst) 321 { 322 *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) | 323 DMA_CHAN_CFG_DST_BURST_H3(dst_burst); 324 } 325 326 static void sun6i_set_drq_a31(u32 *p_cfg, s8 src_drq, s8 dst_drq) 327 { 328 *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_A31(src_drq) | 329 DMA_CHAN_CFG_DST_DRQ_A31(dst_drq); 330 } 331 332 static void sun6i_set_drq_h6(u32 *p_cfg, s8 src_drq, s8 dst_drq) 333 { 334 *p_cfg |= DMA_CHAN_CFG_SRC_DRQ_H6(src_drq) | 335 DMA_CHAN_CFG_DST_DRQ_H6(dst_drq); 336 } 337 338 static void sun6i_set_mode_a31(u32 *p_cfg, s8 src_mode, s8 dst_mode) 339 { 340 *p_cfg |= DMA_CHAN_CFG_SRC_MODE_A31(src_mode) | 341 DMA_CHAN_CFG_DST_MODE_A31(dst_mode); 342 } 343 344 static void sun6i_set_mode_h6(u32 *p_cfg, s8 src_mode, s8 dst_mode) 345 { 346 *p_cfg |= DMA_CHAN_CFG_SRC_MODE_H6(src_mode) | 347 DMA_CHAN_CFG_DST_MODE_H6(dst_mode); 348 } 349 350 static size_t sun6i_get_chan_size(struct sun6i_pchan *pchan) 351 { 352 struct sun6i_desc *txd = pchan->desc; 353 struct sun6i_dma_lli *lli; 354 size_t bytes; 355 dma_addr_t pos; 356 357 do { 358 pos = readl(pchan->base + DMA_CHAN_LLI_ADDR); 359 bytes = readl(pchan->base + DMA_CHAN_CUR_CNT); 360 } while (pos != readl(pchan->base + DMA_CHAN_LLI_ADDR)); 361 362 if (pos == LLI_LAST_ITEM) 363 return bytes; 364 365 for (lli = txd->v_lli; lli; lli = lli->v_lli_next) { 366 if (lli->p_lli_next == pos) { 367 for (lli = lli->v_lli_next; lli; lli = lli->v_lli_next) 368 bytes += lli->len; 369 break; 370 } 371 } 372 373 return bytes; 374 } 375 376 static void *sun6i_dma_lli_add(struct sun6i_dma_lli *prev, 377 struct sun6i_dma_lli *next, 378 dma_addr_t next_phy, 379 struct sun6i_desc *txd) 380 { 381 if ((!prev && !txd) || !next) 382 return NULL; 383 384 if (!prev) { 385 txd->p_lli = next_phy; 386 txd->v_lli = next; 387 } else { 388 prev->p_lli_next = next_phy; 389 prev->v_lli_next = next; 390 } 391 392 next->p_lli_next = LLI_LAST_ITEM; 393 next->v_lli_next = NULL; 394 395 return next; 396 } 397 398 static inline void sun6i_dma_dump_lli(struct sun6i_vchan *vchan, 399 struct sun6i_dma_lli *v_lli, 400 dma_addr_t p_lli) 401 { 402 dev_dbg(chan2dev(&vchan->vc.chan), 403 "\n\tdesc:\tp - %pad v - 0x%p\n" 404 "\t\tc - 0x%08x s - 0x%08x d - 0x%08x\n" 405 "\t\tl - 0x%08x p - 0x%08x n - 0x%08x\n", 406 &p_lli, v_lli, 407 v_lli->cfg, v_lli->src, v_lli->dst, 408 v_lli->len, v_lli->para, v_lli->p_lli_next); 409 } 410 411 static void sun6i_dma_free_desc(struct virt_dma_desc *vd) 412 { 413 struct sun6i_desc *txd = to_sun6i_desc(&vd->tx); 414 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vd->tx.chan->device); 415 struct sun6i_dma_lli *v_lli, *v_next; 416 dma_addr_t p_lli, p_next; 417 418 if (unlikely(!txd)) 419 return; 420 421 p_lli = txd->p_lli; 422 v_lli = txd->v_lli; 423 424 while (v_lli) { 425 v_next = v_lli->v_lli_next; 426 p_next = v_lli->p_lli_next; 427 428 dma_pool_free(sdev->pool, v_lli, p_lli); 429 430 v_lli = v_next; 431 p_lli = p_next; 432 } 433 434 kfree(txd); 435 } 436 437 static int sun6i_dma_start_desc(struct sun6i_vchan *vchan) 438 { 439 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(vchan->vc.chan.device); 440 struct virt_dma_desc *desc = vchan_next_desc(&vchan->vc); 441 struct sun6i_pchan *pchan = vchan->phy; 442 u32 irq_val, irq_reg, irq_offset; 443 444 if (!pchan) 445 return -EAGAIN; 446 447 if (!desc) { 448 pchan->desc = NULL; 449 pchan->done = NULL; 450 return -EAGAIN; 451 } 452 453 list_del(&desc->node); 454 455 pchan->desc = to_sun6i_desc(&desc->tx); 456 pchan->done = NULL; 457 458 sun6i_dma_dump_lli(vchan, pchan->desc->v_lli, pchan->desc->p_lli); 459 460 irq_reg = pchan->idx / DMA_IRQ_CHAN_NR; 461 irq_offset = pchan->idx % DMA_IRQ_CHAN_NR; 462 463 vchan->irq_type = vchan->cyclic ? DMA_IRQ_PKG : DMA_IRQ_QUEUE; 464 465 irq_val = readl(sdev->base + DMA_IRQ_EN(irq_reg)); 466 irq_val &= ~((DMA_IRQ_HALF | DMA_IRQ_PKG | DMA_IRQ_QUEUE) << 467 (irq_offset * DMA_IRQ_CHAN_WIDTH)); 468 irq_val |= vchan->irq_type << (irq_offset * DMA_IRQ_CHAN_WIDTH); 469 writel(irq_val, sdev->base + DMA_IRQ_EN(irq_reg)); 470 471 writel(pchan->desc->p_lli, pchan->base + DMA_CHAN_LLI_ADDR); 472 writel(DMA_CHAN_ENABLE_START, pchan->base + DMA_CHAN_ENABLE); 473 474 sun6i_dma_dump_com_regs(sdev); 475 sun6i_dma_dump_chan_regs(sdev, pchan); 476 477 return 0; 478 } 479 480 static void sun6i_dma_tasklet(struct tasklet_struct *t) 481 { 482 struct sun6i_dma_dev *sdev = from_tasklet(sdev, t, task); 483 struct sun6i_vchan *vchan; 484 struct sun6i_pchan *pchan; 485 unsigned int pchan_alloc = 0; 486 unsigned int pchan_idx; 487 488 list_for_each_entry(vchan, &sdev->slave.channels, vc.chan.device_node) { 489 spin_lock_irq(&vchan->vc.lock); 490 491 pchan = vchan->phy; 492 493 if (pchan && pchan->done) { 494 if (sun6i_dma_start_desc(vchan)) { 495 /* 496 * No current txd associated with this channel 497 */ 498 dev_dbg(sdev->slave.dev, "pchan %u: free\n", 499 pchan->idx); 500 501 /* Mark this channel free */ 502 vchan->phy = NULL; 503 pchan->vchan = NULL; 504 } 505 } 506 spin_unlock_irq(&vchan->vc.lock); 507 } 508 509 spin_lock_irq(&sdev->lock); 510 for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) { 511 pchan = &sdev->pchans[pchan_idx]; 512 513 if (pchan->vchan || list_empty(&sdev->pending)) 514 continue; 515 516 vchan = list_first_entry(&sdev->pending, 517 struct sun6i_vchan, node); 518 519 /* Remove from pending channels */ 520 list_del_init(&vchan->node); 521 pchan_alloc |= BIT(pchan_idx); 522 523 /* Mark this channel allocated */ 524 pchan->vchan = vchan; 525 vchan->phy = pchan; 526 dev_dbg(sdev->slave.dev, "pchan %u: alloc vchan %p\n", 527 pchan->idx, &vchan->vc); 528 } 529 spin_unlock_irq(&sdev->lock); 530 531 for (pchan_idx = 0; pchan_idx < sdev->num_pchans; pchan_idx++) { 532 if (!(pchan_alloc & BIT(pchan_idx))) 533 continue; 534 535 pchan = sdev->pchans + pchan_idx; 536 vchan = pchan->vchan; 537 if (vchan) { 538 spin_lock_irq(&vchan->vc.lock); 539 sun6i_dma_start_desc(vchan); 540 spin_unlock_irq(&vchan->vc.lock); 541 } 542 } 543 } 544 545 static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id) 546 { 547 struct sun6i_dma_dev *sdev = dev_id; 548 struct sun6i_vchan *vchan; 549 struct sun6i_pchan *pchan; 550 int i, j, ret = IRQ_NONE; 551 u32 status; 552 553 for (i = 0; i < sdev->num_pchans / DMA_IRQ_CHAN_NR; i++) { 554 status = readl(sdev->base + DMA_IRQ_STAT(i)); 555 if (!status) 556 continue; 557 558 dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n", 559 str_high_low(i), status); 560 561 writel(status, sdev->base + DMA_IRQ_STAT(i)); 562 563 for (j = 0; (j < DMA_IRQ_CHAN_NR) && status; j++) { 564 pchan = sdev->pchans + j; 565 vchan = pchan->vchan; 566 if (vchan && (status & vchan->irq_type)) { 567 if (vchan->cyclic) { 568 vchan_cyclic_callback(&pchan->desc->vd); 569 } else { 570 spin_lock(&vchan->vc.lock); 571 vchan_cookie_complete(&pchan->desc->vd); 572 pchan->done = pchan->desc; 573 spin_unlock(&vchan->vc.lock); 574 } 575 } 576 577 status = status >> DMA_IRQ_CHAN_WIDTH; 578 } 579 580 if (!atomic_read(&sdev->tasklet_shutdown)) 581 tasklet_schedule(&sdev->task); 582 ret = IRQ_HANDLED; 583 } 584 585 return ret; 586 } 587 588 static u32 find_burst_size(const u32 burst_lengths, u32 maxburst) 589 { 590 if (!maxburst) 591 return 1; 592 593 if (BIT(maxburst) & burst_lengths) 594 return maxburst; 595 596 /* Hardware only does power-of-two bursts. */ 597 for (u32 burst = rounddown_pow_of_two(maxburst); burst > 0; burst /= 2) 598 if (BIT(burst) & burst_lengths) 599 return burst; 600 601 return 1; 602 } 603 604 static int set_config(struct sun6i_dma_dev *sdev, 605 struct dma_slave_config *sconfig, 606 enum dma_transfer_direction direction, 607 u32 *p_cfg) 608 { 609 enum dma_slave_buswidth src_addr_width, dst_addr_width; 610 u32 src_maxburst, dst_maxburst; 611 s8 src_width, dst_width, src_burst, dst_burst; 612 613 src_addr_width = sconfig->src_addr_width; 614 dst_addr_width = sconfig->dst_addr_width; 615 src_maxburst = sconfig->src_maxburst; 616 dst_maxburst = sconfig->dst_maxburst; 617 618 switch (direction) { 619 case DMA_MEM_TO_DEV: 620 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 621 src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 622 src_maxburst = src_maxburst ? src_maxburst : 8; 623 break; 624 case DMA_DEV_TO_MEM: 625 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) 626 dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 627 dst_maxburst = dst_maxburst ? dst_maxburst : 8; 628 break; 629 default: 630 return -EINVAL; 631 } 632 633 if (!(BIT(src_addr_width) & sdev->slave.src_addr_widths)) 634 return -EINVAL; 635 if (!(BIT(dst_addr_width) & sdev->slave.dst_addr_widths)) 636 return -EINVAL; 637 638 src_width = convert_buswidth(src_addr_width); 639 dst_width = convert_buswidth(dst_addr_width); 640 src_burst = find_burst_size(sdev->cfg->src_burst_lengths, src_maxburst); 641 dst_burst = find_burst_size(sdev->cfg->dst_burst_lengths, dst_maxburst); 642 dst_burst = convert_burst(dst_burst); 643 src_burst = convert_burst(src_burst); 644 645 *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) | 646 DMA_CHAN_CFG_DST_WIDTH(dst_width); 647 648 sdev->cfg->set_burst_length(p_cfg, src_burst, dst_burst); 649 650 return 0; 651 } 652 653 static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev, 654 struct sun6i_dma_lli *v_lli, 655 dma_addr_t src, dma_addr_t dst) 656 { 657 v_lli->src = lower_32_bits(src); 658 v_lli->dst = lower_32_bits(dst); 659 660 if (sdev->cfg->has_high_addr) 661 v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) | 662 DST_HIGH_ADDR(upper_32_bits(dst)); 663 } 664 665 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy( 666 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 667 size_t len, unsigned long flags) 668 { 669 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 670 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 671 struct sun6i_dma_lli *v_lli; 672 struct sun6i_desc *txd; 673 dma_addr_t p_lli; 674 s8 burst, width; 675 676 dev_dbg(chan2dev(chan), 677 "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", 678 __func__, vchan->vc.chan.chan_id, &dest, &src, len, flags); 679 680 if (!len) 681 return NULL; 682 683 txd = kzalloc_obj(*txd, GFP_NOWAIT); 684 if (!txd) 685 return NULL; 686 687 v_lli = dma_pool_alloc(sdev->pool, GFP_DMA32 | GFP_NOWAIT, &p_lli); 688 if (!v_lli) { 689 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n"); 690 goto err_txd_free; 691 } 692 693 v_lli->len = len; 694 v_lli->para = NORMAL_WAIT; 695 sun6i_dma_set_addr(sdev, v_lli, src, dest); 696 697 burst = convert_burst(8); 698 width = convert_buswidth(DMA_SLAVE_BUSWIDTH_4_BYTES); 699 v_lli->cfg = DMA_CHAN_CFG_SRC_WIDTH(width) | 700 DMA_CHAN_CFG_DST_WIDTH(width); 701 702 sdev->cfg->set_burst_length(&v_lli->cfg, burst, burst); 703 sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, DRQ_SDRAM); 704 sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, LINEAR_MODE); 705 706 sun6i_dma_lli_add(NULL, v_lli, p_lli, txd); 707 708 sun6i_dma_dump_lli(vchan, v_lli, p_lli); 709 710 return vchan_tx_prep(&vchan->vc, &txd->vd, flags); 711 712 err_txd_free: 713 kfree(txd); 714 return NULL; 715 } 716 717 static struct dma_async_tx_descriptor *sun6i_dma_prep_slave_sg( 718 struct dma_chan *chan, struct scatterlist *sgl, 719 unsigned int sg_len, enum dma_transfer_direction dir, 720 unsigned long flags, void *context) 721 { 722 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 723 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 724 struct dma_slave_config *sconfig = &vchan->cfg; 725 struct sun6i_dma_lli *v_lli, *prev = NULL; 726 struct sun6i_desc *txd; 727 struct scatterlist *sg; 728 dma_addr_t p_lli; 729 u32 lli_cfg; 730 int i, ret; 731 732 if (!sgl) 733 return NULL; 734 735 ret = set_config(sdev, sconfig, dir, &lli_cfg); 736 if (ret) { 737 dev_err(chan2dev(chan), "Invalid DMA configuration\n"); 738 return NULL; 739 } 740 741 txd = kzalloc_obj(*txd, GFP_NOWAIT); 742 if (!txd) 743 return NULL; 744 745 for_each_sg(sgl, sg, sg_len, i) { 746 v_lli = dma_pool_alloc(sdev->pool, GFP_DMA32 | GFP_NOWAIT, &p_lli); 747 if (!v_lli) 748 goto err_lli_free; 749 750 v_lli->len = sg_dma_len(sg); 751 v_lli->para = NORMAL_WAIT; 752 753 if (dir == DMA_MEM_TO_DEV) { 754 sun6i_dma_set_addr(sdev, v_lli, 755 sg_dma_address(sg), 756 sconfig->dst_addr); 757 v_lli->cfg = lli_cfg; 758 sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); 759 sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE); 760 761 dev_dbg(chan2dev(chan), 762 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", 763 __func__, vchan->vc.chan.chan_id, 764 &sconfig->dst_addr, &sg_dma_address(sg), 765 sg_dma_len(sg), flags); 766 767 } else { 768 sun6i_dma_set_addr(sdev, v_lli, 769 sconfig->src_addr, 770 sg_dma_address(sg)); 771 v_lli->cfg = lli_cfg; 772 sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); 773 sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE); 774 775 dev_dbg(chan2dev(chan), 776 "%s; chan: %d, dest: %pad, src: %pad, len: %u. flags: 0x%08lx\n", 777 __func__, vchan->vc.chan.chan_id, 778 &sg_dma_address(sg), &sconfig->src_addr, 779 sg_dma_len(sg), flags); 780 } 781 782 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); 783 } 784 785 dev_dbg(chan2dev(chan), "First: %pad\n", &txd->p_lli); 786 for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli; 787 p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next) 788 sun6i_dma_dump_lli(vchan, v_lli, p_lli); 789 790 return vchan_tx_prep(&vchan->vc, &txd->vd, flags); 791 792 err_lli_free: 793 for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli; 794 p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next) 795 dma_pool_free(sdev->pool, v_lli, p_lli); 796 kfree(txd); 797 return NULL; 798 } 799 800 static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_cyclic( 801 struct dma_chan *chan, 802 dma_addr_t buf_addr, 803 size_t buf_len, 804 size_t period_len, 805 enum dma_transfer_direction dir, 806 unsigned long flags) 807 { 808 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 809 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 810 struct dma_slave_config *sconfig = &vchan->cfg; 811 struct sun6i_dma_lli *v_lli, *prev = NULL; 812 struct sun6i_desc *txd; 813 dma_addr_t p_lli; 814 u32 lli_cfg; 815 unsigned int i, periods = buf_len / period_len; 816 int ret; 817 818 ret = set_config(sdev, sconfig, dir, &lli_cfg); 819 if (ret) { 820 dev_err(chan2dev(chan), "Invalid DMA configuration\n"); 821 return NULL; 822 } 823 824 txd = kzalloc_obj(*txd, GFP_NOWAIT); 825 if (!txd) 826 return NULL; 827 828 for (i = 0; i < periods; i++) { 829 v_lli = dma_pool_alloc(sdev->pool, GFP_DMA32 | GFP_NOWAIT, &p_lli); 830 if (!v_lli) { 831 dev_err(sdev->slave.dev, "Failed to alloc lli memory\n"); 832 goto err_lli_free; 833 } 834 835 v_lli->len = period_len; 836 v_lli->para = NORMAL_WAIT; 837 838 if (dir == DMA_MEM_TO_DEV) { 839 sun6i_dma_set_addr(sdev, v_lli, 840 buf_addr + period_len * i, 841 sconfig->dst_addr); 842 v_lli->cfg = lli_cfg; 843 sdev->cfg->set_drq(&v_lli->cfg, DRQ_SDRAM, vchan->port); 844 sdev->cfg->set_mode(&v_lli->cfg, LINEAR_MODE, IO_MODE); 845 dev_dbg(chan2dev(chan), 846 "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", 847 __func__, vchan->vc.chan.chan_id, 848 &sconfig->dst_addr, &buf_addr, 849 buf_len, flags); 850 } else { 851 sun6i_dma_set_addr(sdev, v_lli, 852 sconfig->src_addr, 853 buf_addr + period_len * i); 854 v_lli->cfg = lli_cfg; 855 sdev->cfg->set_drq(&v_lli->cfg, vchan->port, DRQ_SDRAM); 856 sdev->cfg->set_mode(&v_lli->cfg, IO_MODE, LINEAR_MODE); 857 dev_dbg(chan2dev(chan), 858 "%s; chan: %d, dest: %pad, src: %pad, len: %zu. flags: 0x%08lx\n", 859 __func__, vchan->vc.chan.chan_id, 860 &buf_addr, &sconfig->src_addr, 861 buf_len, flags); 862 } 863 864 prev = sun6i_dma_lli_add(prev, v_lli, p_lli, txd); 865 } 866 867 prev->p_lli_next = txd->p_lli; /* cyclic list */ 868 869 vchan->cyclic = true; 870 871 return vchan_tx_prep(&vchan->vc, &txd->vd, flags); 872 873 err_lli_free: 874 for (p_lli = txd->p_lli, v_lli = txd->v_lli; v_lli; 875 p_lli = v_lli->p_lli_next, v_lli = v_lli->v_lli_next) 876 dma_pool_free(sdev->pool, v_lli, p_lli); 877 kfree(txd); 878 return NULL; 879 } 880 881 static int sun6i_dma_config(struct dma_chan *chan, 882 struct dma_slave_config *config) 883 { 884 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 885 886 memcpy(&vchan->cfg, config, sizeof(*config)); 887 888 return 0; 889 } 890 891 static int sun6i_dma_pause(struct dma_chan *chan) 892 { 893 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 894 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 895 struct sun6i_pchan *pchan = vchan->phy; 896 897 dev_dbg(chan2dev(chan), "vchan %p: pause\n", &vchan->vc); 898 899 if (pchan) { 900 writel(DMA_CHAN_PAUSE_PAUSE, 901 pchan->base + DMA_CHAN_PAUSE); 902 } else { 903 spin_lock(&sdev->lock); 904 list_del_init(&vchan->node); 905 spin_unlock(&sdev->lock); 906 } 907 908 return 0; 909 } 910 911 static int sun6i_dma_resume(struct dma_chan *chan) 912 { 913 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 914 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 915 struct sun6i_pchan *pchan = vchan->phy; 916 unsigned long flags; 917 918 dev_dbg(chan2dev(chan), "vchan %p: resume\n", &vchan->vc); 919 920 spin_lock_irqsave(&vchan->vc.lock, flags); 921 922 if (pchan) { 923 writel(DMA_CHAN_PAUSE_RESUME, 924 pchan->base + DMA_CHAN_PAUSE); 925 } else if (!list_empty(&vchan->vc.desc_issued)) { 926 spin_lock(&sdev->lock); 927 list_add_tail(&vchan->node, &sdev->pending); 928 spin_unlock(&sdev->lock); 929 } 930 931 spin_unlock_irqrestore(&vchan->vc.lock, flags); 932 933 return 0; 934 } 935 936 static int sun6i_dma_terminate_all(struct dma_chan *chan) 937 { 938 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 939 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 940 struct sun6i_pchan *pchan = vchan->phy; 941 unsigned long flags; 942 LIST_HEAD(head); 943 944 spin_lock(&sdev->lock); 945 list_del_init(&vchan->node); 946 spin_unlock(&sdev->lock); 947 948 spin_lock_irqsave(&vchan->vc.lock, flags); 949 950 if (pchan && pchan->desc && pchan->desc != pchan->done) { 951 struct virt_dma_desc *vd = &pchan->desc->vd; 952 953 vchan_terminate_vdesc(vd); 954 } 955 956 vchan->cyclic = false; 957 vchan_get_all_descriptors(&vchan->vc, &head); 958 959 if (pchan) { 960 writel(DMA_CHAN_ENABLE_STOP, pchan->base + DMA_CHAN_ENABLE); 961 writel(DMA_CHAN_PAUSE_RESUME, pchan->base + DMA_CHAN_PAUSE); 962 963 vchan->phy = NULL; 964 pchan->vchan = NULL; 965 pchan->desc = NULL; 966 pchan->done = NULL; 967 } 968 969 spin_unlock_irqrestore(&vchan->vc.lock, flags); 970 971 vchan_dma_desc_free_list(&vchan->vc, &head); 972 973 return 0; 974 } 975 976 static enum dma_status sun6i_dma_tx_status(struct dma_chan *chan, 977 dma_cookie_t cookie, 978 struct dma_tx_state *state) 979 { 980 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 981 struct sun6i_pchan *pchan = vchan->phy; 982 struct sun6i_dma_lli *lli; 983 struct virt_dma_desc *vd; 984 enum dma_status ret; 985 unsigned long flags; 986 size_t bytes = 0; 987 988 ret = dma_cookie_status(chan, cookie, state); 989 if (ret == DMA_COMPLETE || !state) 990 return ret; 991 992 spin_lock_irqsave(&vchan->vc.lock, flags); 993 994 vd = vchan_find_desc(&vchan->vc, cookie); 995 996 if (vd) { 997 struct sun6i_desc *txd = to_sun6i_desc(&vd->tx); 998 for (lli = txd->v_lli; lli != NULL; lli = lli->v_lli_next) 999 bytes += lli->len; 1000 } else if (!pchan || !pchan->desc) { 1001 bytes = 0; 1002 } else { 1003 bytes = sun6i_get_chan_size(pchan); 1004 } 1005 1006 spin_unlock_irqrestore(&vchan->vc.lock, flags); 1007 1008 dma_set_residue(state, bytes); 1009 1010 return ret; 1011 } 1012 1013 static void sun6i_dma_issue_pending(struct dma_chan *chan) 1014 { 1015 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 1016 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 1017 unsigned long flags; 1018 1019 spin_lock_irqsave(&vchan->vc.lock, flags); 1020 1021 if (vchan_issue_pending(&vchan->vc)) { 1022 spin_lock(&sdev->lock); 1023 1024 if (!vchan->phy && list_empty(&vchan->node)) { 1025 list_add_tail(&vchan->node, &sdev->pending); 1026 tasklet_schedule(&sdev->task); 1027 dev_dbg(chan2dev(chan), "vchan %p: issued\n", 1028 &vchan->vc); 1029 } 1030 1031 spin_unlock(&sdev->lock); 1032 } else { 1033 dev_dbg(chan2dev(chan), "vchan %p: nothing to issue\n", 1034 &vchan->vc); 1035 } 1036 1037 spin_unlock_irqrestore(&vchan->vc.lock, flags); 1038 } 1039 1040 static void sun6i_dma_free_chan_resources(struct dma_chan *chan) 1041 { 1042 struct sun6i_dma_dev *sdev = to_sun6i_dma_dev(chan->device); 1043 struct sun6i_vchan *vchan = to_sun6i_vchan(chan); 1044 unsigned long flags; 1045 1046 spin_lock_irqsave(&sdev->lock, flags); 1047 list_del_init(&vchan->node); 1048 spin_unlock_irqrestore(&sdev->lock, flags); 1049 1050 vchan_free_chan_resources(&vchan->vc); 1051 } 1052 1053 static struct dma_chan *sun6i_dma_of_xlate(struct of_phandle_args *dma_spec, 1054 struct of_dma *ofdma) 1055 { 1056 struct sun6i_dma_dev *sdev = ofdma->of_dma_data; 1057 struct sun6i_vchan *vchan; 1058 struct dma_chan *chan; 1059 u8 port = dma_spec->args[0]; 1060 1061 if (port > sdev->max_request) 1062 return NULL; 1063 1064 chan = dma_get_any_slave_channel(&sdev->slave); 1065 if (!chan) 1066 return NULL; 1067 1068 vchan = to_sun6i_vchan(chan); 1069 vchan->port = port; 1070 1071 return chan; 1072 } 1073 1074 static inline void sun6i_kill_tasklet(struct sun6i_dma_dev *sdev) 1075 { 1076 /* Disable all interrupts from DMA */ 1077 writel(0, sdev->base + DMA_IRQ_EN(0)); 1078 writel(0, sdev->base + DMA_IRQ_EN(1)); 1079 1080 /* Prevent spurious interrupts from scheduling the tasklet */ 1081 atomic_inc(&sdev->tasklet_shutdown); 1082 1083 /* Make sure we won't have any further interrupts */ 1084 devm_free_irq(sdev->slave.dev, sdev->irq, sdev); 1085 1086 /* Actually prevent the tasklet from being scheduled */ 1087 tasklet_kill(&sdev->task); 1088 } 1089 1090 static inline void sun6i_dma_free(struct sun6i_dma_dev *sdev) 1091 { 1092 int i; 1093 1094 for (i = 0; i < sdev->num_vchans; i++) { 1095 struct sun6i_vchan *vchan = &sdev->vchans[i]; 1096 1097 list_del(&vchan->vc.chan.device_node); 1098 tasklet_kill(&vchan->vc.task); 1099 } 1100 } 1101 1102 /* 1103 * For A31: 1104 * 1105 * There's 16 physical channels that can work in parallel. 1106 * 1107 * However we have 30 different endpoints for our requests. 1108 * 1109 * Since the channels are able to handle only an unidirectional 1110 * transfer, we need to allocate more virtual channels so that 1111 * everyone can grab one channel. 1112 * 1113 * Some devices can't work in both direction (mostly because it 1114 * wouldn't make sense), so we have a bit fewer virtual channels than 1115 * 2 channels per endpoints. 1116 */ 1117 1118 static struct sun6i_dma_config sun6i_a31_dma_cfg = { 1119 .nr_max_channels = 16, 1120 .nr_max_requests = 30, 1121 .nr_max_vchans = 53, 1122 .set_burst_length = sun6i_set_burst_length_a31, 1123 .set_drq = sun6i_set_drq_a31, 1124 .set_mode = sun6i_set_mode_a31, 1125 .src_burst_lengths = BIT(1) | BIT(8), 1126 .dst_burst_lengths = BIT(1) | BIT(8), 1127 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1128 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1129 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), 1130 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1131 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1132 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), 1133 }; 1134 1135 /* 1136 * The A23 only has 8 physical channels, a maximum DRQ port id of 24, 1137 * and a total of 37 usable source and destination endpoints. 1138 */ 1139 1140 static struct sun6i_dma_config sun8i_a23_dma_cfg = { 1141 .nr_max_channels = 8, 1142 .nr_max_requests = 24, 1143 .nr_max_vchans = 37, 1144 .clock_autogate_enable = sun6i_enable_clock_autogate_a23, 1145 .set_burst_length = sun6i_set_burst_length_a31, 1146 .set_drq = sun6i_set_drq_a31, 1147 .set_mode = sun6i_set_mode_a31, 1148 .src_burst_lengths = BIT(1) | BIT(8), 1149 .dst_burst_lengths = BIT(1) | BIT(8), 1150 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1151 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1152 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), 1153 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1154 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1155 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), 1156 }; 1157 1158 static struct sun6i_dma_config sun8i_a83t_dma_cfg = { 1159 .nr_max_channels = 8, 1160 .nr_max_requests = 28, 1161 .nr_max_vchans = 39, 1162 .clock_autogate_enable = sun6i_enable_clock_autogate_a23, 1163 .set_burst_length = sun6i_set_burst_length_a31, 1164 .set_drq = sun6i_set_drq_a31, 1165 .set_mode = sun6i_set_mode_a31, 1166 .src_burst_lengths = BIT(1) | BIT(8), 1167 .dst_burst_lengths = BIT(1) | BIT(8), 1168 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1169 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1170 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), 1171 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1172 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1173 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), 1174 }; 1175 1176 /* 1177 * The H3 has 12 physical channels, a maximum DRQ port id of 27, 1178 * and a total of 34 usable source and destination endpoints. 1179 * It also supports additional burst lengths and bus widths, 1180 * and the burst length fields have different offsets. 1181 */ 1182 1183 static struct sun6i_dma_config sun8i_h3_dma_cfg = { 1184 .nr_max_channels = 12, 1185 .nr_max_requests = 27, 1186 .nr_max_vchans = 34, 1187 .clock_autogate_enable = sun6i_enable_clock_autogate_h3, 1188 .set_burst_length = sun6i_set_burst_length_h3, 1189 .set_drq = sun6i_set_drq_a31, 1190 .set_mode = sun6i_set_mode_a31, 1191 .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), 1192 .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), 1193 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1194 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1195 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1196 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), 1197 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1198 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1199 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1200 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), 1201 }; 1202 1203 /* 1204 * The A64 binding uses the number of dma channels from the 1205 * device tree node. 1206 */ 1207 static struct sun6i_dma_config sun50i_a64_dma_cfg = { 1208 .clock_autogate_enable = sun6i_enable_clock_autogate_h3, 1209 .set_burst_length = sun6i_set_burst_length_h3, 1210 .set_drq = sun6i_set_drq_a31, 1211 .set_mode = sun6i_set_mode_a31, 1212 .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), 1213 .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), 1214 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1215 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1216 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1217 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), 1218 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1219 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1220 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1221 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), 1222 }; 1223 1224 /* 1225 * The A100 binding uses the number of dma channels from the 1226 * device tree node. 1227 */ 1228 static struct sun6i_dma_config sun50i_a100_dma_cfg = { 1229 .clock_autogate_enable = sun6i_enable_clock_autogate_h3, 1230 .set_burst_length = sun6i_set_burst_length_h3, 1231 .set_drq = sun6i_set_drq_h6, 1232 .set_mode = sun6i_set_mode_h6, 1233 .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), 1234 .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), 1235 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1236 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1237 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1238 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), 1239 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1240 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1241 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1242 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), 1243 .has_high_addr = true, 1244 .has_mbus_clk = true, 1245 }; 1246 1247 /* 1248 * The H6 binding uses the number of dma channels from the 1249 * device tree node. 1250 */ 1251 static struct sun6i_dma_config sun50i_h6_dma_cfg = { 1252 .clock_autogate_enable = sun6i_enable_clock_autogate_h3, 1253 .set_burst_length = sun6i_set_burst_length_h3, 1254 .set_drq = sun6i_set_drq_h6, 1255 .set_mode = sun6i_set_mode_h6, 1256 .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), 1257 .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16), 1258 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1259 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1260 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1261 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), 1262 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1263 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1264 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | 1265 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES), 1266 .has_mbus_clk = true, 1267 }; 1268 1269 /* 1270 * The V3s have only 8 physical channels, a maximum DRQ port id of 23, 1271 * and a total of 24 usable source and destination endpoints. 1272 */ 1273 1274 static struct sun6i_dma_config sun8i_v3s_dma_cfg = { 1275 .nr_max_channels = 8, 1276 .nr_max_requests = 23, 1277 .nr_max_vchans = 24, 1278 .clock_autogate_enable = sun6i_enable_clock_autogate_a23, 1279 .set_burst_length = sun6i_set_burst_length_a31, 1280 .set_drq = sun6i_set_drq_a31, 1281 .set_mode = sun6i_set_mode_a31, 1282 .src_burst_lengths = BIT(1) | BIT(8), 1283 .dst_burst_lengths = BIT(1) | BIT(8), 1284 .src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1285 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1286 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), 1287 .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | 1288 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | 1289 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES), 1290 }; 1291 1292 static const struct of_device_id sun6i_dma_match[] = { 1293 { .compatible = "allwinner,sun6i-a31-dma", .data = &sun6i_a31_dma_cfg }, 1294 { .compatible = "allwinner,sun8i-a23-dma", .data = &sun8i_a23_dma_cfg }, 1295 { .compatible = "allwinner,sun8i-a83t-dma", .data = &sun8i_a83t_dma_cfg }, 1296 { .compatible = "allwinner,sun8i-h3-dma", .data = &sun8i_h3_dma_cfg }, 1297 { .compatible = "allwinner,sun8i-v3s-dma", .data = &sun8i_v3s_dma_cfg }, 1298 { .compatible = "allwinner,sun20i-d1-dma", .data = &sun50i_a100_dma_cfg }, 1299 { .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg }, 1300 { .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg }, 1301 { .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg }, 1302 { /* sentinel */ } 1303 }; 1304 MODULE_DEVICE_TABLE(of, sun6i_dma_match); 1305 1306 static int sun6i_dma_probe(struct platform_device *pdev) 1307 { 1308 struct device_node *np = pdev->dev.of_node; 1309 struct sun6i_dma_dev *sdc; 1310 int ret, i; 1311 1312 sdc = devm_kzalloc(&pdev->dev, sizeof(*sdc), GFP_KERNEL); 1313 if (!sdc) 1314 return -ENOMEM; 1315 1316 sdc->cfg = of_device_get_match_data(&pdev->dev); 1317 if (!sdc->cfg) 1318 return -ENODEV; 1319 1320 sdc->base = devm_platform_ioremap_resource(pdev, 0); 1321 if (IS_ERR(sdc->base)) 1322 return PTR_ERR(sdc->base); 1323 1324 sdc->irq = platform_get_irq(pdev, 0); 1325 if (sdc->irq < 0) 1326 return sdc->irq; 1327 1328 sdc->clk = devm_clk_get(&pdev->dev, NULL); 1329 if (IS_ERR(sdc->clk)) { 1330 dev_err(&pdev->dev, "No clock specified\n"); 1331 return PTR_ERR(sdc->clk); 1332 } 1333 1334 if (sdc->cfg->has_mbus_clk) { 1335 sdc->clk_mbus = devm_clk_get(&pdev->dev, "mbus"); 1336 if (IS_ERR(sdc->clk_mbus)) { 1337 dev_err(&pdev->dev, "No mbus clock specified\n"); 1338 return PTR_ERR(sdc->clk_mbus); 1339 } 1340 } 1341 1342 sdc->rstc = devm_reset_control_get(&pdev->dev, NULL); 1343 if (IS_ERR(sdc->rstc)) { 1344 dev_err(&pdev->dev, "No reset controller specified\n"); 1345 return PTR_ERR(sdc->rstc); 1346 } 1347 1348 sdc->pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev, 1349 sizeof(struct sun6i_dma_lli), 4, 0); 1350 if (!sdc->pool) { 1351 dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); 1352 return -ENOMEM; 1353 } 1354 1355 platform_set_drvdata(pdev, sdc); 1356 INIT_LIST_HEAD(&sdc->pending); 1357 spin_lock_init(&sdc->lock); 1358 1359 dma_set_max_seg_size(&pdev->dev, SZ_32M - 1); 1360 1361 dma_cap_set(DMA_PRIVATE, sdc->slave.cap_mask); 1362 dma_cap_set(DMA_MEMCPY, sdc->slave.cap_mask); 1363 dma_cap_set(DMA_SLAVE, sdc->slave.cap_mask); 1364 dma_cap_set(DMA_CYCLIC, sdc->slave.cap_mask); 1365 1366 INIT_LIST_HEAD(&sdc->slave.channels); 1367 sdc->slave.device_free_chan_resources = sun6i_dma_free_chan_resources; 1368 sdc->slave.device_tx_status = sun6i_dma_tx_status; 1369 sdc->slave.device_issue_pending = sun6i_dma_issue_pending; 1370 sdc->slave.device_prep_slave_sg = sun6i_dma_prep_slave_sg; 1371 sdc->slave.device_prep_dma_memcpy = sun6i_dma_prep_dma_memcpy; 1372 sdc->slave.device_prep_dma_cyclic = sun6i_dma_prep_dma_cyclic; 1373 sdc->slave.copy_align = DMAENGINE_ALIGN_4_BYTES; 1374 sdc->slave.device_config = sun6i_dma_config; 1375 sdc->slave.device_pause = sun6i_dma_pause; 1376 sdc->slave.device_resume = sun6i_dma_resume; 1377 sdc->slave.device_terminate_all = sun6i_dma_terminate_all; 1378 sdc->slave.src_addr_widths = sdc->cfg->src_addr_widths; 1379 sdc->slave.dst_addr_widths = sdc->cfg->dst_addr_widths; 1380 sdc->slave.directions = BIT(DMA_DEV_TO_MEM) | 1381 BIT(DMA_MEM_TO_DEV); 1382 sdc->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1383 sdc->slave.dev = &pdev->dev; 1384 1385 sdc->num_pchans = sdc->cfg->nr_max_channels; 1386 sdc->num_vchans = sdc->cfg->nr_max_vchans; 1387 sdc->max_request = sdc->cfg->nr_max_requests; 1388 1389 ret = of_property_read_u32(np, "dma-channels", &sdc->num_pchans); 1390 if (ret && !sdc->num_pchans) { 1391 dev_err(&pdev->dev, "Can't get dma-channels.\n"); 1392 return ret; 1393 } 1394 1395 ret = of_property_read_u32(np, "dma-requests", &sdc->max_request); 1396 if (ret && !sdc->max_request) { 1397 dev_info(&pdev->dev, "Missing dma-requests, using %u.\n", 1398 DMA_CHAN_MAX_DRQ_A31); 1399 sdc->max_request = DMA_CHAN_MAX_DRQ_A31; 1400 } 1401 1402 /* 1403 * If the number of vchans is not specified, derive it from the 1404 * highest port number, at most one channel per port and direction. 1405 */ 1406 if (!sdc->num_vchans) 1407 sdc->num_vchans = 2 * (sdc->max_request + 1); 1408 1409 sdc->pchans = devm_kcalloc(&pdev->dev, sdc->num_pchans, 1410 sizeof(struct sun6i_pchan), GFP_KERNEL); 1411 if (!sdc->pchans) 1412 return -ENOMEM; 1413 1414 sdc->vchans = devm_kcalloc(&pdev->dev, sdc->num_vchans, 1415 sizeof(struct sun6i_vchan), GFP_KERNEL); 1416 if (!sdc->vchans) 1417 return -ENOMEM; 1418 1419 tasklet_setup(&sdc->task, sun6i_dma_tasklet); 1420 1421 for (i = 0; i < sdc->num_pchans; i++) { 1422 struct sun6i_pchan *pchan = &sdc->pchans[i]; 1423 1424 pchan->idx = i; 1425 pchan->base = sdc->base + 0x100 + i * 0x40; 1426 } 1427 1428 for (i = 0; i < sdc->num_vchans; i++) { 1429 struct sun6i_vchan *vchan = &sdc->vchans[i]; 1430 1431 INIT_LIST_HEAD(&vchan->node); 1432 vchan->vc.desc_free = sun6i_dma_free_desc; 1433 vchan_init(&vchan->vc, &sdc->slave); 1434 } 1435 1436 ret = reset_control_deassert(sdc->rstc); 1437 if (ret) { 1438 dev_err(&pdev->dev, "Couldn't deassert the device from reset\n"); 1439 goto err_chan_free; 1440 } 1441 1442 ret = clk_prepare_enable(sdc->clk); 1443 if (ret) { 1444 dev_err(&pdev->dev, "Couldn't enable the clock\n"); 1445 goto err_reset_assert; 1446 } 1447 1448 if (sdc->cfg->has_mbus_clk) { 1449 ret = clk_prepare_enable(sdc->clk_mbus); 1450 if (ret) { 1451 dev_err(&pdev->dev, "Couldn't enable mbus clock\n"); 1452 goto err_clk_disable; 1453 } 1454 } 1455 1456 ret = devm_request_irq(&pdev->dev, sdc->irq, sun6i_dma_interrupt, 0, 1457 dev_name(&pdev->dev), sdc); 1458 if (ret) { 1459 dev_err(&pdev->dev, "Cannot request IRQ\n"); 1460 goto err_mbus_clk_disable; 1461 } 1462 1463 ret = dma_async_device_register(&sdc->slave); 1464 if (ret) { 1465 dev_warn(&pdev->dev, "Failed to register DMA engine device\n"); 1466 goto err_irq_disable; 1467 } 1468 1469 ret = of_dma_controller_register(pdev->dev.of_node, sun6i_dma_of_xlate, 1470 sdc); 1471 if (ret) { 1472 dev_err(&pdev->dev, "of_dma_controller_register failed\n"); 1473 goto err_dma_unregister; 1474 } 1475 1476 if (sdc->cfg->clock_autogate_enable) 1477 sdc->cfg->clock_autogate_enable(sdc); 1478 1479 return 0; 1480 1481 err_dma_unregister: 1482 dma_async_device_unregister(&sdc->slave); 1483 err_irq_disable: 1484 sun6i_kill_tasklet(sdc); 1485 err_mbus_clk_disable: 1486 clk_disable_unprepare(sdc->clk_mbus); 1487 err_clk_disable: 1488 clk_disable_unprepare(sdc->clk); 1489 err_reset_assert: 1490 reset_control_assert(sdc->rstc); 1491 err_chan_free: 1492 sun6i_dma_free(sdc); 1493 return ret; 1494 } 1495 1496 static void sun6i_dma_remove(struct platform_device *pdev) 1497 { 1498 struct sun6i_dma_dev *sdc = platform_get_drvdata(pdev); 1499 1500 of_dma_controller_free(pdev->dev.of_node); 1501 dma_async_device_unregister(&sdc->slave); 1502 1503 sun6i_kill_tasklet(sdc); 1504 1505 clk_disable_unprepare(sdc->clk_mbus); 1506 clk_disable_unprepare(sdc->clk); 1507 reset_control_assert(sdc->rstc); 1508 1509 sun6i_dma_free(sdc); 1510 } 1511 1512 static struct platform_driver sun6i_dma_driver = { 1513 .probe = sun6i_dma_probe, 1514 .remove = sun6i_dma_remove, 1515 .driver = { 1516 .name = "sun6i-dma", 1517 .of_match_table = sun6i_dma_match, 1518 }, 1519 }; 1520 module_platform_driver(sun6i_dma_driver); 1521 1522 MODULE_DESCRIPTION("Allwinner A31 DMA Controller Driver"); 1523 MODULE_AUTHOR("Sugar <shuge@allwinnertech.com>"); 1524 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1525 MODULE_LICENSE("GPL"); 1526