1 /* 2 * Copyright (C) 2017 Spreadtrum Communications Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/dma/sprd-dma.h> 10 #include <linux/errno.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_dma.h> 18 #include <linux/of_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/slab.h> 21 22 #include "virt-dma.h" 23 24 #define SPRD_DMA_CHN_REG_OFFSET 0x1000 25 #define SPRD_DMA_CHN_REG_LENGTH 0x40 26 #define SPRD_DMA_MEMCPY_MIN_SIZE 64 27 28 /* DMA global registers definition */ 29 #define SPRD_DMA_GLB_PAUSE 0x0 30 #define SPRD_DMA_GLB_FRAG_WAIT 0x4 31 #define SPRD_DMA_GLB_REQ_PEND0_EN 0x8 32 #define SPRD_DMA_GLB_REQ_PEND1_EN 0xc 33 #define SPRD_DMA_GLB_INT_RAW_STS 0x10 34 #define SPRD_DMA_GLB_INT_MSK_STS 0x14 35 #define SPRD_DMA_GLB_REQ_STS 0x18 36 #define SPRD_DMA_GLB_CHN_EN_STS 0x1c 37 #define SPRD_DMA_GLB_DEBUG_STS 0x20 38 #define SPRD_DMA_GLB_ARB_SEL_STS 0x24 39 #define SPRD_DMA_GLB_2STAGE_GRP1 0x28 40 #define SPRD_DMA_GLB_2STAGE_GRP2 0x2c 41 #define SPRD_DMA_GLB_REQ_UID(uid) (0x4 * ((uid) - 1)) 42 #define SPRD_DMA_GLB_REQ_UID_OFFSET 0x2000 43 44 /* DMA channel registers definition */ 45 #define SPRD_DMA_CHN_PAUSE 0x0 46 #define SPRD_DMA_CHN_REQ 0x4 47 #define SPRD_DMA_CHN_CFG 0x8 48 #define SPRD_DMA_CHN_INTC 0xc 49 #define SPRD_DMA_CHN_SRC_ADDR 0x10 50 #define SPRD_DMA_CHN_DES_ADDR 0x14 51 #define SPRD_DMA_CHN_FRG_LEN 0x18 52 #define SPRD_DMA_CHN_BLK_LEN 0x1c 53 #define SPRD_DMA_CHN_TRSC_LEN 0x20 54 #define SPRD_DMA_CHN_TRSF_STEP 0x24 55 #define SPRD_DMA_CHN_WARP_PTR 0x28 56 #define SPRD_DMA_CHN_WARP_TO 0x2c 57 #define SPRD_DMA_CHN_LLIST_PTR 0x30 58 #define SPRD_DMA_CHN_FRAG_STEP 0x34 59 #define SPRD_DMA_CHN_SRC_BLK_STEP 0x38 60 #define SPRD_DMA_CHN_DES_BLK_STEP 0x3c 61 62 /* SPRD_DMA_GLB_2STAGE_GRP register definition */ 63 #define SPRD_DMA_GLB_2STAGE_EN BIT(24) 64 #define SPRD_DMA_GLB_CHN_INT_MASK GENMASK(23, 20) 65 #define SPRD_DMA_GLB_DEST_INT BIT(22) 66 #define SPRD_DMA_GLB_SRC_INT BIT(20) 67 #define SPRD_DMA_GLB_LIST_DONE_TRG BIT(19) 68 #define SPRD_DMA_GLB_TRANS_DONE_TRG BIT(18) 69 #define SPRD_DMA_GLB_BLOCK_DONE_TRG BIT(17) 70 #define SPRD_DMA_GLB_FRAG_DONE_TRG BIT(16) 71 #define SPRD_DMA_GLB_TRG_OFFSET 16 72 #define SPRD_DMA_GLB_DEST_CHN_MASK GENMASK(13, 8) 73 #define SPRD_DMA_GLB_DEST_CHN_OFFSET 8 74 #define SPRD_DMA_GLB_SRC_CHN_MASK GENMASK(5, 0) 75 76 /* SPRD_DMA_CHN_INTC register definition */ 77 #define SPRD_DMA_INT_MASK GENMASK(4, 0) 78 #define SPRD_DMA_INT_CLR_OFFSET 24 79 #define SPRD_DMA_FRAG_INT_EN BIT(0) 80 #define SPRD_DMA_BLK_INT_EN BIT(1) 81 #define SPRD_DMA_TRANS_INT_EN BIT(2) 82 #define SPRD_DMA_LIST_INT_EN BIT(3) 83 #define SPRD_DMA_CFG_ERR_INT_EN BIT(4) 84 85 /* SPRD_DMA_CHN_CFG register definition */ 86 #define SPRD_DMA_CHN_EN BIT(0) 87 #define SPRD_DMA_LINKLIST_EN BIT(4) 88 #define SPRD_DMA_WAIT_BDONE_OFFSET 24 89 #define SPRD_DMA_DONOT_WAIT_BDONE 1 90 91 /* SPRD_DMA_CHN_REQ register definition */ 92 #define SPRD_DMA_REQ_EN BIT(0) 93 94 /* SPRD_DMA_CHN_PAUSE register definition */ 95 #define SPRD_DMA_PAUSE_EN BIT(0) 96 #define SPRD_DMA_PAUSE_STS BIT(2) 97 #define SPRD_DMA_PAUSE_CNT 0x2000 98 99 /* DMA_CHN_WARP_* register definition */ 100 #define SPRD_DMA_HIGH_ADDR_MASK GENMASK(31, 28) 101 #define SPRD_DMA_LOW_ADDR_MASK GENMASK(31, 0) 102 #define SPRD_DMA_WRAP_ADDR_MASK GENMASK(27, 0) 103 #define SPRD_DMA_HIGH_ADDR_OFFSET 4 104 105 /* SPRD_DMA_CHN_INTC register definition */ 106 #define SPRD_DMA_FRAG_INT_STS BIT(16) 107 #define SPRD_DMA_BLK_INT_STS BIT(17) 108 #define SPRD_DMA_TRSC_INT_STS BIT(18) 109 #define SPRD_DMA_LIST_INT_STS BIT(19) 110 #define SPRD_DMA_CFGERR_INT_STS BIT(20) 111 #define SPRD_DMA_CHN_INT_STS \ 112 (SPRD_DMA_FRAG_INT_STS | SPRD_DMA_BLK_INT_STS | \ 113 SPRD_DMA_TRSC_INT_STS | SPRD_DMA_LIST_INT_STS | \ 114 SPRD_DMA_CFGERR_INT_STS) 115 116 /* SPRD_DMA_CHN_FRG_LEN register definition */ 117 #define SPRD_DMA_SRC_DATAWIDTH_OFFSET 30 118 #define SPRD_DMA_DES_DATAWIDTH_OFFSET 28 119 #define SPRD_DMA_SWT_MODE_OFFSET 26 120 #define SPRD_DMA_REQ_MODE_OFFSET 24 121 #define SPRD_DMA_REQ_MODE_MASK GENMASK(1, 0) 122 #define SPRD_DMA_WRAP_SEL_DEST BIT(23) 123 #define SPRD_DMA_WRAP_EN BIT(22) 124 #define SPRD_DMA_FIX_SEL_OFFSET 21 125 #define SPRD_DMA_FIX_EN_OFFSET 20 126 #define SPRD_DMA_LLIST_END BIT(19) 127 #define SPRD_DMA_FRG_LEN_MASK GENMASK(16, 0) 128 129 /* SPRD_DMA_CHN_BLK_LEN register definition */ 130 #define SPRD_DMA_BLK_LEN_MASK GENMASK(16, 0) 131 132 /* SPRD_DMA_CHN_TRSC_LEN register definition */ 133 #define SPRD_DMA_TRSC_LEN_MASK GENMASK(27, 0) 134 135 /* SPRD_DMA_CHN_TRSF_STEP register definition */ 136 #define SPRD_DMA_DEST_TRSF_STEP_OFFSET 16 137 #define SPRD_DMA_SRC_TRSF_STEP_OFFSET 0 138 #define SPRD_DMA_TRSF_STEP_MASK GENMASK(15, 0) 139 140 /* SPRD DMA_SRC_BLK_STEP register definition */ 141 #define SPRD_DMA_LLIST_HIGH_MASK GENMASK(31, 28) 142 #define SPRD_DMA_LLIST_HIGH_SHIFT 28 143 144 /* define DMA channel mode & trigger mode mask */ 145 #define SPRD_DMA_CHN_MODE_MASK GENMASK(7, 0) 146 #define SPRD_DMA_TRG_MODE_MASK GENMASK(7, 0) 147 #define SPRD_DMA_INT_TYPE_MASK GENMASK(7, 0) 148 149 /* define the DMA transfer step type */ 150 #define SPRD_DMA_NONE_STEP 0 151 #define SPRD_DMA_BYTE_STEP 1 152 #define SPRD_DMA_SHORT_STEP 2 153 #define SPRD_DMA_WORD_STEP 4 154 #define SPRD_DMA_DWORD_STEP 8 155 156 #define SPRD_DMA_SOFTWARE_UID 0 157 158 /* dma data width values */ 159 enum sprd_dma_datawidth { 160 SPRD_DMA_DATAWIDTH_1_BYTE, 161 SPRD_DMA_DATAWIDTH_2_BYTES, 162 SPRD_DMA_DATAWIDTH_4_BYTES, 163 SPRD_DMA_DATAWIDTH_8_BYTES, 164 }; 165 166 /* dma channel hardware configuration */ 167 struct sprd_dma_chn_hw { 168 u32 pause; 169 u32 req; 170 u32 cfg; 171 u32 intc; 172 u32 src_addr; 173 u32 des_addr; 174 u32 frg_len; 175 u32 blk_len; 176 u32 trsc_len; 177 u32 trsf_step; 178 u32 wrap_ptr; 179 u32 wrap_to; 180 u32 llist_ptr; 181 u32 frg_step; 182 u32 src_blk_step; 183 u32 des_blk_step; 184 }; 185 186 /* dma request description */ 187 struct sprd_dma_desc { 188 struct virt_dma_desc vd; 189 struct sprd_dma_chn_hw chn_hw; 190 enum dma_transfer_direction dir; 191 }; 192 193 /* dma channel description */ 194 struct sprd_dma_chn { 195 struct virt_dma_chan vc; 196 void __iomem *chn_base; 197 struct sprd_dma_linklist linklist; 198 struct dma_slave_config slave_cfg; 199 u32 chn_num; 200 u32 dev_id; 201 enum sprd_dma_chn_mode chn_mode; 202 enum sprd_dma_trg_mode trg_mode; 203 enum sprd_dma_int_type int_type; 204 struct sprd_dma_desc *cur_desc; 205 }; 206 207 /* SPRD dma device */ 208 struct sprd_dma_dev { 209 struct dma_device dma_dev; 210 void __iomem *glb_base; 211 struct clk *clk; 212 struct clk *ashb_clk; 213 int irq; 214 u32 total_chns; 215 struct sprd_dma_chn channels[0]; 216 }; 217 218 static void sprd_dma_free_desc(struct virt_dma_desc *vd); 219 static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param); 220 static struct of_dma_filter_info sprd_dma_info = { 221 .filter_fn = sprd_dma_filter_fn, 222 }; 223 224 static inline struct sprd_dma_chn *to_sprd_dma_chan(struct dma_chan *c) 225 { 226 return container_of(c, struct sprd_dma_chn, vc.chan); 227 } 228 229 static inline struct sprd_dma_dev *to_sprd_dma_dev(struct dma_chan *c) 230 { 231 struct sprd_dma_chn *schan = to_sprd_dma_chan(c); 232 233 return container_of(schan, struct sprd_dma_dev, channels[c->chan_id]); 234 } 235 236 static inline struct sprd_dma_desc *to_sprd_dma_desc(struct virt_dma_desc *vd) 237 { 238 return container_of(vd, struct sprd_dma_desc, vd); 239 } 240 241 static void sprd_dma_glb_update(struct sprd_dma_dev *sdev, u32 reg, 242 u32 mask, u32 val) 243 { 244 u32 orig = readl(sdev->glb_base + reg); 245 u32 tmp; 246 247 tmp = (orig & ~mask) | val; 248 writel(tmp, sdev->glb_base + reg); 249 } 250 251 static void sprd_dma_chn_update(struct sprd_dma_chn *schan, u32 reg, 252 u32 mask, u32 val) 253 { 254 u32 orig = readl(schan->chn_base + reg); 255 u32 tmp; 256 257 tmp = (orig & ~mask) | val; 258 writel(tmp, schan->chn_base + reg); 259 } 260 261 static int sprd_dma_enable(struct sprd_dma_dev *sdev) 262 { 263 int ret; 264 265 ret = clk_prepare_enable(sdev->clk); 266 if (ret) 267 return ret; 268 269 /* 270 * The ashb_clk is optional and only for AGCP DMA controller, so we 271 * need add one condition to check if the ashb_clk need enable. 272 */ 273 if (!IS_ERR(sdev->ashb_clk)) 274 ret = clk_prepare_enable(sdev->ashb_clk); 275 276 return ret; 277 } 278 279 static void sprd_dma_disable(struct sprd_dma_dev *sdev) 280 { 281 clk_disable_unprepare(sdev->clk); 282 283 /* 284 * Need to check if we need disable the optional ashb_clk for AGCP DMA. 285 */ 286 if (!IS_ERR(sdev->ashb_clk)) 287 clk_disable_unprepare(sdev->ashb_clk); 288 } 289 290 static void sprd_dma_set_uid(struct sprd_dma_chn *schan) 291 { 292 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan); 293 u32 dev_id = schan->dev_id; 294 295 if (dev_id != SPRD_DMA_SOFTWARE_UID) { 296 u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET + 297 SPRD_DMA_GLB_REQ_UID(dev_id); 298 299 writel(schan->chn_num + 1, sdev->glb_base + uid_offset); 300 } 301 } 302 303 static void sprd_dma_unset_uid(struct sprd_dma_chn *schan) 304 { 305 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan); 306 u32 dev_id = schan->dev_id; 307 308 if (dev_id != SPRD_DMA_SOFTWARE_UID) { 309 u32 uid_offset = SPRD_DMA_GLB_REQ_UID_OFFSET + 310 SPRD_DMA_GLB_REQ_UID(dev_id); 311 312 writel(0, sdev->glb_base + uid_offset); 313 } 314 } 315 316 static void sprd_dma_clear_int(struct sprd_dma_chn *schan) 317 { 318 sprd_dma_chn_update(schan, SPRD_DMA_CHN_INTC, 319 SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET, 320 SPRD_DMA_INT_MASK << SPRD_DMA_INT_CLR_OFFSET); 321 } 322 323 static void sprd_dma_enable_chn(struct sprd_dma_chn *schan) 324 { 325 sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN, 326 SPRD_DMA_CHN_EN); 327 } 328 329 static void sprd_dma_disable_chn(struct sprd_dma_chn *schan) 330 { 331 sprd_dma_chn_update(schan, SPRD_DMA_CHN_CFG, SPRD_DMA_CHN_EN, 0); 332 } 333 334 static void sprd_dma_soft_request(struct sprd_dma_chn *schan) 335 { 336 sprd_dma_chn_update(schan, SPRD_DMA_CHN_REQ, SPRD_DMA_REQ_EN, 337 SPRD_DMA_REQ_EN); 338 } 339 340 static void sprd_dma_pause_resume(struct sprd_dma_chn *schan, bool enable) 341 { 342 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan); 343 u32 pause, timeout = SPRD_DMA_PAUSE_CNT; 344 345 if (enable) { 346 sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE, 347 SPRD_DMA_PAUSE_EN, SPRD_DMA_PAUSE_EN); 348 349 do { 350 pause = readl(schan->chn_base + SPRD_DMA_CHN_PAUSE); 351 if (pause & SPRD_DMA_PAUSE_STS) 352 break; 353 354 cpu_relax(); 355 } while (--timeout > 0); 356 357 if (!timeout) 358 dev_warn(sdev->dma_dev.dev, 359 "pause dma controller timeout\n"); 360 } else { 361 sprd_dma_chn_update(schan, SPRD_DMA_CHN_PAUSE, 362 SPRD_DMA_PAUSE_EN, 0); 363 } 364 } 365 366 static void sprd_dma_stop_and_disable(struct sprd_dma_chn *schan) 367 { 368 u32 cfg = readl(schan->chn_base + SPRD_DMA_CHN_CFG); 369 370 if (!(cfg & SPRD_DMA_CHN_EN)) 371 return; 372 373 sprd_dma_pause_resume(schan, true); 374 sprd_dma_disable_chn(schan); 375 } 376 377 static unsigned long sprd_dma_get_src_addr(struct sprd_dma_chn *schan) 378 { 379 unsigned long addr, addr_high; 380 381 addr = readl(schan->chn_base + SPRD_DMA_CHN_SRC_ADDR); 382 addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_PTR) & 383 SPRD_DMA_HIGH_ADDR_MASK; 384 385 return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET); 386 } 387 388 static unsigned long sprd_dma_get_dst_addr(struct sprd_dma_chn *schan) 389 { 390 unsigned long addr, addr_high; 391 392 addr = readl(schan->chn_base + SPRD_DMA_CHN_DES_ADDR); 393 addr_high = readl(schan->chn_base + SPRD_DMA_CHN_WARP_TO) & 394 SPRD_DMA_HIGH_ADDR_MASK; 395 396 return addr | (addr_high << SPRD_DMA_HIGH_ADDR_OFFSET); 397 } 398 399 static enum sprd_dma_int_type sprd_dma_get_int_type(struct sprd_dma_chn *schan) 400 { 401 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan); 402 u32 intc_sts = readl(schan->chn_base + SPRD_DMA_CHN_INTC) & 403 SPRD_DMA_CHN_INT_STS; 404 405 switch (intc_sts) { 406 case SPRD_DMA_CFGERR_INT_STS: 407 return SPRD_DMA_CFGERR_INT; 408 409 case SPRD_DMA_LIST_INT_STS: 410 return SPRD_DMA_LIST_INT; 411 412 case SPRD_DMA_TRSC_INT_STS: 413 return SPRD_DMA_TRANS_INT; 414 415 case SPRD_DMA_BLK_INT_STS: 416 return SPRD_DMA_BLK_INT; 417 418 case SPRD_DMA_FRAG_INT_STS: 419 return SPRD_DMA_FRAG_INT; 420 421 default: 422 dev_warn(sdev->dma_dev.dev, "incorrect dma interrupt type\n"); 423 return SPRD_DMA_NO_INT; 424 } 425 } 426 427 static enum sprd_dma_req_mode sprd_dma_get_req_type(struct sprd_dma_chn *schan) 428 { 429 u32 frag_reg = readl(schan->chn_base + SPRD_DMA_CHN_FRG_LEN); 430 431 return (frag_reg >> SPRD_DMA_REQ_MODE_OFFSET) & SPRD_DMA_REQ_MODE_MASK; 432 } 433 434 static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan) 435 { 436 struct sprd_dma_dev *sdev = to_sprd_dma_dev(&schan->vc.chan); 437 u32 val, chn = schan->chn_num + 1; 438 439 switch (schan->chn_mode) { 440 case SPRD_DMA_SRC_CHN0: 441 val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; 442 val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; 443 val |= SPRD_DMA_GLB_2STAGE_EN; 444 if (schan->int_type != SPRD_DMA_NO_INT) 445 val |= SPRD_DMA_GLB_SRC_INT; 446 447 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); 448 break; 449 450 case SPRD_DMA_SRC_CHN1: 451 val = chn & SPRD_DMA_GLB_SRC_CHN_MASK; 452 val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET; 453 val |= SPRD_DMA_GLB_2STAGE_EN; 454 if (schan->int_type != SPRD_DMA_NO_INT) 455 val |= SPRD_DMA_GLB_SRC_INT; 456 457 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); 458 break; 459 460 case SPRD_DMA_DST_CHN0: 461 val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & 462 SPRD_DMA_GLB_DEST_CHN_MASK; 463 val |= SPRD_DMA_GLB_2STAGE_EN; 464 if (schan->int_type != SPRD_DMA_NO_INT) 465 val |= SPRD_DMA_GLB_DEST_INT; 466 467 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val); 468 break; 469 470 case SPRD_DMA_DST_CHN1: 471 val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) & 472 SPRD_DMA_GLB_DEST_CHN_MASK; 473 val |= SPRD_DMA_GLB_2STAGE_EN; 474 if (schan->int_type != SPRD_DMA_NO_INT) 475 val |= SPRD_DMA_GLB_DEST_INT; 476 477 sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val); 478 break; 479 480 default: 481 dev_err(sdev->dma_dev.dev, "invalid channel mode setting %d\n", 482 schan->chn_mode); 483 return -EINVAL; 484 } 485 486 return 0; 487 } 488 489 static void sprd_dma_set_chn_config(struct sprd_dma_chn *schan, 490 struct sprd_dma_desc *sdesc) 491 { 492 struct sprd_dma_chn_hw *cfg = &sdesc->chn_hw; 493 494 writel(cfg->pause, schan->chn_base + SPRD_DMA_CHN_PAUSE); 495 writel(cfg->cfg, schan->chn_base + SPRD_DMA_CHN_CFG); 496 writel(cfg->intc, schan->chn_base + SPRD_DMA_CHN_INTC); 497 writel(cfg->src_addr, schan->chn_base + SPRD_DMA_CHN_SRC_ADDR); 498 writel(cfg->des_addr, schan->chn_base + SPRD_DMA_CHN_DES_ADDR); 499 writel(cfg->frg_len, schan->chn_base + SPRD_DMA_CHN_FRG_LEN); 500 writel(cfg->blk_len, schan->chn_base + SPRD_DMA_CHN_BLK_LEN); 501 writel(cfg->trsc_len, schan->chn_base + SPRD_DMA_CHN_TRSC_LEN); 502 writel(cfg->trsf_step, schan->chn_base + SPRD_DMA_CHN_TRSF_STEP); 503 writel(cfg->wrap_ptr, schan->chn_base + SPRD_DMA_CHN_WARP_PTR); 504 writel(cfg->wrap_to, schan->chn_base + SPRD_DMA_CHN_WARP_TO); 505 writel(cfg->llist_ptr, schan->chn_base + SPRD_DMA_CHN_LLIST_PTR); 506 writel(cfg->frg_step, schan->chn_base + SPRD_DMA_CHN_FRAG_STEP); 507 writel(cfg->src_blk_step, schan->chn_base + SPRD_DMA_CHN_SRC_BLK_STEP); 508 writel(cfg->des_blk_step, schan->chn_base + SPRD_DMA_CHN_DES_BLK_STEP); 509 writel(cfg->req, schan->chn_base + SPRD_DMA_CHN_REQ); 510 } 511 512 static void sprd_dma_start(struct sprd_dma_chn *schan) 513 { 514 struct virt_dma_desc *vd = vchan_next_desc(&schan->vc); 515 516 if (!vd) 517 return; 518 519 list_del(&vd->node); 520 schan->cur_desc = to_sprd_dma_desc(vd); 521 522 /* 523 * Set 2-stage configuration if the channel starts one 2-stage 524 * transfer. 525 */ 526 if (schan->chn_mode && sprd_dma_set_2stage_config(schan)) 527 return; 528 529 /* 530 * Copy the DMA configuration from DMA descriptor to this hardware 531 * channel. 532 */ 533 sprd_dma_set_chn_config(schan, schan->cur_desc); 534 sprd_dma_set_uid(schan); 535 sprd_dma_enable_chn(schan); 536 537 if (schan->dev_id == SPRD_DMA_SOFTWARE_UID && 538 schan->chn_mode != SPRD_DMA_DST_CHN0 && 539 schan->chn_mode != SPRD_DMA_DST_CHN1) 540 sprd_dma_soft_request(schan); 541 } 542 543 static void sprd_dma_stop(struct sprd_dma_chn *schan) 544 { 545 sprd_dma_stop_and_disable(schan); 546 sprd_dma_unset_uid(schan); 547 sprd_dma_clear_int(schan); 548 schan->cur_desc = NULL; 549 } 550 551 static bool sprd_dma_check_trans_done(struct sprd_dma_desc *sdesc, 552 enum sprd_dma_int_type int_type, 553 enum sprd_dma_req_mode req_mode) 554 { 555 if (int_type == SPRD_DMA_NO_INT) 556 return false; 557 558 if (int_type >= req_mode + 1) 559 return true; 560 else 561 return false; 562 } 563 564 static irqreturn_t dma_irq_handle(int irq, void *dev_id) 565 { 566 struct sprd_dma_dev *sdev = (struct sprd_dma_dev *)dev_id; 567 u32 irq_status = readl(sdev->glb_base + SPRD_DMA_GLB_INT_MSK_STS); 568 struct sprd_dma_chn *schan; 569 struct sprd_dma_desc *sdesc; 570 enum sprd_dma_req_mode req_type; 571 enum sprd_dma_int_type int_type; 572 bool trans_done = false, cyclic = false; 573 u32 i; 574 575 while (irq_status) { 576 i = __ffs(irq_status); 577 irq_status &= (irq_status - 1); 578 schan = &sdev->channels[i]; 579 580 spin_lock(&schan->vc.lock); 581 582 sdesc = schan->cur_desc; 583 if (!sdesc) { 584 spin_unlock(&schan->vc.lock); 585 return IRQ_HANDLED; 586 } 587 588 int_type = sprd_dma_get_int_type(schan); 589 req_type = sprd_dma_get_req_type(schan); 590 sprd_dma_clear_int(schan); 591 592 /* cyclic mode schedule callback */ 593 cyclic = schan->linklist.phy_addr ? true : false; 594 if (cyclic == true) { 595 vchan_cyclic_callback(&sdesc->vd); 596 } else { 597 /* Check if the dma request descriptor is done. */ 598 trans_done = sprd_dma_check_trans_done(sdesc, int_type, 599 req_type); 600 if (trans_done == true) { 601 vchan_cookie_complete(&sdesc->vd); 602 schan->cur_desc = NULL; 603 sprd_dma_start(schan); 604 } 605 } 606 spin_unlock(&schan->vc.lock); 607 } 608 609 return IRQ_HANDLED; 610 } 611 612 static int sprd_dma_alloc_chan_resources(struct dma_chan *chan) 613 { 614 return pm_runtime_get_sync(chan->device->dev); 615 } 616 617 static void sprd_dma_free_chan_resources(struct dma_chan *chan) 618 { 619 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 620 struct virt_dma_desc *cur_vd = NULL; 621 unsigned long flags; 622 623 spin_lock_irqsave(&schan->vc.lock, flags); 624 if (schan->cur_desc) 625 cur_vd = &schan->cur_desc->vd; 626 627 sprd_dma_stop(schan); 628 spin_unlock_irqrestore(&schan->vc.lock, flags); 629 630 if (cur_vd) 631 sprd_dma_free_desc(cur_vd); 632 633 vchan_free_chan_resources(&schan->vc); 634 pm_runtime_put(chan->device->dev); 635 } 636 637 static enum dma_status sprd_dma_tx_status(struct dma_chan *chan, 638 dma_cookie_t cookie, 639 struct dma_tx_state *txstate) 640 { 641 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 642 struct virt_dma_desc *vd; 643 unsigned long flags; 644 enum dma_status ret; 645 u32 pos; 646 647 ret = dma_cookie_status(chan, cookie, txstate); 648 if (ret == DMA_COMPLETE || !txstate) 649 return ret; 650 651 spin_lock_irqsave(&schan->vc.lock, flags); 652 vd = vchan_find_desc(&schan->vc, cookie); 653 if (vd) { 654 struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd); 655 struct sprd_dma_chn_hw *hw = &sdesc->chn_hw; 656 657 if (hw->trsc_len > 0) 658 pos = hw->trsc_len; 659 else if (hw->blk_len > 0) 660 pos = hw->blk_len; 661 else if (hw->frg_len > 0) 662 pos = hw->frg_len; 663 else 664 pos = 0; 665 } else if (schan->cur_desc && schan->cur_desc->vd.tx.cookie == cookie) { 666 struct sprd_dma_desc *sdesc = schan->cur_desc; 667 668 if (sdesc->dir == DMA_DEV_TO_MEM) 669 pos = sprd_dma_get_dst_addr(schan); 670 else 671 pos = sprd_dma_get_src_addr(schan); 672 } else { 673 pos = 0; 674 } 675 spin_unlock_irqrestore(&schan->vc.lock, flags); 676 677 dma_set_residue(txstate, pos); 678 return ret; 679 } 680 681 static void sprd_dma_issue_pending(struct dma_chan *chan) 682 { 683 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 684 unsigned long flags; 685 686 spin_lock_irqsave(&schan->vc.lock, flags); 687 if (vchan_issue_pending(&schan->vc) && !schan->cur_desc) 688 sprd_dma_start(schan); 689 spin_unlock_irqrestore(&schan->vc.lock, flags); 690 } 691 692 static int sprd_dma_get_datawidth(enum dma_slave_buswidth buswidth) 693 { 694 switch (buswidth) { 695 case DMA_SLAVE_BUSWIDTH_1_BYTE: 696 case DMA_SLAVE_BUSWIDTH_2_BYTES: 697 case DMA_SLAVE_BUSWIDTH_4_BYTES: 698 case DMA_SLAVE_BUSWIDTH_8_BYTES: 699 return ffs(buswidth) - 1; 700 701 default: 702 return -EINVAL; 703 } 704 } 705 706 static int sprd_dma_get_step(enum dma_slave_buswidth buswidth) 707 { 708 switch (buswidth) { 709 case DMA_SLAVE_BUSWIDTH_1_BYTE: 710 case DMA_SLAVE_BUSWIDTH_2_BYTES: 711 case DMA_SLAVE_BUSWIDTH_4_BYTES: 712 case DMA_SLAVE_BUSWIDTH_8_BYTES: 713 return buswidth; 714 715 default: 716 return -EINVAL; 717 } 718 } 719 720 static int sprd_dma_fill_desc(struct dma_chan *chan, 721 struct sprd_dma_chn_hw *hw, 722 unsigned int sglen, int sg_index, 723 dma_addr_t src, dma_addr_t dst, u32 len, 724 enum dma_transfer_direction dir, 725 unsigned long flags, 726 struct dma_slave_config *slave_cfg) 727 { 728 struct sprd_dma_dev *sdev = to_sprd_dma_dev(chan); 729 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 730 enum sprd_dma_chn_mode chn_mode = schan->chn_mode; 731 u32 req_mode = (flags >> SPRD_DMA_REQ_SHIFT) & SPRD_DMA_REQ_MODE_MASK; 732 u32 int_mode = flags & SPRD_DMA_INT_MASK; 733 int src_datawidth, dst_datawidth, src_step, dst_step; 734 u32 temp, fix_mode = 0, fix_en = 0; 735 phys_addr_t llist_ptr; 736 737 if (dir == DMA_MEM_TO_DEV) { 738 src_step = sprd_dma_get_step(slave_cfg->src_addr_width); 739 if (src_step < 0) { 740 dev_err(sdev->dma_dev.dev, "invalid source step\n"); 741 return src_step; 742 } 743 744 /* 745 * For 2-stage transfer, destination channel step can not be 0, 746 * since destination device is AON IRAM. 747 */ 748 if (chn_mode == SPRD_DMA_DST_CHN0 || 749 chn_mode == SPRD_DMA_DST_CHN1) 750 dst_step = src_step; 751 else 752 dst_step = SPRD_DMA_NONE_STEP; 753 } else { 754 dst_step = sprd_dma_get_step(slave_cfg->dst_addr_width); 755 if (dst_step < 0) { 756 dev_err(sdev->dma_dev.dev, "invalid destination step\n"); 757 return dst_step; 758 } 759 src_step = SPRD_DMA_NONE_STEP; 760 } 761 762 src_datawidth = sprd_dma_get_datawidth(slave_cfg->src_addr_width); 763 if (src_datawidth < 0) { 764 dev_err(sdev->dma_dev.dev, "invalid source datawidth\n"); 765 return src_datawidth; 766 } 767 768 dst_datawidth = sprd_dma_get_datawidth(slave_cfg->dst_addr_width); 769 if (dst_datawidth < 0) { 770 dev_err(sdev->dma_dev.dev, "invalid destination datawidth\n"); 771 return dst_datawidth; 772 } 773 774 if (slave_cfg->slave_id) 775 schan->dev_id = slave_cfg->slave_id; 776 777 hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET; 778 779 /* 780 * wrap_ptr and wrap_to will save the high 4 bits source address and 781 * destination address. 782 */ 783 hw->wrap_ptr = (src >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK; 784 hw->wrap_to = (dst >> SPRD_DMA_HIGH_ADDR_OFFSET) & SPRD_DMA_HIGH_ADDR_MASK; 785 hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK; 786 hw->des_addr = dst & SPRD_DMA_LOW_ADDR_MASK; 787 788 /* 789 * If the src step and dst step both are 0 or both are not 0, that means 790 * we can not enable the fix mode. If one is 0 and another one is not, 791 * we can enable the fix mode. 792 */ 793 if ((src_step != 0 && dst_step != 0) || (src_step | dst_step) == 0) { 794 fix_en = 0; 795 } else { 796 fix_en = 1; 797 if (src_step) 798 fix_mode = 1; 799 else 800 fix_mode = 0; 801 } 802 803 hw->intc = int_mode | SPRD_DMA_CFG_ERR_INT_EN; 804 805 temp = src_datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET; 806 temp |= dst_datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET; 807 temp |= req_mode << SPRD_DMA_REQ_MODE_OFFSET; 808 temp |= fix_mode << SPRD_DMA_FIX_SEL_OFFSET; 809 temp |= fix_en << SPRD_DMA_FIX_EN_OFFSET; 810 temp |= schan->linklist.wrap_addr ? 811 SPRD_DMA_WRAP_EN | SPRD_DMA_WRAP_SEL_DEST : 0; 812 temp |= slave_cfg->src_maxburst & SPRD_DMA_FRG_LEN_MASK; 813 hw->frg_len = temp; 814 815 hw->blk_len = slave_cfg->src_maxburst & SPRD_DMA_BLK_LEN_MASK; 816 hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK; 817 818 temp = (dst_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET; 819 temp |= (src_step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET; 820 hw->trsf_step = temp; 821 822 /* link-list configuration */ 823 if (schan->linklist.phy_addr) { 824 hw->cfg |= SPRD_DMA_LINKLIST_EN; 825 826 /* link-list index */ 827 temp = sglen ? (sg_index + 1) % sglen : 0; 828 829 /* Next link-list configuration's physical address offset */ 830 temp = temp * sizeof(*hw) + SPRD_DMA_CHN_SRC_ADDR; 831 /* 832 * Set the link-list pointer point to next link-list 833 * configuration's physical address. 834 */ 835 llist_ptr = schan->linklist.phy_addr + temp; 836 hw->llist_ptr = lower_32_bits(llist_ptr); 837 hw->src_blk_step = (upper_32_bits(llist_ptr) << SPRD_DMA_LLIST_HIGH_SHIFT) & 838 SPRD_DMA_LLIST_HIGH_MASK; 839 840 if (schan->linklist.wrap_addr) { 841 hw->wrap_ptr |= schan->linklist.wrap_addr & 842 SPRD_DMA_WRAP_ADDR_MASK; 843 hw->wrap_to |= dst & SPRD_DMA_WRAP_ADDR_MASK; 844 } 845 } else { 846 hw->llist_ptr = 0; 847 hw->src_blk_step = 0; 848 } 849 850 hw->frg_step = 0; 851 hw->des_blk_step = 0; 852 return 0; 853 } 854 855 static int sprd_dma_fill_linklist_desc(struct dma_chan *chan, 856 unsigned int sglen, int sg_index, 857 dma_addr_t src, dma_addr_t dst, u32 len, 858 enum dma_transfer_direction dir, 859 unsigned long flags, 860 struct dma_slave_config *slave_cfg) 861 { 862 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 863 struct sprd_dma_chn_hw *hw; 864 865 if (!schan->linklist.virt_addr) 866 return -EINVAL; 867 868 hw = (struct sprd_dma_chn_hw *)(schan->linklist.virt_addr + 869 sg_index * sizeof(*hw)); 870 871 return sprd_dma_fill_desc(chan, hw, sglen, sg_index, src, dst, len, 872 dir, flags, slave_cfg); 873 } 874 875 static struct dma_async_tx_descriptor * 876 sprd_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 877 size_t len, unsigned long flags) 878 { 879 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 880 struct sprd_dma_desc *sdesc; 881 struct sprd_dma_chn_hw *hw; 882 enum sprd_dma_datawidth datawidth; 883 u32 step, temp; 884 885 sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT); 886 if (!sdesc) 887 return NULL; 888 889 hw = &sdesc->chn_hw; 890 891 hw->cfg = SPRD_DMA_DONOT_WAIT_BDONE << SPRD_DMA_WAIT_BDONE_OFFSET; 892 hw->intc = SPRD_DMA_TRANS_INT | SPRD_DMA_CFG_ERR_INT_EN; 893 hw->src_addr = src & SPRD_DMA_LOW_ADDR_MASK; 894 hw->des_addr = dest & SPRD_DMA_LOW_ADDR_MASK; 895 hw->wrap_ptr = (src >> SPRD_DMA_HIGH_ADDR_OFFSET) & 896 SPRD_DMA_HIGH_ADDR_MASK; 897 hw->wrap_to = (dest >> SPRD_DMA_HIGH_ADDR_OFFSET) & 898 SPRD_DMA_HIGH_ADDR_MASK; 899 900 if (IS_ALIGNED(len, 8)) { 901 datawidth = SPRD_DMA_DATAWIDTH_8_BYTES; 902 step = SPRD_DMA_DWORD_STEP; 903 } else if (IS_ALIGNED(len, 4)) { 904 datawidth = SPRD_DMA_DATAWIDTH_4_BYTES; 905 step = SPRD_DMA_WORD_STEP; 906 } else if (IS_ALIGNED(len, 2)) { 907 datawidth = SPRD_DMA_DATAWIDTH_2_BYTES; 908 step = SPRD_DMA_SHORT_STEP; 909 } else { 910 datawidth = SPRD_DMA_DATAWIDTH_1_BYTE; 911 step = SPRD_DMA_BYTE_STEP; 912 } 913 914 temp = datawidth << SPRD_DMA_SRC_DATAWIDTH_OFFSET; 915 temp |= datawidth << SPRD_DMA_DES_DATAWIDTH_OFFSET; 916 temp |= SPRD_DMA_TRANS_REQ << SPRD_DMA_REQ_MODE_OFFSET; 917 temp |= len & SPRD_DMA_FRG_LEN_MASK; 918 hw->frg_len = temp; 919 920 hw->blk_len = len & SPRD_DMA_BLK_LEN_MASK; 921 hw->trsc_len = len & SPRD_DMA_TRSC_LEN_MASK; 922 923 temp = (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_DEST_TRSF_STEP_OFFSET; 924 temp |= (step & SPRD_DMA_TRSF_STEP_MASK) << SPRD_DMA_SRC_TRSF_STEP_OFFSET; 925 hw->trsf_step = temp; 926 927 return vchan_tx_prep(&schan->vc, &sdesc->vd, flags); 928 } 929 930 static struct dma_async_tx_descriptor * 931 sprd_dma_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 932 unsigned int sglen, enum dma_transfer_direction dir, 933 unsigned long flags, void *context) 934 { 935 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 936 struct dma_slave_config *slave_cfg = &schan->slave_cfg; 937 dma_addr_t src = 0, dst = 0; 938 dma_addr_t start_src = 0, start_dst = 0; 939 struct sprd_dma_desc *sdesc; 940 struct scatterlist *sg; 941 u32 len = 0; 942 int ret, i; 943 944 if (!is_slave_direction(dir)) 945 return NULL; 946 947 if (context) { 948 struct sprd_dma_linklist *ll_cfg = 949 (struct sprd_dma_linklist *)context; 950 951 schan->linklist.phy_addr = ll_cfg->phy_addr; 952 schan->linklist.virt_addr = ll_cfg->virt_addr; 953 schan->linklist.wrap_addr = ll_cfg->wrap_addr; 954 } else { 955 schan->linklist.phy_addr = 0; 956 schan->linklist.virt_addr = 0; 957 schan->linklist.wrap_addr = 0; 958 } 959 960 /* 961 * Set channel mode, interrupt mode and trigger mode for 2-stage 962 * transfer. 963 */ 964 schan->chn_mode = 965 (flags >> SPRD_DMA_CHN_MODE_SHIFT) & SPRD_DMA_CHN_MODE_MASK; 966 schan->trg_mode = 967 (flags >> SPRD_DMA_TRG_MODE_SHIFT) & SPRD_DMA_TRG_MODE_MASK; 968 schan->int_type = flags & SPRD_DMA_INT_TYPE_MASK; 969 970 sdesc = kzalloc(sizeof(*sdesc), GFP_NOWAIT); 971 if (!sdesc) 972 return NULL; 973 974 sdesc->dir = dir; 975 976 for_each_sg(sgl, sg, sglen, i) { 977 len = sg_dma_len(sg); 978 979 if (dir == DMA_MEM_TO_DEV) { 980 src = sg_dma_address(sg); 981 dst = slave_cfg->dst_addr; 982 } else { 983 src = slave_cfg->src_addr; 984 dst = sg_dma_address(sg); 985 } 986 987 if (!i) { 988 start_src = src; 989 start_dst = dst; 990 } 991 992 /* 993 * The link-list mode needs at least 2 link-list 994 * configurations. If there is only one sg, it doesn't 995 * need to fill the link-list configuration. 996 */ 997 if (sglen < 2) 998 break; 999 1000 ret = sprd_dma_fill_linklist_desc(chan, sglen, i, src, dst, len, 1001 dir, flags, slave_cfg); 1002 if (ret) { 1003 kfree(sdesc); 1004 return NULL; 1005 } 1006 } 1007 1008 ret = sprd_dma_fill_desc(chan, &sdesc->chn_hw, 0, 0, start_src, 1009 start_dst, len, dir, flags, slave_cfg); 1010 if (ret) { 1011 kfree(sdesc); 1012 return NULL; 1013 } 1014 1015 return vchan_tx_prep(&schan->vc, &sdesc->vd, flags); 1016 } 1017 1018 static int sprd_dma_slave_config(struct dma_chan *chan, 1019 struct dma_slave_config *config) 1020 { 1021 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 1022 struct dma_slave_config *slave_cfg = &schan->slave_cfg; 1023 1024 memcpy(slave_cfg, config, sizeof(*config)); 1025 return 0; 1026 } 1027 1028 static int sprd_dma_pause(struct dma_chan *chan) 1029 { 1030 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 1031 unsigned long flags; 1032 1033 spin_lock_irqsave(&schan->vc.lock, flags); 1034 sprd_dma_pause_resume(schan, true); 1035 spin_unlock_irqrestore(&schan->vc.lock, flags); 1036 1037 return 0; 1038 } 1039 1040 static int sprd_dma_resume(struct dma_chan *chan) 1041 { 1042 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 1043 unsigned long flags; 1044 1045 spin_lock_irqsave(&schan->vc.lock, flags); 1046 sprd_dma_pause_resume(schan, false); 1047 spin_unlock_irqrestore(&schan->vc.lock, flags); 1048 1049 return 0; 1050 } 1051 1052 static int sprd_dma_terminate_all(struct dma_chan *chan) 1053 { 1054 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 1055 struct virt_dma_desc *cur_vd = NULL; 1056 unsigned long flags; 1057 LIST_HEAD(head); 1058 1059 spin_lock_irqsave(&schan->vc.lock, flags); 1060 if (schan->cur_desc) 1061 cur_vd = &schan->cur_desc->vd; 1062 1063 sprd_dma_stop(schan); 1064 1065 vchan_get_all_descriptors(&schan->vc, &head); 1066 spin_unlock_irqrestore(&schan->vc.lock, flags); 1067 1068 if (cur_vd) 1069 sprd_dma_free_desc(cur_vd); 1070 1071 vchan_dma_desc_free_list(&schan->vc, &head); 1072 return 0; 1073 } 1074 1075 static void sprd_dma_free_desc(struct virt_dma_desc *vd) 1076 { 1077 struct sprd_dma_desc *sdesc = to_sprd_dma_desc(vd); 1078 1079 kfree(sdesc); 1080 } 1081 1082 static bool sprd_dma_filter_fn(struct dma_chan *chan, void *param) 1083 { 1084 struct sprd_dma_chn *schan = to_sprd_dma_chan(chan); 1085 u32 slave_id = *(u32 *)param; 1086 1087 schan->dev_id = slave_id; 1088 return true; 1089 } 1090 1091 static int sprd_dma_probe(struct platform_device *pdev) 1092 { 1093 struct device_node *np = pdev->dev.of_node; 1094 struct sprd_dma_dev *sdev; 1095 struct sprd_dma_chn *dma_chn; 1096 u32 chn_count; 1097 int ret, i; 1098 1099 ret = device_property_read_u32(&pdev->dev, "#dma-channels", &chn_count); 1100 if (ret) { 1101 dev_err(&pdev->dev, "get dma channels count failed\n"); 1102 return ret; 1103 } 1104 1105 sdev = devm_kzalloc(&pdev->dev, 1106 struct_size(sdev, channels, chn_count), 1107 GFP_KERNEL); 1108 if (!sdev) 1109 return -ENOMEM; 1110 1111 sdev->clk = devm_clk_get(&pdev->dev, "enable"); 1112 if (IS_ERR(sdev->clk)) { 1113 dev_err(&pdev->dev, "get enable clock failed\n"); 1114 return PTR_ERR(sdev->clk); 1115 } 1116 1117 /* ashb clock is optional for AGCP DMA */ 1118 sdev->ashb_clk = devm_clk_get(&pdev->dev, "ashb_eb"); 1119 if (IS_ERR(sdev->ashb_clk)) 1120 dev_warn(&pdev->dev, "no optional ashb eb clock\n"); 1121 1122 /* 1123 * We have three DMA controllers: AP DMA, AON DMA and AGCP DMA. For AGCP 1124 * DMA controller, it can or do not request the irq, which will save 1125 * system power without resuming system by DMA interrupts if AGCP DMA 1126 * does not request the irq. Thus the DMA interrupts property should 1127 * be optional. 1128 */ 1129 sdev->irq = platform_get_irq(pdev, 0); 1130 if (sdev->irq > 0) { 1131 ret = devm_request_irq(&pdev->dev, sdev->irq, dma_irq_handle, 1132 0, "sprd_dma", (void *)sdev); 1133 if (ret < 0) { 1134 dev_err(&pdev->dev, "request dma irq failed\n"); 1135 return ret; 1136 } 1137 } else { 1138 dev_warn(&pdev->dev, "no interrupts for the dma controller\n"); 1139 } 1140 1141 sdev->glb_base = devm_platform_ioremap_resource(pdev, 0); 1142 if (IS_ERR(sdev->glb_base)) 1143 return PTR_ERR(sdev->glb_base); 1144 1145 dma_cap_set(DMA_MEMCPY, sdev->dma_dev.cap_mask); 1146 sdev->total_chns = chn_count; 1147 sdev->dma_dev.chancnt = chn_count; 1148 INIT_LIST_HEAD(&sdev->dma_dev.channels); 1149 INIT_LIST_HEAD(&sdev->dma_dev.global_node); 1150 sdev->dma_dev.dev = &pdev->dev; 1151 sdev->dma_dev.device_alloc_chan_resources = sprd_dma_alloc_chan_resources; 1152 sdev->dma_dev.device_free_chan_resources = sprd_dma_free_chan_resources; 1153 sdev->dma_dev.device_tx_status = sprd_dma_tx_status; 1154 sdev->dma_dev.device_issue_pending = sprd_dma_issue_pending; 1155 sdev->dma_dev.device_prep_dma_memcpy = sprd_dma_prep_dma_memcpy; 1156 sdev->dma_dev.device_prep_slave_sg = sprd_dma_prep_slave_sg; 1157 sdev->dma_dev.device_config = sprd_dma_slave_config; 1158 sdev->dma_dev.device_pause = sprd_dma_pause; 1159 sdev->dma_dev.device_resume = sprd_dma_resume; 1160 sdev->dma_dev.device_terminate_all = sprd_dma_terminate_all; 1161 1162 for (i = 0; i < chn_count; i++) { 1163 dma_chn = &sdev->channels[i]; 1164 dma_chn->chn_num = i; 1165 dma_chn->cur_desc = NULL; 1166 /* get each channel's registers base address. */ 1167 dma_chn->chn_base = sdev->glb_base + SPRD_DMA_CHN_REG_OFFSET + 1168 SPRD_DMA_CHN_REG_LENGTH * i; 1169 1170 dma_chn->vc.desc_free = sprd_dma_free_desc; 1171 vchan_init(&dma_chn->vc, &sdev->dma_dev); 1172 } 1173 1174 platform_set_drvdata(pdev, sdev); 1175 ret = sprd_dma_enable(sdev); 1176 if (ret) 1177 return ret; 1178 1179 pm_runtime_set_active(&pdev->dev); 1180 pm_runtime_enable(&pdev->dev); 1181 1182 ret = pm_runtime_get_sync(&pdev->dev); 1183 if (ret < 0) 1184 goto err_rpm; 1185 1186 ret = dma_async_device_register(&sdev->dma_dev); 1187 if (ret < 0) { 1188 dev_err(&pdev->dev, "register dma device failed:%d\n", ret); 1189 goto err_register; 1190 } 1191 1192 sprd_dma_info.dma_cap = sdev->dma_dev.cap_mask; 1193 ret = of_dma_controller_register(np, of_dma_simple_xlate, 1194 &sprd_dma_info); 1195 if (ret) 1196 goto err_of_register; 1197 1198 pm_runtime_put(&pdev->dev); 1199 return 0; 1200 1201 err_of_register: 1202 dma_async_device_unregister(&sdev->dma_dev); 1203 err_register: 1204 pm_runtime_put_noidle(&pdev->dev); 1205 pm_runtime_disable(&pdev->dev); 1206 err_rpm: 1207 sprd_dma_disable(sdev); 1208 return ret; 1209 } 1210 1211 static int sprd_dma_remove(struct platform_device *pdev) 1212 { 1213 struct sprd_dma_dev *sdev = platform_get_drvdata(pdev); 1214 struct sprd_dma_chn *c, *cn; 1215 int ret; 1216 1217 ret = pm_runtime_get_sync(&pdev->dev); 1218 if (ret < 0) 1219 return ret; 1220 1221 /* explicitly free the irq */ 1222 if (sdev->irq > 0) 1223 devm_free_irq(&pdev->dev, sdev->irq, sdev); 1224 1225 list_for_each_entry_safe(c, cn, &sdev->dma_dev.channels, 1226 vc.chan.device_node) { 1227 list_del(&c->vc.chan.device_node); 1228 tasklet_kill(&c->vc.task); 1229 } 1230 1231 of_dma_controller_free(pdev->dev.of_node); 1232 dma_async_device_unregister(&sdev->dma_dev); 1233 sprd_dma_disable(sdev); 1234 1235 pm_runtime_put_noidle(&pdev->dev); 1236 pm_runtime_disable(&pdev->dev); 1237 return 0; 1238 } 1239 1240 static const struct of_device_id sprd_dma_match[] = { 1241 { .compatible = "sprd,sc9860-dma", }, 1242 {}, 1243 }; 1244 1245 static int __maybe_unused sprd_dma_runtime_suspend(struct device *dev) 1246 { 1247 struct sprd_dma_dev *sdev = dev_get_drvdata(dev); 1248 1249 sprd_dma_disable(sdev); 1250 return 0; 1251 } 1252 1253 static int __maybe_unused sprd_dma_runtime_resume(struct device *dev) 1254 { 1255 struct sprd_dma_dev *sdev = dev_get_drvdata(dev); 1256 int ret; 1257 1258 ret = sprd_dma_enable(sdev); 1259 if (ret) 1260 dev_err(sdev->dma_dev.dev, "enable dma failed\n"); 1261 1262 return ret; 1263 } 1264 1265 static const struct dev_pm_ops sprd_dma_pm_ops = { 1266 SET_RUNTIME_PM_OPS(sprd_dma_runtime_suspend, 1267 sprd_dma_runtime_resume, 1268 NULL) 1269 }; 1270 1271 static struct platform_driver sprd_dma_driver = { 1272 .probe = sprd_dma_probe, 1273 .remove = sprd_dma_remove, 1274 .driver = { 1275 .name = "sprd-dma", 1276 .of_match_table = sprd_dma_match, 1277 .pm = &sprd_dma_pm_ops, 1278 }, 1279 }; 1280 module_platform_driver(sprd_dma_driver); 1281 1282 MODULE_LICENSE("GPL v2"); 1283 MODULE_DESCRIPTION("DMA driver for Spreadtrum"); 1284 MODULE_AUTHOR("Baolin Wang <baolin.wang@spreadtrum.com>"); 1285 MODULE_AUTHOR("Eric Long <eric.long@spreadtrum.com>"); 1286 MODULE_ALIAS("platform:sprd-dma"); 1287