1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. 4 */ 5 /* 6 * QCOM BAM DMA engine driver 7 * 8 * QCOM BAM DMA blocks are distributed amongst a number of the on-chip 9 * peripherals on the MSM 8x74. The configuration of the channels are dependent 10 * on the way they are hard wired to that specific peripheral. The peripheral 11 * device tree entries specify the configuration of each channel. 12 * 13 * The DMA controller requires the use of external memory for storage of the 14 * hardware descriptors for each channel. The descriptor FIFO is accessed as a 15 * circular buffer and operations are managed according to the offset within the 16 * FIFO. After pipe/channel reset, all of the pipe registers and internal state 17 * are back to defaults. 18 * 19 * During DMA operations, we write descriptors to the FIFO, being careful to 20 * handle wrapping and then write the last FIFO offset to that channel's 21 * P_EVNT_REG register to kick off the transaction. The P_SW_OFSTS register 22 * indicates the current FIFO offset that is being processed, so there is some 23 * indication of where the hardware is currently working. 24 */ 25 26 #include <linux/kernel.h> 27 #include <linux/io.h> 28 #include <linux/init.h> 29 #include <linux/slab.h> 30 #include <linux/module.h> 31 #include <linux/interrupt.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/scatterlist.h> 34 #include <linux/device.h> 35 #include <linux/platform_device.h> 36 #include <linux/of.h> 37 #include <linux/of_address.h> 38 #include <linux/of_irq.h> 39 #include <linux/of_dma.h> 40 #include <linux/circ_buf.h> 41 #include <linux/clk.h> 42 #include <linux/dmaengine.h> 43 #include <linux/pm_runtime.h> 44 45 #include "../dmaengine.h" 46 #include "../virt-dma.h" 47 48 struct bam_desc_hw { 49 __le32 addr; /* Buffer physical address */ 50 __le16 size; /* Buffer size in bytes */ 51 __le16 flags; 52 }; 53 54 #define BAM_DMA_AUTOSUSPEND_DELAY 100 55 56 #define DESC_FLAG_INT BIT(15) 57 #define DESC_FLAG_EOT BIT(14) 58 #define DESC_FLAG_EOB BIT(13) 59 #define DESC_FLAG_NWD BIT(12) 60 #define DESC_FLAG_CMD BIT(11) 61 62 #define BAM_NDP_REVISION_START 0x20 63 #define BAM_NDP_REVISION_END 0x27 64 65 struct bam_async_desc { 66 struct virt_dma_desc vd; 67 68 u32 num_desc; 69 u32 xfer_len; 70 71 /* transaction flags, EOT|EOB|NWD */ 72 u16 flags; 73 74 struct bam_desc_hw *curr_desc; 75 76 /* list node for the desc in the bam_chan list of descriptors */ 77 struct list_head desc_node; 78 enum dma_transfer_direction dir; 79 size_t length; 80 struct bam_desc_hw desc[] __counted_by(num_desc); 81 }; 82 83 enum bam_reg { 84 BAM_CTRL, 85 BAM_REVISION, 86 BAM_NUM_PIPES, 87 BAM_DESC_CNT_TRSHLD, 88 BAM_IRQ_SRCS, 89 BAM_IRQ_SRCS_MSK, 90 BAM_IRQ_SRCS_UNMASKED, 91 BAM_IRQ_STTS, 92 BAM_IRQ_CLR, 93 BAM_IRQ_EN, 94 BAM_CNFG_BITS, 95 BAM_IRQ_SRCS_EE, 96 BAM_IRQ_SRCS_MSK_EE, 97 BAM_P_CTRL, 98 BAM_P_RST, 99 BAM_P_HALT, 100 BAM_P_IRQ_STTS, 101 BAM_P_IRQ_CLR, 102 BAM_P_IRQ_EN, 103 BAM_P_EVNT_DEST_ADDR, 104 BAM_P_EVNT_REG, 105 BAM_P_SW_OFSTS, 106 BAM_P_DATA_FIFO_ADDR, 107 BAM_P_DESC_FIFO_ADDR, 108 BAM_P_EVNT_GEN_TRSHLD, 109 BAM_P_FIFO_SIZES, 110 }; 111 112 struct reg_offset_data { 113 u32 base_offset; 114 unsigned int pipe_mult, evnt_mult, ee_mult; 115 }; 116 117 static const struct reg_offset_data bam_v1_3_reg_info[] = { 118 [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 }, 119 [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 }, 120 [BAM_NUM_PIPES] = { 0x0FBC, 0x00, 0x00, 0x00 }, 121 [BAM_DESC_CNT_TRSHLD] = { 0x0F88, 0x00, 0x00, 0x00 }, 122 [BAM_IRQ_SRCS] = { 0x0F8C, 0x00, 0x00, 0x00 }, 123 [BAM_IRQ_SRCS_MSK] = { 0x0F90, 0x00, 0x00, 0x00 }, 124 [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 }, 125 [BAM_IRQ_STTS] = { 0x0F94, 0x00, 0x00, 0x00 }, 126 [BAM_IRQ_CLR] = { 0x0F98, 0x00, 0x00, 0x00 }, 127 [BAM_IRQ_EN] = { 0x0F9C, 0x00, 0x00, 0x00 }, 128 [BAM_CNFG_BITS] = { 0x0FFC, 0x00, 0x00, 0x00 }, 129 [BAM_IRQ_SRCS_EE] = { 0x1800, 0x00, 0x00, 0x80 }, 130 [BAM_IRQ_SRCS_MSK_EE] = { 0x1804, 0x00, 0x00, 0x80 }, 131 [BAM_P_CTRL] = { 0x0000, 0x80, 0x00, 0x00 }, 132 [BAM_P_RST] = { 0x0004, 0x80, 0x00, 0x00 }, 133 [BAM_P_HALT] = { 0x0008, 0x80, 0x00, 0x00 }, 134 [BAM_P_IRQ_STTS] = { 0x0010, 0x80, 0x00, 0x00 }, 135 [BAM_P_IRQ_CLR] = { 0x0014, 0x80, 0x00, 0x00 }, 136 [BAM_P_IRQ_EN] = { 0x0018, 0x80, 0x00, 0x00 }, 137 [BAM_P_EVNT_DEST_ADDR] = { 0x102C, 0x00, 0x40, 0x00 }, 138 [BAM_P_EVNT_REG] = { 0x1018, 0x00, 0x40, 0x00 }, 139 [BAM_P_SW_OFSTS] = { 0x1000, 0x00, 0x40, 0x00 }, 140 [BAM_P_DATA_FIFO_ADDR] = { 0x1024, 0x00, 0x40, 0x00 }, 141 [BAM_P_DESC_FIFO_ADDR] = { 0x101C, 0x00, 0x40, 0x00 }, 142 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 }, 143 [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 }, 144 }; 145 146 static const struct reg_offset_data bam_v1_4_reg_info[] = { 147 [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, 148 [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 }, 149 [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 }, 150 [BAM_DESC_CNT_TRSHLD] = { 0x0008, 0x00, 0x00, 0x00 }, 151 [BAM_IRQ_SRCS] = { 0x000C, 0x00, 0x00, 0x00 }, 152 [BAM_IRQ_SRCS_MSK] = { 0x0010, 0x00, 0x00, 0x00 }, 153 [BAM_IRQ_SRCS_UNMASKED] = { 0x0030, 0x00, 0x00, 0x00 }, 154 [BAM_IRQ_STTS] = { 0x0014, 0x00, 0x00, 0x00 }, 155 [BAM_IRQ_CLR] = { 0x0018, 0x00, 0x00, 0x00 }, 156 [BAM_IRQ_EN] = { 0x001C, 0x00, 0x00, 0x00 }, 157 [BAM_CNFG_BITS] = { 0x007C, 0x00, 0x00, 0x00 }, 158 [BAM_IRQ_SRCS_EE] = { 0x0800, 0x00, 0x00, 0x80 }, 159 [BAM_IRQ_SRCS_MSK_EE] = { 0x0804, 0x00, 0x00, 0x80 }, 160 [BAM_P_CTRL] = { 0x1000, 0x1000, 0x00, 0x00 }, 161 [BAM_P_RST] = { 0x1004, 0x1000, 0x00, 0x00 }, 162 [BAM_P_HALT] = { 0x1008, 0x1000, 0x00, 0x00 }, 163 [BAM_P_IRQ_STTS] = { 0x1010, 0x1000, 0x00, 0x00 }, 164 [BAM_P_IRQ_CLR] = { 0x1014, 0x1000, 0x00, 0x00 }, 165 [BAM_P_IRQ_EN] = { 0x1018, 0x1000, 0x00, 0x00 }, 166 [BAM_P_EVNT_DEST_ADDR] = { 0x182C, 0x00, 0x1000, 0x00 }, 167 [BAM_P_EVNT_REG] = { 0x1818, 0x00, 0x1000, 0x00 }, 168 [BAM_P_SW_OFSTS] = { 0x1800, 0x00, 0x1000, 0x00 }, 169 [BAM_P_DATA_FIFO_ADDR] = { 0x1824, 0x00, 0x1000, 0x00 }, 170 [BAM_P_DESC_FIFO_ADDR] = { 0x181C, 0x00, 0x1000, 0x00 }, 171 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1828, 0x00, 0x1000, 0x00 }, 172 [BAM_P_FIFO_SIZES] = { 0x1820, 0x00, 0x1000, 0x00 }, 173 }; 174 175 static const struct reg_offset_data bam_v1_7_reg_info[] = { 176 [BAM_CTRL] = { 0x00000, 0x00, 0x00, 0x00 }, 177 [BAM_REVISION] = { 0x01000, 0x00, 0x00, 0x00 }, 178 [BAM_NUM_PIPES] = { 0x01008, 0x00, 0x00, 0x00 }, 179 [BAM_DESC_CNT_TRSHLD] = { 0x00008, 0x00, 0x00, 0x00 }, 180 [BAM_IRQ_SRCS] = { 0x03010, 0x00, 0x00, 0x00 }, 181 [BAM_IRQ_SRCS_MSK] = { 0x03014, 0x00, 0x00, 0x00 }, 182 [BAM_IRQ_SRCS_UNMASKED] = { 0x03018, 0x00, 0x00, 0x00 }, 183 [BAM_IRQ_STTS] = { 0x00014, 0x00, 0x00, 0x00 }, 184 [BAM_IRQ_CLR] = { 0x00018, 0x00, 0x00, 0x00 }, 185 [BAM_IRQ_EN] = { 0x0001C, 0x00, 0x00, 0x00 }, 186 [BAM_CNFG_BITS] = { 0x0007C, 0x00, 0x00, 0x00 }, 187 [BAM_IRQ_SRCS_EE] = { 0x03000, 0x00, 0x00, 0x1000 }, 188 [BAM_IRQ_SRCS_MSK_EE] = { 0x03004, 0x00, 0x00, 0x1000 }, 189 [BAM_P_CTRL] = { 0x13000, 0x1000, 0x00, 0x00 }, 190 [BAM_P_RST] = { 0x13004, 0x1000, 0x00, 0x00 }, 191 [BAM_P_HALT] = { 0x13008, 0x1000, 0x00, 0x00 }, 192 [BAM_P_IRQ_STTS] = { 0x13010, 0x1000, 0x00, 0x00 }, 193 [BAM_P_IRQ_CLR] = { 0x13014, 0x1000, 0x00, 0x00 }, 194 [BAM_P_IRQ_EN] = { 0x13018, 0x1000, 0x00, 0x00 }, 195 [BAM_P_EVNT_DEST_ADDR] = { 0x1382C, 0x00, 0x1000, 0x00 }, 196 [BAM_P_EVNT_REG] = { 0x13818, 0x00, 0x1000, 0x00 }, 197 [BAM_P_SW_OFSTS] = { 0x13800, 0x00, 0x1000, 0x00 }, 198 [BAM_P_DATA_FIFO_ADDR] = { 0x13824, 0x00, 0x1000, 0x00 }, 199 [BAM_P_DESC_FIFO_ADDR] = { 0x1381C, 0x00, 0x1000, 0x00 }, 200 [BAM_P_EVNT_GEN_TRSHLD] = { 0x13828, 0x00, 0x1000, 0x00 }, 201 [BAM_P_FIFO_SIZES] = { 0x13820, 0x00, 0x1000, 0x00 }, 202 }; 203 204 /* BAM CTRL */ 205 #define BAM_SW_RST BIT(0) 206 #define BAM_EN BIT(1) 207 #define BAM_EN_ACCUM BIT(4) 208 #define BAM_TESTBUS_SEL_SHIFT 5 209 #define BAM_TESTBUS_SEL_MASK 0x3F 210 #define BAM_DESC_CACHE_SEL_SHIFT 13 211 #define BAM_DESC_CACHE_SEL_MASK 0x3 212 #define BAM_CACHED_DESC_STORE BIT(15) 213 #define IBC_DISABLE BIT(16) 214 215 /* BAM REVISION */ 216 #define REVISION_SHIFT 0 217 #define REVISION_MASK 0xFF 218 #define NUM_EES_SHIFT 8 219 #define NUM_EES_MASK 0xF 220 #define CE_BUFFER_SIZE BIT(13) 221 #define AXI_ACTIVE BIT(14) 222 #define USE_VMIDMT BIT(15) 223 #define SECURED BIT(16) 224 #define BAM_HAS_NO_BYPASS BIT(17) 225 #define HIGH_FREQUENCY_BAM BIT(18) 226 #define INACTIV_TMRS_EXST BIT(19) 227 #define NUM_INACTIV_TMRS BIT(20) 228 #define DESC_CACHE_DEPTH_SHIFT 21 229 #define DESC_CACHE_DEPTH_1 (0 << DESC_CACHE_DEPTH_SHIFT) 230 #define DESC_CACHE_DEPTH_2 (1 << DESC_CACHE_DEPTH_SHIFT) 231 #define DESC_CACHE_DEPTH_3 (2 << DESC_CACHE_DEPTH_SHIFT) 232 #define DESC_CACHE_DEPTH_4 (3 << DESC_CACHE_DEPTH_SHIFT) 233 #define CMD_DESC_EN BIT(23) 234 #define INACTIV_TMR_BASE_SHIFT 24 235 #define INACTIV_TMR_BASE_MASK 0xFF 236 237 /* BAM NUM PIPES */ 238 #define BAM_NUM_PIPES_SHIFT 0 239 #define BAM_NUM_PIPES_MASK 0xFF 240 #define PERIPH_NON_PIPE_GRP_SHIFT 16 241 #define PERIPH_NON_PIP_GRP_MASK 0xFF 242 #define BAM_NON_PIPE_GRP_SHIFT 24 243 #define BAM_NON_PIPE_GRP_MASK 0xFF 244 245 /* BAM CNFG BITS */ 246 #define BAM_PIPE_CNFG BIT(2) 247 #define BAM_FULL_PIPE BIT(11) 248 #define BAM_NO_EXT_P_RST BIT(12) 249 #define BAM_IBC_DISABLE BIT(13) 250 #define BAM_SB_CLK_REQ BIT(14) 251 #define BAM_PSM_CSW_REQ BIT(15) 252 #define BAM_PSM_P_RES BIT(16) 253 #define BAM_AU_P_RES BIT(17) 254 #define BAM_SI_P_RES BIT(18) 255 #define BAM_WB_P_RES BIT(19) 256 #define BAM_WB_BLK_CSW BIT(20) 257 #define BAM_WB_CSW_ACK_IDL BIT(21) 258 #define BAM_WB_RETR_SVPNT BIT(22) 259 #define BAM_WB_DSC_AVL_P_RST BIT(23) 260 #define BAM_REG_P_EN BIT(24) 261 #define BAM_PSM_P_HD_DATA BIT(25) 262 #define BAM_AU_ACCUMED BIT(26) 263 #define BAM_CMD_ENABLE BIT(27) 264 265 #define BAM_CNFG_BITS_DEFAULT (BAM_PIPE_CNFG | \ 266 BAM_NO_EXT_P_RST | \ 267 BAM_IBC_DISABLE | \ 268 BAM_SB_CLK_REQ | \ 269 BAM_PSM_CSW_REQ | \ 270 BAM_PSM_P_RES | \ 271 BAM_AU_P_RES | \ 272 BAM_SI_P_RES | \ 273 BAM_WB_P_RES | \ 274 BAM_WB_BLK_CSW | \ 275 BAM_WB_CSW_ACK_IDL | \ 276 BAM_WB_RETR_SVPNT | \ 277 BAM_WB_DSC_AVL_P_RST | \ 278 BAM_REG_P_EN | \ 279 BAM_PSM_P_HD_DATA | \ 280 BAM_AU_ACCUMED | \ 281 BAM_CMD_ENABLE) 282 283 /* PIPE CTRL */ 284 #define P_EN BIT(1) 285 #define P_DIRECTION BIT(3) 286 #define P_SYS_STRM BIT(4) 287 #define P_SYS_MODE BIT(5) 288 #define P_AUTO_EOB BIT(6) 289 #define P_AUTO_EOB_SEL_SHIFT 7 290 #define P_AUTO_EOB_SEL_512 (0 << P_AUTO_EOB_SEL_SHIFT) 291 #define P_AUTO_EOB_SEL_256 (1 << P_AUTO_EOB_SEL_SHIFT) 292 #define P_AUTO_EOB_SEL_128 (2 << P_AUTO_EOB_SEL_SHIFT) 293 #define P_AUTO_EOB_SEL_64 (3 << P_AUTO_EOB_SEL_SHIFT) 294 #define P_PREFETCH_LIMIT_SHIFT 9 295 #define P_PREFETCH_LIMIT_32 (0 << P_PREFETCH_LIMIT_SHIFT) 296 #define P_PREFETCH_LIMIT_16 (1 << P_PREFETCH_LIMIT_SHIFT) 297 #define P_PREFETCH_LIMIT_4 (2 << P_PREFETCH_LIMIT_SHIFT) 298 #define P_WRITE_NWD BIT(11) 299 #define P_LOCK_GROUP_SHIFT 16 300 #define P_LOCK_GROUP_MASK 0x1F 301 302 /* BAM_DESC_CNT_TRSHLD */ 303 #define CNT_TRSHLD 0xffff 304 #define DEFAULT_CNT_THRSHLD 0x4 305 306 /* BAM_IRQ_SRCS */ 307 #define BAM_IRQ BIT(31) 308 #define P_IRQ 0x7fffffff 309 310 /* BAM_IRQ_SRCS_MSK */ 311 #define BAM_IRQ_MSK BAM_IRQ 312 #define P_IRQ_MSK P_IRQ 313 314 /* BAM_IRQ_STTS */ 315 #define BAM_TIMER_IRQ BIT(4) 316 #define BAM_EMPTY_IRQ BIT(3) 317 #define BAM_ERROR_IRQ BIT(2) 318 #define BAM_HRESP_ERR_IRQ BIT(1) 319 320 /* BAM_IRQ_CLR */ 321 #define BAM_TIMER_CLR BIT(4) 322 #define BAM_EMPTY_CLR BIT(3) 323 #define BAM_ERROR_CLR BIT(2) 324 #define BAM_HRESP_ERR_CLR BIT(1) 325 326 /* BAM_IRQ_EN */ 327 #define BAM_TIMER_EN BIT(4) 328 #define BAM_EMPTY_EN BIT(3) 329 #define BAM_ERROR_EN BIT(2) 330 #define BAM_HRESP_ERR_EN BIT(1) 331 332 /* BAM_P_IRQ_EN */ 333 #define P_PRCSD_DESC_EN BIT(0) 334 #define P_TIMER_EN BIT(1) 335 #define P_WAKE_EN BIT(2) 336 #define P_OUT_OF_DESC_EN BIT(3) 337 #define P_ERR_EN BIT(4) 338 #define P_TRNSFR_END_EN BIT(5) 339 #define P_DEFAULT_IRQS_EN (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN) 340 341 /* BAM_P_SW_OFSTS */ 342 #define P_SW_OFSTS_MASK 0xffff 343 344 #define BAM_DESC_FIFO_SIZE SZ_32K 345 #define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1) 346 #define BAM_FIFO_SIZE (SZ_32K - 8) 347 #define IS_BUSY(chan) (CIRC_SPACE(bchan->tail, bchan->head,\ 348 MAX_DESCRIPTORS + 1) == 0) 349 350 struct bam_chan { 351 struct virt_dma_chan vc; 352 353 struct bam_device *bdev; 354 355 /* configuration from device tree */ 356 u32 id; 357 358 /* runtime configuration */ 359 struct dma_slave_config slave; 360 361 /* fifo storage */ 362 struct bam_desc_hw *fifo_virt; 363 dma_addr_t fifo_phys; 364 365 /* fifo markers */ 366 unsigned short head; /* start of active descriptor entries */ 367 unsigned short tail; /* end of active descriptor entries */ 368 369 unsigned int initialized; /* is the channel hw initialized? */ 370 unsigned int paused; /* is the channel paused? */ 371 unsigned int reconfigure; /* new slave config? */ 372 /* list of descriptors currently processed */ 373 struct list_head desc_list; 374 375 struct list_head node; 376 }; 377 378 static inline struct bam_chan *to_bam_chan(struct dma_chan *common) 379 { 380 return container_of(common, struct bam_chan, vc.chan); 381 } 382 383 struct bam_device { 384 void __iomem *regs; 385 struct device *dev; 386 struct dma_device common; 387 struct bam_chan *channels; 388 u32 num_channels; 389 u32 num_ees; 390 391 /* execution environment ID, from DT */ 392 u32 ee; 393 bool controlled_remotely; 394 bool powered_remotely; 395 u32 active_channels; 396 397 const struct reg_offset_data *layout; 398 399 struct clk *bamclk; 400 int irq; 401 402 /* dma start transaction tasklet */ 403 struct tasklet_struct task; 404 u32 bam_revision; 405 }; 406 407 /** 408 * bam_addr - returns BAM register address 409 * @bdev: bam device 410 * @pipe: pipe instance (ignored when register doesn't have multiple instances) 411 * @reg: register enum 412 */ 413 static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe, 414 enum bam_reg reg) 415 { 416 const struct reg_offset_data r = bdev->layout[reg]; 417 418 return bdev->regs + r.base_offset + 419 r.pipe_mult * pipe + 420 r.evnt_mult * pipe + 421 r.ee_mult * bdev->ee; 422 } 423 424 /** 425 * bam_reset() - reset and initialize BAM registers 426 * @bdev: bam device 427 */ 428 static void bam_reset(struct bam_device *bdev) 429 { 430 u32 val; 431 432 /* s/w reset bam */ 433 /* after reset all pipes are disabled and idle */ 434 val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL)); 435 val |= BAM_SW_RST; 436 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 437 val &= ~BAM_SW_RST; 438 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 439 440 /* make sure previous stores are visible before enabling BAM */ 441 wmb(); 442 443 /* enable bam */ 444 val |= BAM_EN; 445 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 446 447 /* set descriptor threshold, start with 4 bytes */ 448 if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START, 449 BAM_NDP_REVISION_END)) 450 writel_relaxed(DEFAULT_CNT_THRSHLD, 451 bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD)); 452 453 /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */ 454 writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS)); 455 456 /* enable irqs for errors */ 457 writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN, 458 bam_addr(bdev, 0, BAM_IRQ_EN)); 459 460 /* unmask global bam interrupt */ 461 writel_relaxed(BAM_IRQ_MSK, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 462 } 463 464 /** 465 * bam_reset_channel - Reset individual BAM DMA channel 466 * @bchan: bam channel 467 * 468 * This function resets a specific BAM channel 469 */ 470 static void bam_reset_channel(struct bam_chan *bchan) 471 { 472 struct bam_device *bdev = bchan->bdev; 473 474 lockdep_assert_held(&bchan->vc.lock); 475 476 /* reset channel */ 477 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_RST)); 478 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_RST)); 479 480 /* don't allow cpu to reorder BAM register accesses done after this */ 481 wmb(); 482 483 /* make sure hw is initialized when channel is used the first time */ 484 bchan->initialized = 0; 485 } 486 487 /** 488 * bam_chan_init_hw - Initialize channel hardware 489 * @bchan: bam channel 490 * @dir: DMA transfer direction 491 * 492 * This function resets and initializes the BAM channel 493 */ 494 static void bam_chan_init_hw(struct bam_chan *bchan, 495 enum dma_transfer_direction dir) 496 { 497 struct bam_device *bdev = bchan->bdev; 498 u32 val; 499 500 /* Reset the channel to clear internal state of the FIFO */ 501 bam_reset_channel(bchan); 502 503 /* 504 * write out 8 byte aligned address. We have enough space for this 505 * because we allocated 1 more descriptor (8 bytes) than we can use 506 */ 507 writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)), 508 bam_addr(bdev, bchan->id, BAM_P_DESC_FIFO_ADDR)); 509 writel_relaxed(BAM_FIFO_SIZE, 510 bam_addr(bdev, bchan->id, BAM_P_FIFO_SIZES)); 511 512 /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */ 513 writel_relaxed(P_DEFAULT_IRQS_EN, 514 bam_addr(bdev, bchan->id, BAM_P_IRQ_EN)); 515 516 /* unmask the specific pipe and EE combo */ 517 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 518 val |= BIT(bchan->id); 519 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 520 521 /* don't allow cpu to reorder the channel enable done below */ 522 wmb(); 523 524 /* set fixed direction and mode, then enable channel */ 525 val = P_EN | P_SYS_MODE; 526 if (dir == DMA_DEV_TO_MEM) 527 val |= P_DIRECTION; 528 529 writel_relaxed(val, bam_addr(bdev, bchan->id, BAM_P_CTRL)); 530 531 bchan->initialized = 1; 532 533 /* init FIFO pointers */ 534 bchan->head = 0; 535 bchan->tail = 0; 536 } 537 538 /** 539 * bam_alloc_chan - Allocate channel resources for DMA channel. 540 * @chan: specified channel 541 * 542 * This function allocates the FIFO descriptor memory 543 */ 544 static int bam_alloc_chan(struct dma_chan *chan) 545 { 546 struct bam_chan *bchan = to_bam_chan(chan); 547 struct bam_device *bdev = bchan->bdev; 548 549 if (bchan->fifo_virt) 550 return 0; 551 552 /* allocate FIFO descriptor space, but only if necessary */ 553 bchan->fifo_virt = dma_alloc_wc(bdev->dev, BAM_DESC_FIFO_SIZE, 554 &bchan->fifo_phys, GFP_KERNEL); 555 556 if (!bchan->fifo_virt) { 557 dev_err(bdev->dev, "Failed to allocate desc fifo\n"); 558 return -ENOMEM; 559 } 560 561 if (bdev->active_channels++ == 0 && bdev->powered_remotely) 562 bam_reset(bdev); 563 564 return 0; 565 } 566 567 /** 568 * bam_free_chan - Frees dma resources associated with specific channel 569 * @chan: specified channel 570 * 571 * Free the allocated fifo descriptor memory and channel resources 572 * 573 */ 574 static void bam_free_chan(struct dma_chan *chan) 575 { 576 struct bam_chan *bchan = to_bam_chan(chan); 577 struct bam_device *bdev = bchan->bdev; 578 u32 val; 579 unsigned long flags; 580 int ret; 581 582 ret = pm_runtime_get_sync(bdev->dev); 583 if (ret < 0) 584 return; 585 586 vchan_free_chan_resources(to_virt_chan(chan)); 587 588 if (!list_empty(&bchan->desc_list)) { 589 dev_err(bchan->bdev->dev, "Cannot free busy channel\n"); 590 goto err; 591 } 592 593 spin_lock_irqsave(&bchan->vc.lock, flags); 594 bam_reset_channel(bchan); 595 spin_unlock_irqrestore(&bchan->vc.lock, flags); 596 597 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt, 598 bchan->fifo_phys); 599 bchan->fifo_virt = NULL; 600 601 /* mask irq for pipe/channel */ 602 val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 603 val &= ~BIT(bchan->id); 604 writel_relaxed(val, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 605 606 /* disable irq */ 607 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN)); 608 609 if (--bdev->active_channels == 0 && bdev->powered_remotely) { 610 /* s/w reset bam */ 611 val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL)); 612 val |= BAM_SW_RST; 613 writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL)); 614 } 615 616 err: 617 pm_runtime_mark_last_busy(bdev->dev); 618 pm_runtime_put_autosuspend(bdev->dev); 619 } 620 621 /** 622 * bam_slave_config - set slave configuration for channel 623 * @chan: dma channel 624 * @cfg: slave configuration 625 * 626 * Sets slave configuration for channel 627 * 628 */ 629 static int bam_slave_config(struct dma_chan *chan, 630 struct dma_slave_config *cfg) 631 { 632 struct bam_chan *bchan = to_bam_chan(chan); 633 unsigned long flag; 634 635 spin_lock_irqsave(&bchan->vc.lock, flag); 636 memcpy(&bchan->slave, cfg, sizeof(*cfg)); 637 bchan->reconfigure = 1; 638 spin_unlock_irqrestore(&bchan->vc.lock, flag); 639 640 return 0; 641 } 642 643 /** 644 * bam_prep_slave_sg - Prep slave sg transaction 645 * 646 * @chan: dma channel 647 * @sgl: scatter gather list 648 * @sg_len: length of sg 649 * @direction: DMA transfer direction 650 * @flags: DMA flags 651 * @context: transfer context (unused) 652 */ 653 static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, 654 struct scatterlist *sgl, unsigned int sg_len, 655 enum dma_transfer_direction direction, unsigned long flags, 656 void *context) 657 { 658 struct bam_chan *bchan = to_bam_chan(chan); 659 struct bam_device *bdev = bchan->bdev; 660 struct bam_async_desc *async_desc; 661 struct scatterlist *sg; 662 u32 i; 663 struct bam_desc_hw *desc; 664 unsigned int num_alloc = 0; 665 666 667 if (!is_slave_direction(direction)) { 668 dev_err(bdev->dev, "invalid dma direction\n"); 669 return NULL; 670 } 671 672 /* calculate number of required entries */ 673 for_each_sg(sgl, sg, sg_len, i) 674 num_alloc += DIV_ROUND_UP(sg_dma_len(sg), BAM_FIFO_SIZE); 675 676 /* allocate enough room to accommodate the number of entries */ 677 async_desc = kzalloc(struct_size(async_desc, desc, num_alloc), 678 GFP_NOWAIT); 679 680 if (!async_desc) 681 return NULL; 682 683 if (flags & DMA_PREP_FENCE) 684 async_desc->flags |= DESC_FLAG_NWD; 685 686 if (flags & DMA_PREP_INTERRUPT) 687 async_desc->flags |= DESC_FLAG_EOT; 688 689 async_desc->num_desc = num_alloc; 690 async_desc->curr_desc = async_desc->desc; 691 async_desc->dir = direction; 692 693 /* fill in temporary descriptors */ 694 desc = async_desc->desc; 695 for_each_sg(sgl, sg, sg_len, i) { 696 unsigned int remainder = sg_dma_len(sg); 697 unsigned int curr_offset = 0; 698 699 do { 700 if (flags & DMA_PREP_CMD) 701 desc->flags |= cpu_to_le16(DESC_FLAG_CMD); 702 703 desc->addr = cpu_to_le32(sg_dma_address(sg) + 704 curr_offset); 705 706 if (remainder > BAM_FIFO_SIZE) { 707 desc->size = cpu_to_le16(BAM_FIFO_SIZE); 708 remainder -= BAM_FIFO_SIZE; 709 curr_offset += BAM_FIFO_SIZE; 710 } else { 711 desc->size = cpu_to_le16(remainder); 712 remainder = 0; 713 } 714 715 async_desc->length += le16_to_cpu(desc->size); 716 desc++; 717 } while (remainder > 0); 718 } 719 720 return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags); 721 } 722 723 /** 724 * bam_dma_terminate_all - terminate all transactions on a channel 725 * @chan: bam dma channel 726 * 727 * Dequeues and frees all transactions 728 * No callbacks are done 729 * 730 */ 731 static int bam_dma_terminate_all(struct dma_chan *chan) 732 { 733 struct bam_chan *bchan = to_bam_chan(chan); 734 struct bam_async_desc *async_desc, *tmp; 735 unsigned long flag; 736 LIST_HEAD(head); 737 738 /* remove all transactions, including active transaction */ 739 spin_lock_irqsave(&bchan->vc.lock, flag); 740 /* 741 * If we have transactions queued, then some might be committed to the 742 * hardware in the desc fifo. The only way to reset the desc fifo is 743 * to do a hardware reset (either by pipe or the entire block). 744 * bam_chan_init_hw() will trigger a pipe reset, and also reinit the 745 * pipe. If the pipe is left disabled (default state after pipe reset) 746 * and is accessed by a connected hardware engine, a fatal error in 747 * the BAM will occur. There is a small window where this could happen 748 * with bam_chan_init_hw(), but it is assumed that the caller has 749 * stopped activity on any attached hardware engine. Make sure to do 750 * this first so that the BAM hardware doesn't cause memory corruption 751 * by accessing freed resources. 752 */ 753 if (!list_empty(&bchan->desc_list)) { 754 async_desc = list_first_entry(&bchan->desc_list, 755 struct bam_async_desc, desc_node); 756 bam_chan_init_hw(bchan, async_desc->dir); 757 } 758 759 list_for_each_entry_safe(async_desc, tmp, 760 &bchan->desc_list, desc_node) { 761 list_add(&async_desc->vd.node, &bchan->vc.desc_issued); 762 list_del(&async_desc->desc_node); 763 } 764 765 vchan_get_all_descriptors(&bchan->vc, &head); 766 spin_unlock_irqrestore(&bchan->vc.lock, flag); 767 768 vchan_dma_desc_free_list(&bchan->vc, &head); 769 770 return 0; 771 } 772 773 /** 774 * bam_pause - Pause DMA channel 775 * @chan: dma channel 776 * 777 */ 778 static int bam_pause(struct dma_chan *chan) 779 { 780 struct bam_chan *bchan = to_bam_chan(chan); 781 struct bam_device *bdev = bchan->bdev; 782 unsigned long flag; 783 int ret; 784 785 ret = pm_runtime_get_sync(bdev->dev); 786 if (ret < 0) 787 return ret; 788 789 spin_lock_irqsave(&bchan->vc.lock, flag); 790 writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT)); 791 bchan->paused = 1; 792 spin_unlock_irqrestore(&bchan->vc.lock, flag); 793 pm_runtime_mark_last_busy(bdev->dev); 794 pm_runtime_put_autosuspend(bdev->dev); 795 796 return 0; 797 } 798 799 /** 800 * bam_resume - Resume DMA channel operations 801 * @chan: dma channel 802 * 803 */ 804 static int bam_resume(struct dma_chan *chan) 805 { 806 struct bam_chan *bchan = to_bam_chan(chan); 807 struct bam_device *bdev = bchan->bdev; 808 unsigned long flag; 809 int ret; 810 811 ret = pm_runtime_get_sync(bdev->dev); 812 if (ret < 0) 813 return ret; 814 815 spin_lock_irqsave(&bchan->vc.lock, flag); 816 writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT)); 817 bchan->paused = 0; 818 spin_unlock_irqrestore(&bchan->vc.lock, flag); 819 pm_runtime_mark_last_busy(bdev->dev); 820 pm_runtime_put_autosuspend(bdev->dev); 821 822 return 0; 823 } 824 825 /** 826 * process_channel_irqs - processes the channel interrupts 827 * @bdev: bam controller 828 * 829 * This function processes the channel interrupts 830 * 831 */ 832 static u32 process_channel_irqs(struct bam_device *bdev) 833 { 834 u32 i, srcs, pipe_stts, offset, avail; 835 unsigned long flags; 836 struct bam_async_desc *async_desc, *tmp; 837 838 srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE)); 839 840 /* return early if no pipe/channel interrupts are present */ 841 if (!(srcs & P_IRQ)) 842 return srcs; 843 844 for (i = 0; i < bdev->num_channels; i++) { 845 struct bam_chan *bchan = &bdev->channels[i]; 846 847 if (!(srcs & BIT(i))) 848 continue; 849 850 /* clear pipe irq */ 851 pipe_stts = readl_relaxed(bam_addr(bdev, i, BAM_P_IRQ_STTS)); 852 853 writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR)); 854 855 spin_lock_irqsave(&bchan->vc.lock, flags); 856 857 offset = readl_relaxed(bam_addr(bdev, i, BAM_P_SW_OFSTS)) & 858 P_SW_OFSTS_MASK; 859 offset /= sizeof(struct bam_desc_hw); 860 861 /* Number of bytes available to read */ 862 avail = CIRC_CNT(offset, bchan->head, MAX_DESCRIPTORS + 1); 863 864 if (offset < bchan->head) 865 avail--; 866 867 list_for_each_entry_safe(async_desc, tmp, 868 &bchan->desc_list, desc_node) { 869 /* Not enough data to read */ 870 if (avail < async_desc->xfer_len) 871 break; 872 873 /* manage FIFO */ 874 bchan->head += async_desc->xfer_len; 875 bchan->head %= MAX_DESCRIPTORS; 876 877 async_desc->num_desc -= async_desc->xfer_len; 878 async_desc->curr_desc += async_desc->xfer_len; 879 avail -= async_desc->xfer_len; 880 881 /* 882 * if complete, process cookie. Otherwise 883 * push back to front of desc_issued so that 884 * it gets restarted by the tasklet 885 */ 886 if (!async_desc->num_desc) { 887 vchan_cookie_complete(&async_desc->vd); 888 } else { 889 list_add(&async_desc->vd.node, 890 &bchan->vc.desc_issued); 891 } 892 list_del(&async_desc->desc_node); 893 } 894 895 spin_unlock_irqrestore(&bchan->vc.lock, flags); 896 } 897 898 return srcs; 899 } 900 901 /** 902 * bam_dma_irq - irq handler for bam controller 903 * @irq: IRQ of interrupt 904 * @data: callback data 905 * 906 * IRQ handler for the bam controller 907 */ 908 static irqreturn_t bam_dma_irq(int irq, void *data) 909 { 910 struct bam_device *bdev = data; 911 u32 clr_mask = 0, srcs = 0; 912 int ret; 913 914 srcs |= process_channel_irqs(bdev); 915 916 /* kick off tasklet to start next dma transfer */ 917 if (srcs & P_IRQ) 918 tasklet_schedule(&bdev->task); 919 920 ret = pm_runtime_get_sync(bdev->dev); 921 if (ret < 0) 922 return IRQ_NONE; 923 924 if (srcs & BAM_IRQ) { 925 clr_mask = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_STTS)); 926 927 /* 928 * don't allow reorder of the various accesses to the BAM 929 * registers 930 */ 931 mb(); 932 933 writel_relaxed(clr_mask, bam_addr(bdev, 0, BAM_IRQ_CLR)); 934 } 935 936 pm_runtime_mark_last_busy(bdev->dev); 937 pm_runtime_put_autosuspend(bdev->dev); 938 939 return IRQ_HANDLED; 940 } 941 942 /** 943 * bam_tx_status - returns status of transaction 944 * @chan: dma channel 945 * @cookie: transaction cookie 946 * @txstate: DMA transaction state 947 * 948 * Return status of dma transaction 949 */ 950 static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 951 struct dma_tx_state *txstate) 952 { 953 struct bam_chan *bchan = to_bam_chan(chan); 954 struct bam_async_desc *async_desc; 955 struct virt_dma_desc *vd; 956 int ret; 957 size_t residue = 0; 958 unsigned int i; 959 unsigned long flags; 960 961 ret = dma_cookie_status(chan, cookie, txstate); 962 if (ret == DMA_COMPLETE) 963 return ret; 964 965 if (!txstate) 966 return bchan->paused ? DMA_PAUSED : ret; 967 968 spin_lock_irqsave(&bchan->vc.lock, flags); 969 vd = vchan_find_desc(&bchan->vc, cookie); 970 if (vd) { 971 residue = container_of(vd, struct bam_async_desc, vd)->length; 972 } else { 973 list_for_each_entry(async_desc, &bchan->desc_list, desc_node) { 974 if (async_desc->vd.tx.cookie != cookie) 975 continue; 976 977 for (i = 0; i < async_desc->num_desc; i++) 978 residue += le16_to_cpu( 979 async_desc->curr_desc[i].size); 980 } 981 } 982 983 spin_unlock_irqrestore(&bchan->vc.lock, flags); 984 985 dma_set_residue(txstate, residue); 986 987 if (ret == DMA_IN_PROGRESS && bchan->paused) 988 ret = DMA_PAUSED; 989 990 return ret; 991 } 992 993 /** 994 * bam_apply_new_config 995 * @bchan: bam dma channel 996 * @dir: DMA direction 997 */ 998 static void bam_apply_new_config(struct bam_chan *bchan, 999 enum dma_transfer_direction dir) 1000 { 1001 struct bam_device *bdev = bchan->bdev; 1002 u32 maxburst; 1003 1004 if (!bdev->controlled_remotely) { 1005 if (dir == DMA_DEV_TO_MEM) 1006 maxburst = bchan->slave.src_maxburst; 1007 else 1008 maxburst = bchan->slave.dst_maxburst; 1009 if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START, 1010 BAM_NDP_REVISION_END)) 1011 writel_relaxed(maxburst, 1012 bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD)); 1013 } 1014 1015 bchan->reconfigure = 0; 1016 } 1017 1018 /** 1019 * bam_start_dma - start next transaction 1020 * @bchan: bam dma channel 1021 */ 1022 static void bam_start_dma(struct bam_chan *bchan) 1023 { 1024 struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc); 1025 struct bam_device *bdev = bchan->bdev; 1026 struct bam_async_desc *async_desc = NULL; 1027 struct bam_desc_hw *desc; 1028 struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt, 1029 sizeof(struct bam_desc_hw)); 1030 int ret; 1031 unsigned int avail; 1032 struct dmaengine_desc_callback cb; 1033 1034 lockdep_assert_held(&bchan->vc.lock); 1035 1036 if (!vd) 1037 return; 1038 1039 ret = pm_runtime_get_sync(bdev->dev); 1040 if (ret < 0) 1041 return; 1042 1043 while (vd && !IS_BUSY(bchan)) { 1044 list_del(&vd->node); 1045 1046 async_desc = container_of(vd, struct bam_async_desc, vd); 1047 1048 /* on first use, initialize the channel hardware */ 1049 if (!bchan->initialized) 1050 bam_chan_init_hw(bchan, async_desc->dir); 1051 1052 /* apply new slave config changes, if necessary */ 1053 if (bchan->reconfigure) 1054 bam_apply_new_config(bchan, async_desc->dir); 1055 1056 desc = async_desc->curr_desc; 1057 avail = CIRC_SPACE(bchan->tail, bchan->head, 1058 MAX_DESCRIPTORS + 1); 1059 1060 if (async_desc->num_desc > avail) 1061 async_desc->xfer_len = avail; 1062 else 1063 async_desc->xfer_len = async_desc->num_desc; 1064 1065 /* set any special flags on the last descriptor */ 1066 if (async_desc->num_desc == async_desc->xfer_len) 1067 desc[async_desc->xfer_len - 1].flags |= 1068 cpu_to_le16(async_desc->flags); 1069 1070 vd = vchan_next_desc(&bchan->vc); 1071 1072 dmaengine_desc_get_callback(&async_desc->vd.tx, &cb); 1073 1074 /* 1075 * An interrupt is generated at this desc, if 1076 * - FIFO is FULL. 1077 * - No more descriptors to add. 1078 * - If a callback completion was requested for this DESC, 1079 * In this case, BAM will deliver the completion callback 1080 * for this desc and continue processing the next desc. 1081 */ 1082 if (((avail <= async_desc->xfer_len) || !vd || 1083 dmaengine_desc_callback_valid(&cb)) && 1084 !(async_desc->flags & DESC_FLAG_EOT)) 1085 desc[async_desc->xfer_len - 1].flags |= 1086 cpu_to_le16(DESC_FLAG_INT); 1087 1088 if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) { 1089 u32 partial = MAX_DESCRIPTORS - bchan->tail; 1090 1091 memcpy(&fifo[bchan->tail], desc, 1092 partial * sizeof(struct bam_desc_hw)); 1093 memcpy(fifo, &desc[partial], 1094 (async_desc->xfer_len - partial) * 1095 sizeof(struct bam_desc_hw)); 1096 } else { 1097 memcpy(&fifo[bchan->tail], desc, 1098 async_desc->xfer_len * 1099 sizeof(struct bam_desc_hw)); 1100 } 1101 1102 bchan->tail += async_desc->xfer_len; 1103 bchan->tail %= MAX_DESCRIPTORS; 1104 list_add_tail(&async_desc->desc_node, &bchan->desc_list); 1105 } 1106 1107 /* ensure descriptor writes and dma start not reordered */ 1108 wmb(); 1109 writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw), 1110 bam_addr(bdev, bchan->id, BAM_P_EVNT_REG)); 1111 1112 pm_runtime_mark_last_busy(bdev->dev); 1113 pm_runtime_put_autosuspend(bdev->dev); 1114 } 1115 1116 /** 1117 * dma_tasklet - DMA IRQ tasklet 1118 * @t: tasklet argument (bam controller structure) 1119 * 1120 * Sets up next DMA operation and then processes all completed transactions 1121 */ 1122 static void dma_tasklet(struct tasklet_struct *t) 1123 { 1124 struct bam_device *bdev = from_tasklet(bdev, t, task); 1125 struct bam_chan *bchan; 1126 unsigned long flags; 1127 unsigned int i; 1128 1129 /* go through the channels and kick off transactions */ 1130 for (i = 0; i < bdev->num_channels; i++) { 1131 bchan = &bdev->channels[i]; 1132 spin_lock_irqsave(&bchan->vc.lock, flags); 1133 1134 if (!list_empty(&bchan->vc.desc_issued) && !IS_BUSY(bchan)) 1135 bam_start_dma(bchan); 1136 spin_unlock_irqrestore(&bchan->vc.lock, flags); 1137 } 1138 1139 } 1140 1141 /** 1142 * bam_issue_pending - starts pending transactions 1143 * @chan: dma channel 1144 * 1145 * Calls tasklet directly which in turn starts any pending transactions 1146 */ 1147 static void bam_issue_pending(struct dma_chan *chan) 1148 { 1149 struct bam_chan *bchan = to_bam_chan(chan); 1150 unsigned long flags; 1151 1152 spin_lock_irqsave(&bchan->vc.lock, flags); 1153 1154 /* if work pending and idle, start a transaction */ 1155 if (vchan_issue_pending(&bchan->vc) && !IS_BUSY(bchan)) 1156 bam_start_dma(bchan); 1157 1158 spin_unlock_irqrestore(&bchan->vc.lock, flags); 1159 } 1160 1161 /** 1162 * bam_dma_free_desc - free descriptor memory 1163 * @vd: virtual descriptor 1164 * 1165 */ 1166 static void bam_dma_free_desc(struct virt_dma_desc *vd) 1167 { 1168 struct bam_async_desc *async_desc = container_of(vd, 1169 struct bam_async_desc, vd); 1170 1171 kfree(async_desc); 1172 } 1173 1174 static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec, 1175 struct of_dma *of) 1176 { 1177 struct bam_device *bdev = container_of(of->of_dma_data, 1178 struct bam_device, common); 1179 unsigned int request; 1180 1181 if (dma_spec->args_count != 1) 1182 return NULL; 1183 1184 request = dma_spec->args[0]; 1185 if (request >= bdev->num_channels) 1186 return NULL; 1187 1188 return dma_get_slave_channel(&(bdev->channels[request].vc.chan)); 1189 } 1190 1191 /** 1192 * bam_init 1193 * @bdev: bam device 1194 * 1195 * Initialization helper for global bam registers 1196 */ 1197 static int bam_init(struct bam_device *bdev) 1198 { 1199 u32 val; 1200 1201 /* read revision and configuration information */ 1202 val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION)); 1203 if (!bdev->num_ees) 1204 bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK; 1205 1206 bdev->bam_revision = val & REVISION_MASK; 1207 1208 /* check that configured EE is within range */ 1209 if (bdev->ee >= bdev->num_ees) 1210 return -EINVAL; 1211 1212 if (!bdev->num_channels) { 1213 val = readl_relaxed(bam_addr(bdev, 0, BAM_NUM_PIPES)); 1214 bdev->num_channels = val & BAM_NUM_PIPES_MASK; 1215 } 1216 1217 /* Reset BAM now if fully controlled locally */ 1218 if (!bdev->controlled_remotely && !bdev->powered_remotely) 1219 bam_reset(bdev); 1220 1221 return 0; 1222 } 1223 1224 static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan, 1225 u32 index) 1226 { 1227 bchan->id = index; 1228 bchan->bdev = bdev; 1229 1230 vchan_init(&bchan->vc, &bdev->common); 1231 bchan->vc.desc_free = bam_dma_free_desc; 1232 INIT_LIST_HEAD(&bchan->desc_list); 1233 } 1234 1235 static const struct of_device_id bam_of_match[] = { 1236 { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info }, 1237 { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info }, 1238 { .compatible = "qcom,bam-v1.7.0", .data = &bam_v1_7_reg_info }, 1239 {} 1240 }; 1241 1242 MODULE_DEVICE_TABLE(of, bam_of_match); 1243 1244 static int bam_dma_probe(struct platform_device *pdev) 1245 { 1246 struct bam_device *bdev; 1247 const struct of_device_id *match; 1248 int ret, i; 1249 1250 bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL); 1251 if (!bdev) 1252 return -ENOMEM; 1253 1254 bdev->dev = &pdev->dev; 1255 1256 match = of_match_node(bam_of_match, pdev->dev.of_node); 1257 if (!match) { 1258 dev_err(&pdev->dev, "Unsupported BAM module\n"); 1259 return -ENODEV; 1260 } 1261 1262 bdev->layout = match->data; 1263 1264 bdev->regs = devm_platform_ioremap_resource(pdev, 0); 1265 if (IS_ERR(bdev->regs)) 1266 return PTR_ERR(bdev->regs); 1267 1268 bdev->irq = platform_get_irq(pdev, 0); 1269 if (bdev->irq < 0) 1270 return bdev->irq; 1271 1272 ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee); 1273 if (ret) { 1274 dev_err(bdev->dev, "Execution environment unspecified\n"); 1275 return ret; 1276 } 1277 1278 bdev->controlled_remotely = of_property_read_bool(pdev->dev.of_node, 1279 "qcom,controlled-remotely"); 1280 bdev->powered_remotely = of_property_read_bool(pdev->dev.of_node, 1281 "qcom,powered-remotely"); 1282 1283 if (bdev->controlled_remotely || bdev->powered_remotely) 1284 bdev->bamclk = devm_clk_get_optional(bdev->dev, "bam_clk"); 1285 else 1286 bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk"); 1287 1288 if (IS_ERR(bdev->bamclk)) 1289 return PTR_ERR(bdev->bamclk); 1290 1291 if (!bdev->bamclk) { 1292 ret = of_property_read_u32(pdev->dev.of_node, "num-channels", 1293 &bdev->num_channels); 1294 if (ret) 1295 dev_err(bdev->dev, "num-channels unspecified in dt\n"); 1296 1297 ret = of_property_read_u32(pdev->dev.of_node, "qcom,num-ees", 1298 &bdev->num_ees); 1299 if (ret) 1300 dev_err(bdev->dev, "num-ees unspecified in dt\n"); 1301 } 1302 1303 ret = clk_prepare_enable(bdev->bamclk); 1304 if (ret) { 1305 dev_err(bdev->dev, "failed to prepare/enable clock\n"); 1306 return ret; 1307 } 1308 1309 ret = bam_init(bdev); 1310 if (ret) 1311 goto err_disable_clk; 1312 1313 tasklet_setup(&bdev->task, dma_tasklet); 1314 1315 bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels, 1316 sizeof(*bdev->channels), GFP_KERNEL); 1317 1318 if (!bdev->channels) { 1319 ret = -ENOMEM; 1320 goto err_tasklet_kill; 1321 } 1322 1323 /* allocate and initialize channels */ 1324 INIT_LIST_HEAD(&bdev->common.channels); 1325 1326 for (i = 0; i < bdev->num_channels; i++) 1327 bam_channel_init(bdev, &bdev->channels[i], i); 1328 1329 ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq, 1330 IRQF_TRIGGER_HIGH, "bam_dma", bdev); 1331 if (ret) 1332 goto err_bam_channel_exit; 1333 1334 /* set max dma segment size */ 1335 bdev->common.dev = bdev->dev; 1336 dma_set_max_seg_size(bdev->common.dev, BAM_FIFO_SIZE); 1337 1338 platform_set_drvdata(pdev, bdev); 1339 1340 /* set capabilities */ 1341 dma_cap_zero(bdev->common.cap_mask); 1342 dma_cap_set(DMA_SLAVE, bdev->common.cap_mask); 1343 1344 /* initialize dmaengine apis */ 1345 bdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 1346 bdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 1347 bdev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; 1348 bdev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES; 1349 bdev->common.device_alloc_chan_resources = bam_alloc_chan; 1350 bdev->common.device_free_chan_resources = bam_free_chan; 1351 bdev->common.device_prep_slave_sg = bam_prep_slave_sg; 1352 bdev->common.device_config = bam_slave_config; 1353 bdev->common.device_pause = bam_pause; 1354 bdev->common.device_resume = bam_resume; 1355 bdev->common.device_terminate_all = bam_dma_terminate_all; 1356 bdev->common.device_issue_pending = bam_issue_pending; 1357 bdev->common.device_tx_status = bam_tx_status; 1358 bdev->common.dev = bdev->dev; 1359 1360 ret = dma_async_device_register(&bdev->common); 1361 if (ret) { 1362 dev_err(bdev->dev, "failed to register dma async device\n"); 1363 goto err_bam_channel_exit; 1364 } 1365 1366 ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate, 1367 &bdev->common); 1368 if (ret) 1369 goto err_unregister_dma; 1370 1371 pm_runtime_irq_safe(&pdev->dev); 1372 pm_runtime_set_autosuspend_delay(&pdev->dev, BAM_DMA_AUTOSUSPEND_DELAY); 1373 pm_runtime_use_autosuspend(&pdev->dev); 1374 pm_runtime_mark_last_busy(&pdev->dev); 1375 pm_runtime_set_active(&pdev->dev); 1376 pm_runtime_enable(&pdev->dev); 1377 1378 return 0; 1379 1380 err_unregister_dma: 1381 dma_async_device_unregister(&bdev->common); 1382 err_bam_channel_exit: 1383 for (i = 0; i < bdev->num_channels; i++) 1384 tasklet_kill(&bdev->channels[i].vc.task); 1385 err_tasklet_kill: 1386 tasklet_kill(&bdev->task); 1387 err_disable_clk: 1388 clk_disable_unprepare(bdev->bamclk); 1389 1390 return ret; 1391 } 1392 1393 static void bam_dma_remove(struct platform_device *pdev) 1394 { 1395 struct bam_device *bdev = platform_get_drvdata(pdev); 1396 u32 i; 1397 1398 pm_runtime_force_suspend(&pdev->dev); 1399 1400 of_dma_controller_free(pdev->dev.of_node); 1401 dma_async_device_unregister(&bdev->common); 1402 1403 /* mask all interrupts for this execution environment */ 1404 writel_relaxed(0, bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); 1405 1406 devm_free_irq(bdev->dev, bdev->irq, bdev); 1407 1408 for (i = 0; i < bdev->num_channels; i++) { 1409 bam_dma_terminate_all(&bdev->channels[i].vc.chan); 1410 tasklet_kill(&bdev->channels[i].vc.task); 1411 1412 if (!bdev->channels[i].fifo_virt) 1413 continue; 1414 1415 dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, 1416 bdev->channels[i].fifo_virt, 1417 bdev->channels[i].fifo_phys); 1418 } 1419 1420 tasklet_kill(&bdev->task); 1421 1422 clk_disable_unprepare(bdev->bamclk); 1423 } 1424 1425 static int __maybe_unused bam_dma_runtime_suspend(struct device *dev) 1426 { 1427 struct bam_device *bdev = dev_get_drvdata(dev); 1428 1429 clk_disable(bdev->bamclk); 1430 1431 return 0; 1432 } 1433 1434 static int __maybe_unused bam_dma_runtime_resume(struct device *dev) 1435 { 1436 struct bam_device *bdev = dev_get_drvdata(dev); 1437 int ret; 1438 1439 ret = clk_enable(bdev->bamclk); 1440 if (ret < 0) { 1441 dev_err(dev, "clk_enable failed: %d\n", ret); 1442 return ret; 1443 } 1444 1445 return 0; 1446 } 1447 1448 static int __maybe_unused bam_dma_suspend(struct device *dev) 1449 { 1450 struct bam_device *bdev = dev_get_drvdata(dev); 1451 1452 pm_runtime_force_suspend(dev); 1453 clk_unprepare(bdev->bamclk); 1454 1455 return 0; 1456 } 1457 1458 static int __maybe_unused bam_dma_resume(struct device *dev) 1459 { 1460 struct bam_device *bdev = dev_get_drvdata(dev); 1461 int ret; 1462 1463 ret = clk_prepare(bdev->bamclk); 1464 if (ret) 1465 return ret; 1466 1467 pm_runtime_force_resume(dev); 1468 1469 return 0; 1470 } 1471 1472 static const struct dev_pm_ops bam_dma_pm_ops = { 1473 SET_LATE_SYSTEM_SLEEP_PM_OPS(bam_dma_suspend, bam_dma_resume) 1474 SET_RUNTIME_PM_OPS(bam_dma_runtime_suspend, bam_dma_runtime_resume, 1475 NULL) 1476 }; 1477 1478 static struct platform_driver bam_dma_driver = { 1479 .probe = bam_dma_probe, 1480 .remove = bam_dma_remove, 1481 .driver = { 1482 .name = "bam-dma-engine", 1483 .pm = &bam_dma_pm_ops, 1484 .of_match_table = bam_of_match, 1485 }, 1486 }; 1487 1488 module_platform_driver(bam_dma_driver); 1489 1490 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>"); 1491 MODULE_DESCRIPTION("QCOM BAM DMA engine driver"); 1492 MODULE_LICENSE("GPL v2"); 1493