1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright 2015 Robert Jarzmik <robert.jarzmik@free.fr> 4 */ 5 6 #include <linux/err.h> 7 #include <linux/module.h> 8 #include <linux/init.h> 9 #include <linux/types.h> 10 #include <linux/interrupt.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/slab.h> 13 #include <linux/string_choices.h> 14 #include <linux/dmaengine.h> 15 #include <linux/platform_device.h> 16 #include <linux/device.h> 17 #include <linux/platform_data/mmp_dma.h> 18 #include <linux/dmapool.h> 19 #include <linux/of.h> 20 #include <linux/of_dma.h> 21 #include <linux/wait.h> 22 #include <linux/dma/pxa-dma.h> 23 24 #include "dmaengine.h" 25 #include "virt-dma.h" 26 27 #define DCSR(n) (0x0000 + ((n) << 2)) 28 #define DALGN(n) 0x00a0 29 #define DINT 0x00f0 30 #define DDADR(n) (0x0200 + ((n) << 4)) 31 #define DSADR(n) (0x0204 + ((n) << 4)) 32 #define DTADR(n) (0x0208 + ((n) << 4)) 33 #define DCMD(n) (0x020c + ((n) << 4)) 34 35 #define PXA_DCSR_RUN BIT(31) /* Run Bit (read / write) */ 36 #define PXA_DCSR_NODESC BIT(30) /* No-Descriptor Fetch (read / write) */ 37 #define PXA_DCSR_STOPIRQEN BIT(29) /* Stop Interrupt Enable (R/W) */ 38 #define PXA_DCSR_REQPEND BIT(8) /* Request Pending (read-only) */ 39 #define PXA_DCSR_STOPSTATE BIT(3) /* Stop State (read-only) */ 40 #define PXA_DCSR_ENDINTR BIT(2) /* End Interrupt (read / write) */ 41 #define PXA_DCSR_STARTINTR BIT(1) /* Start Interrupt (read / write) */ 42 #define PXA_DCSR_BUSERR BIT(0) /* Bus Error Interrupt (read / write) */ 43 44 #define PXA_DCSR_EORIRQEN BIT(28) /* End of Receive IRQ Enable (R/W) */ 45 #define PXA_DCSR_EORJMPEN BIT(27) /* Jump to next descriptor on EOR */ 46 #define PXA_DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ 47 #define PXA_DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ 48 #define PXA_DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ 49 #define PXA_DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ 50 #define PXA_DCSR_EORINTR BIT(9) /* The end of Receive */ 51 52 #define DRCMR_MAPVLD BIT(7) /* Map Valid (read / write) */ 53 #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ 54 55 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ 56 #define DDADR_STOP BIT(0) /* Stop (read / write) */ 57 58 #define PXA_DCMD_INCSRCADDR BIT(31) /* Source Address Increment Setting. */ 59 #define PXA_DCMD_INCTRGADDR BIT(30) /* Target Address Increment Setting. */ 60 #define PXA_DCMD_FLOWSRC BIT(29) /* Flow Control by the source. */ 61 #define PXA_DCMD_FLOWTRG BIT(28) /* Flow Control by the target. */ 62 #define PXA_DCMD_STARTIRQEN BIT(22) /* Start Interrupt Enable */ 63 #define PXA_DCMD_ENDIRQEN BIT(21) /* End Interrupt Enable */ 64 #define PXA_DCMD_ENDIAN BIT(18) /* Device Endian-ness. */ 65 #define PXA_DCMD_BURST8 (1 << 16) /* 8 byte burst */ 66 #define PXA_DCMD_BURST16 (2 << 16) /* 16 byte burst */ 67 #define PXA_DCMD_BURST32 (3 << 16) /* 32 byte burst */ 68 #define PXA_DCMD_WIDTH1 (1 << 14) /* 1 byte width */ 69 #define PXA_DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ 70 #define PXA_DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ 71 #define PXA_DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ 72 73 #define PDMA_ALIGNMENT 3 74 #define PDMA_MAX_DESC_BYTES (PXA_DCMD_LENGTH & ~((1 << PDMA_ALIGNMENT) - 1)) 75 76 struct pxad_desc_hw { 77 u32 ddadr; /* Points to the next descriptor + flags */ 78 u32 dsadr; /* DSADR value for the current transfer */ 79 u32 dtadr; /* DTADR value for the current transfer */ 80 u32 dcmd; /* DCMD value for the current transfer */ 81 } __aligned(16); 82 83 struct pxad_desc_sw { 84 struct virt_dma_desc vd; /* Virtual descriptor */ 85 int nb_desc; /* Number of hw. descriptors */ 86 size_t len; /* Number of bytes xfered */ 87 dma_addr_t first; /* First descriptor's addr */ 88 89 /* At least one descriptor has an src/dst address not multiple of 8 */ 90 bool misaligned; 91 bool cyclic; 92 struct dma_pool *desc_pool; /* Channel's used allocator */ 93 94 struct pxad_desc_hw *hw_desc[] __counted_by(nb_desc); 95 /* DMA coherent descriptors */ 96 }; 97 98 struct pxad_phy { 99 int idx; 100 void __iomem *base; 101 struct pxad_chan *vchan; 102 }; 103 104 struct pxad_chan { 105 struct virt_dma_chan vc; /* Virtual channel */ 106 u32 drcmr; /* Requestor of the channel */ 107 enum pxad_chan_prio prio; /* Required priority of phy */ 108 /* 109 * At least one desc_sw in submitted or issued transfers on this channel 110 * has one address such as: addr % 8 != 0. This implies the DALGN 111 * setting on the phy. 112 */ 113 bool misaligned; 114 struct dma_slave_config cfg; /* Runtime config */ 115 116 /* protected by vc->lock */ 117 struct pxad_phy *phy; 118 struct dma_pool *desc_pool; /* Descriptors pool */ 119 dma_cookie_t bus_error; 120 121 wait_queue_head_t wq_state; 122 }; 123 124 struct pxad_device { 125 struct dma_device slave; 126 int nr_chans; 127 int nr_requestors; 128 void __iomem *base; 129 struct pxad_phy *phys; 130 spinlock_t phy_lock; /* Phy association */ 131 #ifdef CONFIG_DEBUG_FS 132 struct dentry *dbgfs_root; 133 struct dentry **dbgfs_chan; 134 #endif 135 }; 136 137 #define tx_to_pxad_desc(tx) \ 138 container_of(tx, struct pxad_desc_sw, async_tx) 139 #define to_pxad_chan(dchan) \ 140 container_of(dchan, struct pxad_chan, vc.chan) 141 #define to_pxad_dev(dmadev) \ 142 container_of(dmadev, struct pxad_device, slave) 143 #define to_pxad_sw_desc(_vd) \ 144 container_of((_vd), struct pxad_desc_sw, vd) 145 146 #define _phy_readl_relaxed(phy, _reg) \ 147 readl_relaxed((phy)->base + _reg((phy)->idx)) 148 #define phy_readl_relaxed(phy, _reg) \ 149 ({ \ 150 u32 _v; \ 151 _v = readl_relaxed((phy)->base + _reg((phy)->idx)); \ 152 dev_vdbg(&phy->vchan->vc.chan.dev->device, \ 153 "%s(): readl(%s): 0x%08x\n", __func__, #_reg, \ 154 _v); \ 155 _v; \ 156 }) 157 #define phy_writel(phy, val, _reg) \ 158 do { \ 159 writel((val), (phy)->base + _reg((phy)->idx)); \ 160 dev_vdbg(&phy->vchan->vc.chan.dev->device, \ 161 "%s(): writel(0x%08x, %s)\n", \ 162 __func__, (u32)(val), #_reg); \ 163 } while (0) 164 #define phy_writel_relaxed(phy, val, _reg) \ 165 do { \ 166 writel_relaxed((val), (phy)->base + _reg((phy)->idx)); \ 167 dev_vdbg(&phy->vchan->vc.chan.dev->device, \ 168 "%s(): writel_relaxed(0x%08x, %s)\n", \ 169 __func__, (u32)(val), #_reg); \ 170 } while (0) 171 172 static unsigned int pxad_drcmr(unsigned int line) 173 { 174 if (line < 64) 175 return 0x100 + line * 4; 176 return 0x1000 + line * 4; 177 } 178 179 static bool pxad_filter_fn(struct dma_chan *chan, void *param); 180 181 /* 182 * Debug fs 183 */ 184 #ifdef CONFIG_DEBUG_FS 185 #include <linux/debugfs.h> 186 #include <linux/uaccess.h> 187 #include <linux/seq_file.h> 188 189 static int requester_chan_show(struct seq_file *s, void *p) 190 { 191 struct pxad_phy *phy = s->private; 192 int i; 193 u32 drcmr; 194 195 seq_printf(s, "DMA channel %d requester :\n", phy->idx); 196 for (i = 0; i < 70; i++) { 197 drcmr = readl_relaxed(phy->base + pxad_drcmr(i)); 198 if ((drcmr & DRCMR_CHLNUM) == phy->idx) 199 seq_printf(s, "\tRequester %d (MAPVLD=%d)\n", i, 200 !!(drcmr & DRCMR_MAPVLD)); 201 } 202 return 0; 203 } 204 205 static inline int dbg_burst_from_dcmd(u32 dcmd) 206 { 207 int burst = (dcmd >> 16) & 0x3; 208 209 return burst ? 4 << burst : 0; 210 } 211 212 static int is_phys_valid(unsigned long addr) 213 { 214 return pfn_valid(__phys_to_pfn(addr)); 215 } 216 217 #define PXA_DCSR_STR(flag) (dcsr & PXA_DCSR_##flag ? #flag" " : "") 218 #define PXA_DCMD_STR(flag) (dcmd & PXA_DCMD_##flag ? #flag" " : "") 219 220 static int descriptors_show(struct seq_file *s, void *p) 221 { 222 struct pxad_phy *phy = s->private; 223 int i, max_show = 20, burst, width; 224 u32 dcmd; 225 unsigned long phys_desc, ddadr; 226 struct pxad_desc_hw *desc; 227 228 phys_desc = ddadr = _phy_readl_relaxed(phy, DDADR); 229 230 seq_printf(s, "DMA channel %d descriptors :\n", phy->idx); 231 seq_printf(s, "[%03d] First descriptor unknown\n", 0); 232 for (i = 1; i < max_show && is_phys_valid(phys_desc); i++) { 233 desc = phys_to_virt(phys_desc); 234 dcmd = desc->dcmd; 235 burst = dbg_burst_from_dcmd(dcmd); 236 width = (1 << ((dcmd >> 14) & 0x3)) >> 1; 237 238 seq_printf(s, "[%03d] Desc at %08lx(virt %p)\n", 239 i, phys_desc, desc); 240 seq_printf(s, "\tDDADR = %08x\n", desc->ddadr); 241 seq_printf(s, "\tDSADR = %08x\n", desc->dsadr); 242 seq_printf(s, "\tDTADR = %08x\n", desc->dtadr); 243 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", 244 dcmd, 245 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR), 246 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG), 247 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN), 248 PXA_DCMD_STR(ENDIAN), burst, width, 249 dcmd & PXA_DCMD_LENGTH); 250 phys_desc = desc->ddadr; 251 } 252 if (i == max_show) 253 seq_printf(s, "[%03d] Desc at %08lx ... max display reached\n", 254 i, phys_desc); 255 else 256 seq_printf(s, "[%03d] Desc at %08lx is %s\n", 257 i, phys_desc, phys_desc == DDADR_STOP ? 258 "DDADR_STOP" : "invalid"); 259 260 return 0; 261 } 262 263 static int chan_state_show(struct seq_file *s, void *p) 264 { 265 struct pxad_phy *phy = s->private; 266 u32 dcsr, dcmd; 267 int burst, width; 268 static const char * const str_prio[] = { 269 "high", "normal", "low", "invalid" 270 }; 271 272 dcsr = _phy_readl_relaxed(phy, DCSR); 273 dcmd = _phy_readl_relaxed(phy, DCMD); 274 burst = dbg_burst_from_dcmd(dcmd); 275 width = (1 << ((dcmd >> 14) & 0x3)) >> 1; 276 277 seq_printf(s, "DMA channel %d\n", phy->idx); 278 seq_printf(s, "\tPriority : %s\n", 279 str_prio[(phy->idx & 0xf) / 4]); 280 seq_printf(s, "\tUnaligned transfer bit: %s\n", 281 str_yes_no(_phy_readl_relaxed(phy, DALGN) & BIT(phy->idx))); 282 seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", 283 dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC), 284 PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN), 285 PXA_DCSR_STR(EORJMPEN), PXA_DCSR_STR(EORSTOPEN), 286 PXA_DCSR_STR(SETCMPST), PXA_DCSR_STR(CLRCMPST), 287 PXA_DCSR_STR(CMPST), PXA_DCSR_STR(EORINTR), 288 PXA_DCSR_STR(REQPEND), PXA_DCSR_STR(STOPSTATE), 289 PXA_DCSR_STR(ENDINTR), PXA_DCSR_STR(STARTINTR), 290 PXA_DCSR_STR(BUSERR)); 291 292 seq_printf(s, "\tDCMD = %08x (%s%s%s%s%s%s%sburst=%d width=%d len=%d)\n", 293 dcmd, 294 PXA_DCMD_STR(INCSRCADDR), PXA_DCMD_STR(INCTRGADDR), 295 PXA_DCMD_STR(FLOWSRC), PXA_DCMD_STR(FLOWTRG), 296 PXA_DCMD_STR(STARTIRQEN), PXA_DCMD_STR(ENDIRQEN), 297 PXA_DCMD_STR(ENDIAN), burst, width, dcmd & PXA_DCMD_LENGTH); 298 seq_printf(s, "\tDSADR = %08x\n", _phy_readl_relaxed(phy, DSADR)); 299 seq_printf(s, "\tDTADR = %08x\n", _phy_readl_relaxed(phy, DTADR)); 300 seq_printf(s, "\tDDADR = %08x\n", _phy_readl_relaxed(phy, DDADR)); 301 302 return 0; 303 } 304 305 static int state_show(struct seq_file *s, void *p) 306 { 307 struct pxad_device *pdev = s->private; 308 309 /* basic device status */ 310 seq_puts(s, "DMA engine status\n"); 311 seq_printf(s, "\tChannel number: %d\n", pdev->nr_chans); 312 313 return 0; 314 } 315 316 DEFINE_SHOW_ATTRIBUTE(state); 317 DEFINE_SHOW_ATTRIBUTE(chan_state); 318 DEFINE_SHOW_ATTRIBUTE(descriptors); 319 DEFINE_SHOW_ATTRIBUTE(requester_chan); 320 321 static struct dentry *pxad_dbg_alloc_chan(struct pxad_device *pdev, 322 int ch, struct dentry *chandir) 323 { 324 char chan_name[11]; 325 struct dentry *chan; 326 void *dt; 327 328 scnprintf(chan_name, sizeof(chan_name), "%d", ch); 329 chan = debugfs_create_dir(chan_name, chandir); 330 dt = (void *)&pdev->phys[ch]; 331 332 debugfs_create_file("state", 0400, chan, dt, &chan_state_fops); 333 debugfs_create_file("descriptors", 0400, chan, dt, &descriptors_fops); 334 debugfs_create_file("requesters", 0400, chan, dt, &requester_chan_fops); 335 336 return chan; 337 } 338 339 static void pxad_init_debugfs(struct pxad_device *pdev) 340 { 341 int i; 342 struct dentry *chandir; 343 344 pdev->dbgfs_chan = 345 kmalloc_objs(struct dentry *, pdev->nr_chans); 346 if (!pdev->dbgfs_chan) 347 return; 348 349 pdev->dbgfs_root = debugfs_create_dir(dev_name(pdev->slave.dev), NULL); 350 351 debugfs_create_file("state", 0400, pdev->dbgfs_root, pdev, &state_fops); 352 353 chandir = debugfs_create_dir("channels", pdev->dbgfs_root); 354 355 for (i = 0; i < pdev->nr_chans; i++) 356 pdev->dbgfs_chan[i] = pxad_dbg_alloc_chan(pdev, i, chandir); 357 } 358 359 static void pxad_cleanup_debugfs(struct pxad_device *pdev) 360 { 361 debugfs_remove_recursive(pdev->dbgfs_root); 362 } 363 #else 364 static inline void pxad_init_debugfs(struct pxad_device *pdev) {} 365 static inline void pxad_cleanup_debugfs(struct pxad_device *pdev) {} 366 #endif 367 368 static struct pxad_phy *lookup_phy(struct pxad_chan *pchan) 369 { 370 int prio, i; 371 struct pxad_device *pdev = to_pxad_dev(pchan->vc.chan.device); 372 struct pxad_phy *phy, *found = NULL; 373 unsigned long flags; 374 375 /* 376 * dma channel priorities 377 * ch 0 - 3, 16 - 19 <--> (0) 378 * ch 4 - 7, 20 - 23 <--> (1) 379 * ch 8 - 11, 24 - 27 <--> (2) 380 * ch 12 - 15, 28 - 31 <--> (3) 381 */ 382 383 spin_lock_irqsave(&pdev->phy_lock, flags); 384 for (prio = pchan->prio; prio >= PXAD_PRIO_HIGHEST; prio--) { 385 for (i = 0; i < pdev->nr_chans; i++) { 386 if (prio != (i & 0xf) >> 2) 387 continue; 388 phy = &pdev->phys[i]; 389 if (!phy->vchan) { 390 phy->vchan = pchan; 391 found = phy; 392 goto out_unlock; 393 } 394 } 395 } 396 397 out_unlock: 398 spin_unlock_irqrestore(&pdev->phy_lock, flags); 399 dev_dbg(&pchan->vc.chan.dev->device, 400 "%s(): phy=%p(%d)\n", __func__, found, 401 found ? found->idx : -1); 402 403 return found; 404 } 405 406 static void pxad_free_phy(struct pxad_chan *chan) 407 { 408 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); 409 unsigned long flags; 410 u32 reg; 411 412 dev_dbg(&chan->vc.chan.dev->device, 413 "%s(): freeing\n", __func__); 414 if (!chan->phy) 415 return; 416 417 /* clear the channel mapping in DRCMR */ 418 if (chan->drcmr <= pdev->nr_requestors) { 419 reg = pxad_drcmr(chan->drcmr); 420 writel_relaxed(0, chan->phy->base + reg); 421 } 422 423 spin_lock_irqsave(&pdev->phy_lock, flags); 424 chan->phy->vchan = NULL; 425 chan->phy = NULL; 426 spin_unlock_irqrestore(&pdev->phy_lock, flags); 427 } 428 429 static bool is_chan_running(struct pxad_chan *chan) 430 { 431 u32 dcsr; 432 struct pxad_phy *phy = chan->phy; 433 434 if (!phy) 435 return false; 436 dcsr = phy_readl_relaxed(phy, DCSR); 437 return dcsr & PXA_DCSR_RUN; 438 } 439 440 static bool is_running_chan_misaligned(struct pxad_chan *chan) 441 { 442 u32 dalgn; 443 444 BUG_ON(!chan->phy); 445 dalgn = phy_readl_relaxed(chan->phy, DALGN); 446 return dalgn & (BIT(chan->phy->idx)); 447 } 448 449 static void phy_enable(struct pxad_phy *phy, bool misaligned) 450 { 451 struct pxad_device *pdev; 452 u32 reg, dalgn; 453 454 if (!phy->vchan) 455 return; 456 457 dev_dbg(&phy->vchan->vc.chan.dev->device, 458 "%s(); phy=%p(%d) misaligned=%d\n", __func__, 459 phy, phy->idx, misaligned); 460 461 pdev = to_pxad_dev(phy->vchan->vc.chan.device); 462 if (phy->vchan->drcmr <= pdev->nr_requestors) { 463 reg = pxad_drcmr(phy->vchan->drcmr); 464 writel_relaxed(DRCMR_MAPVLD | phy->idx, phy->base + reg); 465 } 466 467 dalgn = phy_readl_relaxed(phy, DALGN); 468 if (misaligned) 469 dalgn |= BIT(phy->idx); 470 else 471 dalgn &= ~BIT(phy->idx); 472 phy_writel_relaxed(phy, dalgn, DALGN); 473 474 phy_writel(phy, PXA_DCSR_STOPIRQEN | PXA_DCSR_ENDINTR | 475 PXA_DCSR_BUSERR | PXA_DCSR_RUN, DCSR); 476 } 477 478 static void phy_disable(struct pxad_phy *phy) 479 { 480 u32 dcsr; 481 482 if (!phy) 483 return; 484 485 dcsr = phy_readl_relaxed(phy, DCSR); 486 dev_dbg(&phy->vchan->vc.chan.dev->device, 487 "%s(): phy=%p(%d)\n", __func__, phy, phy->idx); 488 phy_writel(phy, dcsr & ~PXA_DCSR_RUN & ~PXA_DCSR_STOPIRQEN, DCSR); 489 } 490 491 static void pxad_launch_chan(struct pxad_chan *chan, 492 struct pxad_desc_sw *desc) 493 { 494 dev_dbg(&chan->vc.chan.dev->device, 495 "%s(): desc=%p\n", __func__, desc); 496 if (!chan->phy) { 497 chan->phy = lookup_phy(chan); 498 if (!chan->phy) { 499 dev_dbg(&chan->vc.chan.dev->device, 500 "%s(): no free dma channel\n", __func__); 501 return; 502 } 503 } 504 chan->bus_error = 0; 505 506 /* 507 * Program the descriptor's address into the DMA controller, 508 * then start the DMA transaction 509 */ 510 phy_writel(chan->phy, desc->first, DDADR); 511 phy_enable(chan->phy, chan->misaligned); 512 wake_up(&chan->wq_state); 513 } 514 515 static void set_updater_desc(struct pxad_desc_sw *sw_desc, 516 unsigned long flags) 517 { 518 struct pxad_desc_hw *updater = 519 sw_desc->hw_desc[sw_desc->nb_desc - 1]; 520 dma_addr_t dma = sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr; 521 522 updater->ddadr = DDADR_STOP; 523 updater->dsadr = dma; 524 updater->dtadr = dma + 8; 525 updater->dcmd = PXA_DCMD_WIDTH4 | PXA_DCMD_BURST32 | 526 (PXA_DCMD_LENGTH & sizeof(u32)); 527 if (flags & DMA_PREP_INTERRUPT) 528 updater->dcmd |= PXA_DCMD_ENDIRQEN; 529 if (sw_desc->cyclic) 530 sw_desc->hw_desc[sw_desc->nb_desc - 2]->ddadr = sw_desc->first; 531 } 532 533 static bool is_desc_completed(struct virt_dma_desc *vd) 534 { 535 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); 536 struct pxad_desc_hw *updater = 537 sw_desc->hw_desc[sw_desc->nb_desc - 1]; 538 539 return updater->dtadr != (updater->dsadr + 8); 540 } 541 542 static void pxad_desc_chain(struct virt_dma_desc *vd1, 543 struct virt_dma_desc *vd2) 544 { 545 struct pxad_desc_sw *desc1 = to_pxad_sw_desc(vd1); 546 struct pxad_desc_sw *desc2 = to_pxad_sw_desc(vd2); 547 dma_addr_t dma_to_chain; 548 549 dma_to_chain = desc2->first; 550 desc1->hw_desc[desc1->nb_desc - 1]->ddadr = dma_to_chain; 551 } 552 553 static bool pxad_try_hotchain(struct virt_dma_chan *vc, 554 struct virt_dma_desc *vd) 555 { 556 struct virt_dma_desc *vd_last_issued = NULL; 557 struct pxad_chan *chan = to_pxad_chan(&vc->chan); 558 559 /* 560 * Attempt to hot chain the tx if the phy is still running. This is 561 * considered successful only if either the channel is still running 562 * after the chaining, or if the chained transfer is completed after 563 * having been hot chained. 564 * A change of alignment is not allowed, and forbids hotchaining. 565 */ 566 if (is_chan_running(chan)) { 567 BUG_ON(list_empty(&vc->desc_issued)); 568 569 if (!is_running_chan_misaligned(chan) && 570 to_pxad_sw_desc(vd)->misaligned) 571 return false; 572 573 vd_last_issued = list_entry(vc->desc_issued.prev, 574 struct virt_dma_desc, node); 575 pxad_desc_chain(vd_last_issued, vd); 576 if (is_chan_running(chan) || is_desc_completed(vd)) 577 return true; 578 } 579 580 return false; 581 } 582 583 static unsigned int clear_chan_irq(struct pxad_phy *phy) 584 { 585 u32 dcsr; 586 u32 dint = readl(phy->base + DINT); 587 588 if (!(dint & BIT(phy->idx))) 589 return PXA_DCSR_RUN; 590 591 /* clear irq */ 592 dcsr = phy_readl_relaxed(phy, DCSR); 593 phy_writel(phy, dcsr, DCSR); 594 if ((dcsr & PXA_DCSR_BUSERR) && (phy->vchan)) 595 dev_warn(&phy->vchan->vc.chan.dev->device, 596 "%s(chan=%p): PXA_DCSR_BUSERR\n", 597 __func__, &phy->vchan); 598 599 return dcsr & ~PXA_DCSR_RUN; 600 } 601 602 static irqreturn_t pxad_chan_handler(int irq, void *dev_id) 603 { 604 struct pxad_phy *phy = dev_id; 605 struct pxad_chan *chan = phy->vchan; 606 struct virt_dma_desc *vd, *tmp; 607 unsigned int dcsr; 608 bool vd_completed; 609 dma_cookie_t last_started = 0; 610 611 BUG_ON(!chan); 612 613 dcsr = clear_chan_irq(phy); 614 if (dcsr & PXA_DCSR_RUN) 615 return IRQ_NONE; 616 617 spin_lock(&chan->vc.lock); 618 list_for_each_entry_safe(vd, tmp, &chan->vc.desc_issued, node) { 619 vd_completed = is_desc_completed(vd); 620 dev_dbg(&chan->vc.chan.dev->device, 621 "%s(): checking txd %p[%x]: completed=%d dcsr=0x%x\n", 622 __func__, vd, vd->tx.cookie, vd_completed, 623 dcsr); 624 last_started = vd->tx.cookie; 625 if (to_pxad_sw_desc(vd)->cyclic) { 626 vchan_cyclic_callback(vd); 627 break; 628 } 629 if (vd_completed) { 630 list_del(&vd->node); 631 vchan_cookie_complete(vd); 632 } else { 633 break; 634 } 635 } 636 637 if (dcsr & PXA_DCSR_BUSERR) { 638 chan->bus_error = last_started; 639 phy_disable(phy); 640 } 641 642 if (!chan->bus_error && dcsr & PXA_DCSR_STOPSTATE) { 643 dev_dbg(&chan->vc.chan.dev->device, 644 "%s(): channel stopped, submitted_empty=%d issued_empty=%d", 645 __func__, 646 list_empty(&chan->vc.desc_submitted), 647 list_empty(&chan->vc.desc_issued)); 648 phy_writel_relaxed(phy, dcsr & ~PXA_DCSR_STOPIRQEN, DCSR); 649 650 if (list_empty(&chan->vc.desc_issued)) { 651 chan->misaligned = 652 !list_empty(&chan->vc.desc_submitted); 653 } else { 654 vd = list_first_entry(&chan->vc.desc_issued, 655 struct virt_dma_desc, node); 656 pxad_launch_chan(chan, to_pxad_sw_desc(vd)); 657 } 658 } 659 spin_unlock(&chan->vc.lock); 660 wake_up(&chan->wq_state); 661 662 return IRQ_HANDLED; 663 } 664 665 static irqreturn_t pxad_int_handler(int irq, void *dev_id) 666 { 667 struct pxad_device *pdev = dev_id; 668 struct pxad_phy *phy; 669 u32 dint = readl(pdev->base + DINT); 670 int i, ret = IRQ_NONE; 671 672 while (dint) { 673 i = __ffs(dint); 674 dint &= (dint - 1); 675 phy = &pdev->phys[i]; 676 if (pxad_chan_handler(irq, phy) == IRQ_HANDLED) 677 ret = IRQ_HANDLED; 678 } 679 680 return ret; 681 } 682 683 static int pxad_alloc_chan_resources(struct dma_chan *dchan) 684 { 685 struct pxad_chan *chan = to_pxad_chan(dchan); 686 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); 687 688 if (chan->desc_pool) 689 return 1; 690 691 chan->desc_pool = dma_pool_create(dma_chan_name(dchan), 692 pdev->slave.dev, 693 sizeof(struct pxad_desc_hw), 694 __alignof__(struct pxad_desc_hw), 695 0); 696 if (!chan->desc_pool) { 697 dev_err(&chan->vc.chan.dev->device, 698 "%s(): unable to allocate descriptor pool\n", 699 __func__); 700 return -ENOMEM; 701 } 702 703 return 1; 704 } 705 706 static void pxad_free_chan_resources(struct dma_chan *dchan) 707 { 708 struct pxad_chan *chan = to_pxad_chan(dchan); 709 710 vchan_free_chan_resources(&chan->vc); 711 dma_pool_destroy(chan->desc_pool); 712 chan->desc_pool = NULL; 713 714 chan->drcmr = U32_MAX; 715 chan->prio = PXAD_PRIO_LOWEST; 716 } 717 718 static void pxad_free_desc(struct virt_dma_desc *vd) 719 { 720 int i; 721 dma_addr_t dma; 722 struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); 723 724 for (i = sw_desc->nb_desc - 1; i >= 0; i--) { 725 if (i > 0) 726 dma = sw_desc->hw_desc[i - 1]->ddadr; 727 else 728 dma = sw_desc->first; 729 dma_pool_free(sw_desc->desc_pool, 730 sw_desc->hw_desc[i], dma); 731 } 732 sw_desc->nb_desc = 0; 733 kfree(sw_desc); 734 } 735 736 static struct pxad_desc_sw * 737 pxad_alloc_desc(struct pxad_chan *chan, unsigned int nb_hw_desc) 738 { 739 struct pxad_desc_sw *sw_desc; 740 dma_addr_t dma; 741 void *desc; 742 int i; 743 744 sw_desc = kzalloc_flex(*sw_desc, hw_desc, nb_hw_desc, GFP_NOWAIT); 745 if (!sw_desc) 746 return NULL; 747 sw_desc->nb_desc = nb_hw_desc; 748 sw_desc->desc_pool = chan->desc_pool; 749 750 for (i = 0; i < nb_hw_desc; i++) { 751 desc = dma_pool_alloc(sw_desc->desc_pool, GFP_NOWAIT, &dma); 752 if (!desc) { 753 dev_err(&chan->vc.chan.dev->device, 754 "%s(): Couldn't allocate the %dth hw_desc from dma_pool %p\n", 755 __func__, i, sw_desc->desc_pool); 756 sw_desc->nb_desc = i; 757 goto err; 758 } 759 760 sw_desc->hw_desc[i] = desc; 761 762 if (i == 0) 763 sw_desc->first = dma; 764 else 765 sw_desc->hw_desc[i - 1]->ddadr = dma; 766 } 767 768 return sw_desc; 769 err: 770 pxad_free_desc(&sw_desc->vd); 771 return NULL; 772 } 773 774 static dma_cookie_t pxad_tx_submit(struct dma_async_tx_descriptor *tx) 775 { 776 struct virt_dma_chan *vc = to_virt_chan(tx->chan); 777 struct pxad_chan *chan = to_pxad_chan(&vc->chan); 778 struct virt_dma_desc *vd_chained = NULL, 779 *vd = container_of(tx, struct virt_dma_desc, tx); 780 dma_cookie_t cookie; 781 unsigned long flags; 782 783 set_updater_desc(to_pxad_sw_desc(vd), tx->flags); 784 785 spin_lock_irqsave(&vc->lock, flags); 786 cookie = dma_cookie_assign(tx); 787 788 if (list_empty(&vc->desc_submitted) && pxad_try_hotchain(vc, vd)) { 789 list_move_tail(&vd->node, &vc->desc_issued); 790 dev_dbg(&chan->vc.chan.dev->device, 791 "%s(): txd %p[%x]: submitted (hot linked)\n", 792 __func__, vd, cookie); 793 goto out; 794 } 795 796 /* 797 * Fallback to placing the tx in the submitted queue 798 */ 799 if (!list_empty(&vc->desc_submitted)) { 800 vd_chained = list_entry(vc->desc_submitted.prev, 801 struct virt_dma_desc, node); 802 /* 803 * Only chain the descriptors if no new misalignment is 804 * introduced. If a new misalignment is chained, let the channel 805 * stop, and be relaunched in misalign mode from the irq 806 * handler. 807 */ 808 if (chan->misaligned || !to_pxad_sw_desc(vd)->misaligned) 809 pxad_desc_chain(vd_chained, vd); 810 else 811 vd_chained = NULL; 812 } 813 dev_dbg(&chan->vc.chan.dev->device, 814 "%s(): txd %p[%x]: submitted (%s linked)\n", 815 __func__, vd, cookie, vd_chained ? "cold" : "not"); 816 list_move_tail(&vd->node, &vc->desc_submitted); 817 chan->misaligned |= to_pxad_sw_desc(vd)->misaligned; 818 819 out: 820 spin_unlock_irqrestore(&vc->lock, flags); 821 return cookie; 822 } 823 824 static void pxad_issue_pending(struct dma_chan *dchan) 825 { 826 struct pxad_chan *chan = to_pxad_chan(dchan); 827 struct virt_dma_desc *vd_first; 828 unsigned long flags; 829 830 spin_lock_irqsave(&chan->vc.lock, flags); 831 if (list_empty(&chan->vc.desc_submitted)) 832 goto out; 833 834 vd_first = list_first_entry(&chan->vc.desc_submitted, 835 struct virt_dma_desc, node); 836 dev_dbg(&chan->vc.chan.dev->device, 837 "%s(): txd %p[%x]", __func__, vd_first, vd_first->tx.cookie); 838 839 vchan_issue_pending(&chan->vc); 840 if (!pxad_try_hotchain(&chan->vc, vd_first)) 841 pxad_launch_chan(chan, to_pxad_sw_desc(vd_first)); 842 out: 843 spin_unlock_irqrestore(&chan->vc.lock, flags); 844 } 845 846 static inline struct dma_async_tx_descriptor * 847 pxad_tx_prep(struct virt_dma_chan *vc, struct virt_dma_desc *vd, 848 unsigned long tx_flags) 849 { 850 struct dma_async_tx_descriptor *tx; 851 struct pxad_chan *chan = container_of(vc, struct pxad_chan, vc); 852 853 INIT_LIST_HEAD(&vd->node); 854 tx = vchan_tx_prep(vc, vd, tx_flags); 855 tx->tx_submit = pxad_tx_submit; 856 dev_dbg(&chan->vc.chan.dev->device, 857 "%s(): vc=%p txd=%p[%x] flags=0x%lx\n", __func__, 858 vc, vd, vd->tx.cookie, 859 tx_flags); 860 861 return tx; 862 } 863 864 static void pxad_get_config(struct pxad_chan *chan, 865 enum dma_transfer_direction dir, 866 u32 *dcmd, u32 *dev_src, u32 *dev_dst) 867 { 868 u32 maxburst = 0, dev_addr = 0; 869 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 870 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); 871 872 *dcmd = 0; 873 if (dir == DMA_DEV_TO_MEM) { 874 maxburst = chan->cfg.src_maxburst; 875 width = chan->cfg.src_addr_width; 876 dev_addr = chan->cfg.src_addr; 877 *dev_src = dev_addr; 878 *dcmd |= PXA_DCMD_INCTRGADDR; 879 if (chan->drcmr <= pdev->nr_requestors) 880 *dcmd |= PXA_DCMD_FLOWSRC; 881 } 882 if (dir == DMA_MEM_TO_DEV) { 883 maxburst = chan->cfg.dst_maxburst; 884 width = chan->cfg.dst_addr_width; 885 dev_addr = chan->cfg.dst_addr; 886 *dev_dst = dev_addr; 887 *dcmd |= PXA_DCMD_INCSRCADDR; 888 if (chan->drcmr <= pdev->nr_requestors) 889 *dcmd |= PXA_DCMD_FLOWTRG; 890 } 891 if (dir == DMA_MEM_TO_MEM) 892 *dcmd |= PXA_DCMD_BURST32 | PXA_DCMD_INCTRGADDR | 893 PXA_DCMD_INCSRCADDR; 894 895 dev_dbg(&chan->vc.chan.dev->device, 896 "%s(): dev_addr=0x%x maxburst=%d width=%d dir=%d\n", 897 __func__, dev_addr, maxburst, width, dir); 898 899 if (width == DMA_SLAVE_BUSWIDTH_1_BYTE) 900 *dcmd |= PXA_DCMD_WIDTH1; 901 else if (width == DMA_SLAVE_BUSWIDTH_2_BYTES) 902 *dcmd |= PXA_DCMD_WIDTH2; 903 else if (width == DMA_SLAVE_BUSWIDTH_4_BYTES) 904 *dcmd |= PXA_DCMD_WIDTH4; 905 906 if (maxburst == 8) 907 *dcmd |= PXA_DCMD_BURST8; 908 else if (maxburst == 16) 909 *dcmd |= PXA_DCMD_BURST16; 910 else if (maxburst == 32) 911 *dcmd |= PXA_DCMD_BURST32; 912 } 913 914 static struct dma_async_tx_descriptor * 915 pxad_prep_memcpy(struct dma_chan *dchan, 916 dma_addr_t dma_dst, dma_addr_t dma_src, 917 size_t len, unsigned long flags) 918 { 919 struct pxad_chan *chan = to_pxad_chan(dchan); 920 struct pxad_desc_sw *sw_desc; 921 struct pxad_desc_hw *hw_desc; 922 u32 dcmd; 923 unsigned int i, nb_desc = 0; 924 size_t copy; 925 926 if (!dchan || !len) 927 return NULL; 928 929 dev_dbg(&chan->vc.chan.dev->device, 930 "%s(): dma_dst=0x%lx dma_src=0x%lx len=%zu flags=%lx\n", 931 __func__, (unsigned long)dma_dst, (unsigned long)dma_src, 932 len, flags); 933 pxad_get_config(chan, DMA_MEM_TO_MEM, &dcmd, NULL, NULL); 934 935 nb_desc = DIV_ROUND_UP(len, PDMA_MAX_DESC_BYTES); 936 sw_desc = pxad_alloc_desc(chan, nb_desc + 1); 937 if (!sw_desc) 938 return NULL; 939 sw_desc->len = len; 940 941 if (!IS_ALIGNED(dma_src, 1 << PDMA_ALIGNMENT) || 942 !IS_ALIGNED(dma_dst, 1 << PDMA_ALIGNMENT)) 943 sw_desc->misaligned = true; 944 945 i = 0; 946 do { 947 hw_desc = sw_desc->hw_desc[i++]; 948 copy = min_t(size_t, len, PDMA_MAX_DESC_BYTES); 949 hw_desc->dcmd = dcmd | (PXA_DCMD_LENGTH & copy); 950 hw_desc->dsadr = dma_src; 951 hw_desc->dtadr = dma_dst; 952 len -= copy; 953 dma_src += copy; 954 dma_dst += copy; 955 } while (len); 956 set_updater_desc(sw_desc, flags); 957 958 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); 959 } 960 961 static struct dma_async_tx_descriptor * 962 pxad_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 963 unsigned int sg_len, enum dma_transfer_direction dir, 964 unsigned long flags, void *context) 965 { 966 struct pxad_chan *chan = to_pxad_chan(dchan); 967 struct pxad_desc_sw *sw_desc; 968 size_t len, avail; 969 struct scatterlist *sg; 970 dma_addr_t dma; 971 u32 dcmd, dsadr = 0, dtadr = 0; 972 unsigned int nb_desc, i, j = 0; 973 974 if ((sgl == NULL) || (sg_len == 0)) 975 return NULL; 976 977 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr); 978 dev_dbg(&chan->vc.chan.dev->device, 979 "%s(): dir=%d flags=%lx\n", __func__, dir, flags); 980 981 nb_desc = sg_nents_for_dma(sgl, sg_len, PDMA_MAX_DESC_BYTES); 982 sw_desc = pxad_alloc_desc(chan, nb_desc + 1); 983 if (!sw_desc) 984 return NULL; 985 986 for_each_sg(sgl, sg, sg_len, i) { 987 dma = sg_dma_address(sg); 988 avail = sg_dma_len(sg); 989 sw_desc->len += avail; 990 991 do { 992 len = min_t(size_t, avail, PDMA_MAX_DESC_BYTES); 993 if (dma & 0x7) 994 sw_desc->misaligned = true; 995 996 sw_desc->hw_desc[j]->dcmd = 997 dcmd | (PXA_DCMD_LENGTH & len); 998 sw_desc->hw_desc[j]->dsadr = dsadr ? dsadr : dma; 999 sw_desc->hw_desc[j++]->dtadr = dtadr ? dtadr : dma; 1000 1001 dma += len; 1002 avail -= len; 1003 } while (avail); 1004 } 1005 set_updater_desc(sw_desc, flags); 1006 1007 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); 1008 } 1009 1010 static struct dma_async_tx_descriptor * 1011 pxad_prep_dma_cyclic(struct dma_chan *dchan, 1012 dma_addr_t buf_addr, size_t len, size_t period_len, 1013 enum dma_transfer_direction dir, unsigned long flags) 1014 { 1015 struct pxad_chan *chan = to_pxad_chan(dchan); 1016 struct pxad_desc_sw *sw_desc; 1017 struct pxad_desc_hw **phw_desc; 1018 dma_addr_t dma; 1019 u32 dcmd, dsadr = 0, dtadr = 0; 1020 unsigned int nb_desc = 0; 1021 1022 if (!dchan || !len || !period_len) 1023 return NULL; 1024 if ((dir != DMA_DEV_TO_MEM) && (dir != DMA_MEM_TO_DEV)) { 1025 dev_err(&chan->vc.chan.dev->device, 1026 "Unsupported direction for cyclic DMA\n"); 1027 return NULL; 1028 } 1029 /* the buffer length must be a multiple of period_len */ 1030 if (len % period_len != 0 || period_len > PDMA_MAX_DESC_BYTES || 1031 !IS_ALIGNED(period_len, 1 << PDMA_ALIGNMENT)) 1032 return NULL; 1033 1034 pxad_get_config(chan, dir, &dcmd, &dsadr, &dtadr); 1035 dcmd |= PXA_DCMD_ENDIRQEN | (PXA_DCMD_LENGTH & period_len); 1036 dev_dbg(&chan->vc.chan.dev->device, 1037 "%s(): buf_addr=0x%lx len=%zu period=%zu dir=%d flags=%lx\n", 1038 __func__, (unsigned long)buf_addr, len, period_len, dir, flags); 1039 1040 nb_desc = DIV_ROUND_UP(period_len, PDMA_MAX_DESC_BYTES); 1041 nb_desc *= DIV_ROUND_UP(len, period_len); 1042 sw_desc = pxad_alloc_desc(chan, nb_desc + 1); 1043 if (!sw_desc) 1044 return NULL; 1045 sw_desc->cyclic = true; 1046 sw_desc->len = len; 1047 1048 phw_desc = sw_desc->hw_desc; 1049 dma = buf_addr; 1050 do { 1051 phw_desc[0]->dsadr = dsadr ? dsadr : dma; 1052 phw_desc[0]->dtadr = dtadr ? dtadr : dma; 1053 phw_desc[0]->dcmd = dcmd; 1054 phw_desc++; 1055 dma += period_len; 1056 len -= period_len; 1057 } while (len); 1058 set_updater_desc(sw_desc, flags); 1059 1060 return pxad_tx_prep(&chan->vc, &sw_desc->vd, flags); 1061 } 1062 1063 static int pxad_config(struct dma_chan *dchan, 1064 struct dma_slave_config *cfg) 1065 { 1066 struct pxad_chan *chan = to_pxad_chan(dchan); 1067 1068 if (!dchan) 1069 return -EINVAL; 1070 1071 chan->cfg = *cfg; 1072 return 0; 1073 } 1074 1075 static int pxad_terminate_all(struct dma_chan *dchan) 1076 { 1077 struct pxad_chan *chan = to_pxad_chan(dchan); 1078 struct pxad_device *pdev = to_pxad_dev(chan->vc.chan.device); 1079 struct virt_dma_desc *vd = NULL; 1080 unsigned long flags; 1081 struct pxad_phy *phy; 1082 LIST_HEAD(head); 1083 1084 dev_dbg(&chan->vc.chan.dev->device, 1085 "%s(): vchan %p: terminate all\n", __func__, &chan->vc); 1086 1087 spin_lock_irqsave(&chan->vc.lock, flags); 1088 vchan_get_all_descriptors(&chan->vc, &head); 1089 1090 list_for_each_entry(vd, &head, node) { 1091 dev_dbg(&chan->vc.chan.dev->device, 1092 "%s(): cancelling txd %p[%x] (completed=%d)", __func__, 1093 vd, vd->tx.cookie, is_desc_completed(vd)); 1094 } 1095 1096 phy = chan->phy; 1097 if (phy) { 1098 phy_disable(chan->phy); 1099 pxad_free_phy(chan); 1100 chan->phy = NULL; 1101 spin_lock(&pdev->phy_lock); 1102 phy->vchan = NULL; 1103 spin_unlock(&pdev->phy_lock); 1104 } 1105 spin_unlock_irqrestore(&chan->vc.lock, flags); 1106 vchan_dma_desc_free_list(&chan->vc, &head); 1107 1108 return 0; 1109 } 1110 1111 static unsigned int pxad_residue(struct pxad_chan *chan, 1112 dma_cookie_t cookie) 1113 { 1114 struct virt_dma_desc *vd = NULL; 1115 struct pxad_desc_sw *sw_desc = NULL; 1116 struct pxad_desc_hw *hw_desc = NULL; 1117 u32 curr, start, len, end, residue = 0; 1118 unsigned long flags; 1119 bool passed = false; 1120 int i; 1121 1122 /* 1123 * If the channel does not have a phy pointer anymore, it has already 1124 * been completed. Therefore, its residue is 0. 1125 */ 1126 if (!chan->phy) 1127 return 0; 1128 1129 spin_lock_irqsave(&chan->vc.lock, flags); 1130 1131 vd = vchan_find_desc(&chan->vc, cookie); 1132 if (!vd) 1133 goto out; 1134 1135 sw_desc = to_pxad_sw_desc(vd); 1136 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) 1137 curr = phy_readl_relaxed(chan->phy, DSADR); 1138 else 1139 curr = phy_readl_relaxed(chan->phy, DTADR); 1140 1141 /* 1142 * curr has to be actually read before checking descriptor 1143 * completion, so that a curr inside a status updater 1144 * descriptor implies the following test returns true, and 1145 * preventing reordering of curr load and the test. 1146 */ 1147 rmb(); 1148 if (is_desc_completed(vd)) 1149 goto out; 1150 1151 for (i = 0; i < sw_desc->nb_desc - 1; i++) { 1152 hw_desc = sw_desc->hw_desc[i]; 1153 if (sw_desc->hw_desc[0]->dcmd & PXA_DCMD_INCSRCADDR) 1154 start = hw_desc->dsadr; 1155 else 1156 start = hw_desc->dtadr; 1157 len = hw_desc->dcmd & PXA_DCMD_LENGTH; 1158 end = start + len; 1159 1160 /* 1161 * 'passed' will be latched once we found the descriptor 1162 * which lies inside the boundaries of the curr 1163 * pointer. All descriptors that occur in the list 1164 * _after_ we found that partially handled descriptor 1165 * are still to be processed and are hence added to the 1166 * residual bytes counter. 1167 */ 1168 1169 if (passed) { 1170 residue += len; 1171 } else if (curr >= start && curr <= end) { 1172 residue += end - curr; 1173 passed = true; 1174 } 1175 } 1176 if (!passed) 1177 residue = sw_desc->len; 1178 1179 out: 1180 spin_unlock_irqrestore(&chan->vc.lock, flags); 1181 dev_dbg(&chan->vc.chan.dev->device, 1182 "%s(): txd %p[%x] sw_desc=%p: %d\n", 1183 __func__, vd, cookie, sw_desc, residue); 1184 return residue; 1185 } 1186 1187 static enum dma_status pxad_tx_status(struct dma_chan *dchan, 1188 dma_cookie_t cookie, 1189 struct dma_tx_state *txstate) 1190 { 1191 struct pxad_chan *chan = to_pxad_chan(dchan); 1192 enum dma_status ret; 1193 1194 if (cookie == chan->bus_error) 1195 return DMA_ERROR; 1196 1197 ret = dma_cookie_status(dchan, cookie, txstate); 1198 if (likely(txstate && (ret != DMA_ERROR))) 1199 dma_set_residue(txstate, pxad_residue(chan, cookie)); 1200 1201 return ret; 1202 } 1203 1204 static void pxad_synchronize(struct dma_chan *dchan) 1205 { 1206 struct pxad_chan *chan = to_pxad_chan(dchan); 1207 1208 wait_event(chan->wq_state, !is_chan_running(chan)); 1209 vchan_synchronize(&chan->vc); 1210 } 1211 1212 static void pxad_free_channels(struct dma_device *dmadev) 1213 { 1214 struct pxad_chan *c, *cn; 1215 1216 list_for_each_entry_safe(c, cn, &dmadev->channels, 1217 vc.chan.device_node) { 1218 list_del(&c->vc.chan.device_node); 1219 tasklet_kill(&c->vc.task); 1220 } 1221 } 1222 1223 static void pxad_remove(struct platform_device *op) 1224 { 1225 struct pxad_device *pdev = platform_get_drvdata(op); 1226 1227 pxad_cleanup_debugfs(pdev); 1228 pxad_free_channels(&pdev->slave); 1229 } 1230 1231 static int pxad_init_phys(struct platform_device *op, 1232 struct pxad_device *pdev, 1233 unsigned int nb_phy_chans) 1234 { 1235 int irq0, irq, nr_irq = 0, i, ret; 1236 struct pxad_phy *phy; 1237 1238 irq0 = platform_get_irq(op, 0); 1239 if (irq0 < 0) 1240 return irq0; 1241 1242 pdev->phys = devm_kcalloc(&op->dev, nb_phy_chans, 1243 sizeof(pdev->phys[0]), GFP_KERNEL); 1244 if (!pdev->phys) 1245 return -ENOMEM; 1246 1247 for (i = 0; i < nb_phy_chans; i++) 1248 if (platform_get_irq_optional(op, i) > 0) 1249 nr_irq++; 1250 1251 for (i = 0; i < nb_phy_chans; i++) { 1252 phy = &pdev->phys[i]; 1253 phy->base = pdev->base; 1254 phy->idx = i; 1255 irq = platform_get_irq_optional(op, i); 1256 if ((nr_irq > 1) && (irq > 0)) 1257 ret = devm_request_irq(&op->dev, irq, 1258 pxad_chan_handler, 1259 IRQF_SHARED, "pxa-dma", phy); 1260 if ((nr_irq == 1) && (i == 0)) 1261 ret = devm_request_irq(&op->dev, irq0, 1262 pxad_int_handler, 1263 IRQF_SHARED, "pxa-dma", pdev); 1264 if (ret) { 1265 dev_err(pdev->slave.dev, 1266 "%s(): can't request irq %d:%d\n", __func__, 1267 irq, ret); 1268 return ret; 1269 } 1270 } 1271 1272 return 0; 1273 } 1274 1275 static const struct of_device_id pxad_dt_ids[] = { 1276 { .compatible = "marvell,pdma-1.0", }, 1277 {} 1278 }; 1279 MODULE_DEVICE_TABLE(of, pxad_dt_ids); 1280 1281 static struct dma_chan *pxad_dma_xlate(struct of_phandle_args *dma_spec, 1282 struct of_dma *ofdma) 1283 { 1284 struct pxad_device *d = ofdma->of_dma_data; 1285 struct dma_chan *chan; 1286 1287 chan = dma_get_any_slave_channel(&d->slave); 1288 if (!chan) 1289 return NULL; 1290 1291 to_pxad_chan(chan)->drcmr = dma_spec->args[0]; 1292 to_pxad_chan(chan)->prio = dma_spec->args[1]; 1293 1294 return chan; 1295 } 1296 1297 static int pxad_init_dmadev(struct platform_device *op, 1298 struct pxad_device *pdev, 1299 unsigned int nr_phy_chans, 1300 unsigned int nr_requestors) 1301 { 1302 int ret; 1303 unsigned int i; 1304 struct pxad_chan *c; 1305 1306 pdev->nr_chans = nr_phy_chans; 1307 pdev->nr_requestors = nr_requestors; 1308 INIT_LIST_HEAD(&pdev->slave.channels); 1309 pdev->slave.device_alloc_chan_resources = pxad_alloc_chan_resources; 1310 pdev->slave.device_free_chan_resources = pxad_free_chan_resources; 1311 pdev->slave.device_tx_status = pxad_tx_status; 1312 pdev->slave.device_issue_pending = pxad_issue_pending; 1313 pdev->slave.device_config = pxad_config; 1314 pdev->slave.device_synchronize = pxad_synchronize; 1315 pdev->slave.device_terminate_all = pxad_terminate_all; 1316 1317 if (op->dev.coherent_dma_mask) 1318 dma_set_mask(&op->dev, op->dev.coherent_dma_mask); 1319 else 1320 dma_set_mask(&op->dev, DMA_BIT_MASK(32)); 1321 1322 ret = pxad_init_phys(op, pdev, nr_phy_chans); 1323 if (ret) 1324 return ret; 1325 1326 for (i = 0; i < nr_phy_chans; i++) { 1327 c = devm_kzalloc(&op->dev, sizeof(*c), GFP_KERNEL); 1328 if (!c) 1329 return -ENOMEM; 1330 1331 c->drcmr = U32_MAX; 1332 c->prio = PXAD_PRIO_LOWEST; 1333 c->vc.desc_free = pxad_free_desc; 1334 vchan_init(&c->vc, &pdev->slave); 1335 init_waitqueue_head(&c->wq_state); 1336 } 1337 1338 return dmaenginem_async_device_register(&pdev->slave); 1339 } 1340 1341 static int pxad_probe(struct platform_device *op) 1342 { 1343 struct pxad_device *pdev; 1344 const struct dma_slave_map *slave_map = NULL; 1345 struct mmp_dma_platdata *pdata = dev_get_platdata(&op->dev); 1346 int ret, dma_channels = 0, nb_requestors = 0, slave_map_cnt = 0; 1347 const enum dma_slave_buswidth widths = 1348 DMA_SLAVE_BUSWIDTH_1_BYTE | DMA_SLAVE_BUSWIDTH_2_BYTES | 1349 DMA_SLAVE_BUSWIDTH_4_BYTES; 1350 1351 pdev = devm_kzalloc(&op->dev, sizeof(*pdev), GFP_KERNEL); 1352 if (!pdev) 1353 return -ENOMEM; 1354 1355 spin_lock_init(&pdev->phy_lock); 1356 1357 pdev->base = devm_platform_ioremap_resource(op, 0); 1358 if (IS_ERR(pdev->base)) 1359 return PTR_ERR(pdev->base); 1360 1361 if (op->dev.of_node) { 1362 /* Parse new and deprecated dma-channels properties */ 1363 if (of_property_read_u32(op->dev.of_node, "dma-channels", 1364 &dma_channels)) 1365 of_property_read_u32(op->dev.of_node, "#dma-channels", 1366 &dma_channels); 1367 /* Parse new and deprecated dma-requests properties */ 1368 ret = of_property_read_u32(op->dev.of_node, "dma-requests", 1369 &nb_requestors); 1370 if (ret) 1371 ret = of_property_read_u32(op->dev.of_node, "#dma-requests", 1372 &nb_requestors); 1373 if (ret) { 1374 dev_warn(pdev->slave.dev, 1375 "#dma-requests set to default 32 as missing in OF: %d", 1376 ret); 1377 nb_requestors = 32; 1378 } 1379 } else if (pdata && pdata->dma_channels) { 1380 dma_channels = pdata->dma_channels; 1381 nb_requestors = pdata->nb_requestors; 1382 slave_map = pdata->slave_map; 1383 slave_map_cnt = pdata->slave_map_cnt; 1384 } else { 1385 dma_channels = 32; /* default 32 channel */ 1386 } 1387 1388 dma_cap_set(DMA_SLAVE, pdev->slave.cap_mask); 1389 dma_cap_set(DMA_MEMCPY, pdev->slave.cap_mask); 1390 dma_cap_set(DMA_CYCLIC, pdev->slave.cap_mask); 1391 dma_cap_set(DMA_PRIVATE, pdev->slave.cap_mask); 1392 pdev->slave.device_prep_dma_memcpy = pxad_prep_memcpy; 1393 pdev->slave.device_prep_slave_sg = pxad_prep_slave_sg; 1394 pdev->slave.device_prep_dma_cyclic = pxad_prep_dma_cyclic; 1395 pdev->slave.filter.map = slave_map; 1396 pdev->slave.filter.mapcnt = slave_map_cnt; 1397 pdev->slave.filter.fn = pxad_filter_fn; 1398 1399 pdev->slave.copy_align = PDMA_ALIGNMENT; 1400 pdev->slave.src_addr_widths = widths; 1401 pdev->slave.dst_addr_widths = widths; 1402 pdev->slave.directions = BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); 1403 pdev->slave.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR; 1404 pdev->slave.descriptor_reuse = true; 1405 1406 pdev->slave.dev = &op->dev; 1407 ret = pxad_init_dmadev(op, pdev, dma_channels, nb_requestors); 1408 if (ret) { 1409 dev_err(pdev->slave.dev, "unable to register\n"); 1410 return ret; 1411 } 1412 1413 if (op->dev.of_node) { 1414 /* Device-tree DMA controller registration */ 1415 ret = of_dma_controller_register(op->dev.of_node, 1416 pxad_dma_xlate, pdev); 1417 if (ret < 0) { 1418 dev_err(pdev->slave.dev, 1419 "of_dma_controller_register failed\n"); 1420 return ret; 1421 } 1422 } 1423 1424 platform_set_drvdata(op, pdev); 1425 pxad_init_debugfs(pdev); 1426 dev_info(pdev->slave.dev, "initialized %d channels on %d requestors\n", 1427 dma_channels, nb_requestors); 1428 return 0; 1429 } 1430 1431 static const struct platform_device_id pxad_id_table[] = { 1432 { "pxa-dma", }, 1433 { }, 1434 }; 1435 1436 static struct platform_driver pxad_driver = { 1437 .driver = { 1438 .name = "pxa-dma", 1439 .of_match_table = pxad_dt_ids, 1440 }, 1441 .id_table = pxad_id_table, 1442 .probe = pxad_probe, 1443 .remove = pxad_remove, 1444 }; 1445 1446 static bool pxad_filter_fn(struct dma_chan *chan, void *param) 1447 { 1448 struct pxad_chan *c = to_pxad_chan(chan); 1449 struct pxad_param *p = param; 1450 1451 if (chan->device->dev->driver != &pxad_driver.driver) 1452 return false; 1453 1454 c->drcmr = p->drcmr; 1455 c->prio = p->prio; 1456 1457 return true; 1458 } 1459 1460 module_platform_driver(pxad_driver); 1461 1462 MODULE_DESCRIPTION("Marvell PXA Peripheral DMA Driver"); 1463 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>"); 1464 MODULE_LICENSE("GPL v2"); 1465