1 /* 2 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 3 * http://www.samsung.com 4 * 5 * Copyright (C) 2010 Samsung Electronics Co. Ltd. 6 * Jaswinder Singh <jassi.brar@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/kernel.h> 15 #include <linux/io.h> 16 #include <linux/init.h> 17 #include <linux/slab.h> 18 #include <linux/module.h> 19 #include <linux/string.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/dmaengine.h> 24 #include <linux/amba/bus.h> 25 #include <linux/scatterlist.h> 26 #include <linux/of.h> 27 #include <linux/of_dma.h> 28 #include <linux/err.h> 29 #include <linux/pm_runtime.h> 30 31 #include "dmaengine.h" 32 #define PL330_MAX_CHAN 8 33 #define PL330_MAX_IRQS 32 34 #define PL330_MAX_PERI 32 35 #define PL330_MAX_BURST 16 36 37 #define PL330_QUIRK_BROKEN_NO_FLUSHP BIT(0) 38 39 enum pl330_cachectrl { 40 CCTRL0, /* Noncacheable and nonbufferable */ 41 CCTRL1, /* Bufferable only */ 42 CCTRL2, /* Cacheable, but do not allocate */ 43 CCTRL3, /* Cacheable and bufferable, but do not allocate */ 44 INVALID1, /* AWCACHE = 0x1000 */ 45 INVALID2, 46 CCTRL6, /* Cacheable write-through, allocate on writes only */ 47 CCTRL7, /* Cacheable write-back, allocate on writes only */ 48 }; 49 50 enum pl330_byteswap { 51 SWAP_NO, 52 SWAP_2, 53 SWAP_4, 54 SWAP_8, 55 SWAP_16, 56 }; 57 58 /* Register and Bit field Definitions */ 59 #define DS 0x0 60 #define DS_ST_STOP 0x0 61 #define DS_ST_EXEC 0x1 62 #define DS_ST_CMISS 0x2 63 #define DS_ST_UPDTPC 0x3 64 #define DS_ST_WFE 0x4 65 #define DS_ST_ATBRR 0x5 66 #define DS_ST_QBUSY 0x6 67 #define DS_ST_WFP 0x7 68 #define DS_ST_KILL 0x8 69 #define DS_ST_CMPLT 0x9 70 #define DS_ST_FLTCMP 0xe 71 #define DS_ST_FAULT 0xf 72 73 #define DPC 0x4 74 #define INTEN 0x20 75 #define ES 0x24 76 #define INTSTATUS 0x28 77 #define INTCLR 0x2c 78 #define FSM 0x30 79 #define FSC 0x34 80 #define FTM 0x38 81 82 #define _FTC 0x40 83 #define FTC(n) (_FTC + (n)*0x4) 84 85 #define _CS 0x100 86 #define CS(n) (_CS + (n)*0x8) 87 #define CS_CNS (1 << 21) 88 89 #define _CPC 0x104 90 #define CPC(n) (_CPC + (n)*0x8) 91 92 #define _SA 0x400 93 #define SA(n) (_SA + (n)*0x20) 94 95 #define _DA 0x404 96 #define DA(n) (_DA + (n)*0x20) 97 98 #define _CC 0x408 99 #define CC(n) (_CC + (n)*0x20) 100 101 #define CC_SRCINC (1 << 0) 102 #define CC_DSTINC (1 << 14) 103 #define CC_SRCPRI (1 << 8) 104 #define CC_DSTPRI (1 << 22) 105 #define CC_SRCNS (1 << 9) 106 #define CC_DSTNS (1 << 23) 107 #define CC_SRCIA (1 << 10) 108 #define CC_DSTIA (1 << 24) 109 #define CC_SRCBRSTLEN_SHFT 4 110 #define CC_DSTBRSTLEN_SHFT 18 111 #define CC_SRCBRSTSIZE_SHFT 1 112 #define CC_DSTBRSTSIZE_SHFT 15 113 #define CC_SRCCCTRL_SHFT 11 114 #define CC_SRCCCTRL_MASK 0x7 115 #define CC_DSTCCTRL_SHFT 25 116 #define CC_DRCCCTRL_MASK 0x7 117 #define CC_SWAP_SHFT 28 118 119 #define _LC0 0x40c 120 #define LC0(n) (_LC0 + (n)*0x20) 121 122 #define _LC1 0x410 123 #define LC1(n) (_LC1 + (n)*0x20) 124 125 #define DBGSTATUS 0xd00 126 #define DBG_BUSY (1 << 0) 127 128 #define DBGCMD 0xd04 129 #define DBGINST0 0xd08 130 #define DBGINST1 0xd0c 131 132 #define CR0 0xe00 133 #define CR1 0xe04 134 #define CR2 0xe08 135 #define CR3 0xe0c 136 #define CR4 0xe10 137 #define CRD 0xe14 138 139 #define PERIPH_ID 0xfe0 140 #define PERIPH_REV_SHIFT 20 141 #define PERIPH_REV_MASK 0xf 142 #define PERIPH_REV_R0P0 0 143 #define PERIPH_REV_R1P0 1 144 #define PERIPH_REV_R1P1 2 145 146 #define CR0_PERIPH_REQ_SET (1 << 0) 147 #define CR0_BOOT_EN_SET (1 << 1) 148 #define CR0_BOOT_MAN_NS (1 << 2) 149 #define CR0_NUM_CHANS_SHIFT 4 150 #define CR0_NUM_CHANS_MASK 0x7 151 #define CR0_NUM_PERIPH_SHIFT 12 152 #define CR0_NUM_PERIPH_MASK 0x1f 153 #define CR0_NUM_EVENTS_SHIFT 17 154 #define CR0_NUM_EVENTS_MASK 0x1f 155 156 #define CR1_ICACHE_LEN_SHIFT 0 157 #define CR1_ICACHE_LEN_MASK 0x7 158 #define CR1_NUM_ICACHELINES_SHIFT 4 159 #define CR1_NUM_ICACHELINES_MASK 0xf 160 161 #define CRD_DATA_WIDTH_SHIFT 0 162 #define CRD_DATA_WIDTH_MASK 0x7 163 #define CRD_WR_CAP_SHIFT 4 164 #define CRD_WR_CAP_MASK 0x7 165 #define CRD_WR_Q_DEP_SHIFT 8 166 #define CRD_WR_Q_DEP_MASK 0xf 167 #define CRD_RD_CAP_SHIFT 12 168 #define CRD_RD_CAP_MASK 0x7 169 #define CRD_RD_Q_DEP_SHIFT 16 170 #define CRD_RD_Q_DEP_MASK 0xf 171 #define CRD_DATA_BUFF_SHIFT 20 172 #define CRD_DATA_BUFF_MASK 0x3ff 173 174 #define PART 0x330 175 #define DESIGNER 0x41 176 #define REVISION 0x0 177 #define INTEG_CFG 0x0 178 #define PERIPH_ID_VAL ((PART << 0) | (DESIGNER << 12)) 179 180 #define PL330_STATE_STOPPED (1 << 0) 181 #define PL330_STATE_EXECUTING (1 << 1) 182 #define PL330_STATE_WFE (1 << 2) 183 #define PL330_STATE_FAULTING (1 << 3) 184 #define PL330_STATE_COMPLETING (1 << 4) 185 #define PL330_STATE_WFP (1 << 5) 186 #define PL330_STATE_KILLING (1 << 6) 187 #define PL330_STATE_FAULT_COMPLETING (1 << 7) 188 #define PL330_STATE_CACHEMISS (1 << 8) 189 #define PL330_STATE_UPDTPC (1 << 9) 190 #define PL330_STATE_ATBARRIER (1 << 10) 191 #define PL330_STATE_QUEUEBUSY (1 << 11) 192 #define PL330_STATE_INVALID (1 << 15) 193 194 #define PL330_STABLE_STATES (PL330_STATE_STOPPED | PL330_STATE_EXECUTING \ 195 | PL330_STATE_WFE | PL330_STATE_FAULTING) 196 197 #define CMD_DMAADDH 0x54 198 #define CMD_DMAEND 0x00 199 #define CMD_DMAFLUSHP 0x35 200 #define CMD_DMAGO 0xa0 201 #define CMD_DMALD 0x04 202 #define CMD_DMALDP 0x25 203 #define CMD_DMALP 0x20 204 #define CMD_DMALPEND 0x28 205 #define CMD_DMAKILL 0x01 206 #define CMD_DMAMOV 0xbc 207 #define CMD_DMANOP 0x18 208 #define CMD_DMARMB 0x12 209 #define CMD_DMASEV 0x34 210 #define CMD_DMAST 0x08 211 #define CMD_DMASTP 0x29 212 #define CMD_DMASTZ 0x0c 213 #define CMD_DMAWFE 0x36 214 #define CMD_DMAWFP 0x30 215 #define CMD_DMAWMB 0x13 216 217 #define SZ_DMAADDH 3 218 #define SZ_DMAEND 1 219 #define SZ_DMAFLUSHP 2 220 #define SZ_DMALD 1 221 #define SZ_DMALDP 2 222 #define SZ_DMALP 2 223 #define SZ_DMALPEND 2 224 #define SZ_DMAKILL 1 225 #define SZ_DMAMOV 6 226 #define SZ_DMANOP 1 227 #define SZ_DMARMB 1 228 #define SZ_DMASEV 2 229 #define SZ_DMAST 1 230 #define SZ_DMASTP 2 231 #define SZ_DMASTZ 1 232 #define SZ_DMAWFE 2 233 #define SZ_DMAWFP 2 234 #define SZ_DMAWMB 1 235 #define SZ_DMAGO 6 236 237 #define BRST_LEN(ccr) ((((ccr) >> CC_SRCBRSTLEN_SHFT) & 0xf) + 1) 238 #define BRST_SIZE(ccr) (1 << (((ccr) >> CC_SRCBRSTSIZE_SHFT) & 0x7)) 239 240 #define BYTE_TO_BURST(b, ccr) ((b) / BRST_SIZE(ccr) / BRST_LEN(ccr)) 241 #define BURST_TO_BYTE(c, ccr) ((c) * BRST_SIZE(ccr) * BRST_LEN(ccr)) 242 243 /* 244 * With 256 bytes, we can do more than 2.5MB and 5MB xfers per req 245 * at 1byte/burst for P<->M and M<->M respectively. 246 * For typical scenario, at 1word/burst, 10MB and 20MB xfers per req 247 * should be enough for P<->M and M<->M respectively. 248 */ 249 #define MCODE_BUFF_PER_REQ 256 250 251 /* Use this _only_ to wait on transient states */ 252 #define UNTIL(t, s) while (!(_state(t) & (s))) cpu_relax(); 253 254 #ifdef PL330_DEBUG_MCGEN 255 static unsigned cmd_line; 256 #define PL330_DBGCMD_DUMP(off, x...) do { \ 257 printk("%x:", cmd_line); \ 258 printk(x); \ 259 cmd_line += off; \ 260 } while (0) 261 #define PL330_DBGMC_START(addr) (cmd_line = addr) 262 #else 263 #define PL330_DBGCMD_DUMP(off, x...) do {} while (0) 264 #define PL330_DBGMC_START(addr) do {} while (0) 265 #endif 266 267 /* The number of default descriptors */ 268 269 #define NR_DEFAULT_DESC 16 270 271 /* Delay for runtime PM autosuspend, ms */ 272 #define PL330_AUTOSUSPEND_DELAY 20 273 274 /* Populated by the PL330 core driver for DMA API driver's info */ 275 struct pl330_config { 276 u32 periph_id; 277 #define DMAC_MODE_NS (1 << 0) 278 unsigned int mode; 279 unsigned int data_bus_width:10; /* In number of bits */ 280 unsigned int data_buf_dep:11; 281 unsigned int num_chan:4; 282 unsigned int num_peri:6; 283 u32 peri_ns; 284 unsigned int num_events:6; 285 u32 irq_ns; 286 }; 287 288 /** 289 * Request Configuration. 290 * The PL330 core does not modify this and uses the last 291 * working configuration if the request doesn't provide any. 292 * 293 * The Client may want to provide this info only for the 294 * first request and a request with new settings. 295 */ 296 struct pl330_reqcfg { 297 /* Address Incrementing */ 298 unsigned dst_inc:1; 299 unsigned src_inc:1; 300 301 /* 302 * For now, the SRC & DST protection levels 303 * and burst size/length are assumed same. 304 */ 305 bool nonsecure; 306 bool privileged; 307 bool insnaccess; 308 unsigned brst_len:5; 309 unsigned brst_size:3; /* in power of 2 */ 310 311 enum pl330_cachectrl dcctl; 312 enum pl330_cachectrl scctl; 313 enum pl330_byteswap swap; 314 struct pl330_config *pcfg; 315 }; 316 317 /* 318 * One cycle of DMAC operation. 319 * There may be more than one xfer in a request. 320 */ 321 struct pl330_xfer { 322 u32 src_addr; 323 u32 dst_addr; 324 /* Size to xfer */ 325 u32 bytes; 326 }; 327 328 /* The xfer callbacks are made with one of these arguments. */ 329 enum pl330_op_err { 330 /* The all xfers in the request were success. */ 331 PL330_ERR_NONE, 332 /* If req aborted due to global error. */ 333 PL330_ERR_ABORT, 334 /* If req failed due to problem with Channel. */ 335 PL330_ERR_FAIL, 336 }; 337 338 enum dmamov_dst { 339 SAR = 0, 340 CCR, 341 DAR, 342 }; 343 344 enum pl330_dst { 345 SRC = 0, 346 DST, 347 }; 348 349 enum pl330_cond { 350 SINGLE, 351 BURST, 352 ALWAYS, 353 }; 354 355 struct dma_pl330_desc; 356 357 struct _pl330_req { 358 u32 mc_bus; 359 void *mc_cpu; 360 struct dma_pl330_desc *desc; 361 }; 362 363 /* ToBeDone for tasklet */ 364 struct _pl330_tbd { 365 bool reset_dmac; 366 bool reset_mngr; 367 u8 reset_chan; 368 }; 369 370 /* A DMAC Thread */ 371 struct pl330_thread { 372 u8 id; 373 int ev; 374 /* If the channel is not yet acquired by any client */ 375 bool free; 376 /* Parent DMAC */ 377 struct pl330_dmac *dmac; 378 /* Only two at a time */ 379 struct _pl330_req req[2]; 380 /* Index of the last enqueued request */ 381 unsigned lstenq; 382 /* Index of the last submitted request or -1 if the DMA is stopped */ 383 int req_running; 384 }; 385 386 enum pl330_dmac_state { 387 UNINIT, 388 INIT, 389 DYING, 390 }; 391 392 enum desc_status { 393 /* In the DMAC pool */ 394 FREE, 395 /* 396 * Allocated to some channel during prep_xxx 397 * Also may be sitting on the work_list. 398 */ 399 PREP, 400 /* 401 * Sitting on the work_list and already submitted 402 * to the PL330 core. Not more than two descriptors 403 * of a channel can be BUSY at any time. 404 */ 405 BUSY, 406 /* 407 * Sitting on the channel work_list but xfer done 408 * by PL330 core 409 */ 410 DONE, 411 }; 412 413 struct dma_pl330_chan { 414 /* Schedule desc completion */ 415 struct tasklet_struct task; 416 417 /* DMA-Engine Channel */ 418 struct dma_chan chan; 419 420 /* List of submitted descriptors */ 421 struct list_head submitted_list; 422 /* List of issued descriptors */ 423 struct list_head work_list; 424 /* List of completed descriptors */ 425 struct list_head completed_list; 426 427 /* Pointer to the DMAC that manages this channel, 428 * NULL if the channel is available to be acquired. 429 * As the parent, this DMAC also provides descriptors 430 * to the channel. 431 */ 432 struct pl330_dmac *dmac; 433 434 /* To protect channel manipulation */ 435 spinlock_t lock; 436 437 /* 438 * Hardware channel thread of PL330 DMAC. NULL if the channel is 439 * available. 440 */ 441 struct pl330_thread *thread; 442 443 /* For D-to-M and M-to-D channels */ 444 int burst_sz; /* the peripheral fifo width */ 445 int burst_len; /* the number of burst */ 446 dma_addr_t fifo_addr; 447 448 /* for cyclic capability */ 449 bool cyclic; 450 451 /* for runtime pm tracking */ 452 bool active; 453 }; 454 455 struct pl330_dmac { 456 /* DMA-Engine Device */ 457 struct dma_device ddma; 458 459 /* Holds info about sg limitations */ 460 struct device_dma_parameters dma_parms; 461 462 /* Pool of descriptors available for the DMAC's channels */ 463 struct list_head desc_pool; 464 /* To protect desc_pool manipulation */ 465 spinlock_t pool_lock; 466 467 /* Size of MicroCode buffers for each channel. */ 468 unsigned mcbufsz; 469 /* ioremap'ed address of PL330 registers. */ 470 void __iomem *base; 471 /* Populated by the PL330 core driver during pl330_add */ 472 struct pl330_config pcfg; 473 474 spinlock_t lock; 475 /* Maximum possible events/irqs */ 476 int events[32]; 477 /* BUS address of MicroCode buffer */ 478 dma_addr_t mcode_bus; 479 /* CPU address of MicroCode buffer */ 480 void *mcode_cpu; 481 /* List of all Channel threads */ 482 struct pl330_thread *channels; 483 /* Pointer to the MANAGER thread */ 484 struct pl330_thread *manager; 485 /* To handle bad news in interrupt */ 486 struct tasklet_struct tasks; 487 struct _pl330_tbd dmac_tbd; 488 /* State of DMAC operation */ 489 enum pl330_dmac_state state; 490 /* Holds list of reqs with due callbacks */ 491 struct list_head req_done; 492 493 /* Peripheral channels connected to this DMAC */ 494 unsigned int num_peripherals; 495 struct dma_pl330_chan *peripherals; /* keep at end */ 496 int quirks; 497 }; 498 499 static struct pl330_of_quirks { 500 char *quirk; 501 int id; 502 } of_quirks[] = { 503 { 504 .quirk = "arm,pl330-broken-no-flushp", 505 .id = PL330_QUIRK_BROKEN_NO_FLUSHP, 506 } 507 }; 508 509 struct dma_pl330_desc { 510 /* To attach to a queue as child */ 511 struct list_head node; 512 513 /* Descriptor for the DMA Engine API */ 514 struct dma_async_tx_descriptor txd; 515 516 /* Xfer for PL330 core */ 517 struct pl330_xfer px; 518 519 struct pl330_reqcfg rqcfg; 520 521 enum desc_status status; 522 523 int bytes_requested; 524 bool last; 525 526 /* The channel which currently holds this desc */ 527 struct dma_pl330_chan *pchan; 528 529 enum dma_transfer_direction rqtype; 530 /* Index of peripheral for the xfer. */ 531 unsigned peri:5; 532 /* Hook to attach to DMAC's list of reqs with due callback */ 533 struct list_head rqd; 534 }; 535 536 struct _xfer_spec { 537 u32 ccr; 538 struct dma_pl330_desc *desc; 539 }; 540 541 static inline bool _queue_empty(struct pl330_thread *thrd) 542 { 543 return thrd->req[0].desc == NULL && thrd->req[1].desc == NULL; 544 } 545 546 static inline bool _queue_full(struct pl330_thread *thrd) 547 { 548 return thrd->req[0].desc != NULL && thrd->req[1].desc != NULL; 549 } 550 551 static inline bool is_manager(struct pl330_thread *thrd) 552 { 553 return thrd->dmac->manager == thrd; 554 } 555 556 /* If manager of the thread is in Non-Secure mode */ 557 static inline bool _manager_ns(struct pl330_thread *thrd) 558 { 559 return (thrd->dmac->pcfg.mode & DMAC_MODE_NS) ? true : false; 560 } 561 562 static inline u32 get_revision(u32 periph_id) 563 { 564 return (periph_id >> PERIPH_REV_SHIFT) & PERIPH_REV_MASK; 565 } 566 567 static inline u32 _emit_ADDH(unsigned dry_run, u8 buf[], 568 enum pl330_dst da, u16 val) 569 { 570 if (dry_run) 571 return SZ_DMAADDH; 572 573 buf[0] = CMD_DMAADDH; 574 buf[0] |= (da << 1); 575 buf[1] = val; 576 buf[2] = val >> 8; 577 578 PL330_DBGCMD_DUMP(SZ_DMAADDH, "\tDMAADDH %s %u\n", 579 da == 1 ? "DA" : "SA", val); 580 581 return SZ_DMAADDH; 582 } 583 584 static inline u32 _emit_END(unsigned dry_run, u8 buf[]) 585 { 586 if (dry_run) 587 return SZ_DMAEND; 588 589 buf[0] = CMD_DMAEND; 590 591 PL330_DBGCMD_DUMP(SZ_DMAEND, "\tDMAEND\n"); 592 593 return SZ_DMAEND; 594 } 595 596 static inline u32 _emit_FLUSHP(unsigned dry_run, u8 buf[], u8 peri) 597 { 598 if (dry_run) 599 return SZ_DMAFLUSHP; 600 601 buf[0] = CMD_DMAFLUSHP; 602 603 peri &= 0x1f; 604 peri <<= 3; 605 buf[1] = peri; 606 607 PL330_DBGCMD_DUMP(SZ_DMAFLUSHP, "\tDMAFLUSHP %u\n", peri >> 3); 608 609 return SZ_DMAFLUSHP; 610 } 611 612 static inline u32 _emit_LD(unsigned dry_run, u8 buf[], enum pl330_cond cond) 613 { 614 if (dry_run) 615 return SZ_DMALD; 616 617 buf[0] = CMD_DMALD; 618 619 if (cond == SINGLE) 620 buf[0] |= (0 << 1) | (1 << 0); 621 else if (cond == BURST) 622 buf[0] |= (1 << 1) | (1 << 0); 623 624 PL330_DBGCMD_DUMP(SZ_DMALD, "\tDMALD%c\n", 625 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 626 627 return SZ_DMALD; 628 } 629 630 static inline u32 _emit_LDP(unsigned dry_run, u8 buf[], 631 enum pl330_cond cond, u8 peri) 632 { 633 if (dry_run) 634 return SZ_DMALDP; 635 636 buf[0] = CMD_DMALDP; 637 638 if (cond == BURST) 639 buf[0] |= (1 << 1); 640 641 peri &= 0x1f; 642 peri <<= 3; 643 buf[1] = peri; 644 645 PL330_DBGCMD_DUMP(SZ_DMALDP, "\tDMALDP%c %u\n", 646 cond == SINGLE ? 'S' : 'B', peri >> 3); 647 648 return SZ_DMALDP; 649 } 650 651 static inline u32 _emit_LP(unsigned dry_run, u8 buf[], 652 unsigned loop, u8 cnt) 653 { 654 if (dry_run) 655 return SZ_DMALP; 656 657 buf[0] = CMD_DMALP; 658 659 if (loop) 660 buf[0] |= (1 << 1); 661 662 cnt--; /* DMAC increments by 1 internally */ 663 buf[1] = cnt; 664 665 PL330_DBGCMD_DUMP(SZ_DMALP, "\tDMALP_%c %u\n", loop ? '1' : '0', cnt); 666 667 return SZ_DMALP; 668 } 669 670 struct _arg_LPEND { 671 enum pl330_cond cond; 672 bool forever; 673 unsigned loop; 674 u8 bjump; 675 }; 676 677 static inline u32 _emit_LPEND(unsigned dry_run, u8 buf[], 678 const struct _arg_LPEND *arg) 679 { 680 enum pl330_cond cond = arg->cond; 681 bool forever = arg->forever; 682 unsigned loop = arg->loop; 683 u8 bjump = arg->bjump; 684 685 if (dry_run) 686 return SZ_DMALPEND; 687 688 buf[0] = CMD_DMALPEND; 689 690 if (loop) 691 buf[0] |= (1 << 2); 692 693 if (!forever) 694 buf[0] |= (1 << 4); 695 696 if (cond == SINGLE) 697 buf[0] |= (0 << 1) | (1 << 0); 698 else if (cond == BURST) 699 buf[0] |= (1 << 1) | (1 << 0); 700 701 buf[1] = bjump; 702 703 PL330_DBGCMD_DUMP(SZ_DMALPEND, "\tDMALP%s%c_%c bjmpto_%x\n", 704 forever ? "FE" : "END", 705 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A'), 706 loop ? '1' : '0', 707 bjump); 708 709 return SZ_DMALPEND; 710 } 711 712 static inline u32 _emit_KILL(unsigned dry_run, u8 buf[]) 713 { 714 if (dry_run) 715 return SZ_DMAKILL; 716 717 buf[0] = CMD_DMAKILL; 718 719 return SZ_DMAKILL; 720 } 721 722 static inline u32 _emit_MOV(unsigned dry_run, u8 buf[], 723 enum dmamov_dst dst, u32 val) 724 { 725 if (dry_run) 726 return SZ_DMAMOV; 727 728 buf[0] = CMD_DMAMOV; 729 buf[1] = dst; 730 buf[2] = val; 731 buf[3] = val >> 8; 732 buf[4] = val >> 16; 733 buf[5] = val >> 24; 734 735 PL330_DBGCMD_DUMP(SZ_DMAMOV, "\tDMAMOV %s 0x%x\n", 736 dst == SAR ? "SAR" : (dst == DAR ? "DAR" : "CCR"), val); 737 738 return SZ_DMAMOV; 739 } 740 741 static inline u32 _emit_NOP(unsigned dry_run, u8 buf[]) 742 { 743 if (dry_run) 744 return SZ_DMANOP; 745 746 buf[0] = CMD_DMANOP; 747 748 PL330_DBGCMD_DUMP(SZ_DMANOP, "\tDMANOP\n"); 749 750 return SZ_DMANOP; 751 } 752 753 static inline u32 _emit_RMB(unsigned dry_run, u8 buf[]) 754 { 755 if (dry_run) 756 return SZ_DMARMB; 757 758 buf[0] = CMD_DMARMB; 759 760 PL330_DBGCMD_DUMP(SZ_DMARMB, "\tDMARMB\n"); 761 762 return SZ_DMARMB; 763 } 764 765 static inline u32 _emit_SEV(unsigned dry_run, u8 buf[], u8 ev) 766 { 767 if (dry_run) 768 return SZ_DMASEV; 769 770 buf[0] = CMD_DMASEV; 771 772 ev &= 0x1f; 773 ev <<= 3; 774 buf[1] = ev; 775 776 PL330_DBGCMD_DUMP(SZ_DMASEV, "\tDMASEV %u\n", ev >> 3); 777 778 return SZ_DMASEV; 779 } 780 781 static inline u32 _emit_ST(unsigned dry_run, u8 buf[], enum pl330_cond cond) 782 { 783 if (dry_run) 784 return SZ_DMAST; 785 786 buf[0] = CMD_DMAST; 787 788 if (cond == SINGLE) 789 buf[0] |= (0 << 1) | (1 << 0); 790 else if (cond == BURST) 791 buf[0] |= (1 << 1) | (1 << 0); 792 793 PL330_DBGCMD_DUMP(SZ_DMAST, "\tDMAST%c\n", 794 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'A')); 795 796 return SZ_DMAST; 797 } 798 799 static inline u32 _emit_STP(unsigned dry_run, u8 buf[], 800 enum pl330_cond cond, u8 peri) 801 { 802 if (dry_run) 803 return SZ_DMASTP; 804 805 buf[0] = CMD_DMASTP; 806 807 if (cond == BURST) 808 buf[0] |= (1 << 1); 809 810 peri &= 0x1f; 811 peri <<= 3; 812 buf[1] = peri; 813 814 PL330_DBGCMD_DUMP(SZ_DMASTP, "\tDMASTP%c %u\n", 815 cond == SINGLE ? 'S' : 'B', peri >> 3); 816 817 return SZ_DMASTP; 818 } 819 820 static inline u32 _emit_STZ(unsigned dry_run, u8 buf[]) 821 { 822 if (dry_run) 823 return SZ_DMASTZ; 824 825 buf[0] = CMD_DMASTZ; 826 827 PL330_DBGCMD_DUMP(SZ_DMASTZ, "\tDMASTZ\n"); 828 829 return SZ_DMASTZ; 830 } 831 832 static inline u32 _emit_WFE(unsigned dry_run, u8 buf[], u8 ev, 833 unsigned invalidate) 834 { 835 if (dry_run) 836 return SZ_DMAWFE; 837 838 buf[0] = CMD_DMAWFE; 839 840 ev &= 0x1f; 841 ev <<= 3; 842 buf[1] = ev; 843 844 if (invalidate) 845 buf[1] |= (1 << 1); 846 847 PL330_DBGCMD_DUMP(SZ_DMAWFE, "\tDMAWFE %u%s\n", 848 ev >> 3, invalidate ? ", I" : ""); 849 850 return SZ_DMAWFE; 851 } 852 853 static inline u32 _emit_WFP(unsigned dry_run, u8 buf[], 854 enum pl330_cond cond, u8 peri) 855 { 856 if (dry_run) 857 return SZ_DMAWFP; 858 859 buf[0] = CMD_DMAWFP; 860 861 if (cond == SINGLE) 862 buf[0] |= (0 << 1) | (0 << 0); 863 else if (cond == BURST) 864 buf[0] |= (1 << 1) | (0 << 0); 865 else 866 buf[0] |= (0 << 1) | (1 << 0); 867 868 peri &= 0x1f; 869 peri <<= 3; 870 buf[1] = peri; 871 872 PL330_DBGCMD_DUMP(SZ_DMAWFP, "\tDMAWFP%c %u\n", 873 cond == SINGLE ? 'S' : (cond == BURST ? 'B' : 'P'), peri >> 3); 874 875 return SZ_DMAWFP; 876 } 877 878 static inline u32 _emit_WMB(unsigned dry_run, u8 buf[]) 879 { 880 if (dry_run) 881 return SZ_DMAWMB; 882 883 buf[0] = CMD_DMAWMB; 884 885 PL330_DBGCMD_DUMP(SZ_DMAWMB, "\tDMAWMB\n"); 886 887 return SZ_DMAWMB; 888 } 889 890 struct _arg_GO { 891 u8 chan; 892 u32 addr; 893 unsigned ns; 894 }; 895 896 static inline u32 _emit_GO(unsigned dry_run, u8 buf[], 897 const struct _arg_GO *arg) 898 { 899 u8 chan = arg->chan; 900 u32 addr = arg->addr; 901 unsigned ns = arg->ns; 902 903 if (dry_run) 904 return SZ_DMAGO; 905 906 buf[0] = CMD_DMAGO; 907 buf[0] |= (ns << 1); 908 buf[1] = chan & 0x7; 909 buf[2] = addr; 910 buf[3] = addr >> 8; 911 buf[4] = addr >> 16; 912 buf[5] = addr >> 24; 913 914 return SZ_DMAGO; 915 } 916 917 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 918 919 /* Returns Time-Out */ 920 static bool _until_dmac_idle(struct pl330_thread *thrd) 921 { 922 void __iomem *regs = thrd->dmac->base; 923 unsigned long loops = msecs_to_loops(5); 924 925 do { 926 /* Until Manager is Idle */ 927 if (!(readl(regs + DBGSTATUS) & DBG_BUSY)) 928 break; 929 930 cpu_relax(); 931 } while (--loops); 932 933 if (!loops) 934 return true; 935 936 return false; 937 } 938 939 static inline void _execute_DBGINSN(struct pl330_thread *thrd, 940 u8 insn[], bool as_manager) 941 { 942 void __iomem *regs = thrd->dmac->base; 943 u32 val; 944 945 val = (insn[0] << 16) | (insn[1] << 24); 946 if (!as_manager) { 947 val |= (1 << 0); 948 val |= (thrd->id << 8); /* Channel Number */ 949 } 950 writel(val, regs + DBGINST0); 951 952 val = le32_to_cpu(*((__le32 *)&insn[2])); 953 writel(val, regs + DBGINST1); 954 955 /* If timed out due to halted state-machine */ 956 if (_until_dmac_idle(thrd)) { 957 dev_err(thrd->dmac->ddma.dev, "DMAC halted!\n"); 958 return; 959 } 960 961 /* Get going */ 962 writel(0, regs + DBGCMD); 963 } 964 965 static inline u32 _state(struct pl330_thread *thrd) 966 { 967 void __iomem *regs = thrd->dmac->base; 968 u32 val; 969 970 if (is_manager(thrd)) 971 val = readl(regs + DS) & 0xf; 972 else 973 val = readl(regs + CS(thrd->id)) & 0xf; 974 975 switch (val) { 976 case DS_ST_STOP: 977 return PL330_STATE_STOPPED; 978 case DS_ST_EXEC: 979 return PL330_STATE_EXECUTING; 980 case DS_ST_CMISS: 981 return PL330_STATE_CACHEMISS; 982 case DS_ST_UPDTPC: 983 return PL330_STATE_UPDTPC; 984 case DS_ST_WFE: 985 return PL330_STATE_WFE; 986 case DS_ST_FAULT: 987 return PL330_STATE_FAULTING; 988 case DS_ST_ATBRR: 989 if (is_manager(thrd)) 990 return PL330_STATE_INVALID; 991 else 992 return PL330_STATE_ATBARRIER; 993 case DS_ST_QBUSY: 994 if (is_manager(thrd)) 995 return PL330_STATE_INVALID; 996 else 997 return PL330_STATE_QUEUEBUSY; 998 case DS_ST_WFP: 999 if (is_manager(thrd)) 1000 return PL330_STATE_INVALID; 1001 else 1002 return PL330_STATE_WFP; 1003 case DS_ST_KILL: 1004 if (is_manager(thrd)) 1005 return PL330_STATE_INVALID; 1006 else 1007 return PL330_STATE_KILLING; 1008 case DS_ST_CMPLT: 1009 if (is_manager(thrd)) 1010 return PL330_STATE_INVALID; 1011 else 1012 return PL330_STATE_COMPLETING; 1013 case DS_ST_FLTCMP: 1014 if (is_manager(thrd)) 1015 return PL330_STATE_INVALID; 1016 else 1017 return PL330_STATE_FAULT_COMPLETING; 1018 default: 1019 return PL330_STATE_INVALID; 1020 } 1021 } 1022 1023 static void _stop(struct pl330_thread *thrd) 1024 { 1025 void __iomem *regs = thrd->dmac->base; 1026 u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1027 1028 if (_state(thrd) == PL330_STATE_FAULT_COMPLETING) 1029 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1030 1031 /* Return if nothing needs to be done */ 1032 if (_state(thrd) == PL330_STATE_COMPLETING 1033 || _state(thrd) == PL330_STATE_KILLING 1034 || _state(thrd) == PL330_STATE_STOPPED) 1035 return; 1036 1037 _emit_KILL(0, insn); 1038 1039 /* Stop generating interrupts for SEV */ 1040 writel(readl(regs + INTEN) & ~(1 << thrd->ev), regs + INTEN); 1041 1042 _execute_DBGINSN(thrd, insn, is_manager(thrd)); 1043 } 1044 1045 /* Start doing req 'idx' of thread 'thrd' */ 1046 static bool _trigger(struct pl330_thread *thrd) 1047 { 1048 void __iomem *regs = thrd->dmac->base; 1049 struct _pl330_req *req; 1050 struct dma_pl330_desc *desc; 1051 struct _arg_GO go; 1052 unsigned ns; 1053 u8 insn[6] = {0, 0, 0, 0, 0, 0}; 1054 int idx; 1055 1056 /* Return if already ACTIVE */ 1057 if (_state(thrd) != PL330_STATE_STOPPED) 1058 return true; 1059 1060 idx = 1 - thrd->lstenq; 1061 if (thrd->req[idx].desc != NULL) { 1062 req = &thrd->req[idx]; 1063 } else { 1064 idx = thrd->lstenq; 1065 if (thrd->req[idx].desc != NULL) 1066 req = &thrd->req[idx]; 1067 else 1068 req = NULL; 1069 } 1070 1071 /* Return if no request */ 1072 if (!req) 1073 return true; 1074 1075 /* Return if req is running */ 1076 if (idx == thrd->req_running) 1077 return true; 1078 1079 desc = req->desc; 1080 1081 ns = desc->rqcfg.nonsecure ? 1 : 0; 1082 1083 /* See 'Abort Sources' point-4 at Page 2-25 */ 1084 if (_manager_ns(thrd) && !ns) 1085 dev_info(thrd->dmac->ddma.dev, "%s:%d Recipe for ABORT!\n", 1086 __func__, __LINE__); 1087 1088 go.chan = thrd->id; 1089 go.addr = req->mc_bus; 1090 go.ns = ns; 1091 _emit_GO(0, insn, &go); 1092 1093 /* Set to generate interrupts for SEV */ 1094 writel(readl(regs + INTEN) | (1 << thrd->ev), regs + INTEN); 1095 1096 /* Only manager can execute GO */ 1097 _execute_DBGINSN(thrd, insn, true); 1098 1099 thrd->req_running = idx; 1100 1101 return true; 1102 } 1103 1104 static bool _start(struct pl330_thread *thrd) 1105 { 1106 switch (_state(thrd)) { 1107 case PL330_STATE_FAULT_COMPLETING: 1108 UNTIL(thrd, PL330_STATE_FAULTING | PL330_STATE_KILLING); 1109 1110 if (_state(thrd) == PL330_STATE_KILLING) 1111 UNTIL(thrd, PL330_STATE_STOPPED) 1112 1113 case PL330_STATE_FAULTING: 1114 _stop(thrd); 1115 1116 case PL330_STATE_KILLING: 1117 case PL330_STATE_COMPLETING: 1118 UNTIL(thrd, PL330_STATE_STOPPED) 1119 1120 case PL330_STATE_STOPPED: 1121 return _trigger(thrd); 1122 1123 case PL330_STATE_WFP: 1124 case PL330_STATE_QUEUEBUSY: 1125 case PL330_STATE_ATBARRIER: 1126 case PL330_STATE_UPDTPC: 1127 case PL330_STATE_CACHEMISS: 1128 case PL330_STATE_EXECUTING: 1129 return true; 1130 1131 case PL330_STATE_WFE: /* For RESUME, nothing yet */ 1132 default: 1133 return false; 1134 } 1135 } 1136 1137 static inline int _ldst_memtomem(unsigned dry_run, u8 buf[], 1138 const struct _xfer_spec *pxs, int cyc) 1139 { 1140 int off = 0; 1141 struct pl330_config *pcfg = pxs->desc->rqcfg.pcfg; 1142 1143 /* check lock-up free version */ 1144 if (get_revision(pcfg->periph_id) >= PERIPH_REV_R1P0) { 1145 while (cyc--) { 1146 off += _emit_LD(dry_run, &buf[off], ALWAYS); 1147 off += _emit_ST(dry_run, &buf[off], ALWAYS); 1148 } 1149 } else { 1150 while (cyc--) { 1151 off += _emit_LD(dry_run, &buf[off], ALWAYS); 1152 off += _emit_RMB(dry_run, &buf[off]); 1153 off += _emit_ST(dry_run, &buf[off], ALWAYS); 1154 off += _emit_WMB(dry_run, &buf[off]); 1155 } 1156 } 1157 1158 return off; 1159 } 1160 1161 static inline int _ldst_devtomem(struct pl330_dmac *pl330, unsigned dry_run, 1162 u8 buf[], const struct _xfer_spec *pxs, 1163 int cyc) 1164 { 1165 int off = 0; 1166 enum pl330_cond cond; 1167 1168 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) 1169 cond = BURST; 1170 else 1171 cond = SINGLE; 1172 1173 while (cyc--) { 1174 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); 1175 off += _emit_LDP(dry_run, &buf[off], cond, pxs->desc->peri); 1176 off += _emit_ST(dry_run, &buf[off], ALWAYS); 1177 1178 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) 1179 off += _emit_FLUSHP(dry_run, &buf[off], 1180 pxs->desc->peri); 1181 } 1182 1183 return off; 1184 } 1185 1186 static inline int _ldst_memtodev(struct pl330_dmac *pl330, 1187 unsigned dry_run, u8 buf[], 1188 const struct _xfer_spec *pxs, int cyc) 1189 { 1190 int off = 0; 1191 enum pl330_cond cond; 1192 1193 if (pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) 1194 cond = BURST; 1195 else 1196 cond = SINGLE; 1197 1198 while (cyc--) { 1199 off += _emit_WFP(dry_run, &buf[off], cond, pxs->desc->peri); 1200 off += _emit_LD(dry_run, &buf[off], ALWAYS); 1201 off += _emit_STP(dry_run, &buf[off], cond, pxs->desc->peri); 1202 1203 if (!(pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP)) 1204 off += _emit_FLUSHP(dry_run, &buf[off], 1205 pxs->desc->peri); 1206 } 1207 1208 return off; 1209 } 1210 1211 static int _bursts(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], 1212 const struct _xfer_spec *pxs, int cyc) 1213 { 1214 int off = 0; 1215 1216 switch (pxs->desc->rqtype) { 1217 case DMA_MEM_TO_DEV: 1218 off += _ldst_memtodev(pl330, dry_run, &buf[off], pxs, cyc); 1219 break; 1220 case DMA_DEV_TO_MEM: 1221 off += _ldst_devtomem(pl330, dry_run, &buf[off], pxs, cyc); 1222 break; 1223 case DMA_MEM_TO_MEM: 1224 off += _ldst_memtomem(dry_run, &buf[off], pxs, cyc); 1225 break; 1226 default: 1227 off += 0x40000000; /* Scare off the Client */ 1228 break; 1229 } 1230 1231 return off; 1232 } 1233 1234 /* Returns bytes consumed and updates bursts */ 1235 static inline int _loop(struct pl330_dmac *pl330, unsigned dry_run, u8 buf[], 1236 unsigned long *bursts, const struct _xfer_spec *pxs) 1237 { 1238 int cyc, cycmax, szlp, szlpend, szbrst, off; 1239 unsigned lcnt0, lcnt1, ljmp0, ljmp1; 1240 struct _arg_LPEND lpend; 1241 1242 if (*bursts == 1) 1243 return _bursts(pl330, dry_run, buf, pxs, 1); 1244 1245 /* Max iterations possible in DMALP is 256 */ 1246 if (*bursts >= 256*256) { 1247 lcnt1 = 256; 1248 lcnt0 = 256; 1249 cyc = *bursts / lcnt1 / lcnt0; 1250 } else if (*bursts > 256) { 1251 lcnt1 = 256; 1252 lcnt0 = *bursts / lcnt1; 1253 cyc = 1; 1254 } else { 1255 lcnt1 = *bursts; 1256 lcnt0 = 0; 1257 cyc = 1; 1258 } 1259 1260 szlp = _emit_LP(1, buf, 0, 0); 1261 szbrst = _bursts(pl330, 1, buf, pxs, 1); 1262 1263 lpend.cond = ALWAYS; 1264 lpend.forever = false; 1265 lpend.loop = 0; 1266 lpend.bjump = 0; 1267 szlpend = _emit_LPEND(1, buf, &lpend); 1268 1269 if (lcnt0) { 1270 szlp *= 2; 1271 szlpend *= 2; 1272 } 1273 1274 /* 1275 * Max bursts that we can unroll due to limit on the 1276 * size of backward jump that can be encoded in DMALPEND 1277 * which is 8-bits and hence 255 1278 */ 1279 cycmax = (255 - (szlp + szlpend)) / szbrst; 1280 1281 cyc = (cycmax < cyc) ? cycmax : cyc; 1282 1283 off = 0; 1284 1285 if (lcnt0) { 1286 off += _emit_LP(dry_run, &buf[off], 0, lcnt0); 1287 ljmp0 = off; 1288 } 1289 1290 off += _emit_LP(dry_run, &buf[off], 1, lcnt1); 1291 ljmp1 = off; 1292 1293 off += _bursts(pl330, dry_run, &buf[off], pxs, cyc); 1294 1295 lpend.cond = ALWAYS; 1296 lpend.forever = false; 1297 lpend.loop = 1; 1298 lpend.bjump = off - ljmp1; 1299 off += _emit_LPEND(dry_run, &buf[off], &lpend); 1300 1301 if (lcnt0) { 1302 lpend.cond = ALWAYS; 1303 lpend.forever = false; 1304 lpend.loop = 0; 1305 lpend.bjump = off - ljmp0; 1306 off += _emit_LPEND(dry_run, &buf[off], &lpend); 1307 } 1308 1309 *bursts = lcnt1 * cyc; 1310 if (lcnt0) 1311 *bursts *= lcnt0; 1312 1313 return off; 1314 } 1315 1316 static inline int _setup_loops(struct pl330_dmac *pl330, 1317 unsigned dry_run, u8 buf[], 1318 const struct _xfer_spec *pxs) 1319 { 1320 struct pl330_xfer *x = &pxs->desc->px; 1321 u32 ccr = pxs->ccr; 1322 unsigned long c, bursts = BYTE_TO_BURST(x->bytes, ccr); 1323 int off = 0; 1324 1325 while (bursts) { 1326 c = bursts; 1327 off += _loop(pl330, dry_run, &buf[off], &c, pxs); 1328 bursts -= c; 1329 } 1330 1331 return off; 1332 } 1333 1334 static inline int _setup_xfer(struct pl330_dmac *pl330, 1335 unsigned dry_run, u8 buf[], 1336 const struct _xfer_spec *pxs) 1337 { 1338 struct pl330_xfer *x = &pxs->desc->px; 1339 int off = 0; 1340 1341 /* DMAMOV SAR, x->src_addr */ 1342 off += _emit_MOV(dry_run, &buf[off], SAR, x->src_addr); 1343 /* DMAMOV DAR, x->dst_addr */ 1344 off += _emit_MOV(dry_run, &buf[off], DAR, x->dst_addr); 1345 1346 /* Setup Loop(s) */ 1347 off += _setup_loops(pl330, dry_run, &buf[off], pxs); 1348 1349 return off; 1350 } 1351 1352 /* 1353 * A req is a sequence of one or more xfer units. 1354 * Returns the number of bytes taken to setup the MC for the req. 1355 */ 1356 static int _setup_req(struct pl330_dmac *pl330, unsigned dry_run, 1357 struct pl330_thread *thrd, unsigned index, 1358 struct _xfer_spec *pxs) 1359 { 1360 struct _pl330_req *req = &thrd->req[index]; 1361 struct pl330_xfer *x; 1362 u8 *buf = req->mc_cpu; 1363 int off = 0; 1364 1365 PL330_DBGMC_START(req->mc_bus); 1366 1367 /* DMAMOV CCR, ccr */ 1368 off += _emit_MOV(dry_run, &buf[off], CCR, pxs->ccr); 1369 1370 x = &pxs->desc->px; 1371 /* Error if xfer length is not aligned at burst size */ 1372 if (x->bytes % (BRST_SIZE(pxs->ccr) * BRST_LEN(pxs->ccr))) 1373 return -EINVAL; 1374 1375 off += _setup_xfer(pl330, dry_run, &buf[off], pxs); 1376 1377 /* DMASEV peripheral/event */ 1378 off += _emit_SEV(dry_run, &buf[off], thrd->ev); 1379 /* DMAEND */ 1380 off += _emit_END(dry_run, &buf[off]); 1381 1382 return off; 1383 } 1384 1385 static inline u32 _prepare_ccr(const struct pl330_reqcfg *rqc) 1386 { 1387 u32 ccr = 0; 1388 1389 if (rqc->src_inc) 1390 ccr |= CC_SRCINC; 1391 1392 if (rqc->dst_inc) 1393 ccr |= CC_DSTINC; 1394 1395 /* We set same protection levels for Src and DST for now */ 1396 if (rqc->privileged) 1397 ccr |= CC_SRCPRI | CC_DSTPRI; 1398 if (rqc->nonsecure) 1399 ccr |= CC_SRCNS | CC_DSTNS; 1400 if (rqc->insnaccess) 1401 ccr |= CC_SRCIA | CC_DSTIA; 1402 1403 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_SRCBRSTLEN_SHFT); 1404 ccr |= (((rqc->brst_len - 1) & 0xf) << CC_DSTBRSTLEN_SHFT); 1405 1406 ccr |= (rqc->brst_size << CC_SRCBRSTSIZE_SHFT); 1407 ccr |= (rqc->brst_size << CC_DSTBRSTSIZE_SHFT); 1408 1409 ccr |= (rqc->scctl << CC_SRCCCTRL_SHFT); 1410 ccr |= (rqc->dcctl << CC_DSTCCTRL_SHFT); 1411 1412 ccr |= (rqc->swap << CC_SWAP_SHFT); 1413 1414 return ccr; 1415 } 1416 1417 /* 1418 * Submit a list of xfers after which the client wants notification. 1419 * Client is not notified after each xfer unit, just once after all 1420 * xfer units are done or some error occurs. 1421 */ 1422 static int pl330_submit_req(struct pl330_thread *thrd, 1423 struct dma_pl330_desc *desc) 1424 { 1425 struct pl330_dmac *pl330 = thrd->dmac; 1426 struct _xfer_spec xs; 1427 unsigned long flags; 1428 unsigned idx; 1429 u32 ccr; 1430 int ret = 0; 1431 1432 if (pl330->state == DYING 1433 || pl330->dmac_tbd.reset_chan & (1 << thrd->id)) { 1434 dev_info(thrd->dmac->ddma.dev, "%s:%d\n", 1435 __func__, __LINE__); 1436 return -EAGAIN; 1437 } 1438 1439 /* If request for non-existing peripheral */ 1440 if (desc->rqtype != DMA_MEM_TO_MEM && 1441 desc->peri >= pl330->pcfg.num_peri) { 1442 dev_info(thrd->dmac->ddma.dev, 1443 "%s:%d Invalid peripheral(%u)!\n", 1444 __func__, __LINE__, desc->peri); 1445 return -EINVAL; 1446 } 1447 1448 spin_lock_irqsave(&pl330->lock, flags); 1449 1450 if (_queue_full(thrd)) { 1451 ret = -EAGAIN; 1452 goto xfer_exit; 1453 } 1454 1455 /* Prefer Secure Channel */ 1456 if (!_manager_ns(thrd)) 1457 desc->rqcfg.nonsecure = 0; 1458 else 1459 desc->rqcfg.nonsecure = 1; 1460 1461 ccr = _prepare_ccr(&desc->rqcfg); 1462 1463 idx = thrd->req[0].desc == NULL ? 0 : 1; 1464 1465 xs.ccr = ccr; 1466 xs.desc = desc; 1467 1468 /* First dry run to check if req is acceptable */ 1469 ret = _setup_req(pl330, 1, thrd, idx, &xs); 1470 if (ret < 0) 1471 goto xfer_exit; 1472 1473 if (ret > pl330->mcbufsz / 2) { 1474 dev_info(pl330->ddma.dev, "%s:%d Try increasing mcbufsz (%i/%i)\n", 1475 __func__, __LINE__, ret, pl330->mcbufsz / 2); 1476 ret = -ENOMEM; 1477 goto xfer_exit; 1478 } 1479 1480 /* Hook the request */ 1481 thrd->lstenq = idx; 1482 thrd->req[idx].desc = desc; 1483 _setup_req(pl330, 0, thrd, idx, &xs); 1484 1485 ret = 0; 1486 1487 xfer_exit: 1488 spin_unlock_irqrestore(&pl330->lock, flags); 1489 1490 return ret; 1491 } 1492 1493 static void dma_pl330_rqcb(struct dma_pl330_desc *desc, enum pl330_op_err err) 1494 { 1495 struct dma_pl330_chan *pch; 1496 unsigned long flags; 1497 1498 if (!desc) 1499 return; 1500 1501 pch = desc->pchan; 1502 1503 /* If desc aborted */ 1504 if (!pch) 1505 return; 1506 1507 spin_lock_irqsave(&pch->lock, flags); 1508 1509 desc->status = DONE; 1510 1511 spin_unlock_irqrestore(&pch->lock, flags); 1512 1513 tasklet_schedule(&pch->task); 1514 } 1515 1516 static void pl330_dotask(unsigned long data) 1517 { 1518 struct pl330_dmac *pl330 = (struct pl330_dmac *) data; 1519 unsigned long flags; 1520 int i; 1521 1522 spin_lock_irqsave(&pl330->lock, flags); 1523 1524 /* The DMAC itself gone nuts */ 1525 if (pl330->dmac_tbd.reset_dmac) { 1526 pl330->state = DYING; 1527 /* Reset the manager too */ 1528 pl330->dmac_tbd.reset_mngr = true; 1529 /* Clear the reset flag */ 1530 pl330->dmac_tbd.reset_dmac = false; 1531 } 1532 1533 if (pl330->dmac_tbd.reset_mngr) { 1534 _stop(pl330->manager); 1535 /* Reset all channels */ 1536 pl330->dmac_tbd.reset_chan = (1 << pl330->pcfg.num_chan) - 1; 1537 /* Clear the reset flag */ 1538 pl330->dmac_tbd.reset_mngr = false; 1539 } 1540 1541 for (i = 0; i < pl330->pcfg.num_chan; i++) { 1542 1543 if (pl330->dmac_tbd.reset_chan & (1 << i)) { 1544 struct pl330_thread *thrd = &pl330->channels[i]; 1545 void __iomem *regs = pl330->base; 1546 enum pl330_op_err err; 1547 1548 _stop(thrd); 1549 1550 if (readl(regs + FSC) & (1 << thrd->id)) 1551 err = PL330_ERR_FAIL; 1552 else 1553 err = PL330_ERR_ABORT; 1554 1555 spin_unlock_irqrestore(&pl330->lock, flags); 1556 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, err); 1557 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, err); 1558 spin_lock_irqsave(&pl330->lock, flags); 1559 1560 thrd->req[0].desc = NULL; 1561 thrd->req[1].desc = NULL; 1562 thrd->req_running = -1; 1563 1564 /* Clear the reset flag */ 1565 pl330->dmac_tbd.reset_chan &= ~(1 << i); 1566 } 1567 } 1568 1569 spin_unlock_irqrestore(&pl330->lock, flags); 1570 1571 return; 1572 } 1573 1574 /* Returns 1 if state was updated, 0 otherwise */ 1575 static int pl330_update(struct pl330_dmac *pl330) 1576 { 1577 struct dma_pl330_desc *descdone, *tmp; 1578 unsigned long flags; 1579 void __iomem *regs; 1580 u32 val; 1581 int id, ev, ret = 0; 1582 1583 regs = pl330->base; 1584 1585 spin_lock_irqsave(&pl330->lock, flags); 1586 1587 val = readl(regs + FSM) & 0x1; 1588 if (val) 1589 pl330->dmac_tbd.reset_mngr = true; 1590 else 1591 pl330->dmac_tbd.reset_mngr = false; 1592 1593 val = readl(regs + FSC) & ((1 << pl330->pcfg.num_chan) - 1); 1594 pl330->dmac_tbd.reset_chan |= val; 1595 if (val) { 1596 int i = 0; 1597 while (i < pl330->pcfg.num_chan) { 1598 if (val & (1 << i)) { 1599 dev_info(pl330->ddma.dev, 1600 "Reset Channel-%d\t CS-%x FTC-%x\n", 1601 i, readl(regs + CS(i)), 1602 readl(regs + FTC(i))); 1603 _stop(&pl330->channels[i]); 1604 } 1605 i++; 1606 } 1607 } 1608 1609 /* Check which event happened i.e, thread notified */ 1610 val = readl(regs + ES); 1611 if (pl330->pcfg.num_events < 32 1612 && val & ~((1 << pl330->pcfg.num_events) - 1)) { 1613 pl330->dmac_tbd.reset_dmac = true; 1614 dev_err(pl330->ddma.dev, "%s:%d Unexpected!\n", __func__, 1615 __LINE__); 1616 ret = 1; 1617 goto updt_exit; 1618 } 1619 1620 for (ev = 0; ev < pl330->pcfg.num_events; ev++) { 1621 if (val & (1 << ev)) { /* Event occurred */ 1622 struct pl330_thread *thrd; 1623 u32 inten = readl(regs + INTEN); 1624 int active; 1625 1626 /* Clear the event */ 1627 if (inten & (1 << ev)) 1628 writel(1 << ev, regs + INTCLR); 1629 1630 ret = 1; 1631 1632 id = pl330->events[ev]; 1633 1634 thrd = &pl330->channels[id]; 1635 1636 active = thrd->req_running; 1637 if (active == -1) /* Aborted */ 1638 continue; 1639 1640 /* Detach the req */ 1641 descdone = thrd->req[active].desc; 1642 thrd->req[active].desc = NULL; 1643 1644 thrd->req_running = -1; 1645 1646 /* Get going again ASAP */ 1647 _start(thrd); 1648 1649 /* For now, just make a list of callbacks to be done */ 1650 list_add_tail(&descdone->rqd, &pl330->req_done); 1651 } 1652 } 1653 1654 /* Now that we are in no hurry, do the callbacks */ 1655 list_for_each_entry_safe(descdone, tmp, &pl330->req_done, rqd) { 1656 list_del(&descdone->rqd); 1657 spin_unlock_irqrestore(&pl330->lock, flags); 1658 dma_pl330_rqcb(descdone, PL330_ERR_NONE); 1659 spin_lock_irqsave(&pl330->lock, flags); 1660 } 1661 1662 updt_exit: 1663 spin_unlock_irqrestore(&pl330->lock, flags); 1664 1665 if (pl330->dmac_tbd.reset_dmac 1666 || pl330->dmac_tbd.reset_mngr 1667 || pl330->dmac_tbd.reset_chan) { 1668 ret = 1; 1669 tasklet_schedule(&pl330->tasks); 1670 } 1671 1672 return ret; 1673 } 1674 1675 /* Reserve an event */ 1676 static inline int _alloc_event(struct pl330_thread *thrd) 1677 { 1678 struct pl330_dmac *pl330 = thrd->dmac; 1679 int ev; 1680 1681 for (ev = 0; ev < pl330->pcfg.num_events; ev++) 1682 if (pl330->events[ev] == -1) { 1683 pl330->events[ev] = thrd->id; 1684 return ev; 1685 } 1686 1687 return -1; 1688 } 1689 1690 static bool _chan_ns(const struct pl330_dmac *pl330, int i) 1691 { 1692 return pl330->pcfg.irq_ns & (1 << i); 1693 } 1694 1695 /* Upon success, returns IdentityToken for the 1696 * allocated channel, NULL otherwise. 1697 */ 1698 static struct pl330_thread *pl330_request_channel(struct pl330_dmac *pl330) 1699 { 1700 struct pl330_thread *thrd = NULL; 1701 int chans, i; 1702 1703 if (pl330->state == DYING) 1704 return NULL; 1705 1706 chans = pl330->pcfg.num_chan; 1707 1708 for (i = 0; i < chans; i++) { 1709 thrd = &pl330->channels[i]; 1710 if ((thrd->free) && (!_manager_ns(thrd) || 1711 _chan_ns(pl330, i))) { 1712 thrd->ev = _alloc_event(thrd); 1713 if (thrd->ev >= 0) { 1714 thrd->free = false; 1715 thrd->lstenq = 1; 1716 thrd->req[0].desc = NULL; 1717 thrd->req[1].desc = NULL; 1718 thrd->req_running = -1; 1719 break; 1720 } 1721 } 1722 thrd = NULL; 1723 } 1724 1725 return thrd; 1726 } 1727 1728 /* Release an event */ 1729 static inline void _free_event(struct pl330_thread *thrd, int ev) 1730 { 1731 struct pl330_dmac *pl330 = thrd->dmac; 1732 1733 /* If the event is valid and was held by the thread */ 1734 if (ev >= 0 && ev < pl330->pcfg.num_events 1735 && pl330->events[ev] == thrd->id) 1736 pl330->events[ev] = -1; 1737 } 1738 1739 static void pl330_release_channel(struct pl330_thread *thrd) 1740 { 1741 struct pl330_dmac *pl330; 1742 1743 if (!thrd || thrd->free) 1744 return; 1745 1746 _stop(thrd); 1747 1748 dma_pl330_rqcb(thrd->req[1 - thrd->lstenq].desc, PL330_ERR_ABORT); 1749 dma_pl330_rqcb(thrd->req[thrd->lstenq].desc, PL330_ERR_ABORT); 1750 1751 pl330 = thrd->dmac; 1752 1753 _free_event(thrd, thrd->ev); 1754 thrd->free = true; 1755 } 1756 1757 /* Initialize the structure for PL330 configuration, that can be used 1758 * by the client driver the make best use of the DMAC 1759 */ 1760 static void read_dmac_config(struct pl330_dmac *pl330) 1761 { 1762 void __iomem *regs = pl330->base; 1763 u32 val; 1764 1765 val = readl(regs + CRD) >> CRD_DATA_WIDTH_SHIFT; 1766 val &= CRD_DATA_WIDTH_MASK; 1767 pl330->pcfg.data_bus_width = 8 * (1 << val); 1768 1769 val = readl(regs + CRD) >> CRD_DATA_BUFF_SHIFT; 1770 val &= CRD_DATA_BUFF_MASK; 1771 pl330->pcfg.data_buf_dep = val + 1; 1772 1773 val = readl(regs + CR0) >> CR0_NUM_CHANS_SHIFT; 1774 val &= CR0_NUM_CHANS_MASK; 1775 val += 1; 1776 pl330->pcfg.num_chan = val; 1777 1778 val = readl(regs + CR0); 1779 if (val & CR0_PERIPH_REQ_SET) { 1780 val = (val >> CR0_NUM_PERIPH_SHIFT) & CR0_NUM_PERIPH_MASK; 1781 val += 1; 1782 pl330->pcfg.num_peri = val; 1783 pl330->pcfg.peri_ns = readl(regs + CR4); 1784 } else { 1785 pl330->pcfg.num_peri = 0; 1786 } 1787 1788 val = readl(regs + CR0); 1789 if (val & CR0_BOOT_MAN_NS) 1790 pl330->pcfg.mode |= DMAC_MODE_NS; 1791 else 1792 pl330->pcfg.mode &= ~DMAC_MODE_NS; 1793 1794 val = readl(regs + CR0) >> CR0_NUM_EVENTS_SHIFT; 1795 val &= CR0_NUM_EVENTS_MASK; 1796 val += 1; 1797 pl330->pcfg.num_events = val; 1798 1799 pl330->pcfg.irq_ns = readl(regs + CR3); 1800 } 1801 1802 static inline void _reset_thread(struct pl330_thread *thrd) 1803 { 1804 struct pl330_dmac *pl330 = thrd->dmac; 1805 1806 thrd->req[0].mc_cpu = pl330->mcode_cpu 1807 + (thrd->id * pl330->mcbufsz); 1808 thrd->req[0].mc_bus = pl330->mcode_bus 1809 + (thrd->id * pl330->mcbufsz); 1810 thrd->req[0].desc = NULL; 1811 1812 thrd->req[1].mc_cpu = thrd->req[0].mc_cpu 1813 + pl330->mcbufsz / 2; 1814 thrd->req[1].mc_bus = thrd->req[0].mc_bus 1815 + pl330->mcbufsz / 2; 1816 thrd->req[1].desc = NULL; 1817 1818 thrd->req_running = -1; 1819 } 1820 1821 static int dmac_alloc_threads(struct pl330_dmac *pl330) 1822 { 1823 int chans = pl330->pcfg.num_chan; 1824 struct pl330_thread *thrd; 1825 int i; 1826 1827 /* Allocate 1 Manager and 'chans' Channel threads */ 1828 pl330->channels = kzalloc((1 + chans) * sizeof(*thrd), 1829 GFP_KERNEL); 1830 if (!pl330->channels) 1831 return -ENOMEM; 1832 1833 /* Init Channel threads */ 1834 for (i = 0; i < chans; i++) { 1835 thrd = &pl330->channels[i]; 1836 thrd->id = i; 1837 thrd->dmac = pl330; 1838 _reset_thread(thrd); 1839 thrd->free = true; 1840 } 1841 1842 /* MANAGER is indexed at the end */ 1843 thrd = &pl330->channels[chans]; 1844 thrd->id = chans; 1845 thrd->dmac = pl330; 1846 thrd->free = false; 1847 pl330->manager = thrd; 1848 1849 return 0; 1850 } 1851 1852 static int dmac_alloc_resources(struct pl330_dmac *pl330) 1853 { 1854 int chans = pl330->pcfg.num_chan; 1855 int ret; 1856 1857 /* 1858 * Alloc MicroCode buffer for 'chans' Channel threads. 1859 * A channel's buffer offset is (Channel_Id * MCODE_BUFF_PERCHAN) 1860 */ 1861 pl330->mcode_cpu = dma_alloc_attrs(pl330->ddma.dev, 1862 chans * pl330->mcbufsz, 1863 &pl330->mcode_bus, GFP_KERNEL, 1864 DMA_ATTR_PRIVILEGED); 1865 if (!pl330->mcode_cpu) { 1866 dev_err(pl330->ddma.dev, "%s:%d Can't allocate memory!\n", 1867 __func__, __LINE__); 1868 return -ENOMEM; 1869 } 1870 1871 ret = dmac_alloc_threads(pl330); 1872 if (ret) { 1873 dev_err(pl330->ddma.dev, "%s:%d Can't to create channels for DMAC!\n", 1874 __func__, __LINE__); 1875 dma_free_coherent(pl330->ddma.dev, 1876 chans * pl330->mcbufsz, 1877 pl330->mcode_cpu, pl330->mcode_bus); 1878 return ret; 1879 } 1880 1881 return 0; 1882 } 1883 1884 static int pl330_add(struct pl330_dmac *pl330) 1885 { 1886 int i, ret; 1887 1888 /* Check if we can handle this DMAC */ 1889 if ((pl330->pcfg.periph_id & 0xfffff) != PERIPH_ID_VAL) { 1890 dev_err(pl330->ddma.dev, "PERIPH_ID 0x%x !\n", 1891 pl330->pcfg.periph_id); 1892 return -EINVAL; 1893 } 1894 1895 /* Read the configuration of the DMAC */ 1896 read_dmac_config(pl330); 1897 1898 if (pl330->pcfg.num_events == 0) { 1899 dev_err(pl330->ddma.dev, "%s:%d Can't work without events!\n", 1900 __func__, __LINE__); 1901 return -EINVAL; 1902 } 1903 1904 spin_lock_init(&pl330->lock); 1905 1906 INIT_LIST_HEAD(&pl330->req_done); 1907 1908 /* Use default MC buffer size if not provided */ 1909 if (!pl330->mcbufsz) 1910 pl330->mcbufsz = MCODE_BUFF_PER_REQ * 2; 1911 1912 /* Mark all events as free */ 1913 for (i = 0; i < pl330->pcfg.num_events; i++) 1914 pl330->events[i] = -1; 1915 1916 /* Allocate resources needed by the DMAC */ 1917 ret = dmac_alloc_resources(pl330); 1918 if (ret) { 1919 dev_err(pl330->ddma.dev, "Unable to create channels for DMAC\n"); 1920 return ret; 1921 } 1922 1923 tasklet_init(&pl330->tasks, pl330_dotask, (unsigned long) pl330); 1924 1925 pl330->state = INIT; 1926 1927 return 0; 1928 } 1929 1930 static int dmac_free_threads(struct pl330_dmac *pl330) 1931 { 1932 struct pl330_thread *thrd; 1933 int i; 1934 1935 /* Release Channel threads */ 1936 for (i = 0; i < pl330->pcfg.num_chan; i++) { 1937 thrd = &pl330->channels[i]; 1938 pl330_release_channel(thrd); 1939 } 1940 1941 /* Free memory */ 1942 kfree(pl330->channels); 1943 1944 return 0; 1945 } 1946 1947 static void pl330_del(struct pl330_dmac *pl330) 1948 { 1949 pl330->state = UNINIT; 1950 1951 tasklet_kill(&pl330->tasks); 1952 1953 /* Free DMAC resources */ 1954 dmac_free_threads(pl330); 1955 1956 dma_free_coherent(pl330->ddma.dev, 1957 pl330->pcfg.num_chan * pl330->mcbufsz, pl330->mcode_cpu, 1958 pl330->mcode_bus); 1959 } 1960 1961 /* forward declaration */ 1962 static struct amba_driver pl330_driver; 1963 1964 static inline struct dma_pl330_chan * 1965 to_pchan(struct dma_chan *ch) 1966 { 1967 if (!ch) 1968 return NULL; 1969 1970 return container_of(ch, struct dma_pl330_chan, chan); 1971 } 1972 1973 static inline struct dma_pl330_desc * 1974 to_desc(struct dma_async_tx_descriptor *tx) 1975 { 1976 return container_of(tx, struct dma_pl330_desc, txd); 1977 } 1978 1979 static inline void fill_queue(struct dma_pl330_chan *pch) 1980 { 1981 struct dma_pl330_desc *desc; 1982 int ret; 1983 1984 list_for_each_entry(desc, &pch->work_list, node) { 1985 1986 /* If already submitted */ 1987 if (desc->status == BUSY) 1988 continue; 1989 1990 ret = pl330_submit_req(pch->thread, desc); 1991 if (!ret) { 1992 desc->status = BUSY; 1993 } else if (ret == -EAGAIN) { 1994 /* QFull or DMAC Dying */ 1995 break; 1996 } else { 1997 /* Unacceptable request */ 1998 desc->status = DONE; 1999 dev_err(pch->dmac->ddma.dev, "%s:%d Bad Desc(%d)\n", 2000 __func__, __LINE__, desc->txd.cookie); 2001 tasklet_schedule(&pch->task); 2002 } 2003 } 2004 } 2005 2006 static void pl330_tasklet(unsigned long data) 2007 { 2008 struct dma_pl330_chan *pch = (struct dma_pl330_chan *)data; 2009 struct dma_pl330_desc *desc, *_dt; 2010 unsigned long flags; 2011 bool power_down = false; 2012 2013 spin_lock_irqsave(&pch->lock, flags); 2014 2015 /* Pick up ripe tomatoes */ 2016 list_for_each_entry_safe(desc, _dt, &pch->work_list, node) 2017 if (desc->status == DONE) { 2018 if (!pch->cyclic) 2019 dma_cookie_complete(&desc->txd); 2020 list_move_tail(&desc->node, &pch->completed_list); 2021 } 2022 2023 /* Try to submit a req imm. next to the last completed cookie */ 2024 fill_queue(pch); 2025 2026 if (list_empty(&pch->work_list)) { 2027 spin_lock(&pch->thread->dmac->lock); 2028 _stop(pch->thread); 2029 spin_unlock(&pch->thread->dmac->lock); 2030 power_down = true; 2031 pch->active = false; 2032 } else { 2033 /* Make sure the PL330 Channel thread is active */ 2034 spin_lock(&pch->thread->dmac->lock); 2035 _start(pch->thread); 2036 spin_unlock(&pch->thread->dmac->lock); 2037 } 2038 2039 while (!list_empty(&pch->completed_list)) { 2040 struct dmaengine_desc_callback cb; 2041 2042 desc = list_first_entry(&pch->completed_list, 2043 struct dma_pl330_desc, node); 2044 2045 dmaengine_desc_get_callback(&desc->txd, &cb); 2046 2047 if (pch->cyclic) { 2048 desc->status = PREP; 2049 list_move_tail(&desc->node, &pch->work_list); 2050 if (power_down) { 2051 pch->active = true; 2052 spin_lock(&pch->thread->dmac->lock); 2053 _start(pch->thread); 2054 spin_unlock(&pch->thread->dmac->lock); 2055 power_down = false; 2056 } 2057 } else { 2058 desc->status = FREE; 2059 list_move_tail(&desc->node, &pch->dmac->desc_pool); 2060 } 2061 2062 dma_descriptor_unmap(&desc->txd); 2063 2064 if (dmaengine_desc_callback_valid(&cb)) { 2065 spin_unlock_irqrestore(&pch->lock, flags); 2066 dmaengine_desc_callback_invoke(&cb, NULL); 2067 spin_lock_irqsave(&pch->lock, flags); 2068 } 2069 } 2070 spin_unlock_irqrestore(&pch->lock, flags); 2071 2072 /* If work list empty, power down */ 2073 if (power_down) { 2074 pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2075 pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 2076 } 2077 } 2078 2079 static struct dma_chan *of_dma_pl330_xlate(struct of_phandle_args *dma_spec, 2080 struct of_dma *ofdma) 2081 { 2082 int count = dma_spec->args_count; 2083 struct pl330_dmac *pl330 = ofdma->of_dma_data; 2084 unsigned int chan_id; 2085 2086 if (!pl330) 2087 return NULL; 2088 2089 if (count != 1) 2090 return NULL; 2091 2092 chan_id = dma_spec->args[0]; 2093 if (chan_id >= pl330->num_peripherals) 2094 return NULL; 2095 2096 return dma_get_slave_channel(&pl330->peripherals[chan_id].chan); 2097 } 2098 2099 static int pl330_alloc_chan_resources(struct dma_chan *chan) 2100 { 2101 struct dma_pl330_chan *pch = to_pchan(chan); 2102 struct pl330_dmac *pl330 = pch->dmac; 2103 unsigned long flags; 2104 2105 spin_lock_irqsave(&pl330->lock, flags); 2106 2107 dma_cookie_init(chan); 2108 pch->cyclic = false; 2109 2110 pch->thread = pl330_request_channel(pl330); 2111 if (!pch->thread) { 2112 spin_unlock_irqrestore(&pl330->lock, flags); 2113 return -ENOMEM; 2114 } 2115 2116 tasklet_init(&pch->task, pl330_tasklet, (unsigned long) pch); 2117 2118 spin_unlock_irqrestore(&pl330->lock, flags); 2119 2120 return 1; 2121 } 2122 2123 static int pl330_config(struct dma_chan *chan, 2124 struct dma_slave_config *slave_config) 2125 { 2126 struct dma_pl330_chan *pch = to_pchan(chan); 2127 2128 if (slave_config->direction == DMA_MEM_TO_DEV) { 2129 if (slave_config->dst_addr) 2130 pch->fifo_addr = slave_config->dst_addr; 2131 if (slave_config->dst_addr_width) 2132 pch->burst_sz = __ffs(slave_config->dst_addr_width); 2133 if (slave_config->dst_maxburst) 2134 pch->burst_len = slave_config->dst_maxburst; 2135 } else if (slave_config->direction == DMA_DEV_TO_MEM) { 2136 if (slave_config->src_addr) 2137 pch->fifo_addr = slave_config->src_addr; 2138 if (slave_config->src_addr_width) 2139 pch->burst_sz = __ffs(slave_config->src_addr_width); 2140 if (slave_config->src_maxburst) 2141 pch->burst_len = slave_config->src_maxburst; 2142 } 2143 2144 return 0; 2145 } 2146 2147 static int pl330_terminate_all(struct dma_chan *chan) 2148 { 2149 struct dma_pl330_chan *pch = to_pchan(chan); 2150 struct dma_pl330_desc *desc; 2151 unsigned long flags; 2152 struct pl330_dmac *pl330 = pch->dmac; 2153 LIST_HEAD(list); 2154 bool power_down = false; 2155 2156 pm_runtime_get_sync(pl330->ddma.dev); 2157 spin_lock_irqsave(&pch->lock, flags); 2158 spin_lock(&pl330->lock); 2159 _stop(pch->thread); 2160 spin_unlock(&pl330->lock); 2161 2162 pch->thread->req[0].desc = NULL; 2163 pch->thread->req[1].desc = NULL; 2164 pch->thread->req_running = -1; 2165 power_down = pch->active; 2166 pch->active = false; 2167 2168 /* Mark all desc done */ 2169 list_for_each_entry(desc, &pch->submitted_list, node) { 2170 desc->status = FREE; 2171 dma_cookie_complete(&desc->txd); 2172 } 2173 2174 list_for_each_entry(desc, &pch->work_list , node) { 2175 desc->status = FREE; 2176 dma_cookie_complete(&desc->txd); 2177 } 2178 2179 list_splice_tail_init(&pch->submitted_list, &pl330->desc_pool); 2180 list_splice_tail_init(&pch->work_list, &pl330->desc_pool); 2181 list_splice_tail_init(&pch->completed_list, &pl330->desc_pool); 2182 spin_unlock_irqrestore(&pch->lock, flags); 2183 pm_runtime_mark_last_busy(pl330->ddma.dev); 2184 if (power_down) 2185 pm_runtime_put_autosuspend(pl330->ddma.dev); 2186 pm_runtime_put_autosuspend(pl330->ddma.dev); 2187 2188 return 0; 2189 } 2190 2191 /* 2192 * We don't support DMA_RESUME command because of hardware 2193 * limitations, so after pausing the channel we cannot restore 2194 * it to active state. We have to terminate channel and setup 2195 * DMA transfer again. This pause feature was implemented to 2196 * allow safely read residue before channel termination. 2197 */ 2198 static int pl330_pause(struct dma_chan *chan) 2199 { 2200 struct dma_pl330_chan *pch = to_pchan(chan); 2201 struct pl330_dmac *pl330 = pch->dmac; 2202 unsigned long flags; 2203 2204 pm_runtime_get_sync(pl330->ddma.dev); 2205 spin_lock_irqsave(&pch->lock, flags); 2206 2207 spin_lock(&pl330->lock); 2208 _stop(pch->thread); 2209 spin_unlock(&pl330->lock); 2210 2211 spin_unlock_irqrestore(&pch->lock, flags); 2212 pm_runtime_mark_last_busy(pl330->ddma.dev); 2213 pm_runtime_put_autosuspend(pl330->ddma.dev); 2214 2215 return 0; 2216 } 2217 2218 static void pl330_free_chan_resources(struct dma_chan *chan) 2219 { 2220 struct dma_pl330_chan *pch = to_pchan(chan); 2221 struct pl330_dmac *pl330 = pch->dmac; 2222 unsigned long flags; 2223 2224 tasklet_kill(&pch->task); 2225 2226 pm_runtime_get_sync(pch->dmac->ddma.dev); 2227 spin_lock_irqsave(&pl330->lock, flags); 2228 2229 pl330_release_channel(pch->thread); 2230 pch->thread = NULL; 2231 2232 if (pch->cyclic) 2233 list_splice_tail_init(&pch->work_list, &pch->dmac->desc_pool); 2234 2235 spin_unlock_irqrestore(&pl330->lock, flags); 2236 pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2237 pm_runtime_put_autosuspend(pch->dmac->ddma.dev); 2238 } 2239 2240 static int pl330_get_current_xferred_count(struct dma_pl330_chan *pch, 2241 struct dma_pl330_desc *desc) 2242 { 2243 struct pl330_thread *thrd = pch->thread; 2244 struct pl330_dmac *pl330 = pch->dmac; 2245 void __iomem *regs = thrd->dmac->base; 2246 u32 val, addr; 2247 2248 pm_runtime_get_sync(pl330->ddma.dev); 2249 val = addr = 0; 2250 if (desc->rqcfg.src_inc) { 2251 val = readl(regs + SA(thrd->id)); 2252 addr = desc->px.src_addr; 2253 } else { 2254 val = readl(regs + DA(thrd->id)); 2255 addr = desc->px.dst_addr; 2256 } 2257 pm_runtime_mark_last_busy(pch->dmac->ddma.dev); 2258 pm_runtime_put_autosuspend(pl330->ddma.dev); 2259 2260 /* If DMAMOV hasn't finished yet, SAR/DAR can be zero */ 2261 if (!val) 2262 return 0; 2263 2264 return val - addr; 2265 } 2266 2267 static enum dma_status 2268 pl330_tx_status(struct dma_chan *chan, dma_cookie_t cookie, 2269 struct dma_tx_state *txstate) 2270 { 2271 enum dma_status ret; 2272 unsigned long flags; 2273 struct dma_pl330_desc *desc, *running = NULL, *last_enq = NULL; 2274 struct dma_pl330_chan *pch = to_pchan(chan); 2275 unsigned int transferred, residual = 0; 2276 2277 ret = dma_cookie_status(chan, cookie, txstate); 2278 2279 if (!txstate) 2280 return ret; 2281 2282 if (ret == DMA_COMPLETE) 2283 goto out; 2284 2285 spin_lock_irqsave(&pch->lock, flags); 2286 spin_lock(&pch->thread->dmac->lock); 2287 2288 if (pch->thread->req_running != -1) 2289 running = pch->thread->req[pch->thread->req_running].desc; 2290 2291 last_enq = pch->thread->req[pch->thread->lstenq].desc; 2292 2293 /* Check in pending list */ 2294 list_for_each_entry(desc, &pch->work_list, node) { 2295 if (desc->status == DONE) 2296 transferred = desc->bytes_requested; 2297 else if (running && desc == running) 2298 transferred = 2299 pl330_get_current_xferred_count(pch, desc); 2300 else if (desc->status == BUSY) 2301 /* 2302 * Busy but not running means either just enqueued, 2303 * or finished and not yet marked done 2304 */ 2305 if (desc == last_enq) 2306 transferred = 0; 2307 else 2308 transferred = desc->bytes_requested; 2309 else 2310 transferred = 0; 2311 residual += desc->bytes_requested - transferred; 2312 if (desc->txd.cookie == cookie) { 2313 switch (desc->status) { 2314 case DONE: 2315 ret = DMA_COMPLETE; 2316 break; 2317 case PREP: 2318 case BUSY: 2319 ret = DMA_IN_PROGRESS; 2320 break; 2321 default: 2322 WARN_ON(1); 2323 } 2324 break; 2325 } 2326 if (desc->last) 2327 residual = 0; 2328 } 2329 spin_unlock(&pch->thread->dmac->lock); 2330 spin_unlock_irqrestore(&pch->lock, flags); 2331 2332 out: 2333 dma_set_residue(txstate, residual); 2334 2335 return ret; 2336 } 2337 2338 static void pl330_issue_pending(struct dma_chan *chan) 2339 { 2340 struct dma_pl330_chan *pch = to_pchan(chan); 2341 unsigned long flags; 2342 2343 spin_lock_irqsave(&pch->lock, flags); 2344 if (list_empty(&pch->work_list)) { 2345 /* 2346 * Warn on nothing pending. Empty submitted_list may 2347 * break our pm_runtime usage counter as it is 2348 * updated on work_list emptiness status. 2349 */ 2350 WARN_ON(list_empty(&pch->submitted_list)); 2351 pch->active = true; 2352 pm_runtime_get_sync(pch->dmac->ddma.dev); 2353 } 2354 list_splice_tail_init(&pch->submitted_list, &pch->work_list); 2355 spin_unlock_irqrestore(&pch->lock, flags); 2356 2357 pl330_tasklet((unsigned long)pch); 2358 } 2359 2360 /* 2361 * We returned the last one of the circular list of descriptor(s) 2362 * from prep_xxx, so the argument to submit corresponds to the last 2363 * descriptor of the list. 2364 */ 2365 static dma_cookie_t pl330_tx_submit(struct dma_async_tx_descriptor *tx) 2366 { 2367 struct dma_pl330_desc *desc, *last = to_desc(tx); 2368 struct dma_pl330_chan *pch = to_pchan(tx->chan); 2369 dma_cookie_t cookie; 2370 unsigned long flags; 2371 2372 spin_lock_irqsave(&pch->lock, flags); 2373 2374 /* Assign cookies to all nodes */ 2375 while (!list_empty(&last->node)) { 2376 desc = list_entry(last->node.next, struct dma_pl330_desc, node); 2377 if (pch->cyclic) { 2378 desc->txd.callback = last->txd.callback; 2379 desc->txd.callback_param = last->txd.callback_param; 2380 } 2381 desc->last = false; 2382 2383 dma_cookie_assign(&desc->txd); 2384 2385 list_move_tail(&desc->node, &pch->submitted_list); 2386 } 2387 2388 last->last = true; 2389 cookie = dma_cookie_assign(&last->txd); 2390 list_add_tail(&last->node, &pch->submitted_list); 2391 spin_unlock_irqrestore(&pch->lock, flags); 2392 2393 return cookie; 2394 } 2395 2396 static inline void _init_desc(struct dma_pl330_desc *desc) 2397 { 2398 desc->rqcfg.swap = SWAP_NO; 2399 desc->rqcfg.scctl = CCTRL0; 2400 desc->rqcfg.dcctl = CCTRL0; 2401 desc->txd.tx_submit = pl330_tx_submit; 2402 2403 INIT_LIST_HEAD(&desc->node); 2404 } 2405 2406 /* Returns the number of descriptors added to the DMAC pool */ 2407 static int add_desc(struct pl330_dmac *pl330, gfp_t flg, int count) 2408 { 2409 struct dma_pl330_desc *desc; 2410 unsigned long flags; 2411 int i; 2412 2413 desc = kcalloc(count, sizeof(*desc), flg); 2414 if (!desc) 2415 return 0; 2416 2417 spin_lock_irqsave(&pl330->pool_lock, flags); 2418 2419 for (i = 0; i < count; i++) { 2420 _init_desc(&desc[i]); 2421 list_add_tail(&desc[i].node, &pl330->desc_pool); 2422 } 2423 2424 spin_unlock_irqrestore(&pl330->pool_lock, flags); 2425 2426 return count; 2427 } 2428 2429 static struct dma_pl330_desc *pluck_desc(struct pl330_dmac *pl330) 2430 { 2431 struct dma_pl330_desc *desc = NULL; 2432 unsigned long flags; 2433 2434 spin_lock_irqsave(&pl330->pool_lock, flags); 2435 2436 if (!list_empty(&pl330->desc_pool)) { 2437 desc = list_entry(pl330->desc_pool.next, 2438 struct dma_pl330_desc, node); 2439 2440 list_del_init(&desc->node); 2441 2442 desc->status = PREP; 2443 desc->txd.callback = NULL; 2444 } 2445 2446 spin_unlock_irqrestore(&pl330->pool_lock, flags); 2447 2448 return desc; 2449 } 2450 2451 static struct dma_pl330_desc *pl330_get_desc(struct dma_pl330_chan *pch) 2452 { 2453 struct pl330_dmac *pl330 = pch->dmac; 2454 u8 *peri_id = pch->chan.private; 2455 struct dma_pl330_desc *desc; 2456 2457 /* Pluck one desc from the pool of DMAC */ 2458 desc = pluck_desc(pl330); 2459 2460 /* If the DMAC pool is empty, alloc new */ 2461 if (!desc) { 2462 if (!add_desc(pl330, GFP_ATOMIC, 1)) 2463 return NULL; 2464 2465 /* Try again */ 2466 desc = pluck_desc(pl330); 2467 if (!desc) { 2468 dev_err(pch->dmac->ddma.dev, 2469 "%s:%d ALERT!\n", __func__, __LINE__); 2470 return NULL; 2471 } 2472 } 2473 2474 /* Initialize the descriptor */ 2475 desc->pchan = pch; 2476 desc->txd.cookie = 0; 2477 async_tx_ack(&desc->txd); 2478 2479 desc->peri = peri_id ? pch->chan.chan_id : 0; 2480 desc->rqcfg.pcfg = &pch->dmac->pcfg; 2481 2482 dma_async_tx_descriptor_init(&desc->txd, &pch->chan); 2483 2484 return desc; 2485 } 2486 2487 static inline void fill_px(struct pl330_xfer *px, 2488 dma_addr_t dst, dma_addr_t src, size_t len) 2489 { 2490 px->bytes = len; 2491 px->dst_addr = dst; 2492 px->src_addr = src; 2493 } 2494 2495 static struct dma_pl330_desc * 2496 __pl330_prep_dma_memcpy(struct dma_pl330_chan *pch, dma_addr_t dst, 2497 dma_addr_t src, size_t len) 2498 { 2499 struct dma_pl330_desc *desc = pl330_get_desc(pch); 2500 2501 if (!desc) { 2502 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 2503 __func__, __LINE__); 2504 return NULL; 2505 } 2506 2507 /* 2508 * Ideally we should lookout for reqs bigger than 2509 * those that can be programmed with 256 bytes of 2510 * MC buffer, but considering a req size is seldom 2511 * going to be word-unaligned and more than 200MB, 2512 * we take it easy. 2513 * Also, should the limit is reached we'd rather 2514 * have the platform increase MC buffer size than 2515 * complicating this API driver. 2516 */ 2517 fill_px(&desc->px, dst, src, len); 2518 2519 return desc; 2520 } 2521 2522 /* Call after fixing burst size */ 2523 static inline int get_burst_len(struct dma_pl330_desc *desc, size_t len) 2524 { 2525 struct dma_pl330_chan *pch = desc->pchan; 2526 struct pl330_dmac *pl330 = pch->dmac; 2527 int burst_len; 2528 2529 burst_len = pl330->pcfg.data_bus_width / 8; 2530 burst_len *= pl330->pcfg.data_buf_dep / pl330->pcfg.num_chan; 2531 burst_len >>= desc->rqcfg.brst_size; 2532 2533 /* src/dst_burst_len can't be more than 16 */ 2534 if (burst_len > 16) 2535 burst_len = 16; 2536 2537 while (burst_len > 1) { 2538 if (!(len % (burst_len << desc->rqcfg.brst_size))) 2539 break; 2540 burst_len--; 2541 } 2542 2543 return burst_len; 2544 } 2545 2546 static struct dma_async_tx_descriptor *pl330_prep_dma_cyclic( 2547 struct dma_chan *chan, dma_addr_t dma_addr, size_t len, 2548 size_t period_len, enum dma_transfer_direction direction, 2549 unsigned long flags) 2550 { 2551 struct dma_pl330_desc *desc = NULL, *first = NULL; 2552 struct dma_pl330_chan *pch = to_pchan(chan); 2553 struct pl330_dmac *pl330 = pch->dmac; 2554 unsigned int i; 2555 dma_addr_t dst; 2556 dma_addr_t src; 2557 2558 if (len % period_len != 0) 2559 return NULL; 2560 2561 if (!is_slave_direction(direction)) { 2562 dev_err(pch->dmac->ddma.dev, "%s:%d Invalid dma direction\n", 2563 __func__, __LINE__); 2564 return NULL; 2565 } 2566 2567 for (i = 0; i < len / period_len; i++) { 2568 desc = pl330_get_desc(pch); 2569 if (!desc) { 2570 dev_err(pch->dmac->ddma.dev, "%s:%d Unable to fetch desc\n", 2571 __func__, __LINE__); 2572 2573 if (!first) 2574 return NULL; 2575 2576 spin_lock_irqsave(&pl330->pool_lock, flags); 2577 2578 while (!list_empty(&first->node)) { 2579 desc = list_entry(first->node.next, 2580 struct dma_pl330_desc, node); 2581 list_move_tail(&desc->node, &pl330->desc_pool); 2582 } 2583 2584 list_move_tail(&first->node, &pl330->desc_pool); 2585 2586 spin_unlock_irqrestore(&pl330->pool_lock, flags); 2587 2588 return NULL; 2589 } 2590 2591 switch (direction) { 2592 case DMA_MEM_TO_DEV: 2593 desc->rqcfg.src_inc = 1; 2594 desc->rqcfg.dst_inc = 0; 2595 src = dma_addr; 2596 dst = pch->fifo_addr; 2597 break; 2598 case DMA_DEV_TO_MEM: 2599 desc->rqcfg.src_inc = 0; 2600 desc->rqcfg.dst_inc = 1; 2601 src = pch->fifo_addr; 2602 dst = dma_addr; 2603 break; 2604 default: 2605 break; 2606 } 2607 2608 desc->rqtype = direction; 2609 desc->rqcfg.brst_size = pch->burst_sz; 2610 desc->rqcfg.brst_len = 1; 2611 desc->bytes_requested = period_len; 2612 fill_px(&desc->px, dst, src, period_len); 2613 2614 if (!first) 2615 first = desc; 2616 else 2617 list_add_tail(&desc->node, &first->node); 2618 2619 dma_addr += period_len; 2620 } 2621 2622 if (!desc) 2623 return NULL; 2624 2625 pch->cyclic = true; 2626 desc->txd.flags = flags; 2627 2628 return &desc->txd; 2629 } 2630 2631 static struct dma_async_tx_descriptor * 2632 pl330_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, 2633 dma_addr_t src, size_t len, unsigned long flags) 2634 { 2635 struct dma_pl330_desc *desc; 2636 struct dma_pl330_chan *pch = to_pchan(chan); 2637 struct pl330_dmac *pl330; 2638 int burst; 2639 2640 if (unlikely(!pch || !len)) 2641 return NULL; 2642 2643 pl330 = pch->dmac; 2644 2645 desc = __pl330_prep_dma_memcpy(pch, dst, src, len); 2646 if (!desc) 2647 return NULL; 2648 2649 desc->rqcfg.src_inc = 1; 2650 desc->rqcfg.dst_inc = 1; 2651 desc->rqtype = DMA_MEM_TO_MEM; 2652 2653 /* Select max possible burst size */ 2654 burst = pl330->pcfg.data_bus_width / 8; 2655 2656 /* 2657 * Make sure we use a burst size that aligns with all the memcpy 2658 * parameters because our DMA programming algorithm doesn't cope with 2659 * transfers which straddle an entry in the DMA device's MFIFO. 2660 */ 2661 while ((src | dst | len) & (burst - 1)) 2662 burst /= 2; 2663 2664 desc->rqcfg.brst_size = 0; 2665 while (burst != (1 << desc->rqcfg.brst_size)) 2666 desc->rqcfg.brst_size++; 2667 2668 /* 2669 * If burst size is smaller than bus width then make sure we only 2670 * transfer one at a time to avoid a burst stradling an MFIFO entry. 2671 */ 2672 if (desc->rqcfg.brst_size * 8 < pl330->pcfg.data_bus_width) 2673 desc->rqcfg.brst_len = 1; 2674 2675 desc->rqcfg.brst_len = get_burst_len(desc, len); 2676 desc->bytes_requested = len; 2677 2678 desc->txd.flags = flags; 2679 2680 return &desc->txd; 2681 } 2682 2683 static void __pl330_giveback_desc(struct pl330_dmac *pl330, 2684 struct dma_pl330_desc *first) 2685 { 2686 unsigned long flags; 2687 struct dma_pl330_desc *desc; 2688 2689 if (!first) 2690 return; 2691 2692 spin_lock_irqsave(&pl330->pool_lock, flags); 2693 2694 while (!list_empty(&first->node)) { 2695 desc = list_entry(first->node.next, 2696 struct dma_pl330_desc, node); 2697 list_move_tail(&desc->node, &pl330->desc_pool); 2698 } 2699 2700 list_move_tail(&first->node, &pl330->desc_pool); 2701 2702 spin_unlock_irqrestore(&pl330->pool_lock, flags); 2703 } 2704 2705 static struct dma_async_tx_descriptor * 2706 pl330_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 2707 unsigned int sg_len, enum dma_transfer_direction direction, 2708 unsigned long flg, void *context) 2709 { 2710 struct dma_pl330_desc *first, *desc = NULL; 2711 struct dma_pl330_chan *pch = to_pchan(chan); 2712 struct scatterlist *sg; 2713 int i; 2714 dma_addr_t addr; 2715 2716 if (unlikely(!pch || !sgl || !sg_len)) 2717 return NULL; 2718 2719 addr = pch->fifo_addr; 2720 2721 first = NULL; 2722 2723 for_each_sg(sgl, sg, sg_len, i) { 2724 2725 desc = pl330_get_desc(pch); 2726 if (!desc) { 2727 struct pl330_dmac *pl330 = pch->dmac; 2728 2729 dev_err(pch->dmac->ddma.dev, 2730 "%s:%d Unable to fetch desc\n", 2731 __func__, __LINE__); 2732 __pl330_giveback_desc(pl330, first); 2733 2734 return NULL; 2735 } 2736 2737 if (!first) 2738 first = desc; 2739 else 2740 list_add_tail(&desc->node, &first->node); 2741 2742 if (direction == DMA_MEM_TO_DEV) { 2743 desc->rqcfg.src_inc = 1; 2744 desc->rqcfg.dst_inc = 0; 2745 fill_px(&desc->px, 2746 addr, sg_dma_address(sg), sg_dma_len(sg)); 2747 } else { 2748 desc->rqcfg.src_inc = 0; 2749 desc->rqcfg.dst_inc = 1; 2750 fill_px(&desc->px, 2751 sg_dma_address(sg), addr, sg_dma_len(sg)); 2752 } 2753 2754 desc->rqcfg.brst_size = pch->burst_sz; 2755 desc->rqcfg.brst_len = 1; 2756 desc->rqtype = direction; 2757 desc->bytes_requested = sg_dma_len(sg); 2758 } 2759 2760 /* Return the last desc in the chain */ 2761 desc->txd.flags = flg; 2762 return &desc->txd; 2763 } 2764 2765 static irqreturn_t pl330_irq_handler(int irq, void *data) 2766 { 2767 if (pl330_update(data)) 2768 return IRQ_HANDLED; 2769 else 2770 return IRQ_NONE; 2771 } 2772 2773 #define PL330_DMA_BUSWIDTHS \ 2774 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 2775 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 2776 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 2777 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 2778 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES) 2779 2780 /* 2781 * Runtime PM callbacks are provided by amba/bus.c driver. 2782 * 2783 * It is assumed here that IRQ safe runtime PM is chosen in probe and amba 2784 * bus driver will only disable/enable the clock in runtime PM callbacks. 2785 */ 2786 static int __maybe_unused pl330_suspend(struct device *dev) 2787 { 2788 struct amba_device *pcdev = to_amba_device(dev); 2789 2790 pm_runtime_disable(dev); 2791 2792 if (!pm_runtime_status_suspended(dev)) { 2793 /* amba did not disable the clock */ 2794 amba_pclk_disable(pcdev); 2795 } 2796 amba_pclk_unprepare(pcdev); 2797 2798 return 0; 2799 } 2800 2801 static int __maybe_unused pl330_resume(struct device *dev) 2802 { 2803 struct amba_device *pcdev = to_amba_device(dev); 2804 int ret; 2805 2806 ret = amba_pclk_prepare(pcdev); 2807 if (ret) 2808 return ret; 2809 2810 if (!pm_runtime_status_suspended(dev)) 2811 ret = amba_pclk_enable(pcdev); 2812 2813 pm_runtime_enable(dev); 2814 2815 return ret; 2816 } 2817 2818 static SIMPLE_DEV_PM_OPS(pl330_pm, pl330_suspend, pl330_resume); 2819 2820 static int 2821 pl330_probe(struct amba_device *adev, const struct amba_id *id) 2822 { 2823 struct pl330_config *pcfg; 2824 struct pl330_dmac *pl330; 2825 struct dma_pl330_chan *pch, *_p; 2826 struct dma_device *pd; 2827 struct resource *res; 2828 int i, ret, irq; 2829 int num_chan; 2830 struct device_node *np = adev->dev.of_node; 2831 2832 ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32)); 2833 if (ret) 2834 return ret; 2835 2836 /* Allocate a new DMAC and its Channels */ 2837 pl330 = devm_kzalloc(&adev->dev, sizeof(*pl330), GFP_KERNEL); 2838 if (!pl330) 2839 return -ENOMEM; 2840 2841 pd = &pl330->ddma; 2842 pd->dev = &adev->dev; 2843 2844 pl330->mcbufsz = 0; 2845 2846 /* get quirk */ 2847 for (i = 0; i < ARRAY_SIZE(of_quirks); i++) 2848 if (of_property_read_bool(np, of_quirks[i].quirk)) 2849 pl330->quirks |= of_quirks[i].id; 2850 2851 res = &adev->res; 2852 pl330->base = devm_ioremap_resource(&adev->dev, res); 2853 if (IS_ERR(pl330->base)) 2854 return PTR_ERR(pl330->base); 2855 2856 amba_set_drvdata(adev, pl330); 2857 2858 for (i = 0; i < AMBA_NR_IRQS; i++) { 2859 irq = adev->irq[i]; 2860 if (irq) { 2861 ret = devm_request_irq(&adev->dev, irq, 2862 pl330_irq_handler, 0, 2863 dev_name(&adev->dev), pl330); 2864 if (ret) 2865 return ret; 2866 } else { 2867 break; 2868 } 2869 } 2870 2871 pcfg = &pl330->pcfg; 2872 2873 pcfg->periph_id = adev->periphid; 2874 ret = pl330_add(pl330); 2875 if (ret) 2876 return ret; 2877 2878 INIT_LIST_HEAD(&pl330->desc_pool); 2879 spin_lock_init(&pl330->pool_lock); 2880 2881 /* Create a descriptor pool of default size */ 2882 if (!add_desc(pl330, GFP_KERNEL, NR_DEFAULT_DESC)) 2883 dev_warn(&adev->dev, "unable to allocate desc\n"); 2884 2885 INIT_LIST_HEAD(&pd->channels); 2886 2887 /* Initialize channel parameters */ 2888 num_chan = max_t(int, pcfg->num_peri, pcfg->num_chan); 2889 2890 pl330->num_peripherals = num_chan; 2891 2892 pl330->peripherals = kzalloc(num_chan * sizeof(*pch), GFP_KERNEL); 2893 if (!pl330->peripherals) { 2894 ret = -ENOMEM; 2895 goto probe_err2; 2896 } 2897 2898 for (i = 0; i < num_chan; i++) { 2899 pch = &pl330->peripherals[i]; 2900 2901 pch->chan.private = adev->dev.of_node; 2902 INIT_LIST_HEAD(&pch->submitted_list); 2903 INIT_LIST_HEAD(&pch->work_list); 2904 INIT_LIST_HEAD(&pch->completed_list); 2905 spin_lock_init(&pch->lock); 2906 pch->thread = NULL; 2907 pch->chan.device = pd; 2908 pch->dmac = pl330; 2909 2910 /* Add the channel to the DMAC list */ 2911 list_add_tail(&pch->chan.device_node, &pd->channels); 2912 } 2913 2914 dma_cap_set(DMA_MEMCPY, pd->cap_mask); 2915 if (pcfg->num_peri) { 2916 dma_cap_set(DMA_SLAVE, pd->cap_mask); 2917 dma_cap_set(DMA_CYCLIC, pd->cap_mask); 2918 dma_cap_set(DMA_PRIVATE, pd->cap_mask); 2919 } 2920 2921 pd->device_alloc_chan_resources = pl330_alloc_chan_resources; 2922 pd->device_free_chan_resources = pl330_free_chan_resources; 2923 pd->device_prep_dma_memcpy = pl330_prep_dma_memcpy; 2924 pd->device_prep_dma_cyclic = pl330_prep_dma_cyclic; 2925 pd->device_tx_status = pl330_tx_status; 2926 pd->device_prep_slave_sg = pl330_prep_slave_sg; 2927 pd->device_config = pl330_config; 2928 pd->device_pause = pl330_pause; 2929 pd->device_terminate_all = pl330_terminate_all; 2930 pd->device_issue_pending = pl330_issue_pending; 2931 pd->src_addr_widths = PL330_DMA_BUSWIDTHS; 2932 pd->dst_addr_widths = PL330_DMA_BUSWIDTHS; 2933 pd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 2934 pd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 2935 pd->max_burst = ((pl330->quirks & PL330_QUIRK_BROKEN_NO_FLUSHP) ? 2936 1 : PL330_MAX_BURST); 2937 2938 ret = dma_async_device_register(pd); 2939 if (ret) { 2940 dev_err(&adev->dev, "unable to register DMAC\n"); 2941 goto probe_err3; 2942 } 2943 2944 if (adev->dev.of_node) { 2945 ret = of_dma_controller_register(adev->dev.of_node, 2946 of_dma_pl330_xlate, pl330); 2947 if (ret) { 2948 dev_err(&adev->dev, 2949 "unable to register DMA to the generic DT DMA helpers\n"); 2950 } 2951 } 2952 2953 adev->dev.dma_parms = &pl330->dma_parms; 2954 2955 /* 2956 * This is the limit for transfers with a buswidth of 1, larger 2957 * buswidths will have larger limits. 2958 */ 2959 ret = dma_set_max_seg_size(&adev->dev, 1900800); 2960 if (ret) 2961 dev_err(&adev->dev, "unable to set the seg size\n"); 2962 2963 2964 dev_info(&adev->dev, 2965 "Loaded driver for PL330 DMAC-%x\n", adev->periphid); 2966 dev_info(&adev->dev, 2967 "\tDBUFF-%ux%ubytes Num_Chans-%u Num_Peri-%u Num_Events-%u\n", 2968 pcfg->data_buf_dep, pcfg->data_bus_width / 8, pcfg->num_chan, 2969 pcfg->num_peri, pcfg->num_events); 2970 2971 pm_runtime_irq_safe(&adev->dev); 2972 pm_runtime_use_autosuspend(&adev->dev); 2973 pm_runtime_set_autosuspend_delay(&adev->dev, PL330_AUTOSUSPEND_DELAY); 2974 pm_runtime_mark_last_busy(&adev->dev); 2975 pm_runtime_put_autosuspend(&adev->dev); 2976 2977 return 0; 2978 probe_err3: 2979 /* Idle the DMAC */ 2980 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 2981 chan.device_node) { 2982 2983 /* Remove the channel */ 2984 list_del(&pch->chan.device_node); 2985 2986 /* Flush the channel */ 2987 if (pch->thread) { 2988 pl330_terminate_all(&pch->chan); 2989 pl330_free_chan_resources(&pch->chan); 2990 } 2991 } 2992 probe_err2: 2993 pl330_del(pl330); 2994 2995 return ret; 2996 } 2997 2998 static int pl330_remove(struct amba_device *adev) 2999 { 3000 struct pl330_dmac *pl330 = amba_get_drvdata(adev); 3001 struct dma_pl330_chan *pch, *_p; 3002 int i, irq; 3003 3004 pm_runtime_get_noresume(pl330->ddma.dev); 3005 3006 if (adev->dev.of_node) 3007 of_dma_controller_free(adev->dev.of_node); 3008 3009 for (i = 0; i < AMBA_NR_IRQS; i++) { 3010 irq = adev->irq[i]; 3011 devm_free_irq(&adev->dev, irq, pl330); 3012 } 3013 3014 dma_async_device_unregister(&pl330->ddma); 3015 3016 /* Idle the DMAC */ 3017 list_for_each_entry_safe(pch, _p, &pl330->ddma.channels, 3018 chan.device_node) { 3019 3020 /* Remove the channel */ 3021 list_del(&pch->chan.device_node); 3022 3023 /* Flush the channel */ 3024 if (pch->thread) { 3025 pl330_terminate_all(&pch->chan); 3026 pl330_free_chan_resources(&pch->chan); 3027 } 3028 } 3029 3030 pl330_del(pl330); 3031 3032 return 0; 3033 } 3034 3035 static struct amba_id pl330_ids[] = { 3036 { 3037 .id = 0x00041330, 3038 .mask = 0x000fffff, 3039 }, 3040 { 0, 0 }, 3041 }; 3042 3043 MODULE_DEVICE_TABLE(amba, pl330_ids); 3044 3045 static struct amba_driver pl330_driver = { 3046 .drv = { 3047 .owner = THIS_MODULE, 3048 .name = "dma-pl330", 3049 .pm = &pl330_pm, 3050 }, 3051 .id_table = pl330_ids, 3052 .probe = pl330_probe, 3053 .remove = pl330_remove, 3054 }; 3055 3056 module_amba_driver(pl330_driver); 3057 3058 MODULE_AUTHOR("Jaswinder Singh <jassisinghbrar@gmail.com>"); 3059 MODULE_DESCRIPTION("API Driver for PL330 DMAC"); 3060 MODULE_LICENSE("GPL"); 3061