1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * MOXA ART SoCs DMA Engine support. 4 * 5 * Copyright (C) 2013 Jonas Jensen 6 * 7 * Jonas Jensen <jonas.jensen@gmail.com> 8 */ 9 10 #include <linux/dmaengine.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/err.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/list.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_dma.h> 23 #include <linux/bitops.h> 24 25 #include <asm/cacheflush.h> 26 27 #include "dmaengine.h" 28 #include "virt-dma.h" 29 30 #define APB_DMA_MAX_CHANNEL 4 31 32 #define REG_OFF_ADDRESS_SOURCE 0 33 #define REG_OFF_ADDRESS_DEST 4 34 #define REG_OFF_CYCLES 8 35 #define REG_OFF_CTRL 12 36 #define REG_OFF_CHAN_SIZE 16 37 38 #define APB_DMA_ENABLE BIT(0) 39 #define APB_DMA_FIN_INT_STS BIT(1) 40 #define APB_DMA_FIN_INT_EN BIT(2) 41 #define APB_DMA_BURST_MODE BIT(3) 42 #define APB_DMA_ERR_INT_STS BIT(4) 43 #define APB_DMA_ERR_INT_EN BIT(5) 44 45 /* 46 * Unset: APB 47 * Set: AHB 48 */ 49 #define APB_DMA_SOURCE_SELECT 0x40 50 #define APB_DMA_DEST_SELECT 0x80 51 52 #define APB_DMA_SOURCE 0x100 53 #define APB_DMA_DEST 0x1000 54 55 #define APB_DMA_SOURCE_MASK 0x700 56 #define APB_DMA_DEST_MASK 0x7000 57 58 /* 59 * 000: No increment 60 * 001: +1 (Burst=0), +4 (Burst=1) 61 * 010: +2 (Burst=0), +8 (Burst=1) 62 * 011: +4 (Burst=0), +16 (Burst=1) 63 * 101: -1 (Burst=0), -4 (Burst=1) 64 * 110: -2 (Burst=0), -8 (Burst=1) 65 * 111: -4 (Burst=0), -16 (Burst=1) 66 */ 67 #define APB_DMA_SOURCE_INC_0 0 68 #define APB_DMA_SOURCE_INC_1_4 0x100 69 #define APB_DMA_SOURCE_INC_2_8 0x200 70 #define APB_DMA_SOURCE_INC_4_16 0x300 71 #define APB_DMA_SOURCE_DEC_1_4 0x500 72 #define APB_DMA_SOURCE_DEC_2_8 0x600 73 #define APB_DMA_SOURCE_DEC_4_16 0x700 74 #define APB_DMA_DEST_INC_0 0 75 #define APB_DMA_DEST_INC_1_4 0x1000 76 #define APB_DMA_DEST_INC_2_8 0x2000 77 #define APB_DMA_DEST_INC_4_16 0x3000 78 #define APB_DMA_DEST_DEC_1_4 0x5000 79 #define APB_DMA_DEST_DEC_2_8 0x6000 80 #define APB_DMA_DEST_DEC_4_16 0x7000 81 82 /* 83 * Request signal select source/destination address for DMA hardware handshake. 84 * 85 * The request line number is a property of the DMA controller itself, 86 * e.g. MMC must always request channels where dma_slave_config->slave_id is 5. 87 * 88 * 0: No request / Grant signal 89 * 1-15: Request / Grant signal 90 */ 91 #define APB_DMA_SOURCE_REQ_NO 0x1000000 92 #define APB_DMA_SOURCE_REQ_NO_MASK 0xf000000 93 #define APB_DMA_DEST_REQ_NO 0x10000 94 #define APB_DMA_DEST_REQ_NO_MASK 0xf0000 95 96 #define APB_DMA_DATA_WIDTH 0x100000 97 #define APB_DMA_DATA_WIDTH_MASK 0x300000 98 /* 99 * Data width of transfer: 100 * 101 * 00: Word 102 * 01: Half 103 * 10: Byte 104 */ 105 #define APB_DMA_DATA_WIDTH_4 0 106 #define APB_DMA_DATA_WIDTH_2 0x100000 107 #define APB_DMA_DATA_WIDTH_1 0x200000 108 109 #define APB_DMA_CYCLES_MASK 0x00ffffff 110 111 #define MOXART_DMA_DATA_TYPE_S8 0x00 112 #define MOXART_DMA_DATA_TYPE_S16 0x01 113 #define MOXART_DMA_DATA_TYPE_S32 0x02 114 115 struct moxart_sg { 116 dma_addr_t addr; 117 uint32_t len; 118 }; 119 120 struct moxart_desc { 121 enum dma_transfer_direction dma_dir; 122 dma_addr_t dev_addr; 123 unsigned int sglen; 124 unsigned int dma_cycles; 125 struct virt_dma_desc vd; 126 uint8_t es; 127 struct moxart_sg sg[] __counted_by(sglen); 128 }; 129 130 struct moxart_chan { 131 struct virt_dma_chan vc; 132 133 void __iomem *base; 134 struct moxart_desc *desc; 135 136 struct dma_slave_config cfg; 137 138 bool allocated; 139 bool error; 140 int ch_num; 141 unsigned int line_reqno; 142 unsigned int sgidx; 143 }; 144 145 struct moxart_dmadev { 146 struct dma_device dma_slave; 147 struct moxart_chan slave_chans[APB_DMA_MAX_CHANNEL]; 148 unsigned int irq; 149 }; 150 151 struct moxart_filter_data { 152 struct moxart_dmadev *mdc; 153 struct of_phandle_args *dma_spec; 154 }; 155 156 static const unsigned int es_bytes[] = { 157 [MOXART_DMA_DATA_TYPE_S8] = 1, 158 [MOXART_DMA_DATA_TYPE_S16] = 2, 159 [MOXART_DMA_DATA_TYPE_S32] = 4, 160 }; 161 162 static struct device *chan2dev(struct dma_chan *chan) 163 { 164 return &chan->dev->device; 165 } 166 167 static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c) 168 { 169 return container_of(c, struct moxart_chan, vc.chan); 170 } 171 172 static inline struct moxart_desc *to_moxart_dma_desc( 173 struct dma_async_tx_descriptor *t) 174 { 175 return container_of(t, struct moxart_desc, vd.tx); 176 } 177 178 static void moxart_dma_desc_free(struct virt_dma_desc *vd) 179 { 180 kfree(container_of(vd, struct moxart_desc, vd)); 181 } 182 183 static int moxart_terminate_all(struct dma_chan *chan) 184 { 185 struct moxart_chan *ch = to_moxart_dma_chan(chan); 186 unsigned long flags; 187 LIST_HEAD(head); 188 u32 ctrl; 189 190 dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch); 191 192 spin_lock_irqsave(&ch->vc.lock, flags); 193 194 if (ch->desc) { 195 moxart_dma_desc_free(&ch->desc->vd); 196 ch->desc = NULL; 197 } 198 199 ctrl = readl(ch->base + REG_OFF_CTRL); 200 ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); 201 writel(ctrl, ch->base + REG_OFF_CTRL); 202 203 vchan_get_all_descriptors(&ch->vc, &head); 204 spin_unlock_irqrestore(&ch->vc.lock, flags); 205 vchan_dma_desc_free_list(&ch->vc, &head); 206 207 return 0; 208 } 209 210 static int moxart_slave_config(struct dma_chan *chan, 211 struct dma_slave_config *cfg) 212 { 213 struct moxart_chan *ch = to_moxart_dma_chan(chan); 214 u32 ctrl; 215 216 ch->cfg = *cfg; 217 218 ctrl = readl(ch->base + REG_OFF_CTRL); 219 ctrl |= APB_DMA_BURST_MODE; 220 ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK); 221 ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK); 222 223 switch (ch->cfg.src_addr_width) { 224 case DMA_SLAVE_BUSWIDTH_1_BYTE: 225 ctrl |= APB_DMA_DATA_WIDTH_1; 226 if (ch->cfg.direction != DMA_MEM_TO_DEV) 227 ctrl |= APB_DMA_DEST_INC_1_4; 228 else 229 ctrl |= APB_DMA_SOURCE_INC_1_4; 230 break; 231 case DMA_SLAVE_BUSWIDTH_2_BYTES: 232 ctrl |= APB_DMA_DATA_WIDTH_2; 233 if (ch->cfg.direction != DMA_MEM_TO_DEV) 234 ctrl |= APB_DMA_DEST_INC_2_8; 235 else 236 ctrl |= APB_DMA_SOURCE_INC_2_8; 237 break; 238 case DMA_SLAVE_BUSWIDTH_4_BYTES: 239 ctrl &= ~APB_DMA_DATA_WIDTH; 240 if (ch->cfg.direction != DMA_MEM_TO_DEV) 241 ctrl |= APB_DMA_DEST_INC_4_16; 242 else 243 ctrl |= APB_DMA_SOURCE_INC_4_16; 244 break; 245 default: 246 return -EINVAL; 247 } 248 249 if (ch->cfg.direction == DMA_MEM_TO_DEV) { 250 ctrl &= ~APB_DMA_DEST_SELECT; 251 ctrl |= APB_DMA_SOURCE_SELECT; 252 ctrl |= (ch->line_reqno << 16 & 253 APB_DMA_DEST_REQ_NO_MASK); 254 } else { 255 ctrl |= APB_DMA_DEST_SELECT; 256 ctrl &= ~APB_DMA_SOURCE_SELECT; 257 ctrl |= (ch->line_reqno << 24 & 258 APB_DMA_SOURCE_REQ_NO_MASK); 259 } 260 261 writel(ctrl, ch->base + REG_OFF_CTRL); 262 263 return 0; 264 } 265 266 static struct dma_async_tx_descriptor *moxart_prep_slave_sg( 267 struct dma_chan *chan, struct scatterlist *sgl, 268 unsigned int sg_len, enum dma_transfer_direction dir, 269 unsigned long tx_flags, void *context) 270 { 271 struct moxart_chan *ch = to_moxart_dma_chan(chan); 272 struct moxart_desc *d; 273 enum dma_slave_buswidth dev_width; 274 dma_addr_t dev_addr; 275 struct scatterlist *sgent; 276 unsigned int es; 277 unsigned int i; 278 279 if (!is_slave_direction(dir)) { 280 dev_err(chan2dev(chan), "%s: invalid DMA direction\n", 281 __func__); 282 return NULL; 283 } 284 285 if (dir == DMA_DEV_TO_MEM) { 286 dev_addr = ch->cfg.src_addr; 287 dev_width = ch->cfg.src_addr_width; 288 } else { 289 dev_addr = ch->cfg.dst_addr; 290 dev_width = ch->cfg.dst_addr_width; 291 } 292 293 switch (dev_width) { 294 case DMA_SLAVE_BUSWIDTH_1_BYTE: 295 es = MOXART_DMA_DATA_TYPE_S8; 296 break; 297 case DMA_SLAVE_BUSWIDTH_2_BYTES: 298 es = MOXART_DMA_DATA_TYPE_S16; 299 break; 300 case DMA_SLAVE_BUSWIDTH_4_BYTES: 301 es = MOXART_DMA_DATA_TYPE_S32; 302 break; 303 default: 304 dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n", 305 __func__, dev_width); 306 return NULL; 307 } 308 309 d = kzalloc(struct_size(d, sg, sg_len), GFP_ATOMIC); 310 if (!d) 311 return NULL; 312 d->sglen = sg_len; 313 314 d->dma_dir = dir; 315 d->dev_addr = dev_addr; 316 d->es = es; 317 318 for_each_sg(sgl, sgent, sg_len, i) { 319 d->sg[i].addr = sg_dma_address(sgent); 320 d->sg[i].len = sg_dma_len(sgent); 321 } 322 323 ch->error = 0; 324 325 return vchan_tx_prep(&ch->vc, &d->vd, tx_flags); 326 } 327 328 static struct dma_chan *moxart_of_xlate(struct of_phandle_args *dma_spec, 329 struct of_dma *ofdma) 330 { 331 struct moxart_dmadev *mdc = ofdma->of_dma_data; 332 struct dma_chan *chan; 333 struct moxart_chan *ch; 334 335 chan = dma_get_any_slave_channel(&mdc->dma_slave); 336 if (!chan) 337 return NULL; 338 339 ch = to_moxart_dma_chan(chan); 340 ch->line_reqno = dma_spec->args[0]; 341 342 return chan; 343 } 344 345 static int moxart_alloc_chan_resources(struct dma_chan *chan) 346 { 347 struct moxart_chan *ch = to_moxart_dma_chan(chan); 348 349 dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n", 350 __func__, ch->ch_num); 351 ch->allocated = 1; 352 353 return 0; 354 } 355 356 static void moxart_free_chan_resources(struct dma_chan *chan) 357 { 358 struct moxart_chan *ch = to_moxart_dma_chan(chan); 359 360 vchan_free_chan_resources(&ch->vc); 361 362 dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n", 363 __func__, ch->ch_num); 364 ch->allocated = 0; 365 } 366 367 static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr, 368 dma_addr_t dst_addr) 369 { 370 writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE); 371 writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST); 372 } 373 374 static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len) 375 { 376 struct moxart_desc *d = ch->desc; 377 unsigned int sglen_div = es_bytes[d->es]; 378 379 d->dma_cycles = len >> sglen_div; 380 381 /* 382 * There are 4 cycles on 64 bytes copied, i.e. one cycle copies 16 383 * bytes ( when width is APB_DMAB_DATA_WIDTH_4 ). 384 */ 385 writel(d->dma_cycles, ch->base + REG_OFF_CYCLES); 386 387 dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n", 388 __func__, d->dma_cycles, len); 389 } 390 391 static void moxart_start_dma(struct moxart_chan *ch) 392 { 393 u32 ctrl; 394 395 ctrl = readl(ch->base + REG_OFF_CTRL); 396 ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); 397 writel(ctrl, ch->base + REG_OFF_CTRL); 398 } 399 400 static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx) 401 { 402 struct moxart_desc *d = ch->desc; 403 struct moxart_sg *sg = ch->desc->sg + idx; 404 405 if (ch->desc->dma_dir == DMA_MEM_TO_DEV) 406 moxart_dma_set_params(ch, sg->addr, d->dev_addr); 407 else if (ch->desc->dma_dir == DMA_DEV_TO_MEM) 408 moxart_dma_set_params(ch, d->dev_addr, sg->addr); 409 410 moxart_set_transfer_params(ch, sg->len); 411 412 moxart_start_dma(ch); 413 } 414 415 static void moxart_dma_start_desc(struct dma_chan *chan) 416 { 417 struct moxart_chan *ch = to_moxart_dma_chan(chan); 418 struct virt_dma_desc *vd; 419 420 vd = vchan_next_desc(&ch->vc); 421 422 if (!vd) { 423 ch->desc = NULL; 424 return; 425 } 426 427 list_del(&vd->node); 428 429 ch->desc = to_moxart_dma_desc(&vd->tx); 430 ch->sgidx = 0; 431 432 moxart_dma_start_sg(ch, 0); 433 } 434 435 static void moxart_issue_pending(struct dma_chan *chan) 436 { 437 struct moxart_chan *ch = to_moxart_dma_chan(chan); 438 unsigned long flags; 439 440 spin_lock_irqsave(&ch->vc.lock, flags); 441 if (vchan_issue_pending(&ch->vc) && !ch->desc) 442 moxart_dma_start_desc(chan); 443 spin_unlock_irqrestore(&ch->vc.lock, flags); 444 } 445 446 static size_t moxart_dma_desc_size(struct moxart_desc *d, 447 unsigned int completed_sgs) 448 { 449 unsigned int i; 450 size_t size; 451 452 for (size = i = completed_sgs; i < d->sglen; i++) 453 size += d->sg[i].len; 454 455 return size; 456 } 457 458 static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch) 459 { 460 size_t size; 461 unsigned int completed_cycles, cycles; 462 463 size = moxart_dma_desc_size(ch->desc, ch->sgidx); 464 cycles = readl(ch->base + REG_OFF_CYCLES); 465 completed_cycles = (ch->desc->dma_cycles - cycles); 466 size -= completed_cycles << es_bytes[ch->desc->es]; 467 468 dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size); 469 470 return size; 471 } 472 473 static enum dma_status moxart_tx_status(struct dma_chan *chan, 474 dma_cookie_t cookie, 475 struct dma_tx_state *txstate) 476 { 477 struct moxart_chan *ch = to_moxart_dma_chan(chan); 478 struct virt_dma_desc *vd; 479 struct moxart_desc *d; 480 enum dma_status ret; 481 unsigned long flags; 482 483 /* 484 * dma_cookie_status() assigns initial residue value. 485 */ 486 ret = dma_cookie_status(chan, cookie, txstate); 487 488 spin_lock_irqsave(&ch->vc.lock, flags); 489 vd = vchan_find_desc(&ch->vc, cookie); 490 if (vd) { 491 d = to_moxart_dma_desc(&vd->tx); 492 txstate->residue = moxart_dma_desc_size(d, 0); 493 } else if (ch->desc && ch->desc->vd.tx.cookie == cookie) { 494 txstate->residue = moxart_dma_desc_size_in_flight(ch); 495 } 496 spin_unlock_irqrestore(&ch->vc.lock, flags); 497 498 if (ch->error) 499 return DMA_ERROR; 500 501 return ret; 502 } 503 504 static void moxart_dma_init(struct dma_device *dma, struct device *dev) 505 { 506 dma->device_prep_slave_sg = moxart_prep_slave_sg; 507 dma->device_alloc_chan_resources = moxart_alloc_chan_resources; 508 dma->device_free_chan_resources = moxart_free_chan_resources; 509 dma->device_issue_pending = moxart_issue_pending; 510 dma->device_tx_status = moxart_tx_status; 511 dma->device_config = moxart_slave_config; 512 dma->device_terminate_all = moxart_terminate_all; 513 dma->dev = dev; 514 515 INIT_LIST_HEAD(&dma->channels); 516 } 517 518 static irqreturn_t moxart_dma_interrupt(int irq, void *devid) 519 { 520 struct moxart_dmadev *mc = devid; 521 struct moxart_chan *ch = &mc->slave_chans[0]; 522 unsigned int i; 523 u32 ctrl; 524 525 dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__); 526 527 for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) { 528 if (!ch->allocated) 529 continue; 530 531 ctrl = readl(ch->base + REG_OFF_CTRL); 532 533 dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n", 534 __func__, ch, ch->base, ctrl); 535 536 if (ctrl & APB_DMA_FIN_INT_STS) { 537 ctrl &= ~APB_DMA_FIN_INT_STS; 538 if (ch->desc) { 539 spin_lock(&ch->vc.lock); 540 if (++ch->sgidx < ch->desc->sglen) { 541 moxart_dma_start_sg(ch, ch->sgidx); 542 } else { 543 vchan_cookie_complete(&ch->desc->vd); 544 moxart_dma_start_desc(&ch->vc.chan); 545 } 546 spin_unlock(&ch->vc.lock); 547 } 548 } 549 550 if (ctrl & APB_DMA_ERR_INT_STS) { 551 ctrl &= ~APB_DMA_ERR_INT_STS; 552 ch->error = 1; 553 } 554 555 writel(ctrl, ch->base + REG_OFF_CTRL); 556 } 557 558 return IRQ_HANDLED; 559 } 560 561 static int moxart_probe(struct platform_device *pdev) 562 { 563 struct device *dev = &pdev->dev; 564 struct device_node *node = dev->of_node; 565 void __iomem *dma_base_addr; 566 int ret, i; 567 unsigned int irq; 568 struct moxart_chan *ch; 569 struct moxart_dmadev *mdc; 570 571 mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL); 572 if (!mdc) 573 return -ENOMEM; 574 575 irq = irq_of_parse_and_map(node, 0); 576 if (!irq) { 577 dev_err(dev, "no IRQ resource\n"); 578 return -EINVAL; 579 } 580 581 dma_base_addr = devm_platform_ioremap_resource(pdev, 0); 582 if (IS_ERR(dma_base_addr)) 583 return PTR_ERR(dma_base_addr); 584 585 dma_cap_zero(mdc->dma_slave.cap_mask); 586 dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask); 587 dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask); 588 589 moxart_dma_init(&mdc->dma_slave, dev); 590 591 ch = &mdc->slave_chans[0]; 592 for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) { 593 ch->ch_num = i; 594 ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE; 595 ch->allocated = 0; 596 597 ch->vc.desc_free = moxart_dma_desc_free; 598 vchan_init(&ch->vc, &mdc->dma_slave); 599 600 dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n", 601 __func__, i, ch->ch_num, ch->base); 602 } 603 604 platform_set_drvdata(pdev, mdc); 605 606 ret = devm_request_irq(dev, irq, moxart_dma_interrupt, 0, 607 "moxart-dma-engine", mdc); 608 if (ret) { 609 dev_err(dev, "devm_request_irq failed\n"); 610 return ret; 611 } 612 mdc->irq = irq; 613 614 ret = dma_async_device_register(&mdc->dma_slave); 615 if (ret) { 616 dev_err(dev, "dma_async_device_register failed\n"); 617 return ret; 618 } 619 620 ret = of_dma_controller_register(node, moxart_of_xlate, mdc); 621 if (ret) { 622 dev_err(dev, "of_dma_controller_register failed\n"); 623 dma_async_device_unregister(&mdc->dma_slave); 624 return ret; 625 } 626 627 dev_dbg(dev, "%s: IRQ=%u\n", __func__, irq); 628 629 return 0; 630 } 631 632 static void moxart_remove(struct platform_device *pdev) 633 { 634 struct moxart_dmadev *m = platform_get_drvdata(pdev); 635 636 devm_free_irq(&pdev->dev, m->irq, m); 637 638 dma_async_device_unregister(&m->dma_slave); 639 640 if (pdev->dev.of_node) 641 of_dma_controller_free(pdev->dev.of_node); 642 } 643 644 static const struct of_device_id moxart_dma_match[] = { 645 { .compatible = "moxa,moxart-dma" }, 646 { } 647 }; 648 MODULE_DEVICE_TABLE(of, moxart_dma_match); 649 650 static struct platform_driver moxart_driver = { 651 .probe = moxart_probe, 652 .remove_new = moxart_remove, 653 .driver = { 654 .name = "moxart-dma-engine", 655 .of_match_table = moxart_dma_match, 656 }, 657 }; 658 659 static int moxart_init(void) 660 { 661 return platform_driver_register(&moxart_driver); 662 } 663 subsys_initcall(moxart_init); 664 665 static void __exit moxart_exit(void) 666 { 667 platform_driver_unregister(&moxart_driver); 668 } 669 module_exit(moxart_exit); 670 671 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>"); 672 MODULE_DESCRIPTION("MOXART DMA engine driver"); 673 MODULE_LICENSE("GPL v2"); 674