1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2013 - 2015 Linaro Ltd. 4 * Copyright (c) 2013 HiSilicon Limited. 5 */ 6 #include <linux/sched.h> 7 #include <linux/device.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/dmapool.h> 10 #include <linux/dmaengine.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/spinlock.h> 18 #include <linux/of.h> 19 #include <linux/clk.h> 20 #include <linux/of_dma.h> 21 22 #include "virt-dma.h" 23 24 #define DRIVER_NAME "k3-dma" 25 #define DMA_MAX_SIZE 0x1ffc 26 #define DMA_CYCLIC_MAX_PERIOD 0x1000 27 #define LLI_BLOCK_SIZE (4 * PAGE_SIZE) 28 29 #define INT_STAT 0x00 30 #define INT_TC1 0x04 31 #define INT_TC2 0x08 32 #define INT_ERR1 0x0c 33 #define INT_ERR2 0x10 34 #define INT_TC1_MASK 0x18 35 #define INT_TC2_MASK 0x1c 36 #define INT_ERR1_MASK 0x20 37 #define INT_ERR2_MASK 0x24 38 #define INT_TC1_RAW 0x600 39 #define INT_TC2_RAW 0x608 40 #define INT_ERR1_RAW 0x610 41 #define INT_ERR2_RAW 0x618 42 #define CH_PRI 0x688 43 #define CH_STAT 0x690 44 #define CX_CUR_CNT 0x704 45 #define CX_LLI 0x800 46 #define CX_CNT1 0x80c 47 #define CX_CNT0 0x810 48 #define CX_SRC 0x814 49 #define CX_DST 0x818 50 #define CX_CFG 0x81c 51 52 #define CX_LLI_CHAIN_EN 0x2 53 #define CX_CFG_EN 0x1 54 #define CX_CFG_NODEIRQ BIT(1) 55 #define CX_CFG_MEM2PER (0x1 << 2) 56 #define CX_CFG_PER2MEM (0x2 << 2) 57 #define CX_CFG_SRCINCR (0x1 << 31) 58 #define CX_CFG_DSTINCR (0x1 << 30) 59 60 struct k3_desc_hw { 61 u32 lli; 62 u32 reserved[3]; 63 u32 count; 64 u32 saddr; 65 u32 daddr; 66 u32 config; 67 } __aligned(32); 68 69 struct k3_dma_desc_sw { 70 struct virt_dma_desc vd; 71 dma_addr_t desc_hw_lli; 72 size_t desc_num; 73 size_t size; 74 struct k3_desc_hw *desc_hw; 75 }; 76 77 struct k3_dma_phy; 78 79 struct k3_dma_chan { 80 u32 ccfg; 81 struct virt_dma_chan vc; 82 struct k3_dma_phy *phy; 83 struct list_head node; 84 dma_addr_t dev_addr; 85 enum dma_status status; 86 bool cyclic; 87 struct dma_slave_config slave_config; 88 }; 89 90 struct k3_dma_phy { 91 u32 idx; 92 void __iomem *base; 93 struct k3_dma_chan *vchan; 94 struct k3_dma_desc_sw *ds_run; 95 struct k3_dma_desc_sw *ds_done; 96 }; 97 98 struct k3_dma_dev { 99 struct dma_device slave; 100 void __iomem *base; 101 struct tasklet_struct task; 102 spinlock_t lock; 103 struct list_head chan_pending; 104 struct k3_dma_phy *phy; 105 struct k3_dma_chan *chans; 106 struct clk *clk; 107 struct dma_pool *pool; 108 u32 dma_channels; 109 u32 dma_requests; 110 u32 dma_channel_mask; 111 unsigned int irq; 112 }; 113 114 115 #define K3_FLAG_NOCLK BIT(1) 116 117 struct k3dma_soc_data { 118 unsigned long flags; 119 }; 120 121 122 #define to_k3_dma(dmadev) container_of(dmadev, struct k3_dma_dev, slave) 123 124 static int k3_dma_config_write(struct dma_chan *chan, 125 enum dma_transfer_direction dir, 126 struct dma_slave_config *cfg); 127 128 static struct k3_dma_chan *to_k3_chan(struct dma_chan *chan) 129 { 130 return container_of(chan, struct k3_dma_chan, vc.chan); 131 } 132 133 static void k3_dma_pause_dma(struct k3_dma_phy *phy, bool on) 134 { 135 u32 val = 0; 136 137 if (on) { 138 val = readl_relaxed(phy->base + CX_CFG); 139 val |= CX_CFG_EN; 140 writel_relaxed(val, phy->base + CX_CFG); 141 } else { 142 val = readl_relaxed(phy->base + CX_CFG); 143 val &= ~CX_CFG_EN; 144 writel_relaxed(val, phy->base + CX_CFG); 145 } 146 } 147 148 static void k3_dma_terminate_chan(struct k3_dma_phy *phy, struct k3_dma_dev *d) 149 { 150 u32 val = 0; 151 152 k3_dma_pause_dma(phy, false); 153 154 val = 0x1 << phy->idx; 155 writel_relaxed(val, d->base + INT_TC1_RAW); 156 writel_relaxed(val, d->base + INT_TC2_RAW); 157 writel_relaxed(val, d->base + INT_ERR1_RAW); 158 writel_relaxed(val, d->base + INT_ERR2_RAW); 159 } 160 161 static void k3_dma_set_desc(struct k3_dma_phy *phy, struct k3_desc_hw *hw) 162 { 163 writel_relaxed(hw->lli, phy->base + CX_LLI); 164 writel_relaxed(hw->count, phy->base + CX_CNT0); 165 writel_relaxed(hw->saddr, phy->base + CX_SRC); 166 writel_relaxed(hw->daddr, phy->base + CX_DST); 167 writel_relaxed(hw->config, phy->base + CX_CFG); 168 } 169 170 static u32 k3_dma_get_curr_cnt(struct k3_dma_dev *d, struct k3_dma_phy *phy) 171 { 172 u32 cnt = 0; 173 174 cnt = readl_relaxed(d->base + CX_CUR_CNT + phy->idx * 0x10); 175 cnt &= 0xffff; 176 return cnt; 177 } 178 179 static u32 k3_dma_get_curr_lli(struct k3_dma_phy *phy) 180 { 181 return readl_relaxed(phy->base + CX_LLI); 182 } 183 184 static u32 k3_dma_get_chan_stat(struct k3_dma_dev *d) 185 { 186 return readl_relaxed(d->base + CH_STAT); 187 } 188 189 static void k3_dma_enable_dma(struct k3_dma_dev *d, bool on) 190 { 191 if (on) { 192 /* set same priority */ 193 writel_relaxed(0x0, d->base + CH_PRI); 194 195 /* unmask irq */ 196 writel_relaxed(0xffff, d->base + INT_TC1_MASK); 197 writel_relaxed(0xffff, d->base + INT_TC2_MASK); 198 writel_relaxed(0xffff, d->base + INT_ERR1_MASK); 199 writel_relaxed(0xffff, d->base + INT_ERR2_MASK); 200 } else { 201 /* mask irq */ 202 writel_relaxed(0x0, d->base + INT_TC1_MASK); 203 writel_relaxed(0x0, d->base + INT_TC2_MASK); 204 writel_relaxed(0x0, d->base + INT_ERR1_MASK); 205 writel_relaxed(0x0, d->base + INT_ERR2_MASK); 206 } 207 } 208 209 static irqreturn_t k3_dma_int_handler(int irq, void *dev_id) 210 { 211 struct k3_dma_dev *d = (struct k3_dma_dev *)dev_id; 212 struct k3_dma_phy *p; 213 struct k3_dma_chan *c; 214 u32 stat = readl_relaxed(d->base + INT_STAT); 215 u32 tc1 = readl_relaxed(d->base + INT_TC1); 216 u32 tc2 = readl_relaxed(d->base + INT_TC2); 217 u32 err1 = readl_relaxed(d->base + INT_ERR1); 218 u32 err2 = readl_relaxed(d->base + INT_ERR2); 219 u32 i, irq_chan = 0; 220 221 while (stat) { 222 i = __ffs(stat); 223 stat &= ~BIT(i); 224 if (likely(tc1 & BIT(i)) || (tc2 & BIT(i))) { 225 226 p = &d->phy[i]; 227 c = p->vchan; 228 if (c && (tc1 & BIT(i))) { 229 spin_lock(&c->vc.lock); 230 if (p->ds_run != NULL) { 231 vchan_cookie_complete(&p->ds_run->vd); 232 p->ds_done = p->ds_run; 233 p->ds_run = NULL; 234 } 235 spin_unlock(&c->vc.lock); 236 } 237 if (c && (tc2 & BIT(i))) { 238 spin_lock(&c->vc.lock); 239 if (p->ds_run != NULL) 240 vchan_cyclic_callback(&p->ds_run->vd); 241 spin_unlock(&c->vc.lock); 242 } 243 irq_chan |= BIT(i); 244 } 245 if (unlikely((err1 & BIT(i)) || (err2 & BIT(i)))) 246 dev_warn(d->slave.dev, "DMA ERR\n"); 247 } 248 249 writel_relaxed(irq_chan, d->base + INT_TC1_RAW); 250 writel_relaxed(irq_chan, d->base + INT_TC2_RAW); 251 writel_relaxed(err1, d->base + INT_ERR1_RAW); 252 writel_relaxed(err2, d->base + INT_ERR2_RAW); 253 254 if (irq_chan) 255 tasklet_schedule(&d->task); 256 257 if (irq_chan || err1 || err2) 258 return IRQ_HANDLED; 259 260 return IRQ_NONE; 261 } 262 263 static int k3_dma_start_txd(struct k3_dma_chan *c) 264 { 265 struct k3_dma_dev *d = to_k3_dma(c->vc.chan.device); 266 struct virt_dma_desc *vd = vchan_next_desc(&c->vc); 267 268 if (!c->phy) 269 return -EAGAIN; 270 271 if (BIT(c->phy->idx) & k3_dma_get_chan_stat(d)) 272 return -EAGAIN; 273 274 /* Avoid losing track of ds_run if a transaction is in flight */ 275 if (c->phy->ds_run) 276 return -EAGAIN; 277 278 if (vd) { 279 struct k3_dma_desc_sw *ds = 280 container_of(vd, struct k3_dma_desc_sw, vd); 281 /* 282 * fetch and remove request from vc->desc_issued 283 * so vc->desc_issued only contains desc pending 284 */ 285 list_del(&ds->vd.node); 286 287 c->phy->ds_run = ds; 288 c->phy->ds_done = NULL; 289 /* start dma */ 290 k3_dma_set_desc(c->phy, &ds->desc_hw[0]); 291 return 0; 292 } 293 c->phy->ds_run = NULL; 294 c->phy->ds_done = NULL; 295 return -EAGAIN; 296 } 297 298 static void k3_dma_tasklet(struct tasklet_struct *t) 299 { 300 struct k3_dma_dev *d = from_tasklet(d, t, task); 301 struct k3_dma_phy *p; 302 struct k3_dma_chan *c, *cn; 303 unsigned pch, pch_alloc = 0; 304 305 /* check new dma request of running channel in vc->desc_issued */ 306 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) { 307 spin_lock_irq(&c->vc.lock); 308 p = c->phy; 309 if (p && p->ds_done) { 310 if (k3_dma_start_txd(c)) { 311 /* No current txd associated with this channel */ 312 dev_dbg(d->slave.dev, "pchan %u: free\n", p->idx); 313 /* Mark this channel free */ 314 c->phy = NULL; 315 p->vchan = NULL; 316 } 317 } 318 spin_unlock_irq(&c->vc.lock); 319 } 320 321 /* check new channel request in d->chan_pending */ 322 spin_lock_irq(&d->lock); 323 for (pch = 0; pch < d->dma_channels; pch++) { 324 if (!(d->dma_channel_mask & (1 << pch))) 325 continue; 326 327 p = &d->phy[pch]; 328 329 if (p->vchan == NULL && !list_empty(&d->chan_pending)) { 330 c = list_first_entry(&d->chan_pending, 331 struct k3_dma_chan, node); 332 /* remove from d->chan_pending */ 333 list_del_init(&c->node); 334 pch_alloc |= 1 << pch; 335 /* Mark this channel allocated */ 336 p->vchan = c; 337 c->phy = p; 338 dev_dbg(d->slave.dev, "pchan %u: alloc vchan %p\n", pch, &c->vc); 339 } 340 } 341 spin_unlock_irq(&d->lock); 342 343 for (pch = 0; pch < d->dma_channels; pch++) { 344 if (!(d->dma_channel_mask & (1 << pch))) 345 continue; 346 347 if (pch_alloc & (1 << pch)) { 348 p = &d->phy[pch]; 349 c = p->vchan; 350 if (c) { 351 spin_lock_irq(&c->vc.lock); 352 k3_dma_start_txd(c); 353 spin_unlock_irq(&c->vc.lock); 354 } 355 } 356 } 357 } 358 359 static void k3_dma_free_chan_resources(struct dma_chan *chan) 360 { 361 struct k3_dma_chan *c = to_k3_chan(chan); 362 struct k3_dma_dev *d = to_k3_dma(chan->device); 363 unsigned long flags; 364 365 spin_lock_irqsave(&d->lock, flags); 366 list_del_init(&c->node); 367 spin_unlock_irqrestore(&d->lock, flags); 368 369 vchan_free_chan_resources(&c->vc); 370 c->ccfg = 0; 371 } 372 373 static enum dma_status k3_dma_tx_status(struct dma_chan *chan, 374 dma_cookie_t cookie, struct dma_tx_state *state) 375 { 376 struct k3_dma_chan *c = to_k3_chan(chan); 377 struct k3_dma_dev *d = to_k3_dma(chan->device); 378 struct k3_dma_phy *p; 379 struct virt_dma_desc *vd; 380 unsigned long flags; 381 enum dma_status ret; 382 size_t bytes = 0; 383 384 ret = dma_cookie_status(&c->vc.chan, cookie, state); 385 if (ret == DMA_COMPLETE) 386 return ret; 387 388 spin_lock_irqsave(&c->vc.lock, flags); 389 p = c->phy; 390 ret = c->status; 391 392 /* 393 * If the cookie is on our issue queue, then the residue is 394 * its total size. 395 */ 396 vd = vchan_find_desc(&c->vc, cookie); 397 if (vd && !c->cyclic) { 398 bytes = container_of(vd, struct k3_dma_desc_sw, vd)->size; 399 } else if ((!p) || (!p->ds_run)) { 400 bytes = 0; 401 } else { 402 struct k3_dma_desc_sw *ds = p->ds_run; 403 u32 clli = 0, index = 0; 404 405 bytes = k3_dma_get_curr_cnt(d, p); 406 clli = k3_dma_get_curr_lli(p); 407 index = ((clli - ds->desc_hw_lli) / 408 sizeof(struct k3_desc_hw)) + 1; 409 for (; index < ds->desc_num; index++) { 410 bytes += ds->desc_hw[index].count; 411 /* end of lli */ 412 if (!ds->desc_hw[index].lli) 413 break; 414 } 415 } 416 spin_unlock_irqrestore(&c->vc.lock, flags); 417 dma_set_residue(state, bytes); 418 return ret; 419 } 420 421 static void k3_dma_issue_pending(struct dma_chan *chan) 422 { 423 struct k3_dma_chan *c = to_k3_chan(chan); 424 struct k3_dma_dev *d = to_k3_dma(chan->device); 425 unsigned long flags; 426 427 spin_lock_irqsave(&c->vc.lock, flags); 428 /* add request to vc->desc_issued */ 429 if (vchan_issue_pending(&c->vc)) { 430 spin_lock(&d->lock); 431 if (!c->phy) { 432 if (list_empty(&c->node)) { 433 /* if new channel, add chan_pending */ 434 list_add_tail(&c->node, &d->chan_pending); 435 /* check in tasklet */ 436 tasklet_schedule(&d->task); 437 dev_dbg(d->slave.dev, "vchan %p: issued\n", &c->vc); 438 } 439 } 440 spin_unlock(&d->lock); 441 } else 442 dev_dbg(d->slave.dev, "vchan %p: nothing to issue\n", &c->vc); 443 spin_unlock_irqrestore(&c->vc.lock, flags); 444 } 445 446 static void k3_dma_fill_desc(struct k3_dma_desc_sw *ds, dma_addr_t dst, 447 dma_addr_t src, size_t len, u32 num, u32 ccfg) 448 { 449 if (num != ds->desc_num - 1) 450 ds->desc_hw[num].lli = ds->desc_hw_lli + (num + 1) * 451 sizeof(struct k3_desc_hw); 452 453 ds->desc_hw[num].lli |= CX_LLI_CHAIN_EN; 454 ds->desc_hw[num].count = len; 455 ds->desc_hw[num].saddr = src; 456 ds->desc_hw[num].daddr = dst; 457 ds->desc_hw[num].config = ccfg; 458 } 459 460 static struct k3_dma_desc_sw *k3_dma_alloc_desc_resource(int num, 461 struct dma_chan *chan) 462 { 463 struct k3_dma_chan *c = to_k3_chan(chan); 464 struct k3_dma_desc_sw *ds; 465 struct k3_dma_dev *d = to_k3_dma(chan->device); 466 int lli_limit = LLI_BLOCK_SIZE / sizeof(struct k3_desc_hw); 467 468 if (num > lli_limit) { 469 dev_dbg(chan->device->dev, "vch %p: sg num %d exceed max %d\n", 470 &c->vc, num, lli_limit); 471 return NULL; 472 } 473 474 ds = kzalloc(sizeof(*ds), GFP_NOWAIT); 475 if (!ds) 476 return NULL; 477 478 ds->desc_hw = dma_pool_zalloc(d->pool, GFP_NOWAIT, &ds->desc_hw_lli); 479 if (!ds->desc_hw) { 480 dev_dbg(chan->device->dev, "vch %p: dma alloc fail\n", &c->vc); 481 kfree(ds); 482 return NULL; 483 } 484 ds->desc_num = num; 485 return ds; 486 } 487 488 static struct dma_async_tx_descriptor *k3_dma_prep_memcpy( 489 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, 490 size_t len, unsigned long flags) 491 { 492 struct k3_dma_chan *c = to_k3_chan(chan); 493 struct k3_dma_desc_sw *ds; 494 size_t copy = 0; 495 int num = 0; 496 497 if (!len) 498 return NULL; 499 500 num = DIV_ROUND_UP(len, DMA_MAX_SIZE); 501 502 ds = k3_dma_alloc_desc_resource(num, chan); 503 if (!ds) 504 return NULL; 505 506 c->cyclic = 0; 507 ds->size = len; 508 num = 0; 509 510 if (!c->ccfg) { 511 /* default is memtomem, without calling device_config */ 512 c->ccfg = CX_CFG_SRCINCR | CX_CFG_DSTINCR | CX_CFG_EN; 513 c->ccfg |= (0xf << 20) | (0xf << 24); /* burst = 16 */ 514 c->ccfg |= (0x3 << 12) | (0x3 << 16); /* width = 64 bit */ 515 } 516 517 do { 518 copy = min_t(size_t, len, DMA_MAX_SIZE); 519 k3_dma_fill_desc(ds, dst, src, copy, num++, c->ccfg); 520 521 src += copy; 522 dst += copy; 523 len -= copy; 524 } while (len); 525 526 ds->desc_hw[num-1].lli = 0; /* end of link */ 527 return vchan_tx_prep(&c->vc, &ds->vd, flags); 528 } 529 530 static struct dma_async_tx_descriptor *k3_dma_prep_slave_sg( 531 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sglen, 532 enum dma_transfer_direction dir, unsigned long flags, void *context) 533 { 534 struct k3_dma_chan *c = to_k3_chan(chan); 535 struct k3_dma_desc_sw *ds; 536 size_t len, avail, total = 0; 537 struct scatterlist *sg; 538 dma_addr_t addr, src = 0, dst = 0; 539 int num, i; 540 541 if (sgl == NULL) 542 return NULL; 543 544 c->cyclic = 0; 545 546 num = sg_nents_for_dma(sgl, sglen, DMA_MAX_SIZE); 547 ds = k3_dma_alloc_desc_resource(num, chan); 548 if (!ds) 549 return NULL; 550 num = 0; 551 k3_dma_config_write(chan, dir, &c->slave_config); 552 553 for_each_sg(sgl, sg, sglen, i) { 554 addr = sg_dma_address(sg); 555 avail = sg_dma_len(sg); 556 total += avail; 557 558 do { 559 len = min_t(size_t, avail, DMA_MAX_SIZE); 560 561 if (dir == DMA_MEM_TO_DEV) { 562 src = addr; 563 dst = c->dev_addr; 564 } else if (dir == DMA_DEV_TO_MEM) { 565 src = c->dev_addr; 566 dst = addr; 567 } 568 569 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg); 570 571 addr += len; 572 avail -= len; 573 } while (avail); 574 } 575 576 ds->desc_hw[num-1].lli = 0; /* end of link */ 577 ds->size = total; 578 return vchan_tx_prep(&c->vc, &ds->vd, flags); 579 } 580 581 static struct dma_async_tx_descriptor * 582 k3_dma_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, 583 size_t buf_len, size_t period_len, 584 enum dma_transfer_direction dir, 585 unsigned long flags) 586 { 587 struct k3_dma_chan *c = to_k3_chan(chan); 588 struct k3_dma_desc_sw *ds; 589 size_t len, avail, total = 0; 590 dma_addr_t addr, src = 0, dst = 0; 591 int num = 1, since = 0; 592 size_t modulo = DMA_CYCLIC_MAX_PERIOD; 593 u32 en_tc2 = 0; 594 595 dev_dbg(chan->device->dev, "%s: buf %pad, dst %pad, buf len %zu, period_len = %zu, dir %d\n", 596 __func__, &buf_addr, &to_k3_chan(chan)->dev_addr, 597 buf_len, period_len, (int)dir); 598 599 avail = buf_len; 600 if (avail > modulo) 601 num += DIV_ROUND_UP(avail, modulo) - 1; 602 603 ds = k3_dma_alloc_desc_resource(num, chan); 604 if (!ds) 605 return NULL; 606 607 c->cyclic = 1; 608 addr = buf_addr; 609 avail = buf_len; 610 total = avail; 611 num = 0; 612 k3_dma_config_write(chan, dir, &c->slave_config); 613 614 if (period_len < modulo) 615 modulo = period_len; 616 617 do { 618 len = min_t(size_t, avail, modulo); 619 620 if (dir == DMA_MEM_TO_DEV) { 621 src = addr; 622 dst = c->dev_addr; 623 } else if (dir == DMA_DEV_TO_MEM) { 624 src = c->dev_addr; 625 dst = addr; 626 } 627 since += len; 628 if (since >= period_len) { 629 /* descriptor asks for TC2 interrupt on completion */ 630 en_tc2 = CX_CFG_NODEIRQ; 631 since -= period_len; 632 } else 633 en_tc2 = 0; 634 635 k3_dma_fill_desc(ds, dst, src, len, num++, c->ccfg | en_tc2); 636 637 addr += len; 638 avail -= len; 639 } while (avail); 640 641 /* "Cyclic" == end of link points back to start of link */ 642 ds->desc_hw[num - 1].lli |= ds->desc_hw_lli; 643 644 ds->size = total; 645 646 return vchan_tx_prep(&c->vc, &ds->vd, flags); 647 } 648 649 static int k3_dma_config(struct dma_chan *chan, 650 struct dma_slave_config *cfg) 651 { 652 struct k3_dma_chan *c = to_k3_chan(chan); 653 654 memcpy(&c->slave_config, cfg, sizeof(*cfg)); 655 656 return 0; 657 } 658 659 static int k3_dma_config_write(struct dma_chan *chan, 660 enum dma_transfer_direction dir, 661 struct dma_slave_config *cfg) 662 { 663 struct k3_dma_chan *c = to_k3_chan(chan); 664 u32 maxburst = 0, val = 0; 665 enum dma_slave_buswidth width = DMA_SLAVE_BUSWIDTH_UNDEFINED; 666 667 if (dir == DMA_DEV_TO_MEM) { 668 c->ccfg = CX_CFG_DSTINCR; 669 c->dev_addr = cfg->src_addr; 670 maxburst = cfg->src_maxburst; 671 width = cfg->src_addr_width; 672 } else if (dir == DMA_MEM_TO_DEV) { 673 c->ccfg = CX_CFG_SRCINCR; 674 c->dev_addr = cfg->dst_addr; 675 maxburst = cfg->dst_maxburst; 676 width = cfg->dst_addr_width; 677 } 678 switch (width) { 679 case DMA_SLAVE_BUSWIDTH_1_BYTE: 680 case DMA_SLAVE_BUSWIDTH_2_BYTES: 681 case DMA_SLAVE_BUSWIDTH_4_BYTES: 682 case DMA_SLAVE_BUSWIDTH_8_BYTES: 683 val = __ffs(width); 684 break; 685 default: 686 val = 3; 687 break; 688 } 689 c->ccfg |= (val << 12) | (val << 16); 690 691 if ((maxburst == 0) || (maxburst > 16)) 692 val = 15; 693 else 694 val = maxburst - 1; 695 c->ccfg |= (val << 20) | (val << 24); 696 c->ccfg |= CX_CFG_MEM2PER | CX_CFG_EN; 697 698 /* specific request line */ 699 c->ccfg |= c->vc.chan.chan_id << 4; 700 701 return 0; 702 } 703 704 static void k3_dma_free_desc(struct virt_dma_desc *vd) 705 { 706 struct k3_dma_desc_sw *ds = 707 container_of(vd, struct k3_dma_desc_sw, vd); 708 struct k3_dma_dev *d = to_k3_dma(vd->tx.chan->device); 709 710 dma_pool_free(d->pool, ds->desc_hw, ds->desc_hw_lli); 711 kfree(ds); 712 } 713 714 static int k3_dma_terminate_all(struct dma_chan *chan) 715 { 716 struct k3_dma_chan *c = to_k3_chan(chan); 717 struct k3_dma_dev *d = to_k3_dma(chan->device); 718 struct k3_dma_phy *p = c->phy; 719 unsigned long flags; 720 LIST_HEAD(head); 721 722 dev_dbg(d->slave.dev, "vchan %p: terminate all\n", &c->vc); 723 724 /* Prevent this channel being scheduled */ 725 spin_lock(&d->lock); 726 list_del_init(&c->node); 727 spin_unlock(&d->lock); 728 729 /* Clear the tx descriptor lists */ 730 spin_lock_irqsave(&c->vc.lock, flags); 731 vchan_get_all_descriptors(&c->vc, &head); 732 if (p) { 733 /* vchan is assigned to a pchan - stop the channel */ 734 k3_dma_terminate_chan(p, d); 735 c->phy = NULL; 736 p->vchan = NULL; 737 if (p->ds_run) { 738 vchan_terminate_vdesc(&p->ds_run->vd); 739 p->ds_run = NULL; 740 } 741 p->ds_done = NULL; 742 } 743 spin_unlock_irqrestore(&c->vc.lock, flags); 744 vchan_dma_desc_free_list(&c->vc, &head); 745 746 return 0; 747 } 748 749 static void k3_dma_synchronize(struct dma_chan *chan) 750 { 751 struct k3_dma_chan *c = to_k3_chan(chan); 752 753 vchan_synchronize(&c->vc); 754 } 755 756 static int k3_dma_transfer_pause(struct dma_chan *chan) 757 { 758 struct k3_dma_chan *c = to_k3_chan(chan); 759 struct k3_dma_dev *d = to_k3_dma(chan->device); 760 struct k3_dma_phy *p = c->phy; 761 762 dev_dbg(d->slave.dev, "vchan %p: pause\n", &c->vc); 763 if (c->status == DMA_IN_PROGRESS) { 764 c->status = DMA_PAUSED; 765 if (p) { 766 k3_dma_pause_dma(p, false); 767 } else { 768 spin_lock(&d->lock); 769 list_del_init(&c->node); 770 spin_unlock(&d->lock); 771 } 772 } 773 774 return 0; 775 } 776 777 static int k3_dma_transfer_resume(struct dma_chan *chan) 778 { 779 struct k3_dma_chan *c = to_k3_chan(chan); 780 struct k3_dma_dev *d = to_k3_dma(chan->device); 781 struct k3_dma_phy *p = c->phy; 782 unsigned long flags; 783 784 dev_dbg(d->slave.dev, "vchan %p: resume\n", &c->vc); 785 spin_lock_irqsave(&c->vc.lock, flags); 786 if (c->status == DMA_PAUSED) { 787 c->status = DMA_IN_PROGRESS; 788 if (p) { 789 k3_dma_pause_dma(p, true); 790 } else if (!list_empty(&c->vc.desc_issued)) { 791 spin_lock(&d->lock); 792 list_add_tail(&c->node, &d->chan_pending); 793 spin_unlock(&d->lock); 794 } 795 } 796 spin_unlock_irqrestore(&c->vc.lock, flags); 797 798 return 0; 799 } 800 801 static const struct k3dma_soc_data k3_v1_dma_data = { 802 .flags = 0, 803 }; 804 805 static const struct k3dma_soc_data asp_v1_dma_data = { 806 .flags = K3_FLAG_NOCLK, 807 }; 808 809 static const struct of_device_id k3_pdma_dt_ids[] = { 810 { .compatible = "hisilicon,k3-dma-1.0", 811 .data = &k3_v1_dma_data 812 }, 813 { .compatible = "hisilicon,hisi-pcm-asp-dma-1.0", 814 .data = &asp_v1_dma_data 815 }, 816 {} 817 }; 818 MODULE_DEVICE_TABLE(of, k3_pdma_dt_ids); 819 820 static struct dma_chan *k3_of_dma_simple_xlate(struct of_phandle_args *dma_spec, 821 struct of_dma *ofdma) 822 { 823 struct k3_dma_dev *d = ofdma->of_dma_data; 824 unsigned int request = dma_spec->args[0]; 825 826 if (request >= d->dma_requests) 827 return NULL; 828 829 return dma_get_slave_channel(&(d->chans[request].vc.chan)); 830 } 831 832 static int k3_dma_probe(struct platform_device *op) 833 { 834 const struct k3dma_soc_data *soc_data; 835 struct k3_dma_dev *d; 836 int i, ret, irq = 0; 837 838 d = devm_kzalloc(&op->dev, sizeof(*d), GFP_KERNEL); 839 if (!d) 840 return -ENOMEM; 841 842 soc_data = device_get_match_data(&op->dev); 843 if (!soc_data) 844 return -EINVAL; 845 846 d->base = devm_platform_ioremap_resource(op, 0); 847 if (IS_ERR(d->base)) 848 return PTR_ERR(d->base); 849 850 of_property_read_u32((&op->dev)->of_node, 851 "dma-channels", &d->dma_channels); 852 of_property_read_u32((&op->dev)->of_node, 853 "dma-requests", &d->dma_requests); 854 ret = of_property_read_u32((&op->dev)->of_node, 855 "dma-channel-mask", &d->dma_channel_mask); 856 if (ret) { 857 dev_warn(&op->dev, 858 "dma-channel-mask doesn't exist, considering all as available.\n"); 859 d->dma_channel_mask = (u32)~0UL; 860 } 861 862 if (!(soc_data->flags & K3_FLAG_NOCLK)) { 863 d->clk = devm_clk_get(&op->dev, NULL); 864 if (IS_ERR(d->clk)) { 865 dev_err(&op->dev, "no dma clk\n"); 866 return PTR_ERR(d->clk); 867 } 868 } 869 870 irq = platform_get_irq(op, 0); 871 ret = devm_request_irq(&op->dev, irq, 872 k3_dma_int_handler, 0, DRIVER_NAME, d); 873 if (ret) 874 return ret; 875 876 d->irq = irq; 877 878 /* A DMA memory pool for LLIs, align on 32-byte boundary */ 879 d->pool = dmam_pool_create(DRIVER_NAME, &op->dev, 880 LLI_BLOCK_SIZE, 32, 0); 881 if (!d->pool) 882 return -ENOMEM; 883 884 /* init phy channel */ 885 d->phy = devm_kcalloc(&op->dev, 886 d->dma_channels, sizeof(struct k3_dma_phy), GFP_KERNEL); 887 if (d->phy == NULL) 888 return -ENOMEM; 889 890 for (i = 0; i < d->dma_channels; i++) { 891 struct k3_dma_phy *p; 892 893 if (!(d->dma_channel_mask & BIT(i))) 894 continue; 895 896 p = &d->phy[i]; 897 p->idx = i; 898 p->base = d->base + i * 0x40; 899 } 900 901 INIT_LIST_HEAD(&d->slave.channels); 902 dma_cap_set(DMA_SLAVE, d->slave.cap_mask); 903 dma_cap_set(DMA_MEMCPY, d->slave.cap_mask); 904 dma_cap_set(DMA_CYCLIC, d->slave.cap_mask); 905 d->slave.dev = &op->dev; 906 d->slave.device_free_chan_resources = k3_dma_free_chan_resources; 907 d->slave.device_tx_status = k3_dma_tx_status; 908 d->slave.device_prep_dma_memcpy = k3_dma_prep_memcpy; 909 d->slave.device_prep_slave_sg = k3_dma_prep_slave_sg; 910 d->slave.device_prep_dma_cyclic = k3_dma_prep_dma_cyclic; 911 d->slave.device_issue_pending = k3_dma_issue_pending; 912 d->slave.device_config = k3_dma_config; 913 d->slave.device_pause = k3_dma_transfer_pause; 914 d->slave.device_resume = k3_dma_transfer_resume; 915 d->slave.device_terminate_all = k3_dma_terminate_all; 916 d->slave.device_synchronize = k3_dma_synchronize; 917 d->slave.copy_align = DMAENGINE_ALIGN_8_BYTES; 918 919 /* init virtual channel */ 920 d->chans = devm_kcalloc(&op->dev, 921 d->dma_requests, sizeof(struct k3_dma_chan), GFP_KERNEL); 922 if (d->chans == NULL) 923 return -ENOMEM; 924 925 for (i = 0; i < d->dma_requests; i++) { 926 struct k3_dma_chan *c = &d->chans[i]; 927 928 c->status = DMA_IN_PROGRESS; 929 INIT_LIST_HEAD(&c->node); 930 c->vc.desc_free = k3_dma_free_desc; 931 vchan_init(&c->vc, &d->slave); 932 } 933 934 /* Enable clock before accessing registers */ 935 ret = clk_prepare_enable(d->clk); 936 if (ret < 0) { 937 dev_err(&op->dev, "clk_prepare_enable failed: %d\n", ret); 938 return ret; 939 } 940 941 k3_dma_enable_dma(d, true); 942 943 ret = dma_async_device_register(&d->slave); 944 if (ret) 945 goto dma_async_register_fail; 946 947 ret = of_dma_controller_register((&op->dev)->of_node, 948 k3_of_dma_simple_xlate, d); 949 if (ret) 950 goto of_dma_register_fail; 951 952 spin_lock_init(&d->lock); 953 INIT_LIST_HEAD(&d->chan_pending); 954 tasklet_setup(&d->task, k3_dma_tasklet); 955 platform_set_drvdata(op, d); 956 dev_info(&op->dev, "initialized\n"); 957 958 return 0; 959 960 of_dma_register_fail: 961 dma_async_device_unregister(&d->slave); 962 dma_async_register_fail: 963 clk_disable_unprepare(d->clk); 964 return ret; 965 } 966 967 static void k3_dma_remove(struct platform_device *op) 968 { 969 struct k3_dma_chan *c, *cn; 970 struct k3_dma_dev *d = platform_get_drvdata(op); 971 972 dma_async_device_unregister(&d->slave); 973 of_dma_controller_free((&op->dev)->of_node); 974 975 devm_free_irq(&op->dev, d->irq, d); 976 977 list_for_each_entry_safe(c, cn, &d->slave.channels, vc.chan.device_node) { 978 list_del(&c->vc.chan.device_node); 979 tasklet_kill(&c->vc.task); 980 } 981 tasklet_kill(&d->task); 982 clk_disable_unprepare(d->clk); 983 } 984 985 #ifdef CONFIG_PM_SLEEP 986 static int k3_dma_suspend_dev(struct device *dev) 987 { 988 struct k3_dma_dev *d = dev_get_drvdata(dev); 989 u32 stat = 0; 990 991 stat = k3_dma_get_chan_stat(d); 992 if (stat) { 993 dev_warn(d->slave.dev, 994 "chan %d is running fail to suspend\n", stat); 995 return -1; 996 } 997 k3_dma_enable_dma(d, false); 998 clk_disable_unprepare(d->clk); 999 return 0; 1000 } 1001 1002 static int k3_dma_resume_dev(struct device *dev) 1003 { 1004 struct k3_dma_dev *d = dev_get_drvdata(dev); 1005 int ret = 0; 1006 1007 ret = clk_prepare_enable(d->clk); 1008 if (ret < 0) { 1009 dev_err(d->slave.dev, "clk_prepare_enable failed: %d\n", ret); 1010 return ret; 1011 } 1012 k3_dma_enable_dma(d, true); 1013 return 0; 1014 } 1015 #endif 1016 1017 static SIMPLE_DEV_PM_OPS(k3_dma_pmops, k3_dma_suspend_dev, k3_dma_resume_dev); 1018 1019 static struct platform_driver k3_pdma_driver = { 1020 .driver = { 1021 .name = DRIVER_NAME, 1022 .pm = &k3_dma_pmops, 1023 .of_match_table = k3_pdma_dt_ids, 1024 }, 1025 .probe = k3_dma_probe, 1026 .remove = k3_dma_remove, 1027 }; 1028 1029 module_platform_driver(k3_pdma_driver); 1030 1031 MODULE_DESCRIPTION("HiSilicon k3 DMA Driver"); 1032 MODULE_LICENSE("GPL v2"); 1033